net/mlx5e: Expose physical layer statistical counters to ethtool
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
1 /*
2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include "en.h"
34
35 static void mlx5e_get_drvinfo(struct net_device *dev,
36                               struct ethtool_drvinfo *drvinfo)
37 {
38         struct mlx5e_priv *priv = netdev_priv(dev);
39         struct mlx5_core_dev *mdev = priv->mdev;
40
41         strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
42         strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")",
43                 sizeof(drvinfo->version));
44         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
45                  "%d.%d.%d",
46                  fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev));
47         strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
48                 sizeof(drvinfo->bus_info));
49 }
50
51 struct ptys2ethtool_config {
52         __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
53         __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
54         u32 speed;
55 };
56
57 static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
58
59 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...)               \
60         ({                                                              \
61                 struct ptys2ethtool_config *cfg;                        \
62                 const unsigned int modes[] = { __VA_ARGS__ };           \
63                 unsigned int i;                                         \
64                 cfg = &ptys2ethtool_table[reg_];                        \
65                 cfg->speed = speed_;                                    \
66                 bitmap_zero(cfg->supported,                             \
67                             __ETHTOOL_LINK_MODE_MASK_NBITS);            \
68                 bitmap_zero(cfg->advertised,                            \
69                             __ETHTOOL_LINK_MODE_MASK_NBITS);            \
70                 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) {             \
71                         __set_bit(modes[i], cfg->supported);            \
72                         __set_bit(modes[i], cfg->advertised);           \
73                 }                                                       \
74         })
75
76 void mlx5e_build_ptys2ethtool_map(void)
77 {
78         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000,
79                                        ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
80         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000,
81                                        ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
82         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000,
83                                        ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
84         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000,
85                                        ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
86         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000,
87                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
88         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000,
89                                        ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
90         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000,
91                                        ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
92         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000,
93                                        ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
94         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000,
95                                        ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
96         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000,
97                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
98         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000,
99                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
100         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000,
101                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
102         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000,
103                                        ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
104         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000,
105                                        ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
106         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000,
107                                        ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
108         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000,
109                                        ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
110         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000,
111                                        ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
112         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000,
113                                        ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
114         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000,
115                                        ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
116         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000,
117                                        ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
118         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000,
119                                        ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
120         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000,
121                                        ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
122         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000,
123                                        ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
124         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000,
125                                        ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
126         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000,
127                                        ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
128 }
129
130 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
131 {
132         struct mlx5_core_dev *mdev = priv->mdev;
133         u8 pfc_en_tx;
134         u8 pfc_en_rx;
135         int err;
136
137         err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
138
139         return err ? 0 : pfc_en_tx | pfc_en_rx;
140 }
141
142 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
143 {
144         struct mlx5_core_dev *mdev = priv->mdev;
145         u32 rx_pause;
146         u32 tx_pause;
147         int err;
148
149         err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
150
151         return err ? false : rx_pause | tx_pause;
152 }
153
154 #define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
155 #define MLX5E_NUM_RQ_STATS(priv) \
156         (NUM_RQ_STATS * priv->params.num_channels * \
157          test_bit(MLX5E_STATE_OPENED, &priv->state))
158 #define MLX5E_NUM_SQ_STATS(priv) \
159         (NUM_SQ_STATS * priv->params.num_channels * priv->params.num_tc * \
160          test_bit(MLX5E_STATE_OPENED, &priv->state))
161 #define MLX5E_NUM_PFC_COUNTERS(priv) \
162         ((mlx5e_query_global_pause_combined(priv) + hweight8(mlx5e_query_pfc_combined(priv))) * \
163           NUM_PPORT_PER_PRIO_PFC_COUNTERS)
164
165 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
166 {
167         struct mlx5e_priv *priv = netdev_priv(dev);
168
169         switch (sset) {
170         case ETH_SS_STATS:
171                 return NUM_SW_COUNTERS +
172                        MLX5E_NUM_Q_CNTRS(priv) +
173                        NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS(priv) +
174                        MLX5E_NUM_RQ_STATS(priv) +
175                        MLX5E_NUM_SQ_STATS(priv) +
176                        MLX5E_NUM_PFC_COUNTERS(priv) +
177                        ARRAY_SIZE(mlx5e_pme_status_desc) +
178                        ARRAY_SIZE(mlx5e_pme_error_desc);
179
180         case ETH_SS_PRIV_FLAGS:
181                 return ARRAY_SIZE(mlx5e_priv_flags);
182         case ETH_SS_TEST:
183                 return mlx5e_self_test_num(priv);
184         /* fallthrough */
185         default:
186                 return -EOPNOTSUPP;
187         }
188 }
189
190 static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
191 {
192         int i, j, tc, prio, idx = 0;
193         unsigned long pfc_combined;
194
195         /* SW counters */
196         for (i = 0; i < NUM_SW_COUNTERS; i++)
197                 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
198
199         /* Q counters */
200         for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
201                 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].format);
202
203         /* VPORT counters */
204         for (i = 0; i < NUM_VPORT_COUNTERS; i++)
205                 strcpy(data + (idx++) * ETH_GSTRING_LEN,
206                        vport_stats_desc[i].format);
207
208         /* PPORT counters */
209         for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
210                 strcpy(data + (idx++) * ETH_GSTRING_LEN,
211                        pport_802_3_stats_desc[i].format);
212
213         for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
214                 strcpy(data + (idx++) * ETH_GSTRING_LEN,
215                        pport_2863_stats_desc[i].format);
216
217         for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
218                 strcpy(data + (idx++) * ETH_GSTRING_LEN,
219                        pport_2819_stats_desc[i].format);
220
221         for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
222                 strcpy(data + (idx++) * ETH_GSTRING_LEN,
223                        pport_phy_statistical_stats_desc[i].format);
224
225         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
226                 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
227                         sprintf(data + (idx++) * ETH_GSTRING_LEN,
228                                 pport_per_prio_traffic_stats_desc[i].format, prio);
229         }
230
231         pfc_combined = mlx5e_query_pfc_combined(priv);
232         for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
233                 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
234                         char pfc_string[ETH_GSTRING_LEN];
235
236                         snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
237                         sprintf(data + (idx++) * ETH_GSTRING_LEN,
238                                 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
239                 }
240         }
241
242         if (mlx5e_query_global_pause_combined(priv)) {
243                 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
244                         sprintf(data + (idx++) * ETH_GSTRING_LEN,
245                                 pport_per_prio_pfc_stats_desc[i].format, "global");
246                 }
247         }
248
249         /* port module event counters */
250         for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
251                 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
252
253         for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
254                 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
255
256         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
257                 return;
258
259         /* per channel counters */
260         for (i = 0; i < priv->params.num_channels; i++)
261                 for (j = 0; j < NUM_RQ_STATS; j++)
262                         sprintf(data + (idx++) * ETH_GSTRING_LEN,
263                                 rq_stats_desc[j].format, i);
264
265         for (tc = 0; tc < priv->params.num_tc; tc++)
266                 for (i = 0; i < priv->params.num_channels; i++)
267                         for (j = 0; j < NUM_SQ_STATS; j++)
268                                 sprintf(data + (idx++) * ETH_GSTRING_LEN,
269                                         sq_stats_desc[j].format,
270                                         priv->channeltc_to_txq_map[i][tc]);
271 }
272
273 static void mlx5e_get_strings(struct net_device *dev,
274                               uint32_t stringset, uint8_t *data)
275 {
276         struct mlx5e_priv *priv = netdev_priv(dev);
277         int i;
278
279         switch (stringset) {
280         case ETH_SS_PRIV_FLAGS:
281                 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
282                         strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
283                 break;
284
285         case ETH_SS_TEST:
286                 for (i = 0; i < mlx5e_self_test_num(priv); i++)
287                         strcpy(data + i * ETH_GSTRING_LEN,
288                                mlx5e_self_tests[i]);
289                 break;
290
291         case ETH_SS_STATS:
292                 mlx5e_fill_stats_strings(priv, data);
293                 break;
294         }
295 }
296
297 static void mlx5e_get_ethtool_stats(struct net_device *dev,
298                                     struct ethtool_stats *stats, u64 *data)
299 {
300         struct mlx5e_priv *priv = netdev_priv(dev);
301         struct mlx5_priv *mlx5_priv;
302         int i, j, tc, prio, idx = 0;
303         unsigned long pfc_combined;
304
305         if (!data)
306                 return;
307
308         mutex_lock(&priv->state_lock);
309         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
310                 mlx5e_update_stats(priv);
311         mutex_unlock(&priv->state_lock);
312
313         for (i = 0; i < NUM_SW_COUNTERS; i++)
314                 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
315                                                    sw_stats_desc, i);
316
317         for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
318                 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
319                                                    q_stats_desc, i);
320
321         for (i = 0; i < NUM_VPORT_COUNTERS; i++)
322                 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
323                                                   vport_stats_desc, i);
324
325         for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
326                 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
327                                                   pport_802_3_stats_desc, i);
328
329         for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
330                 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
331                                                   pport_2863_stats_desc, i);
332
333         for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
334                 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
335                                                   pport_2819_stats_desc, i);
336
337         for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
338                 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
339                                                   pport_phy_statistical_stats_desc, i);
340
341         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
342                 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
343                         data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
344                                                  pport_per_prio_traffic_stats_desc, i);
345         }
346
347         pfc_combined = mlx5e_query_pfc_combined(priv);
348         for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
349                 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
350                         data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
351                                                           pport_per_prio_pfc_stats_desc, i);
352                 }
353         }
354
355         if (mlx5e_query_global_pause_combined(priv)) {
356                 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
357                         data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
358                                                           pport_per_prio_pfc_stats_desc, i);
359                 }
360         }
361
362         /* port module event counters */
363         mlx5_priv =  &priv->mdev->priv;
364         for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
365                 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
366                                                    mlx5e_pme_status_desc, i);
367
368         for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
369                 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
370                                                    mlx5e_pme_error_desc, i);
371
372         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
373                 return;
374
375         /* per channel counters */
376         for (i = 0; i < priv->params.num_channels; i++)
377                 for (j = 0; j < NUM_RQ_STATS; j++)
378                         data[idx++] =
379                                MLX5E_READ_CTR64_CPU(&priv->channel[i]->rq.stats,
380                                                     rq_stats_desc, j);
381
382         for (tc = 0; tc < priv->params.num_tc; tc++)
383                 for (i = 0; i < priv->params.num_channels; i++)
384                         for (j = 0; j < NUM_SQ_STATS; j++)
385                                 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->channel[i]->sq[tc].stats,
386                                                                    sq_stats_desc, j);
387 }
388
389 static u32 mlx5e_rx_wqes_to_packets(struct mlx5e_priv *priv, int rq_wq_type,
390                                     int num_wqe)
391 {
392         int packets_per_wqe;
393         int stride_size;
394         int num_strides;
395         int wqe_size;
396
397         if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
398                 return num_wqe;
399
400         stride_size = 1 << priv->params.mpwqe_log_stride_sz;
401         num_strides = 1 << priv->params.mpwqe_log_num_strides;
402         wqe_size = stride_size * num_strides;
403
404         packets_per_wqe = wqe_size /
405                           ALIGN(ETH_DATA_LEN, stride_size);
406         return (1 << (order_base_2(num_wqe * packets_per_wqe) - 1));
407 }
408
409 static u32 mlx5e_packets_to_rx_wqes(struct mlx5e_priv *priv, int rq_wq_type,
410                                     int num_packets)
411 {
412         int packets_per_wqe;
413         int stride_size;
414         int num_strides;
415         int wqe_size;
416         int num_wqes;
417
418         if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
419                 return num_packets;
420
421         stride_size = 1 << priv->params.mpwqe_log_stride_sz;
422         num_strides = 1 << priv->params.mpwqe_log_num_strides;
423         wqe_size = stride_size * num_strides;
424
425         num_packets = (1 << order_base_2(num_packets));
426
427         packets_per_wqe = wqe_size /
428                           ALIGN(ETH_DATA_LEN, stride_size);
429         num_wqes = DIV_ROUND_UP(num_packets, packets_per_wqe);
430         return 1 << (order_base_2(num_wqes));
431 }
432
433 static void mlx5e_get_ringparam(struct net_device *dev,
434                                 struct ethtool_ringparam *param)
435 {
436         struct mlx5e_priv *priv = netdev_priv(dev);
437         int rq_wq_type = priv->params.rq_wq_type;
438
439         param->rx_max_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
440                                                          1 << mlx5_max_log_rq_size(rq_wq_type));
441         param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
442         param->rx_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
443                                                      1 << priv->params.log_rq_size);
444         param->tx_pending     = 1 << priv->params.log_sq_size;
445 }
446
447 static int mlx5e_set_ringparam(struct net_device *dev,
448                                struct ethtool_ringparam *param)
449 {
450         struct mlx5e_priv *priv = netdev_priv(dev);
451         bool was_opened;
452         int rq_wq_type = priv->params.rq_wq_type;
453         u32 rx_pending_wqes;
454         u32 min_rq_size;
455         u32 max_rq_size;
456         u16 min_rx_wqes;
457         u8 log_rq_size;
458         u8 log_sq_size;
459         u32 num_mtts;
460         int err = 0;
461
462         if (param->rx_jumbo_pending) {
463                 netdev_info(dev, "%s: rx_jumbo_pending not supported\n",
464                             __func__);
465                 return -EINVAL;
466         }
467         if (param->rx_mini_pending) {
468                 netdev_info(dev, "%s: rx_mini_pending not supported\n",
469                             __func__);
470                 return -EINVAL;
471         }
472
473         min_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
474                                                1 << mlx5_min_log_rq_size(rq_wq_type));
475         max_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
476                                                1 << mlx5_max_log_rq_size(rq_wq_type));
477         rx_pending_wqes = mlx5e_packets_to_rx_wqes(priv, rq_wq_type,
478                                                    param->rx_pending);
479
480         if (param->rx_pending < min_rq_size) {
481                 netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n",
482                             __func__, param->rx_pending,
483                             min_rq_size);
484                 return -EINVAL;
485         }
486         if (param->rx_pending > max_rq_size) {
487                 netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n",
488                             __func__, param->rx_pending,
489                             max_rq_size);
490                 return -EINVAL;
491         }
492
493         num_mtts = MLX5E_REQUIRED_MTTS(rx_pending_wqes);
494         if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
495             !MLX5E_VALID_NUM_MTTS(num_mtts)) {
496                 netdev_info(dev, "%s: rx_pending (%d) request can't be satisfied, try to reduce.\n",
497                             __func__, param->rx_pending);
498                 return -EINVAL;
499         }
500
501         if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
502                 netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n",
503                             __func__, param->tx_pending,
504                             1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
505                 return -EINVAL;
506         }
507         if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
508                 netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n",
509                             __func__, param->tx_pending,
510                             1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
511                 return -EINVAL;
512         }
513
514         log_rq_size = order_base_2(rx_pending_wqes);
515         log_sq_size = order_base_2(param->tx_pending);
516         min_rx_wqes = mlx5_min_rx_wqes(rq_wq_type, rx_pending_wqes);
517
518         if (log_rq_size == priv->params.log_rq_size &&
519             log_sq_size == priv->params.log_sq_size &&
520             min_rx_wqes == priv->params.min_rx_wqes)
521                 return 0;
522
523         mutex_lock(&priv->state_lock);
524
525         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
526         if (was_opened)
527                 mlx5e_close_locked(dev);
528
529         priv->params.log_rq_size = log_rq_size;
530         priv->params.log_sq_size = log_sq_size;
531         priv->params.min_rx_wqes = min_rx_wqes;
532
533         if (was_opened)
534                 err = mlx5e_open_locked(dev);
535
536         mutex_unlock(&priv->state_lock);
537
538         return err;
539 }
540
541 static void mlx5e_get_channels(struct net_device *dev,
542                                struct ethtool_channels *ch)
543 {
544         struct mlx5e_priv *priv = netdev_priv(dev);
545
546         ch->max_combined   = mlx5e_get_max_num_channels(priv->mdev);
547         ch->combined_count = priv->params.num_channels;
548 }
549
550 static int mlx5e_set_channels(struct net_device *dev,
551                               struct ethtool_channels *ch)
552 {
553         struct mlx5e_priv *priv = netdev_priv(dev);
554         int ncv = mlx5e_get_max_num_channels(priv->mdev);
555         unsigned int count = ch->combined_count;
556         bool arfs_enabled;
557         bool was_opened;
558         int err = 0;
559
560         if (!count) {
561                 netdev_info(dev, "%s: combined_count=0 not supported\n",
562                             __func__);
563                 return -EINVAL;
564         }
565         if (ch->rx_count || ch->tx_count) {
566                 netdev_info(dev, "%s: separate rx/tx count not supported\n",
567                             __func__);
568                 return -EINVAL;
569         }
570         if (count > ncv) {
571                 netdev_info(dev, "%s: count (%d) > max (%d)\n",
572                             __func__, count, ncv);
573                 return -EINVAL;
574         }
575
576         if (priv->params.num_channels == count)
577                 return 0;
578
579         mutex_lock(&priv->state_lock);
580
581         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
582         if (was_opened)
583                 mlx5e_close_locked(dev);
584
585         arfs_enabled = dev->features & NETIF_F_NTUPLE;
586         if (arfs_enabled)
587                 mlx5e_arfs_disable(priv);
588
589         priv->params.num_channels = count;
590         mlx5e_build_default_indir_rqt(priv->mdev, priv->params.indirection_rqt,
591                                       MLX5E_INDIR_RQT_SIZE, count);
592
593         if (was_opened)
594                 err = mlx5e_open_locked(dev);
595         if (err)
596                 goto out;
597
598         if (arfs_enabled) {
599                 err = mlx5e_arfs_enable(priv);
600                 if (err)
601                         netdev_err(dev, "%s: mlx5e_arfs_enable failed: %d\n",
602                                    __func__, err);
603         }
604
605 out:
606         mutex_unlock(&priv->state_lock);
607
608         return err;
609 }
610
611 static int mlx5e_get_coalesce(struct net_device *netdev,
612                               struct ethtool_coalesce *coal)
613 {
614         struct mlx5e_priv *priv = netdev_priv(netdev);
615
616         if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
617                 return -ENOTSUPP;
618
619         coal->rx_coalesce_usecs       = priv->params.rx_cq_moderation.usec;
620         coal->rx_max_coalesced_frames = priv->params.rx_cq_moderation.pkts;
621         coal->tx_coalesce_usecs       = priv->params.tx_cq_moderation.usec;
622         coal->tx_max_coalesced_frames = priv->params.tx_cq_moderation.pkts;
623         coal->use_adaptive_rx_coalesce = priv->params.rx_am_enabled;
624
625         return 0;
626 }
627
628 static int mlx5e_set_coalesce(struct net_device *netdev,
629                               struct ethtool_coalesce *coal)
630 {
631         struct mlx5e_priv *priv    = netdev_priv(netdev);
632         struct mlx5_core_dev *mdev = priv->mdev;
633         struct mlx5e_channel *c;
634         bool restart =
635                 !!coal->use_adaptive_rx_coalesce != priv->params.rx_am_enabled;
636         bool was_opened;
637         int err = 0;
638         int tc;
639         int i;
640
641         if (!MLX5_CAP_GEN(mdev, cq_moderation))
642                 return -ENOTSUPP;
643
644         mutex_lock(&priv->state_lock);
645
646         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
647         if (was_opened && restart) {
648                 mlx5e_close_locked(netdev);
649                 priv->params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce;
650         }
651
652         priv->params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
653         priv->params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
654         priv->params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
655         priv->params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
656
657         if (!was_opened || restart)
658                 goto out;
659
660         for (i = 0; i < priv->params.num_channels; ++i) {
661                 c = priv->channel[i];
662
663                 for (tc = 0; tc < c->num_tc; tc++) {
664                         mlx5_core_modify_cq_moderation(mdev,
665                                                 &c->sq[tc].cq.mcq,
666                                                 coal->tx_coalesce_usecs,
667                                                 coal->tx_max_coalesced_frames);
668                 }
669
670                 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
671                                                coal->rx_coalesce_usecs,
672                                                coal->rx_max_coalesced_frames);
673         }
674
675 out:
676         if (was_opened && restart)
677                 err = mlx5e_open_locked(netdev);
678
679         mutex_unlock(&priv->state_lock);
680         return err;
681 }
682
683 static void ptys2ethtool_supported_link(unsigned long *supported_modes,
684                                         u32 eth_proto_cap)
685 {
686         unsigned long proto_cap = eth_proto_cap;
687         int proto;
688
689         for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
690                 bitmap_or(supported_modes, supported_modes,
691                           ptys2ethtool_table[proto].supported,
692                           __ETHTOOL_LINK_MODE_MASK_NBITS);
693 }
694
695 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
696                                     u32 eth_proto_cap)
697 {
698         unsigned long proto_cap = eth_proto_cap;
699         int proto;
700
701         for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
702                 bitmap_or(advertising_modes, advertising_modes,
703                           ptys2ethtool_table[proto].advertised,
704                           __ETHTOOL_LINK_MODE_MASK_NBITS);
705 }
706
707 static void ptys2ethtool_supported_port(struct ethtool_link_ksettings *link_ksettings,
708                                         u32 eth_proto_cap)
709 {
710         if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
711                            | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
712                            | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
713                            | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
714                            | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
715                            | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
716                 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, FIBRE);
717         }
718
719         if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
720                            | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
721                            | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
722                            | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
723                            | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
724                 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Backplane);
725         }
726 }
727
728 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
729 {
730         u32 max_speed = 0;
731         u32 proto_cap;
732         int err;
733         int i;
734
735         err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
736         if (err)
737                 return err;
738
739         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
740                 if (proto_cap & MLX5E_PROT_MASK(i))
741                         max_speed = max(max_speed, ptys2ethtool_table[i].speed);
742
743         *speed = max_speed;
744         return 0;
745 }
746
747 static void get_speed_duplex(struct net_device *netdev,
748                              u32 eth_proto_oper,
749                              struct ethtool_link_ksettings *link_ksettings)
750 {
751         int i;
752         u32 speed = SPEED_UNKNOWN;
753         u8 duplex = DUPLEX_UNKNOWN;
754
755         if (!netif_carrier_ok(netdev))
756                 goto out;
757
758         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
759                 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
760                         speed = ptys2ethtool_table[i].speed;
761                         duplex = DUPLEX_FULL;
762                         break;
763                 }
764         }
765 out:
766         link_ksettings->base.speed = speed;
767         link_ksettings->base.duplex = duplex;
768 }
769
770 static void get_supported(u32 eth_proto_cap,
771                           struct ethtool_link_ksettings *link_ksettings)
772 {
773         unsigned long *supported = link_ksettings->link_modes.supported;
774
775         ptys2ethtool_supported_port(link_ksettings, eth_proto_cap);
776         ptys2ethtool_supported_link(supported, eth_proto_cap);
777         ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
778         ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Asym_Pause);
779 }
780
781 static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
782                             u8 rx_pause,
783                             struct ethtool_link_ksettings *link_ksettings)
784 {
785         unsigned long *advertising = link_ksettings->link_modes.advertising;
786
787         ptys2ethtool_adver_link(advertising, eth_proto_cap);
788         if (tx_pause)
789                 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
790         if (tx_pause ^ rx_pause)
791                 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
792 }
793
794 static u8 get_connector_port(u32 eth_proto)
795 {
796         if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
797                          | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
798                          | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
799                          | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
800                         return PORT_FIBRE;
801         }
802
803         if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
804                          | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
805                          | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
806                         return PORT_DA;
807         }
808
809         if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
810                          | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
811                          | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
812                          | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
813                         return PORT_NONE;
814         }
815
816         return PORT_OTHER;
817 }
818
819 static void get_lp_advertising(u32 eth_proto_lp,
820                                struct ethtool_link_ksettings *link_ksettings)
821 {
822         unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
823
824         ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
825 }
826
827 static int mlx5e_get_link_ksettings(struct net_device *netdev,
828                                     struct ethtool_link_ksettings *link_ksettings)
829 {
830         struct mlx5e_priv *priv    = netdev_priv(netdev);
831         struct mlx5_core_dev *mdev = priv->mdev;
832         u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
833         u32 eth_proto_cap;
834         u32 eth_proto_admin;
835         u32 eth_proto_lp;
836         u32 eth_proto_oper;
837         u8 an_disable_admin;
838         u8 an_status;
839         int err;
840
841         err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
842         if (err) {
843                 netdev_err(netdev, "%s: query port ptys failed: %d\n",
844                            __func__, err);
845                 goto err_query_ptys;
846         }
847
848         eth_proto_cap    = MLX5_GET(ptys_reg, out, eth_proto_capability);
849         eth_proto_admin  = MLX5_GET(ptys_reg, out, eth_proto_admin);
850         eth_proto_oper   = MLX5_GET(ptys_reg, out, eth_proto_oper);
851         eth_proto_lp     = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
852         an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
853         an_status        = MLX5_GET(ptys_reg, out, an_status);
854
855         ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
856         ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
857
858         get_supported(eth_proto_cap, link_ksettings);
859         get_advertising(eth_proto_admin, 0, 0, link_ksettings);
860         get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
861
862         eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
863
864         link_ksettings->base.port = get_connector_port(eth_proto_oper);
865         get_lp_advertising(eth_proto_lp, link_ksettings);
866
867         if (an_status == MLX5_AN_COMPLETE)
868                 ethtool_link_ksettings_add_link_mode(link_ksettings,
869                                                      lp_advertising, Autoneg);
870
871         link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
872                                                           AUTONEG_ENABLE;
873         ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
874                                              Autoneg);
875         if (!an_disable_admin)
876                 ethtool_link_ksettings_add_link_mode(link_ksettings,
877                                                      advertising, Autoneg);
878
879 err_query_ptys:
880         return err;
881 }
882
883 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
884 {
885         u32 i, ptys_modes = 0;
886
887         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
888                 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
889                                       link_modes,
890                                       __ETHTOOL_LINK_MODE_MASK_NBITS))
891                         ptys_modes |= MLX5E_PROT_MASK(i);
892         }
893
894         return ptys_modes;
895 }
896
897 static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
898 {
899         u32 i, speed_links = 0;
900
901         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
902                 if (ptys2ethtool_table[i].speed == speed)
903                         speed_links |= MLX5E_PROT_MASK(i);
904         }
905
906         return speed_links;
907 }
908
909 static int mlx5e_set_link_ksettings(struct net_device *netdev,
910                                     const struct ethtool_link_ksettings *link_ksettings)
911 {
912         struct mlx5e_priv *priv    = netdev_priv(netdev);
913         struct mlx5_core_dev *mdev = priv->mdev;
914         u32 eth_proto_cap, eth_proto_admin;
915         bool an_changes = false;
916         u8 an_disable_admin;
917         u8 an_disable_cap;
918         bool an_disable;
919         u32 link_modes;
920         u8 an_status;
921         u32 speed;
922         int err;
923
924         speed = link_ksettings->base.speed;
925
926         link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
927                 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
928                 mlx5e_ethtool2ptys_speed_link(speed);
929
930         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
931         if (err) {
932                 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
933                            __func__, err);
934                 goto out;
935         }
936
937         link_modes = link_modes & eth_proto_cap;
938         if (!link_modes) {
939                 netdev_err(netdev, "%s: Not supported link mode(s) requested",
940                            __func__);
941                 err = -EINVAL;
942                 goto out;
943         }
944
945         err = mlx5_query_port_proto_admin(mdev, &eth_proto_admin, MLX5_PTYS_EN);
946         if (err) {
947                 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
948                            __func__, err);
949                 goto out;
950         }
951
952         mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
953                                 &an_disable_cap, &an_disable_admin);
954
955         an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
956         an_changes = ((!an_disable && an_disable_admin) ||
957                       (an_disable && !an_disable_admin));
958
959         if (!an_changes && link_modes == eth_proto_admin)
960                 goto out;
961
962         mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
963         mlx5_toggle_port_link(mdev);
964
965 out:
966         return err;
967 }
968
969 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
970 {
971         struct mlx5e_priv *priv = netdev_priv(netdev);
972
973         return sizeof(priv->params.toeplitz_hash_key);
974 }
975
976 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
977 {
978         return MLX5E_INDIR_RQT_SIZE;
979 }
980
981 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
982                           u8 *hfunc)
983 {
984         struct mlx5e_priv *priv = netdev_priv(netdev);
985
986         if (indir)
987                 memcpy(indir, priv->params.indirection_rqt,
988                        sizeof(priv->params.indirection_rqt));
989
990         if (key)
991                 memcpy(key, priv->params.toeplitz_hash_key,
992                        sizeof(priv->params.toeplitz_hash_key));
993
994         if (hfunc)
995                 *hfunc = priv->params.rss_hfunc;
996
997         return 0;
998 }
999
1000 static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
1001 {
1002         struct mlx5_core_dev *mdev = priv->mdev;
1003         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1004         int i;
1005
1006         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
1007         mlx5e_build_tir_ctx_hash(tirc, priv);
1008
1009         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
1010                 mlx5_core_modify_tir(mdev, priv->indir_tir[i].tirn, in, inlen);
1011 }
1012
1013 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
1014                           const u8 *key, const u8 hfunc)
1015 {
1016         struct mlx5e_priv *priv = netdev_priv(dev);
1017         int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1018         void *in;
1019
1020         if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1021             (hfunc != ETH_RSS_HASH_XOR) &&
1022             (hfunc != ETH_RSS_HASH_TOP))
1023                 return -EINVAL;
1024
1025         in = mlx5_vzalloc(inlen);
1026         if (!in)
1027                 return -ENOMEM;
1028
1029         mutex_lock(&priv->state_lock);
1030
1031         if (indir) {
1032                 u32 rqtn = priv->indir_rqt.rqtn;
1033
1034                 memcpy(priv->params.indirection_rqt, indir,
1035                        sizeof(priv->params.indirection_rqt));
1036                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1037         }
1038
1039         if (key)
1040                 memcpy(priv->params.toeplitz_hash_key, key,
1041                        sizeof(priv->params.toeplitz_hash_key));
1042
1043         if (hfunc != ETH_RSS_HASH_NO_CHANGE)
1044                 priv->params.rss_hfunc = hfunc;
1045
1046         mlx5e_modify_tirs_hash(priv, in, inlen);
1047
1048         mutex_unlock(&priv->state_lock);
1049
1050         kvfree(in);
1051
1052         return 0;
1053 }
1054
1055 static int mlx5e_get_rxnfc(struct net_device *netdev,
1056                            struct ethtool_rxnfc *info, u32 *rule_locs)
1057 {
1058         struct mlx5e_priv *priv = netdev_priv(netdev);
1059         int err = 0;
1060
1061         switch (info->cmd) {
1062         case ETHTOOL_GRXRINGS:
1063                 info->data = priv->params.num_channels;
1064                 break;
1065         case ETHTOOL_GRXCLSRLCNT:
1066                 info->rule_cnt = priv->fs.ethtool.tot_num_rules;
1067                 break;
1068         case ETHTOOL_GRXCLSRULE:
1069                 err = mlx5e_ethtool_get_flow(priv, info, info->fs.location);
1070                 break;
1071         case ETHTOOL_GRXCLSRLALL:
1072                 err = mlx5e_ethtool_get_all_flows(priv, info, rule_locs);
1073                 break;
1074         default:
1075                 err = -EOPNOTSUPP;
1076                 break;
1077         }
1078
1079         return err;
1080 }
1081
1082 static int mlx5e_get_tunable(struct net_device *dev,
1083                              const struct ethtool_tunable *tuna,
1084                              void *data)
1085 {
1086         const struct mlx5e_priv *priv = netdev_priv(dev);
1087         int err = 0;
1088
1089         switch (tuna->id) {
1090         case ETHTOOL_TX_COPYBREAK:
1091                 *(u32 *)data = priv->params.tx_max_inline;
1092                 break;
1093         default:
1094                 err = -EINVAL;
1095                 break;
1096         }
1097
1098         return err;
1099 }
1100
1101 static int mlx5e_set_tunable(struct net_device *dev,
1102                              const struct ethtool_tunable *tuna,
1103                              const void *data)
1104 {
1105         struct mlx5e_priv *priv = netdev_priv(dev);
1106         struct mlx5_core_dev *mdev = priv->mdev;
1107         bool was_opened;
1108         u32 val;
1109         int err = 0;
1110
1111         switch (tuna->id) {
1112         case ETHTOOL_TX_COPYBREAK:
1113                 val = *(u32 *)data;
1114                 if (val > mlx5e_get_max_inline_cap(mdev)) {
1115                         err = -EINVAL;
1116                         break;
1117                 }
1118
1119                 mutex_lock(&priv->state_lock);
1120
1121                 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1122                 if (was_opened)
1123                         mlx5e_close_locked(dev);
1124
1125                 priv->params.tx_max_inline = val;
1126
1127                 if (was_opened)
1128                         err = mlx5e_open_locked(dev);
1129
1130                 mutex_unlock(&priv->state_lock);
1131                 break;
1132         default:
1133                 err = -EINVAL;
1134                 break;
1135         }
1136
1137         return err;
1138 }
1139
1140 static void mlx5e_get_pauseparam(struct net_device *netdev,
1141                                  struct ethtool_pauseparam *pauseparam)
1142 {
1143         struct mlx5e_priv *priv    = netdev_priv(netdev);
1144         struct mlx5_core_dev *mdev = priv->mdev;
1145         int err;
1146
1147         err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1148                                     &pauseparam->tx_pause);
1149         if (err) {
1150                 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1151                            __func__, err);
1152         }
1153 }
1154
1155 static int mlx5e_set_pauseparam(struct net_device *netdev,
1156                                 struct ethtool_pauseparam *pauseparam)
1157 {
1158         struct mlx5e_priv *priv    = netdev_priv(netdev);
1159         struct mlx5_core_dev *mdev = priv->mdev;
1160         int err;
1161
1162         if (pauseparam->autoneg)
1163                 return -EINVAL;
1164
1165         err = mlx5_set_port_pause(mdev,
1166                                   pauseparam->rx_pause ? 1 : 0,
1167                                   pauseparam->tx_pause ? 1 : 0);
1168         if (err) {
1169                 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1170                            __func__, err);
1171         }
1172
1173         return err;
1174 }
1175
1176 static int mlx5e_get_ts_info(struct net_device *dev,
1177                              struct ethtool_ts_info *info)
1178 {
1179         struct mlx5e_priv *priv = netdev_priv(dev);
1180         int ret;
1181
1182         ret = ethtool_op_get_ts_info(dev, info);
1183         if (ret)
1184                 return ret;
1185
1186         info->phc_index = priv->tstamp.ptp ?
1187                           ptp_clock_index(priv->tstamp.ptp) : -1;
1188
1189         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1190                 return 0;
1191
1192         info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1193                                  SOF_TIMESTAMPING_RX_HARDWARE |
1194                                  SOF_TIMESTAMPING_RAW_HARDWARE;
1195
1196         info->tx_types = (BIT(1) << HWTSTAMP_TX_OFF) |
1197                          (BIT(1) << HWTSTAMP_TX_ON);
1198
1199         info->rx_filters = (BIT(1) << HWTSTAMP_FILTER_NONE) |
1200                            (BIT(1) << HWTSTAMP_FILTER_ALL);
1201
1202         return 0;
1203 }
1204
1205 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1206 {
1207         __u32 ret = 0;
1208
1209         if (MLX5_CAP_GEN(mdev, wol_g))
1210                 ret |= WAKE_MAGIC;
1211
1212         if (MLX5_CAP_GEN(mdev, wol_s))
1213                 ret |= WAKE_MAGICSECURE;
1214
1215         if (MLX5_CAP_GEN(mdev, wol_a))
1216                 ret |= WAKE_ARP;
1217
1218         if (MLX5_CAP_GEN(mdev, wol_b))
1219                 ret |= WAKE_BCAST;
1220
1221         if (MLX5_CAP_GEN(mdev, wol_m))
1222                 ret |= WAKE_MCAST;
1223
1224         if (MLX5_CAP_GEN(mdev, wol_u))
1225                 ret |= WAKE_UCAST;
1226
1227         if (MLX5_CAP_GEN(mdev, wol_p))
1228                 ret |= WAKE_PHY;
1229
1230         return ret;
1231 }
1232
1233 static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1234 {
1235         __u32 ret = 0;
1236
1237         if (mode & MLX5_WOL_MAGIC)
1238                 ret |= WAKE_MAGIC;
1239
1240         if (mode & MLX5_WOL_SECURED_MAGIC)
1241                 ret |= WAKE_MAGICSECURE;
1242
1243         if (mode & MLX5_WOL_ARP)
1244                 ret |= WAKE_ARP;
1245
1246         if (mode & MLX5_WOL_BROADCAST)
1247                 ret |= WAKE_BCAST;
1248
1249         if (mode & MLX5_WOL_MULTICAST)
1250                 ret |= WAKE_MCAST;
1251
1252         if (mode & MLX5_WOL_UNICAST)
1253                 ret |= WAKE_UCAST;
1254
1255         if (mode & MLX5_WOL_PHY_ACTIVITY)
1256                 ret |= WAKE_PHY;
1257
1258         return ret;
1259 }
1260
1261 static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1262 {
1263         u8 ret = 0;
1264
1265         if (mode & WAKE_MAGIC)
1266                 ret |= MLX5_WOL_MAGIC;
1267
1268         if (mode & WAKE_MAGICSECURE)
1269                 ret |= MLX5_WOL_SECURED_MAGIC;
1270
1271         if (mode & WAKE_ARP)
1272                 ret |= MLX5_WOL_ARP;
1273
1274         if (mode & WAKE_BCAST)
1275                 ret |= MLX5_WOL_BROADCAST;
1276
1277         if (mode & WAKE_MCAST)
1278                 ret |= MLX5_WOL_MULTICAST;
1279
1280         if (mode & WAKE_UCAST)
1281                 ret |= MLX5_WOL_UNICAST;
1282
1283         if (mode & WAKE_PHY)
1284                 ret |= MLX5_WOL_PHY_ACTIVITY;
1285
1286         return ret;
1287 }
1288
1289 static void mlx5e_get_wol(struct net_device *netdev,
1290                           struct ethtool_wolinfo *wol)
1291 {
1292         struct mlx5e_priv *priv = netdev_priv(netdev);
1293         struct mlx5_core_dev *mdev = priv->mdev;
1294         u8 mlx5_wol_mode;
1295         int err;
1296
1297         memset(wol, 0, sizeof(*wol));
1298
1299         wol->supported = mlx5e_get_wol_supported(mdev);
1300         if (!wol->supported)
1301                 return;
1302
1303         err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1304         if (err)
1305                 return;
1306
1307         wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1308 }
1309
1310 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1311 {
1312         struct mlx5e_priv *priv = netdev_priv(netdev);
1313         struct mlx5_core_dev *mdev = priv->mdev;
1314         __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1315         u32 mlx5_wol_mode;
1316
1317         if (!wol_supported)
1318                 return -ENOTSUPP;
1319
1320         if (wol->wolopts & ~wol_supported)
1321                 return -EINVAL;
1322
1323         mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1324
1325         return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1326 }
1327
1328 static int mlx5e_set_phys_id(struct net_device *dev,
1329                              enum ethtool_phys_id_state state)
1330 {
1331         struct mlx5e_priv *priv = netdev_priv(dev);
1332         struct mlx5_core_dev *mdev = priv->mdev;
1333         u16 beacon_duration;
1334
1335         if (!MLX5_CAP_GEN(mdev, beacon_led))
1336                 return -EOPNOTSUPP;
1337
1338         switch (state) {
1339         case ETHTOOL_ID_ACTIVE:
1340                 beacon_duration = MLX5_BEACON_DURATION_INF;
1341                 break;
1342         case ETHTOOL_ID_INACTIVE:
1343                 beacon_duration = MLX5_BEACON_DURATION_OFF;
1344                 break;
1345         default:
1346                 return -EOPNOTSUPP;
1347         }
1348
1349         return mlx5_set_port_beacon(mdev, beacon_duration);
1350 }
1351
1352 static int mlx5e_get_module_info(struct net_device *netdev,
1353                                  struct ethtool_modinfo *modinfo)
1354 {
1355         struct mlx5e_priv *priv = netdev_priv(netdev);
1356         struct mlx5_core_dev *dev = priv->mdev;
1357         int size_read = 0;
1358         u8 data[4];
1359
1360         size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1361         if (size_read < 2)
1362                 return -EIO;
1363
1364         /* data[0] = identifier byte */
1365         switch (data[0]) {
1366         case MLX5_MODULE_ID_QSFP:
1367                 modinfo->type       = ETH_MODULE_SFF_8436;
1368                 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1369                 break;
1370         case MLX5_MODULE_ID_QSFP_PLUS:
1371         case MLX5_MODULE_ID_QSFP28:
1372                 /* data[1] = revision id */
1373                 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1374                         modinfo->type       = ETH_MODULE_SFF_8636;
1375                         modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1376                 } else {
1377                         modinfo->type       = ETH_MODULE_SFF_8436;
1378                         modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1379                 }
1380                 break;
1381         case MLX5_MODULE_ID_SFP:
1382                 modinfo->type       = ETH_MODULE_SFF_8472;
1383                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1384                 break;
1385         default:
1386                 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1387                            __func__, data[0]);
1388                 return -EINVAL;
1389         }
1390
1391         return 0;
1392 }
1393
1394 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1395                                    struct ethtool_eeprom *ee,
1396                                    u8 *data)
1397 {
1398         struct mlx5e_priv *priv = netdev_priv(netdev);
1399         struct mlx5_core_dev *mdev = priv->mdev;
1400         int offset = ee->offset;
1401         int size_read;
1402         int i = 0;
1403
1404         if (!ee->len)
1405                 return -EINVAL;
1406
1407         memset(data, 0, ee->len);
1408
1409         while (i < ee->len) {
1410                 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1411                                                      data + i);
1412
1413                 if (!size_read)
1414                         /* Done reading */
1415                         return 0;
1416
1417                 if (size_read < 0) {
1418                         netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1419                                    __func__, size_read);
1420                         return 0;
1421                 }
1422
1423                 i += size_read;
1424                 offset += size_read;
1425         }
1426
1427         return 0;
1428 }
1429
1430 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1431
1432 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1433 {
1434         struct mlx5e_priv *priv = netdev_priv(netdev);
1435         struct mlx5_core_dev *mdev = priv->mdev;
1436         bool rx_mode_changed;
1437         u8 rx_cq_period_mode;
1438         int err = 0;
1439         bool reset;
1440
1441         rx_cq_period_mode = enable ?
1442                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1443                 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1444         rx_mode_changed = rx_cq_period_mode != priv->params.rx_cq_period_mode;
1445
1446         if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1447             !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1448                 return -ENOTSUPP;
1449
1450         if (!rx_mode_changed)
1451                 return 0;
1452
1453         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
1454         if (reset)
1455                 mlx5e_close_locked(netdev);
1456
1457         mlx5e_set_rx_cq_mode_params(&priv->params, rx_cq_period_mode);
1458
1459         if (reset)
1460                 err = mlx5e_open_locked(netdev);
1461
1462         return err;
1463 }
1464
1465 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1466                                      bool enable)
1467 {
1468         struct mlx5e_priv *priv = netdev_priv(netdev);
1469         struct mlx5_core_dev *mdev = priv->mdev;
1470         int err = 0;
1471         bool reset;
1472
1473         if (!MLX5_CAP_GEN(mdev, cqe_compression))
1474                 return -ENOTSUPP;
1475
1476         if (enable && priv->tstamp.hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
1477                 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1478                 return -EINVAL;
1479         }
1480
1481         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
1482
1483         if (reset)
1484                 mlx5e_close_locked(netdev);
1485
1486         MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, enable);
1487         priv->params.rx_cqe_compress_def = enable;
1488
1489         if (reset)
1490                 err = mlx5e_open_locked(netdev);
1491         return err;
1492 }
1493
1494 static int mlx5e_handle_pflag(struct net_device *netdev,
1495                               u32 wanted_flags,
1496                               enum mlx5e_priv_flag flag,
1497                               mlx5e_pflag_handler pflag_handler)
1498 {
1499         struct mlx5e_priv *priv = netdev_priv(netdev);
1500         bool enable = !!(wanted_flags & flag);
1501         u32 changes = wanted_flags ^ priv->params.pflags;
1502         int err;
1503
1504         if (!(changes & flag))
1505                 return 0;
1506
1507         err = pflag_handler(netdev, enable);
1508         if (err) {
1509                 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1510                            enable ? "Enable" : "Disable", flag, err);
1511                 return err;
1512         }
1513
1514         MLX5E_SET_PFLAG(priv, flag, enable);
1515         return 0;
1516 }
1517
1518 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1519 {
1520         struct mlx5e_priv *priv = netdev_priv(netdev);
1521         int err;
1522
1523         mutex_lock(&priv->state_lock);
1524         err = mlx5e_handle_pflag(netdev, pflags,
1525                                  MLX5E_PFLAG_RX_CQE_BASED_MODER,
1526                                  set_pflag_rx_cqe_based_moder);
1527         if (err)
1528                 goto out;
1529
1530         err = mlx5e_handle_pflag(netdev, pflags,
1531                                  MLX5E_PFLAG_RX_CQE_COMPRESS,
1532                                  set_pflag_rx_cqe_compress);
1533
1534 out:
1535         mutex_unlock(&priv->state_lock);
1536         return err;
1537 }
1538
1539 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1540 {
1541         struct mlx5e_priv *priv = netdev_priv(netdev);
1542
1543         return priv->params.pflags;
1544 }
1545
1546 static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1547 {
1548         int err = 0;
1549         struct mlx5e_priv *priv = netdev_priv(dev);
1550
1551         switch (cmd->cmd) {
1552         case ETHTOOL_SRXCLSRLINS:
1553                 err = mlx5e_ethtool_flow_replace(priv, &cmd->fs);
1554                 break;
1555         case ETHTOOL_SRXCLSRLDEL:
1556                 err = mlx5e_ethtool_flow_remove(priv, cmd->fs.location);
1557                 break;
1558         default:
1559                 err = -EOPNOTSUPP;
1560                 break;
1561         }
1562
1563         return err;
1564 }
1565
1566 const struct ethtool_ops mlx5e_ethtool_ops = {
1567         .get_drvinfo       = mlx5e_get_drvinfo,
1568         .get_link          = ethtool_op_get_link,
1569         .get_strings       = mlx5e_get_strings,
1570         .get_sset_count    = mlx5e_get_sset_count,
1571         .get_ethtool_stats = mlx5e_get_ethtool_stats,
1572         .get_ringparam     = mlx5e_get_ringparam,
1573         .set_ringparam     = mlx5e_set_ringparam,
1574         .get_channels      = mlx5e_get_channels,
1575         .set_channels      = mlx5e_set_channels,
1576         .get_coalesce      = mlx5e_get_coalesce,
1577         .set_coalesce      = mlx5e_set_coalesce,
1578         .get_link_ksettings  = mlx5e_get_link_ksettings,
1579         .set_link_ksettings  = mlx5e_set_link_ksettings,
1580         .get_rxfh_key_size   = mlx5e_get_rxfh_key_size,
1581         .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1582         .get_rxfh          = mlx5e_get_rxfh,
1583         .set_rxfh          = mlx5e_set_rxfh,
1584         .get_rxnfc         = mlx5e_get_rxnfc,
1585         .set_rxnfc         = mlx5e_set_rxnfc,
1586         .get_tunable       = mlx5e_get_tunable,
1587         .set_tunable       = mlx5e_set_tunable,
1588         .get_pauseparam    = mlx5e_get_pauseparam,
1589         .set_pauseparam    = mlx5e_set_pauseparam,
1590         .get_ts_info       = mlx5e_get_ts_info,
1591         .set_phys_id       = mlx5e_set_phys_id,
1592         .get_wol           = mlx5e_get_wol,
1593         .set_wol           = mlx5e_set_wol,
1594         .get_module_info   = mlx5e_get_module_info,
1595         .get_module_eeprom = mlx5e_get_module_eeprom,
1596         .get_priv_flags    = mlx5e_get_priv_flags,
1597         .set_priv_flags    = mlx5e_set_priv_flags,
1598         .self_test         = mlx5e_self_test,
1599 };