2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 static void mlx5e_get_drvinfo(struct net_device *dev,
36 struct ethtool_drvinfo *drvinfo)
38 struct mlx5e_priv *priv = netdev_priv(dev);
39 struct mlx5_core_dev *mdev = priv->mdev;
41 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
42 strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")",
43 sizeof(drvinfo->version));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev));
47 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
48 sizeof(drvinfo->bus_info));
55 } ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER] = {
56 [MLX5E_1000BASE_CX_SGMII] = {
57 .supported = SUPPORTED_1000baseKX_Full,
58 .advertised = ADVERTISED_1000baseKX_Full,
61 [MLX5E_1000BASE_KX] = {
62 .supported = SUPPORTED_1000baseKX_Full,
63 .advertised = ADVERTISED_1000baseKX_Full,
66 [MLX5E_10GBASE_CX4] = {
67 .supported = SUPPORTED_10000baseKX4_Full,
68 .advertised = ADVERTISED_10000baseKX4_Full,
71 [MLX5E_10GBASE_KX4] = {
72 .supported = SUPPORTED_10000baseKX4_Full,
73 .advertised = ADVERTISED_10000baseKX4_Full,
76 [MLX5E_10GBASE_KR] = {
77 .supported = SUPPORTED_10000baseKR_Full,
78 .advertised = ADVERTISED_10000baseKR_Full,
81 [MLX5E_20GBASE_KR2] = {
82 .supported = SUPPORTED_20000baseKR2_Full,
83 .advertised = ADVERTISED_20000baseKR2_Full,
86 [MLX5E_40GBASE_CR4] = {
87 .supported = SUPPORTED_40000baseCR4_Full,
88 .advertised = ADVERTISED_40000baseCR4_Full,
91 [MLX5E_40GBASE_KR4] = {
92 .supported = SUPPORTED_40000baseKR4_Full,
93 .advertised = ADVERTISED_40000baseKR4_Full,
96 [MLX5E_56GBASE_R4] = {
97 .supported = SUPPORTED_56000baseKR4_Full,
98 .advertised = ADVERTISED_56000baseKR4_Full,
101 [MLX5E_10GBASE_CR] = {
102 .supported = SUPPORTED_10000baseKR_Full,
103 .advertised = ADVERTISED_10000baseKR_Full,
106 [MLX5E_10GBASE_SR] = {
107 .supported = SUPPORTED_10000baseKR_Full,
108 .advertised = ADVERTISED_10000baseKR_Full,
111 [MLX5E_10GBASE_ER] = {
112 .supported = SUPPORTED_10000baseKR_Full,
113 .advertised = ADVERTISED_10000baseKR_Full,
116 [MLX5E_40GBASE_SR4] = {
117 .supported = SUPPORTED_40000baseSR4_Full,
118 .advertised = ADVERTISED_40000baseSR4_Full,
121 [MLX5E_40GBASE_LR4] = {
122 .supported = SUPPORTED_40000baseLR4_Full,
123 .advertised = ADVERTISED_40000baseLR4_Full,
126 [MLX5E_100GBASE_CR4] = {
129 [MLX5E_100GBASE_SR4] = {
132 [MLX5E_100GBASE_KR4] = {
135 [MLX5E_100GBASE_LR4] = {
138 [MLX5E_100BASE_TX] = {
141 [MLX5E_1000BASE_T] = {
142 .supported = SUPPORTED_1000baseT_Full,
143 .advertised = ADVERTISED_1000baseT_Full,
146 [MLX5E_10GBASE_T] = {
147 .supported = SUPPORTED_10000baseT_Full,
148 .advertised = ADVERTISED_10000baseT_Full,
151 [MLX5E_25GBASE_CR] = {
154 [MLX5E_25GBASE_KR] = {
157 [MLX5E_25GBASE_SR] = {
160 [MLX5E_50GBASE_CR2] = {
163 [MLX5E_50GBASE_KR2] = {
168 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
170 struct mlx5_core_dev *mdev = priv->mdev;
175 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
177 return err ? 0 : pfc_en_tx | pfc_en_rx;
180 #define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
181 #define MLX5E_NUM_RQ_STATS(priv) \
182 (NUM_RQ_STATS * priv->params.num_channels * \
183 test_bit(MLX5E_STATE_OPENED, &priv->state))
184 #define MLX5E_NUM_SQ_STATS(priv) \
185 (NUM_SQ_STATS * priv->params.num_channels * priv->params.num_tc * \
186 test_bit(MLX5E_STATE_OPENED, &priv->state))
187 #define MLX5E_NUM_PFC_COUNTERS(priv) hweight8(mlx5e_query_pfc_combined(priv))
189 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
191 struct mlx5e_priv *priv = netdev_priv(dev);
195 return NUM_SW_COUNTERS +
196 MLX5E_NUM_Q_CNTRS(priv) +
197 NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS +
198 MLX5E_NUM_RQ_STATS(priv) +
199 MLX5E_NUM_SQ_STATS(priv) +
200 MLX5E_NUM_PFC_COUNTERS(priv);
201 case ETH_SS_PRIV_FLAGS:
202 return ARRAY_SIZE(mlx5e_priv_flags);
209 static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
211 int i, j, tc, prio, idx = 0;
212 unsigned long pfc_combined;
215 for (i = 0; i < NUM_SW_COUNTERS; i++)
216 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].name);
219 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
220 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].name);
223 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
224 strcpy(data + (idx++) * ETH_GSTRING_LEN,
225 vport_stats_desc[i].name);
228 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
229 strcpy(data + (idx++) * ETH_GSTRING_LEN,
230 pport_802_3_stats_desc[i].name);
232 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
233 strcpy(data + (idx++) * ETH_GSTRING_LEN,
234 pport_2863_stats_desc[i].name);
236 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
237 strcpy(data + (idx++) * ETH_GSTRING_LEN,
238 pport_2819_stats_desc[i].name);
240 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
241 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
242 sprintf(data + (idx++) * ETH_GSTRING_LEN, "prio%d_%s",
244 pport_per_prio_traffic_stats_desc[i].name);
247 pfc_combined = mlx5e_query_pfc_combined(priv);
248 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
249 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
250 sprintf(data + (idx++) * ETH_GSTRING_LEN, "prio%d_%s",
251 prio, pport_per_prio_pfc_stats_desc[i].name);
255 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
258 /* per channel counters */
259 for (i = 0; i < priv->params.num_channels; i++)
260 for (j = 0; j < NUM_RQ_STATS; j++)
261 sprintf(data + (idx++) * ETH_GSTRING_LEN, "rx%d_%s", i,
262 rq_stats_desc[j].name);
264 for (tc = 0; tc < priv->params.num_tc; tc++)
265 for (i = 0; i < priv->params.num_channels; i++)
266 for (j = 0; j < NUM_SQ_STATS; j++)
267 sprintf(data + (idx++) * ETH_GSTRING_LEN,
269 priv->channeltc_to_txq_map[i][tc],
270 sq_stats_desc[j].name);
273 static void mlx5e_get_strings(struct net_device *dev,
274 uint32_t stringset, uint8_t *data)
276 struct mlx5e_priv *priv = netdev_priv(dev);
280 case ETH_SS_PRIV_FLAGS:
281 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
282 strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
289 mlx5e_fill_stats_strings(priv, data);
294 static void mlx5e_get_ethtool_stats(struct net_device *dev,
295 struct ethtool_stats *stats, u64 *data)
297 struct mlx5e_priv *priv = netdev_priv(dev);
298 int i, j, tc, prio, idx = 0;
299 unsigned long pfc_combined;
304 mutex_lock(&priv->state_lock);
305 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
306 mlx5e_update_stats(priv);
307 mutex_unlock(&priv->state_lock);
309 for (i = 0; i < NUM_SW_COUNTERS; i++)
310 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
313 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
314 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
317 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
318 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
319 vport_stats_desc, i);
321 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
322 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
323 pport_802_3_stats_desc, i);
325 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
326 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
327 pport_2863_stats_desc, i);
329 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
330 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
331 pport_2819_stats_desc, i);
333 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
334 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
335 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
336 pport_per_prio_traffic_stats_desc, i);
339 pfc_combined = mlx5e_query_pfc_combined(priv);
340 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
341 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
342 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
343 pport_per_prio_pfc_stats_desc, i);
347 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
350 /* per channel counters */
351 for (i = 0; i < priv->params.num_channels; i++)
352 for (j = 0; j < NUM_RQ_STATS; j++)
354 MLX5E_READ_CTR64_CPU(&priv->channel[i]->rq.stats,
357 for (tc = 0; tc < priv->params.num_tc; tc++)
358 for (i = 0; i < priv->params.num_channels; i++)
359 for (j = 0; j < NUM_SQ_STATS; j++)
360 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->channel[i]->sq[tc].stats,
364 static void mlx5e_get_ringparam(struct net_device *dev,
365 struct ethtool_ringparam *param)
367 struct mlx5e_priv *priv = netdev_priv(dev);
368 int rq_wq_type = priv->params.rq_wq_type;
370 param->rx_max_pending = 1 << mlx5_max_log_rq_size(rq_wq_type);
371 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
372 param->rx_pending = 1 << priv->params.log_rq_size;
373 param->tx_pending = 1 << priv->params.log_sq_size;
376 static int mlx5e_set_ringparam(struct net_device *dev,
377 struct ethtool_ringparam *param)
379 struct mlx5e_priv *priv = netdev_priv(dev);
381 int rq_wq_type = priv->params.rq_wq_type;
387 if (param->rx_jumbo_pending) {
388 netdev_info(dev, "%s: rx_jumbo_pending not supported\n",
392 if (param->rx_mini_pending) {
393 netdev_info(dev, "%s: rx_mini_pending not supported\n",
397 if (param->rx_pending < (1 << mlx5_min_log_rq_size(rq_wq_type))) {
398 netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n",
399 __func__, param->rx_pending,
400 1 << mlx5_min_log_rq_size(rq_wq_type));
403 if (param->rx_pending > (1 << mlx5_max_log_rq_size(rq_wq_type))) {
404 netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n",
405 __func__, param->rx_pending,
406 1 << mlx5_max_log_rq_size(rq_wq_type));
409 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
410 netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n",
411 __func__, param->tx_pending,
412 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
415 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
416 netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n",
417 __func__, param->tx_pending,
418 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
422 log_rq_size = order_base_2(param->rx_pending);
423 log_sq_size = order_base_2(param->tx_pending);
424 min_rx_wqes = mlx5_min_rx_wqes(rq_wq_type, param->rx_pending);
426 if (log_rq_size == priv->params.log_rq_size &&
427 log_sq_size == priv->params.log_sq_size &&
428 min_rx_wqes == priv->params.min_rx_wqes)
431 mutex_lock(&priv->state_lock);
433 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
435 mlx5e_close_locked(dev);
437 priv->params.log_rq_size = log_rq_size;
438 priv->params.log_sq_size = log_sq_size;
439 priv->params.min_rx_wqes = min_rx_wqes;
442 err = mlx5e_open_locked(dev);
444 mutex_unlock(&priv->state_lock);
449 static void mlx5e_get_channels(struct net_device *dev,
450 struct ethtool_channels *ch)
452 struct mlx5e_priv *priv = netdev_priv(dev);
454 ch->max_combined = mlx5e_get_max_num_channels(priv->mdev);
455 ch->combined_count = priv->params.num_channels;
458 static int mlx5e_set_channels(struct net_device *dev,
459 struct ethtool_channels *ch)
461 struct mlx5e_priv *priv = netdev_priv(dev);
462 int ncv = mlx5e_get_max_num_channels(priv->mdev);
463 unsigned int count = ch->combined_count;
469 netdev_info(dev, "%s: combined_count=0 not supported\n",
473 if (ch->rx_count || ch->tx_count) {
474 netdev_info(dev, "%s: separate rx/tx count not supported\n",
479 netdev_info(dev, "%s: count (%d) > max (%d)\n",
480 __func__, count, ncv);
484 if (priv->params.num_channels == count)
487 mutex_lock(&priv->state_lock);
489 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
491 mlx5e_close_locked(dev);
493 arfs_enabled = dev->features & NETIF_F_NTUPLE;
495 mlx5e_arfs_disable(priv);
497 priv->params.num_channels = count;
498 mlx5e_build_default_indir_rqt(priv->mdev, priv->params.indirection_rqt,
499 MLX5E_INDIR_RQT_SIZE, count);
502 err = mlx5e_open_locked(dev);
507 err = mlx5e_arfs_enable(priv);
509 netdev_err(dev, "%s: mlx5e_arfs_enable failed: %d\n",
514 mutex_unlock(&priv->state_lock);
519 static int mlx5e_get_coalesce(struct net_device *netdev,
520 struct ethtool_coalesce *coal)
522 struct mlx5e_priv *priv = netdev_priv(netdev);
524 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
527 coal->rx_coalesce_usecs = priv->params.rx_cq_moderation.usec;
528 coal->rx_max_coalesced_frames = priv->params.rx_cq_moderation.pkts;
529 coal->tx_coalesce_usecs = priv->params.tx_cq_moderation.usec;
530 coal->tx_max_coalesced_frames = priv->params.tx_cq_moderation.pkts;
531 coal->use_adaptive_rx_coalesce = priv->params.rx_am_enabled;
536 static int mlx5e_set_coalesce(struct net_device *netdev,
537 struct ethtool_coalesce *coal)
539 struct mlx5e_priv *priv = netdev_priv(netdev);
540 struct mlx5_core_dev *mdev = priv->mdev;
541 struct mlx5e_channel *c;
543 !!coal->use_adaptive_rx_coalesce != priv->params.rx_am_enabled;
549 if (!MLX5_CAP_GEN(mdev, cq_moderation))
552 mutex_lock(&priv->state_lock);
554 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
555 if (was_opened && restart) {
556 mlx5e_close_locked(netdev);
557 priv->params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce;
560 priv->params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
561 priv->params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
562 priv->params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
563 priv->params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
565 if (!was_opened || restart)
568 for (i = 0; i < priv->params.num_channels; ++i) {
569 c = priv->channel[i];
571 for (tc = 0; tc < c->num_tc; tc++) {
572 mlx5_core_modify_cq_moderation(mdev,
574 coal->tx_coalesce_usecs,
575 coal->tx_max_coalesced_frames);
578 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
579 coal->rx_coalesce_usecs,
580 coal->rx_max_coalesced_frames);
584 if (was_opened && restart)
585 err = mlx5e_open_locked(netdev);
587 mutex_unlock(&priv->state_lock);
591 static u32 ptys2ethtool_supported_link(u32 eth_proto_cap)
594 u32 supported_modes = 0;
596 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
597 if (eth_proto_cap & MLX5E_PROT_MASK(i))
598 supported_modes |= ptys2ethtool_table[i].supported;
600 return supported_modes;
603 static u32 ptys2ethtool_adver_link(u32 eth_proto_cap)
606 u32 advertising_modes = 0;
608 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
609 if (eth_proto_cap & MLX5E_PROT_MASK(i))
610 advertising_modes |= ptys2ethtool_table[i].advertised;
612 return advertising_modes;
615 static u32 ptys2ethtool_supported_port(u32 eth_proto_cap)
617 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
618 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
619 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
620 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
621 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
622 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
623 return SUPPORTED_FIBRE;
626 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
627 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
628 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
629 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
630 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
631 return SUPPORTED_Backplane;
636 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
643 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
647 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
648 if (proto_cap & MLX5E_PROT_MASK(i))
649 max_speed = max(max_speed, ptys2ethtool_table[i].speed);
655 static void get_speed_duplex(struct net_device *netdev,
657 struct ethtool_cmd *cmd)
660 u32 speed = SPEED_UNKNOWN;
661 u8 duplex = DUPLEX_UNKNOWN;
663 if (!netif_carrier_ok(netdev))
666 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
667 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
668 speed = ptys2ethtool_table[i].speed;
669 duplex = DUPLEX_FULL;
674 ethtool_cmd_speed_set(cmd, speed);
675 cmd->duplex = duplex;
678 static void get_supported(u32 eth_proto_cap, u32 *supported)
680 *supported |= ptys2ethtool_supported_port(eth_proto_cap);
681 *supported |= ptys2ethtool_supported_link(eth_proto_cap);
682 *supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
685 static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
686 u8 rx_pause, u32 *advertising)
688 *advertising |= ptys2ethtool_adver_link(eth_proto_cap);
689 *advertising |= tx_pause ? ADVERTISED_Pause : 0;
690 *advertising |= (tx_pause ^ rx_pause) ? ADVERTISED_Asym_Pause : 0;
693 static u8 get_connector_port(u32 eth_proto)
695 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
696 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
697 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
698 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
702 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
703 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
704 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
708 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
709 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
710 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
711 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
718 static void get_lp_advertising(u32 eth_proto_lp, u32 *lp_advertising)
720 *lp_advertising = ptys2ethtool_adver_link(eth_proto_lp);
723 static int mlx5e_get_settings(struct net_device *netdev,
724 struct ethtool_cmd *cmd)
726 struct mlx5e_priv *priv = netdev_priv(netdev);
727 struct mlx5_core_dev *mdev = priv->mdev;
728 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
735 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
738 netdev_err(netdev, "%s: query port ptys failed: %d\n",
743 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
744 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
745 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
746 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
749 cmd->advertising = 0;
751 get_supported(eth_proto_cap, &cmd->supported);
752 get_advertising(eth_proto_admin, 0, 0, &cmd->advertising);
753 get_speed_duplex(netdev, eth_proto_oper, cmd);
755 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
757 cmd->port = get_connector_port(eth_proto_oper);
758 get_lp_advertising(eth_proto_lp, &cmd->lp_advertising);
760 cmd->transceiver = XCVR_INTERNAL;
766 static u32 mlx5e_ethtool2ptys_adver_link(u32 link_modes)
768 u32 i, ptys_modes = 0;
770 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
771 if (ptys2ethtool_table[i].advertised & link_modes)
772 ptys_modes |= MLX5E_PROT_MASK(i);
778 static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
780 u32 i, speed_links = 0;
782 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
783 if (ptys2ethtool_table[i].speed == speed)
784 speed_links |= MLX5E_PROT_MASK(i);
790 static int mlx5e_set_settings(struct net_device *netdev,
791 struct ethtool_cmd *cmd)
793 struct mlx5e_priv *priv = netdev_priv(netdev);
794 struct mlx5_core_dev *mdev = priv->mdev;
797 u32 eth_proto_cap, eth_proto_admin;
800 speed = ethtool_cmd_speed(cmd);
802 link_modes = cmd->autoneg == AUTONEG_ENABLE ?
803 mlx5e_ethtool2ptys_adver_link(cmd->advertising) :
804 mlx5e_ethtool2ptys_speed_link(speed);
806 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
808 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
813 link_modes = link_modes & eth_proto_cap;
815 netdev_err(netdev, "%s: Not supported link mode(s) requested",
821 err = mlx5_query_port_proto_admin(mdev, ð_proto_admin, MLX5_PTYS_EN);
823 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
828 if (link_modes == eth_proto_admin)
831 mlx5_set_port_proto(mdev, link_modes, MLX5_PTYS_EN);
832 mlx5_toggle_port_link(mdev);
838 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
840 struct mlx5e_priv *priv = netdev_priv(netdev);
842 return sizeof(priv->params.toeplitz_hash_key);
845 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
847 return MLX5E_INDIR_RQT_SIZE;
850 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
853 struct mlx5e_priv *priv = netdev_priv(netdev);
856 memcpy(indir, priv->params.indirection_rqt,
857 sizeof(priv->params.indirection_rqt));
860 memcpy(key, priv->params.toeplitz_hash_key,
861 sizeof(priv->params.toeplitz_hash_key));
864 *hfunc = priv->params.rss_hfunc;
869 static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
871 struct mlx5_core_dev *mdev = priv->mdev;
872 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
875 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
876 mlx5e_build_tir_ctx_hash(tirc, priv);
878 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
879 mlx5_core_modify_tir(mdev, priv->indir_tirn[i], in, inlen);
882 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
883 const u8 *key, const u8 hfunc)
885 struct mlx5e_priv *priv = netdev_priv(dev);
886 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
889 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
890 (hfunc != ETH_RSS_HASH_XOR) &&
891 (hfunc != ETH_RSS_HASH_TOP))
894 in = mlx5_vzalloc(inlen);
898 mutex_lock(&priv->state_lock);
901 u32 rqtn = priv->indir_rqtn;
903 memcpy(priv->params.indirection_rqt, indir,
904 sizeof(priv->params.indirection_rqt));
905 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
909 memcpy(priv->params.toeplitz_hash_key, key,
910 sizeof(priv->params.toeplitz_hash_key));
912 if (hfunc != ETH_RSS_HASH_NO_CHANGE)
913 priv->params.rss_hfunc = hfunc;
915 mlx5e_modify_tirs_hash(priv, in, inlen);
917 mutex_unlock(&priv->state_lock);
924 static int mlx5e_get_rxnfc(struct net_device *netdev,
925 struct ethtool_rxnfc *info, u32 *rule_locs)
927 struct mlx5e_priv *priv = netdev_priv(netdev);
931 case ETHTOOL_GRXRINGS:
932 info->data = priv->params.num_channels;
942 static int mlx5e_get_tunable(struct net_device *dev,
943 const struct ethtool_tunable *tuna,
946 const struct mlx5e_priv *priv = netdev_priv(dev);
950 case ETHTOOL_TX_COPYBREAK:
951 *(u32 *)data = priv->params.tx_max_inline;
961 static int mlx5e_set_tunable(struct net_device *dev,
962 const struct ethtool_tunable *tuna,
965 struct mlx5e_priv *priv = netdev_priv(dev);
966 struct mlx5_core_dev *mdev = priv->mdev;
972 case ETHTOOL_TX_COPYBREAK:
974 if (val > mlx5e_get_max_inline_cap(mdev)) {
979 mutex_lock(&priv->state_lock);
981 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
983 mlx5e_close_locked(dev);
985 priv->params.tx_max_inline = val;
988 err = mlx5e_open_locked(dev);
990 mutex_unlock(&priv->state_lock);
1000 static void mlx5e_get_pauseparam(struct net_device *netdev,
1001 struct ethtool_pauseparam *pauseparam)
1003 struct mlx5e_priv *priv = netdev_priv(netdev);
1004 struct mlx5_core_dev *mdev = priv->mdev;
1007 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1008 &pauseparam->tx_pause);
1010 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1015 static int mlx5e_set_pauseparam(struct net_device *netdev,
1016 struct ethtool_pauseparam *pauseparam)
1018 struct mlx5e_priv *priv = netdev_priv(netdev);
1019 struct mlx5_core_dev *mdev = priv->mdev;
1022 if (pauseparam->autoneg)
1025 err = mlx5_set_port_pause(mdev,
1026 pauseparam->rx_pause ? 1 : 0,
1027 pauseparam->tx_pause ? 1 : 0);
1029 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1036 static int mlx5e_get_ts_info(struct net_device *dev,
1037 struct ethtool_ts_info *info)
1039 struct mlx5e_priv *priv = netdev_priv(dev);
1042 ret = ethtool_op_get_ts_info(dev, info);
1046 info->phc_index = priv->tstamp.ptp ?
1047 ptp_clock_index(priv->tstamp.ptp) : -1;
1049 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1052 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1053 SOF_TIMESTAMPING_RX_HARDWARE |
1054 SOF_TIMESTAMPING_RAW_HARDWARE;
1056 info->tx_types = (BIT(1) << HWTSTAMP_TX_OFF) |
1057 (BIT(1) << HWTSTAMP_TX_ON);
1059 info->rx_filters = (BIT(1) << HWTSTAMP_FILTER_NONE) |
1060 (BIT(1) << HWTSTAMP_FILTER_ALL);
1065 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1069 if (MLX5_CAP_GEN(mdev, wol_g))
1072 if (MLX5_CAP_GEN(mdev, wol_s))
1073 ret |= WAKE_MAGICSECURE;
1075 if (MLX5_CAP_GEN(mdev, wol_a))
1078 if (MLX5_CAP_GEN(mdev, wol_b))
1081 if (MLX5_CAP_GEN(mdev, wol_m))
1084 if (MLX5_CAP_GEN(mdev, wol_u))
1087 if (MLX5_CAP_GEN(mdev, wol_p))
1093 static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1097 if (mode & MLX5_WOL_MAGIC)
1100 if (mode & MLX5_WOL_SECURED_MAGIC)
1101 ret |= WAKE_MAGICSECURE;
1103 if (mode & MLX5_WOL_ARP)
1106 if (mode & MLX5_WOL_BROADCAST)
1109 if (mode & MLX5_WOL_MULTICAST)
1112 if (mode & MLX5_WOL_UNICAST)
1115 if (mode & MLX5_WOL_PHY_ACTIVITY)
1121 static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1125 if (mode & WAKE_MAGIC)
1126 ret |= MLX5_WOL_MAGIC;
1128 if (mode & WAKE_MAGICSECURE)
1129 ret |= MLX5_WOL_SECURED_MAGIC;
1131 if (mode & WAKE_ARP)
1132 ret |= MLX5_WOL_ARP;
1134 if (mode & WAKE_BCAST)
1135 ret |= MLX5_WOL_BROADCAST;
1137 if (mode & WAKE_MCAST)
1138 ret |= MLX5_WOL_MULTICAST;
1140 if (mode & WAKE_UCAST)
1141 ret |= MLX5_WOL_UNICAST;
1143 if (mode & WAKE_PHY)
1144 ret |= MLX5_WOL_PHY_ACTIVITY;
1149 static void mlx5e_get_wol(struct net_device *netdev,
1150 struct ethtool_wolinfo *wol)
1152 struct mlx5e_priv *priv = netdev_priv(netdev);
1153 struct mlx5_core_dev *mdev = priv->mdev;
1157 memset(wol, 0, sizeof(*wol));
1159 wol->supported = mlx5e_get_wol_supported(mdev);
1160 if (!wol->supported)
1163 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1167 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1170 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1172 struct mlx5e_priv *priv = netdev_priv(netdev);
1173 struct mlx5_core_dev *mdev = priv->mdev;
1174 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1180 if (wol->wolopts & ~wol_supported)
1183 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1185 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1188 static int mlx5e_set_phys_id(struct net_device *dev,
1189 enum ethtool_phys_id_state state)
1191 struct mlx5e_priv *priv = netdev_priv(dev);
1192 struct mlx5_core_dev *mdev = priv->mdev;
1193 u16 beacon_duration;
1195 if (!MLX5_CAP_GEN(mdev, beacon_led))
1199 case ETHTOOL_ID_ACTIVE:
1200 beacon_duration = MLX5_BEACON_DURATION_INF;
1202 case ETHTOOL_ID_INACTIVE:
1203 beacon_duration = MLX5_BEACON_DURATION_OFF;
1209 return mlx5_set_port_beacon(mdev, beacon_duration);
1212 static int mlx5e_get_module_info(struct net_device *netdev,
1213 struct ethtool_modinfo *modinfo)
1215 struct mlx5e_priv *priv = netdev_priv(netdev);
1216 struct mlx5_core_dev *dev = priv->mdev;
1220 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1224 /* data[0] = identifier byte */
1226 case MLX5_MODULE_ID_QSFP:
1227 modinfo->type = ETH_MODULE_SFF_8436;
1228 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1230 case MLX5_MODULE_ID_QSFP_PLUS:
1231 case MLX5_MODULE_ID_QSFP28:
1232 /* data[1] = revision id */
1233 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1234 modinfo->type = ETH_MODULE_SFF_8636;
1235 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1237 modinfo->type = ETH_MODULE_SFF_8436;
1238 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1241 case MLX5_MODULE_ID_SFP:
1242 modinfo->type = ETH_MODULE_SFF_8472;
1243 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1246 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1254 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1255 struct ethtool_eeprom *ee,
1258 struct mlx5e_priv *priv = netdev_priv(netdev);
1259 struct mlx5_core_dev *mdev = priv->mdev;
1260 int offset = ee->offset;
1267 memset(data, 0, ee->len);
1269 while (i < ee->len) {
1270 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1277 if (size_read < 0) {
1278 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1279 __func__, size_read);
1284 offset += size_read;
1290 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1292 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1294 struct mlx5e_priv *priv = netdev_priv(netdev);
1295 struct mlx5_core_dev *mdev = priv->mdev;
1296 bool rx_mode_changed;
1297 u8 rx_cq_period_mode;
1301 rx_cq_period_mode = enable ?
1302 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1303 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1304 rx_mode_changed = rx_cq_period_mode != priv->params.rx_cq_period_mode;
1306 if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1307 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1310 if (!rx_mode_changed)
1313 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
1315 mlx5e_close_locked(netdev);
1317 mlx5e_set_rx_cq_mode_params(&priv->params, rx_cq_period_mode);
1320 err = mlx5e_open_locked(netdev);
1325 static int mlx5e_handle_pflag(struct net_device *netdev,
1327 enum mlx5e_priv_flag flag,
1328 mlx5e_pflag_handler pflag_handler)
1330 struct mlx5e_priv *priv = netdev_priv(netdev);
1331 bool enable = !!(wanted_flags & flag);
1332 u32 changes = wanted_flags ^ priv->pflags;
1335 if (!(changes & flag))
1338 err = pflag_handler(netdev, enable);
1340 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1341 enable ? "Enable" : "Disable", flag, err);
1345 MLX5E_SET_PRIV_FLAG(priv, flag, enable);
1349 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1351 struct mlx5e_priv *priv = netdev_priv(netdev);
1354 mutex_lock(&priv->state_lock);
1356 err = mlx5e_handle_pflag(netdev, pflags,
1357 MLX5E_PFLAG_RX_CQE_BASED_MODER,
1358 set_pflag_rx_cqe_based_moder);
1360 mutex_unlock(&priv->state_lock);
1361 return err ? -EINVAL : 0;
1364 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1366 struct mlx5e_priv *priv = netdev_priv(netdev);
1368 return priv->pflags;
1371 const struct ethtool_ops mlx5e_ethtool_ops = {
1372 .get_drvinfo = mlx5e_get_drvinfo,
1373 .get_link = ethtool_op_get_link,
1374 .get_strings = mlx5e_get_strings,
1375 .get_sset_count = mlx5e_get_sset_count,
1376 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1377 .get_ringparam = mlx5e_get_ringparam,
1378 .set_ringparam = mlx5e_set_ringparam,
1379 .get_channels = mlx5e_get_channels,
1380 .set_channels = mlx5e_set_channels,
1381 .get_coalesce = mlx5e_get_coalesce,
1382 .set_coalesce = mlx5e_set_coalesce,
1383 .get_settings = mlx5e_get_settings,
1384 .set_settings = mlx5e_set_settings,
1385 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1386 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1387 .get_rxfh = mlx5e_get_rxfh,
1388 .set_rxfh = mlx5e_set_rxfh,
1389 .get_rxnfc = mlx5e_get_rxnfc,
1390 .get_tunable = mlx5e_get_tunable,
1391 .set_tunable = mlx5e_set_tunable,
1392 .get_pauseparam = mlx5e_get_pauseparam,
1393 .set_pauseparam = mlx5e_set_pauseparam,
1394 .get_ts_info = mlx5e_get_ts_info,
1395 .set_phys_id = mlx5e_set_phys_id,
1396 .get_wol = mlx5e_get_wol,
1397 .set_wol = mlx5e_set_wol,
1398 .get_module_info = mlx5e_get_module_info,
1399 .get_module_eeprom = mlx5e_get_module_eeprom,
1400 .get_priv_flags = mlx5e_get_priv_flags,
1401 .set_priv_flags = mlx5e_set_priv_flags