2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "lib/clock.h"
37 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
38 struct ethtool_drvinfo *drvinfo)
40 struct mlx5_core_dev *mdev = priv->mdev;
42 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
43 strlcpy(drvinfo->version, DRIVER_VERSION,
44 sizeof(drvinfo->version));
45 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
47 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
49 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
50 sizeof(drvinfo->bus_info));
53 static void mlx5e_get_drvinfo(struct net_device *dev,
54 struct ethtool_drvinfo *drvinfo)
56 struct mlx5e_priv *priv = netdev_priv(dev);
58 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
61 struct ptys2ethtool_config {
62 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
63 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
67 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
69 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
71 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \
73 struct ptys2ethtool_config *cfg; \
74 const unsigned int modes[] = { __VA_ARGS__ }; \
75 unsigned int i, bit, idx; \
76 cfg = &ptys2##table##_ethtool_table[reg_]; \
77 bitmap_zero(cfg->supported, \
78 __ETHTOOL_LINK_MODE_MASK_NBITS); \
79 bitmap_zero(cfg->advertised, \
80 __ETHTOOL_LINK_MODE_MASK_NBITS); \
81 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
82 bit = modes[i] % 64; \
83 idx = modes[i] / 64; \
84 __set_bit(bit, &cfg->supported[idx]); \
85 __set_bit(bit, &cfg->advertised[idx]); \
89 void mlx5e_build_ptys2ethtool_map(void)
91 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
92 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
93 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
94 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
95 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
96 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
97 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
98 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
99 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
100 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
101 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
102 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
103 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
104 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
105 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
106 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
107 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
108 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
109 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
110 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
111 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
112 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
113 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
114 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
115 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
116 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
117 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
118 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
119 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
120 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
121 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
122 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
123 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
124 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
125 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
126 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
127 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
128 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
129 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
130 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
131 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
132 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
133 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
134 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
135 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
136 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
137 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
138 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
139 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
140 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
141 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
142 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
143 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
144 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
145 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
146 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
147 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
148 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
149 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
150 ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
151 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
152 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
153 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
154 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
155 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
156 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
157 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
158 ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
159 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
160 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
161 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
162 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
163 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
164 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
165 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
166 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
167 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
168 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
170 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
171 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
172 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
173 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
174 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
175 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
176 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
177 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
178 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
179 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
180 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
181 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
182 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
183 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
184 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
185 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
186 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
187 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
188 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
189 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
190 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
191 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
192 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
193 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
194 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
195 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
198 static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
199 struct ptys2ethtool_config **arr,
202 bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
204 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
205 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
206 ARRAY_SIZE(ptys2legacy_ethtool_table);
209 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
212 char name[ETH_GSTRING_LEN];
213 mlx5e_pflag_handler handler;
216 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
218 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
220 int i, num_stats = 0;
224 for (i = 0; i < mlx5e_num_stats_grps; i++)
225 num_stats += mlx5e_stats_grps[i].get_num_stats(priv);
227 case ETH_SS_PRIV_FLAGS:
228 return MLX5E_NUM_PFLAGS;
230 return mlx5e_self_test_num(priv);
237 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
239 struct mlx5e_priv *priv = netdev_priv(dev);
241 return mlx5e_ethtool_get_sset_count(priv, sset);
244 static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, u8 *data)
248 for (i = 0; i < mlx5e_num_stats_grps; i++)
249 idx = mlx5e_stats_grps[i].fill_strings(priv, data, idx);
252 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
257 case ETH_SS_PRIV_FLAGS:
258 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
259 strcpy(data + i * ETH_GSTRING_LEN,
260 mlx5e_priv_flags[i].name);
264 for (i = 0; i < mlx5e_self_test_num(priv); i++)
265 strcpy(data + i * ETH_GSTRING_LEN,
266 mlx5e_self_tests[i]);
270 mlx5e_fill_stats_strings(priv, data);
275 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
277 struct mlx5e_priv *priv = netdev_priv(dev);
279 mlx5e_ethtool_get_strings(priv, stringset, data);
282 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
283 struct ethtool_stats *stats, u64 *data)
287 mutex_lock(&priv->state_lock);
288 mlx5e_update_stats(priv);
289 mutex_unlock(&priv->state_lock);
291 for (i = 0; i < mlx5e_num_stats_grps; i++)
292 idx = mlx5e_stats_grps[i].fill_stats(priv, data, idx);
295 static void mlx5e_get_ethtool_stats(struct net_device *dev,
296 struct ethtool_stats *stats,
299 struct mlx5e_priv *priv = netdev_priv(dev);
301 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
304 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
305 struct ethtool_ringparam *param)
307 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
308 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
309 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
310 param->tx_pending = 1 << priv->channels.params.log_sq_size;
313 static void mlx5e_get_ringparam(struct net_device *dev,
314 struct ethtool_ringparam *param)
316 struct mlx5e_priv *priv = netdev_priv(dev);
318 mlx5e_ethtool_get_ringparam(priv, param);
321 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
322 struct ethtool_ringparam *param)
324 struct mlx5e_channels new_channels = {};
329 if (param->rx_jumbo_pending) {
330 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
334 if (param->rx_mini_pending) {
335 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
340 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
341 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
342 __func__, param->rx_pending,
343 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
347 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
348 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
349 __func__, param->tx_pending,
350 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
354 log_rq_size = order_base_2(param->rx_pending);
355 log_sq_size = order_base_2(param->tx_pending);
357 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
358 log_sq_size == priv->channels.params.log_sq_size)
361 mutex_lock(&priv->state_lock);
363 new_channels.params = priv->channels.params;
364 new_channels.params.log_rq_mtu_frames = log_rq_size;
365 new_channels.params.log_sq_size = log_sq_size;
367 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
368 priv->channels.params = new_channels.params;
372 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
375 mutex_unlock(&priv->state_lock);
380 static int mlx5e_set_ringparam(struct net_device *dev,
381 struct ethtool_ringparam *param)
383 struct mlx5e_priv *priv = netdev_priv(dev);
385 return mlx5e_ethtool_set_ringparam(priv, param);
388 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
389 struct ethtool_channels *ch)
391 ch->max_combined = mlx5e_get_netdev_max_channels(priv->netdev);
392 ch->combined_count = priv->channels.params.num_channels;
395 static void mlx5e_get_channels(struct net_device *dev,
396 struct ethtool_channels *ch)
398 struct mlx5e_priv *priv = netdev_priv(dev);
400 mlx5e_ethtool_get_channels(priv, ch);
403 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
404 struct ethtool_channels *ch)
406 unsigned int count = ch->combined_count;
407 struct mlx5e_channels new_channels = {};
412 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
417 if (priv->channels.params.num_channels == count)
420 mutex_lock(&priv->state_lock);
422 new_channels.params = priv->channels.params;
423 new_channels.params.num_channels = count;
425 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
426 priv->channels.params = new_channels.params;
427 if (!netif_is_rxfh_configured(priv->netdev))
428 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
429 MLX5E_INDIR_RQT_SIZE, count);
433 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
435 mlx5e_arfs_disable(priv);
437 if (!netif_is_rxfh_configured(priv->netdev))
438 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
439 MLX5E_INDIR_RQT_SIZE, count);
441 /* Switch to new channels, set new parameters and close old ones */
442 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
445 int err2 = mlx5e_arfs_enable(priv);
448 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
453 mutex_unlock(&priv->state_lock);
458 static int mlx5e_set_channels(struct net_device *dev,
459 struct ethtool_channels *ch)
461 struct mlx5e_priv *priv = netdev_priv(dev);
463 return mlx5e_ethtool_set_channels(priv, ch);
466 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
467 struct ethtool_coalesce *coal)
469 struct net_dim_cq_moder *rx_moder, *tx_moder;
471 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
474 rx_moder = &priv->channels.params.rx_cq_moderation;
475 coal->rx_coalesce_usecs = rx_moder->usec;
476 coal->rx_max_coalesced_frames = rx_moder->pkts;
477 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
479 tx_moder = &priv->channels.params.tx_cq_moderation;
480 coal->tx_coalesce_usecs = tx_moder->usec;
481 coal->tx_max_coalesced_frames = tx_moder->pkts;
482 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
487 static int mlx5e_get_coalesce(struct net_device *netdev,
488 struct ethtool_coalesce *coal)
490 struct mlx5e_priv *priv = netdev_priv(netdev);
492 return mlx5e_ethtool_get_coalesce(priv, coal);
495 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
496 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
499 mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
501 struct mlx5_core_dev *mdev = priv->mdev;
505 for (i = 0; i < priv->channels.num; ++i) {
506 struct mlx5e_channel *c = priv->channels.c[i];
508 for (tc = 0; tc < c->num_tc; tc++) {
509 mlx5_core_modify_cq_moderation(mdev,
511 coal->tx_coalesce_usecs,
512 coal->tx_max_coalesced_frames);
515 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
516 coal->rx_coalesce_usecs,
517 coal->rx_max_coalesced_frames);
521 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
522 struct ethtool_coalesce *coal)
524 struct net_dim_cq_moder *rx_moder, *tx_moder;
525 struct mlx5_core_dev *mdev = priv->mdev;
526 struct mlx5e_channels new_channels = {};
530 if (!MLX5_CAP_GEN(mdev, cq_moderation))
533 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
534 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
535 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
536 __func__, MLX5E_MAX_COAL_TIME);
540 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
541 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
542 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
543 __func__, MLX5E_MAX_COAL_FRAMES);
547 mutex_lock(&priv->state_lock);
548 new_channels.params = priv->channels.params;
550 rx_moder = &new_channels.params.rx_cq_moderation;
551 rx_moder->usec = coal->rx_coalesce_usecs;
552 rx_moder->pkts = coal->rx_max_coalesced_frames;
553 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
555 tx_moder = &new_channels.params.tx_cq_moderation;
556 tx_moder->usec = coal->tx_coalesce_usecs;
557 tx_moder->pkts = coal->tx_max_coalesced_frames;
558 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
560 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
561 priv->channels.params = new_channels.params;
566 reset = (!!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled) ||
567 (!!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled);
570 mlx5e_set_priv_channels_coalesce(priv, coal);
571 priv->channels.params = new_channels.params;
575 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
578 mutex_unlock(&priv->state_lock);
582 static int mlx5e_set_coalesce(struct net_device *netdev,
583 struct ethtool_coalesce *coal)
585 struct mlx5e_priv *priv = netdev_priv(netdev);
587 return mlx5e_ethtool_set_coalesce(priv, coal);
590 static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev,
591 unsigned long *supported_modes,
594 unsigned long proto_cap = eth_proto_cap;
595 struct ptys2ethtool_config *table;
599 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size);
600 for_each_set_bit(proto, &proto_cap, max_size)
601 bitmap_or(supported_modes, supported_modes,
602 table[proto].supported,
603 __ETHTOOL_LINK_MODE_MASK_NBITS);
606 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
607 u32 eth_proto_cap, bool ext)
609 unsigned long proto_cap = eth_proto_cap;
610 struct ptys2ethtool_config *table;
614 table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
615 max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
616 ARRAY_SIZE(ptys2legacy_ethtool_table);
618 for_each_set_bit(proto, &proto_cap, max_size)
619 bitmap_or(advertising_modes, advertising_modes,
620 table[proto].advertised,
621 __ETHTOOL_LINK_MODE_MASK_NBITS);
624 static const u32 pplm_fec_2_ethtool[] = {
625 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
626 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
627 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
630 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
635 return ETHTOOL_FEC_AUTO;
637 mode = find_first_bit(&fec_mode, size);
639 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
640 return pplm_fec_2_ethtool[mode];
645 /* we use ETHTOOL_FEC_* offset and apply it to ETHTOOL_LINK_MODE_FEC_*_BIT */
646 static u32 ethtool_fec2ethtool_caps(u_long ethtool_fec_code)
650 offset = find_first_bit(ðtool_fec_code, sizeof(u32));
651 offset -= ETHTOOL_FEC_OFF_BIT;
652 offset += ETHTOOL_LINK_MODE_FEC_NONE_BIT;
657 static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
658 struct ethtool_link_ksettings *link_ksettings)
666 err = mlx5e_get_fec_caps(dev, (u8 *)&fec_caps);
668 return (err == -EOPNOTSUPP) ? 0 : err;
670 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
674 for_each_set_bit(bitn, &fec_caps, ARRAY_SIZE(pplm_fec_2_ethtool)) {
675 u_long ethtool_bitmask = pplm_fec_2_ethtool[bitn];
677 offset = ethtool_fec2ethtool_caps(ethtool_bitmask);
678 __set_bit(offset, link_ksettings->link_modes.supported);
681 active_fec = pplm2ethtool_fec(active_fec, sizeof(u32) * BITS_PER_BYTE);
682 offset = ethtool_fec2ethtool_caps(active_fec);
683 __set_bit(offset, link_ksettings->link_modes.advertising);
688 static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
692 if (!connector_type || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
693 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
694 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
695 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
696 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
697 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
698 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
699 ethtool_link_ksettings_add_link_mode(link_ksettings,
702 ethtool_link_ksettings_add_link_mode(link_ksettings,
707 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
708 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
709 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
710 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
711 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
712 ethtool_link_ksettings_add_link_mode(link_ksettings,
715 ethtool_link_ksettings_add_link_mode(link_ksettings,
722 switch (connector_type) {
724 ethtool_link_ksettings_add_link_mode(link_ksettings,
726 ethtool_link_ksettings_add_link_mode(link_ksettings,
730 ethtool_link_ksettings_add_link_mode(link_ksettings,
732 ethtool_link_ksettings_add_link_mode(link_ksettings,
736 ethtool_link_ksettings_add_link_mode(link_ksettings,
738 ethtool_link_ksettings_add_link_mode(link_ksettings,
742 ethtool_link_ksettings_add_link_mode(link_ksettings,
744 ethtool_link_ksettings_add_link_mode(link_ksettings,
747 case MLX5E_PORT_FIBRE:
748 ethtool_link_ksettings_add_link_mode(link_ksettings,
750 ethtool_link_ksettings_add_link_mode(link_ksettings,
754 ethtool_link_ksettings_add_link_mode(link_ksettings,
755 supported, Backplane);
756 ethtool_link_ksettings_add_link_mode(link_ksettings,
757 advertising, Backplane);
759 case MLX5E_PORT_NONE:
760 case MLX5E_PORT_OTHER:
766 static void get_speed_duplex(struct net_device *netdev,
768 struct ethtool_link_ksettings *link_ksettings)
770 struct mlx5e_priv *priv = netdev_priv(netdev);
771 u32 speed = SPEED_UNKNOWN;
772 u8 duplex = DUPLEX_UNKNOWN;
774 if (!netif_carrier_ok(netdev))
777 speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper);
779 speed = SPEED_UNKNOWN;
783 duplex = DUPLEX_FULL;
786 link_ksettings->base.speed = speed;
787 link_ksettings->base.duplex = duplex;
790 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
791 struct ethtool_link_ksettings *link_ksettings)
793 unsigned long *supported = link_ksettings->link_modes.supported;
794 ptys2ethtool_supported_link(mdev, supported, eth_proto_cap);
796 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
799 static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause,
800 struct ethtool_link_ksettings *link_ksettings,
803 unsigned long *advertising = link_ksettings->link_modes.advertising;
804 ptys2ethtool_adver_link(advertising, eth_proto_cap, ext);
807 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
808 if (tx_pause ^ rx_pause)
809 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
812 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
813 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
814 [MLX5E_PORT_NONE] = PORT_NONE,
815 [MLX5E_PORT_TP] = PORT_TP,
816 [MLX5E_PORT_AUI] = PORT_AUI,
817 [MLX5E_PORT_BNC] = PORT_BNC,
818 [MLX5E_PORT_MII] = PORT_MII,
819 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
820 [MLX5E_PORT_DA] = PORT_DA,
821 [MLX5E_PORT_OTHER] = PORT_OTHER,
824 static u8 get_connector_port(u32 eth_proto, u8 connector_type)
826 if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
827 return ptys2connector_type[connector_type];
830 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
831 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
832 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
833 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
838 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
839 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
840 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
845 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
846 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
847 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
848 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
855 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
856 struct ethtool_link_ksettings *link_ksettings)
858 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
859 bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
861 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext);
864 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
865 struct ethtool_link_ksettings *link_ksettings)
867 struct mlx5_core_dev *mdev = priv->mdev;
868 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
882 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
884 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
888 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
889 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
890 eth_proto_capability);
891 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
893 /* Fields: eth_proto_admin and ext_eth_proto_admin are
894 * mutually exclusive. Hence try reading legacy advertising
895 * when extended advertising is zero.
896 * admin_ext indicates how eth_proto_admin should be
900 if (ext && !eth_proto_admin) {
901 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false,
906 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
908 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
909 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
910 an_status = MLX5_GET(ptys_reg, out, an_status);
911 connector_type = MLX5_GET(ptys_reg, out, connector_type);
913 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
915 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
916 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
918 get_supported(mdev, eth_proto_cap, link_ksettings);
919 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings,
921 get_speed_duplex(priv->netdev, eth_proto_oper, link_ksettings);
923 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
925 link_ksettings->base.port = get_connector_port(eth_proto_oper,
927 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
929 get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
931 if (an_status == MLX5_AN_COMPLETE)
932 ethtool_link_ksettings_add_link_mode(link_ksettings,
933 lp_advertising, Autoneg);
935 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
937 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
940 err = get_fec_supported_advertised(mdev, link_ksettings);
942 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
944 err = 0; /* don't fail caps query because of FEC error */
947 if (!an_disable_admin)
948 ethtool_link_ksettings_add_link_mode(link_ksettings,
949 advertising, Autoneg);
955 static int mlx5e_get_link_ksettings(struct net_device *netdev,
956 struct ethtool_link_ksettings *link_ksettings)
958 struct mlx5e_priv *priv = netdev_priv(netdev);
960 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
963 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
965 u32 i, ptys_modes = 0;
967 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
968 if (*ptys2legacy_ethtool_table[i].advertised == 0)
970 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
972 __ETHTOOL_LINK_MODE_MASK_NBITS))
973 ptys_modes |= MLX5E_PROT_MASK(i);
979 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
981 u32 i, ptys_modes = 0;
982 unsigned long modes[2];
984 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
985 if (*ptys2ext_ethtool_table[i].advertised == 0)
987 memset(modes, 0, sizeof(modes));
988 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
989 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
991 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] &&
992 modes[1] == ptys2ext_ethtool_table[i].advertised[1])
993 ptys_modes |= MLX5E_PROT_MASK(i);
998 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
999 const struct ethtool_link_ksettings *link_ksettings)
1001 struct mlx5_core_dev *mdev = priv->mdev;
1002 struct mlx5e_port_eth_proto eproto;
1003 bool an_changes = false;
1004 u8 an_disable_admin;
1014 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
1016 #define MLX5E_PTYS_EXT ((1ULL << ETHTOOL_LINK_MODE_50000baseKR_Full_BIT) - 1)
1018 ext_requested = !!(link_ksettings->link_modes.advertising[0] >
1020 link_ksettings->link_modes.advertising[1]);
1021 ext_supported = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
1022 ext_requested &= ext_supported;
1024 speed = link_ksettings->base.speed;
1025 ethtool2ptys_adver_func = ext_requested ?
1026 mlx5e_ethtool2ptys_ext_adver_link :
1027 mlx5e_ethtool2ptys_adver_link;
1028 err = mlx5_port_query_eth_proto(mdev, 1, ext_requested, &eproto);
1030 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
1034 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
1035 ethtool2ptys_adver_func(link_ksettings->link_modes.advertising) :
1036 mlx5e_port_speed2linkmodes(mdev, speed);
1038 link_modes = link_modes & eproto.cap;
1040 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
1046 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1049 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
1050 an_changes = ((!an_disable && an_disable_admin) ||
1051 (an_disable && !an_disable_admin));
1053 if (!an_changes && link_modes == eproto.admin)
1056 mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext_requested);
1057 mlx5_toggle_port_link(mdev);
1063 static int mlx5e_set_link_ksettings(struct net_device *netdev,
1064 const struct ethtool_link_ksettings *link_ksettings)
1066 struct mlx5e_priv *priv = netdev_priv(netdev);
1068 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1071 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1073 return sizeof(priv->rss_params.toeplitz_hash_key);
1076 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1078 struct mlx5e_priv *priv = netdev_priv(netdev);
1080 return mlx5e_ethtool_get_rxfh_key_size(priv);
1083 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
1085 return MLX5E_INDIR_RQT_SIZE;
1088 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1090 struct mlx5e_priv *priv = netdev_priv(netdev);
1092 return mlx5e_ethtool_get_rxfh_indir_size(priv);
1095 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1098 struct mlx5e_priv *priv = netdev_priv(netdev);
1099 struct mlx5e_rss_params *rss = &priv->rss_params;
1102 memcpy(indir, rss->indirection_rqt,
1103 sizeof(rss->indirection_rqt));
1106 memcpy(key, rss->toeplitz_hash_key,
1107 sizeof(rss->toeplitz_hash_key));
1110 *hfunc = rss->hfunc;
1115 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
1116 const u8 *key, const u8 hfunc)
1118 struct mlx5e_priv *priv = netdev_priv(dev);
1119 struct mlx5e_rss_params *rss = &priv->rss_params;
1120 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1121 bool hash_changed = false;
1124 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1125 (hfunc != ETH_RSS_HASH_XOR) &&
1126 (hfunc != ETH_RSS_HASH_TOP))
1129 in = kvzalloc(inlen, GFP_KERNEL);
1133 mutex_lock(&priv->state_lock);
1135 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) {
1137 hash_changed = true;
1141 memcpy(rss->indirection_rqt, indir,
1142 sizeof(rss->indirection_rqt));
1144 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1145 u32 rqtn = priv->indir_rqt.rqtn;
1146 struct mlx5e_redirect_rqt_param rrp = {
1150 .hfunc = rss->hfunc,
1151 .channels = &priv->channels,
1156 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1161 memcpy(rss->toeplitz_hash_key, key,
1162 sizeof(rss->toeplitz_hash_key));
1163 hash_changed = hash_changed || rss->hfunc == ETH_RSS_HASH_TOP;
1167 mlx5e_modify_tirs_hash(priv, in, inlen);
1169 mutex_unlock(&priv->state_lock);
1176 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1177 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1178 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1179 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1180 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1181 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1182 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1184 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1185 u16 *pfc_prevention_tout)
1187 struct mlx5e_priv *priv = netdev_priv(netdev);
1188 struct mlx5_core_dev *mdev = priv->mdev;
1190 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1191 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1194 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1197 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1200 struct mlx5e_priv *priv = netdev_priv(netdev);
1201 struct mlx5_core_dev *mdev = priv->mdev;
1205 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1206 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1209 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1210 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1213 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1214 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1215 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1216 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1217 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1218 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1222 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1223 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1227 static int mlx5e_get_tunable(struct net_device *dev,
1228 const struct ethtool_tunable *tuna,
1234 case ETHTOOL_PFC_PREVENTION_TOUT:
1235 err = mlx5e_get_pfc_prevention_tout(dev, data);
1245 static int mlx5e_set_tunable(struct net_device *dev,
1246 const struct ethtool_tunable *tuna,
1249 struct mlx5e_priv *priv = netdev_priv(dev);
1252 mutex_lock(&priv->state_lock);
1255 case ETHTOOL_PFC_PREVENTION_TOUT:
1256 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1263 mutex_unlock(&priv->state_lock);
1267 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1268 struct ethtool_pauseparam *pauseparam)
1270 struct mlx5_core_dev *mdev = priv->mdev;
1273 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1274 &pauseparam->tx_pause);
1276 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1281 static void mlx5e_get_pauseparam(struct net_device *netdev,
1282 struct ethtool_pauseparam *pauseparam)
1284 struct mlx5e_priv *priv = netdev_priv(netdev);
1286 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1289 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1290 struct ethtool_pauseparam *pauseparam)
1292 struct mlx5_core_dev *mdev = priv->mdev;
1295 if (pauseparam->autoneg)
1298 err = mlx5_set_port_pause(mdev,
1299 pauseparam->rx_pause ? 1 : 0,
1300 pauseparam->tx_pause ? 1 : 0);
1302 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1309 static int mlx5e_set_pauseparam(struct net_device *netdev,
1310 struct ethtool_pauseparam *pauseparam)
1312 struct mlx5e_priv *priv = netdev_priv(netdev);
1314 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1317 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1318 struct ethtool_ts_info *info)
1320 struct mlx5_core_dev *mdev = priv->mdev;
1322 info->phc_index = mlx5_clock_get_ptp_index(mdev);
1324 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1325 info->phc_index == -1)
1328 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1329 SOF_TIMESTAMPING_RX_HARDWARE |
1330 SOF_TIMESTAMPING_RAW_HARDWARE;
1332 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1333 BIT(HWTSTAMP_TX_ON);
1335 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1336 BIT(HWTSTAMP_FILTER_ALL);
1341 static int mlx5e_get_ts_info(struct net_device *dev,
1342 struct ethtool_ts_info *info)
1344 struct mlx5e_priv *priv = netdev_priv(dev);
1346 return mlx5e_ethtool_get_ts_info(priv, info);
1349 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1353 if (MLX5_CAP_GEN(mdev, wol_g))
1356 if (MLX5_CAP_GEN(mdev, wol_s))
1357 ret |= WAKE_MAGICSECURE;
1359 if (MLX5_CAP_GEN(mdev, wol_a))
1362 if (MLX5_CAP_GEN(mdev, wol_b))
1365 if (MLX5_CAP_GEN(mdev, wol_m))
1368 if (MLX5_CAP_GEN(mdev, wol_u))
1371 if (MLX5_CAP_GEN(mdev, wol_p))
1377 static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1381 if (mode & MLX5_WOL_MAGIC)
1384 if (mode & MLX5_WOL_SECURED_MAGIC)
1385 ret |= WAKE_MAGICSECURE;
1387 if (mode & MLX5_WOL_ARP)
1390 if (mode & MLX5_WOL_BROADCAST)
1393 if (mode & MLX5_WOL_MULTICAST)
1396 if (mode & MLX5_WOL_UNICAST)
1399 if (mode & MLX5_WOL_PHY_ACTIVITY)
1405 static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1409 if (mode & WAKE_MAGIC)
1410 ret |= MLX5_WOL_MAGIC;
1412 if (mode & WAKE_MAGICSECURE)
1413 ret |= MLX5_WOL_SECURED_MAGIC;
1415 if (mode & WAKE_ARP)
1416 ret |= MLX5_WOL_ARP;
1418 if (mode & WAKE_BCAST)
1419 ret |= MLX5_WOL_BROADCAST;
1421 if (mode & WAKE_MCAST)
1422 ret |= MLX5_WOL_MULTICAST;
1424 if (mode & WAKE_UCAST)
1425 ret |= MLX5_WOL_UNICAST;
1427 if (mode & WAKE_PHY)
1428 ret |= MLX5_WOL_PHY_ACTIVITY;
1433 static void mlx5e_get_wol(struct net_device *netdev,
1434 struct ethtool_wolinfo *wol)
1436 struct mlx5e_priv *priv = netdev_priv(netdev);
1437 struct mlx5_core_dev *mdev = priv->mdev;
1441 memset(wol, 0, sizeof(*wol));
1443 wol->supported = mlx5e_get_wol_supported(mdev);
1444 if (!wol->supported)
1447 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1451 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1454 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1456 struct mlx5e_priv *priv = netdev_priv(netdev);
1457 struct mlx5_core_dev *mdev = priv->mdev;
1458 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1464 if (wol->wolopts & ~wol_supported)
1467 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1469 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1472 static int mlx5e_get_fecparam(struct net_device *netdev,
1473 struct ethtool_fecparam *fecparam)
1475 struct mlx5e_priv *priv = netdev_priv(netdev);
1476 struct mlx5_core_dev *mdev = priv->mdev;
1477 u8 fec_configured = 0;
1481 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1486 fecparam->active_fec = pplm2ethtool_fec((u_long)fec_active,
1487 sizeof(u32) * BITS_PER_BYTE);
1489 if (!fecparam->active_fec)
1492 fecparam->fec = pplm2ethtool_fec((u_long)fec_configured,
1493 sizeof(u8) * BITS_PER_BYTE);
1498 static int mlx5e_set_fecparam(struct net_device *netdev,
1499 struct ethtool_fecparam *fecparam)
1501 struct mlx5e_priv *priv = netdev_priv(netdev);
1502 struct mlx5_core_dev *mdev = priv->mdev;
1507 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1508 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1510 fec_policy |= (1 << mode);
1514 err = mlx5e_set_fec_mode(mdev, fec_policy);
1519 mlx5_toggle_port_link(mdev);
1524 static u32 mlx5e_get_msglevel(struct net_device *dev)
1526 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1529 static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1531 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1534 static int mlx5e_set_phys_id(struct net_device *dev,
1535 enum ethtool_phys_id_state state)
1537 struct mlx5e_priv *priv = netdev_priv(dev);
1538 struct mlx5_core_dev *mdev = priv->mdev;
1539 u16 beacon_duration;
1541 if (!MLX5_CAP_GEN(mdev, beacon_led))
1545 case ETHTOOL_ID_ACTIVE:
1546 beacon_duration = MLX5_BEACON_DURATION_INF;
1548 case ETHTOOL_ID_INACTIVE:
1549 beacon_duration = MLX5_BEACON_DURATION_OFF;
1555 return mlx5_set_port_beacon(mdev, beacon_duration);
1558 static int mlx5e_get_module_info(struct net_device *netdev,
1559 struct ethtool_modinfo *modinfo)
1561 struct mlx5e_priv *priv = netdev_priv(netdev);
1562 struct mlx5_core_dev *dev = priv->mdev;
1566 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1570 /* data[0] = identifier byte */
1572 case MLX5_MODULE_ID_QSFP:
1573 modinfo->type = ETH_MODULE_SFF_8436;
1574 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1576 case MLX5_MODULE_ID_QSFP_PLUS:
1577 case MLX5_MODULE_ID_QSFP28:
1578 /* data[1] = revision id */
1579 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1580 modinfo->type = ETH_MODULE_SFF_8636;
1581 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1583 modinfo->type = ETH_MODULE_SFF_8436;
1584 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1587 case MLX5_MODULE_ID_SFP:
1588 modinfo->type = ETH_MODULE_SFF_8472;
1589 modinfo->eeprom_len = MLX5_EEPROM_PAGE_LENGTH;
1592 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1600 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1601 struct ethtool_eeprom *ee,
1604 struct mlx5e_priv *priv = netdev_priv(netdev);
1605 struct mlx5_core_dev *mdev = priv->mdev;
1606 int offset = ee->offset;
1613 memset(data, 0, ee->len);
1615 while (i < ee->len) {
1616 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1623 if (size_read < 0) {
1624 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1625 __func__, size_read);
1630 offset += size_read;
1636 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1639 struct mlx5e_priv *priv = netdev_priv(netdev);
1640 struct mlx5_core_dev *mdev = priv->mdev;
1641 struct mlx5e_channels new_channels = {};
1643 u8 cq_period_mode, current_cq_period_mode;
1645 cq_period_mode = enable ?
1646 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1647 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1648 current_cq_period_mode = is_rx_cq ?
1649 priv->channels.params.rx_cq_moderation.cq_period_mode :
1650 priv->channels.params.tx_cq_moderation.cq_period_mode;
1651 mode_changed = cq_period_mode != current_cq_period_mode;
1653 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1654 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1660 new_channels.params = priv->channels.params;
1662 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1664 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
1666 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1667 priv->channels.params = new_channels.params;
1671 return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
1674 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1676 return set_pflag_cqe_based_moder(netdev, enable, false);
1679 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1681 return set_pflag_cqe_based_moder(netdev, enable, true);
1684 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1686 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1687 struct mlx5e_channels new_channels = {};
1690 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1691 return new_val ? -EOPNOTSUPP : 0;
1693 if (curr_val == new_val)
1696 new_channels.params = priv->channels.params;
1697 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1699 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1700 priv->channels.params = new_channels.params;
1704 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
1708 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1709 MLX5E_GET_PFLAG(&priv->channels.params,
1710 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1715 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1718 struct mlx5e_priv *priv = netdev_priv(netdev);
1719 struct mlx5_core_dev *mdev = priv->mdev;
1721 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1724 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
1725 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1729 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
1730 priv->channels.params.rx_cqe_compress_def = enable;
1735 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1737 struct mlx5e_priv *priv = netdev_priv(netdev);
1738 struct mlx5_core_dev *mdev = priv->mdev;
1739 struct mlx5e_channels new_channels = {};
1742 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1744 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1746 } else if (priv->channels.params.lro_en) {
1747 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n");
1751 new_channels.params = priv->channels.params;
1753 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1754 mlx5e_set_rq_type(mdev, &new_channels.params);
1756 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1757 priv->channels.params = new_channels.params;
1761 return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
1764 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
1766 struct mlx5e_priv *priv = netdev_priv(netdev);
1767 struct mlx5e_channels *channels = &priv->channels;
1768 struct mlx5e_channel *c;
1771 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) ||
1772 priv->channels.params.xdp_prog)
1775 for (i = 0; i < channels->num; i++) {
1778 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1780 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1786 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
1788 struct mlx5e_priv *priv = netdev_priv(netdev);
1789 struct mlx5_core_dev *mdev = priv->mdev;
1790 struct mlx5e_channels new_channels = {};
1793 if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1796 new_channels.params = priv->channels.params;
1798 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
1800 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1801 priv->channels.params = new_channels.params;
1805 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
1809 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
1810 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
1811 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
1812 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
1813 { "rx_striding_rq", set_pflag_rx_striding_rq },
1814 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
1815 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
1818 static int mlx5e_handle_pflag(struct net_device *netdev,
1820 enum mlx5e_priv_flag flag)
1822 struct mlx5e_priv *priv = netdev_priv(netdev);
1823 bool enable = !!(wanted_flags & BIT(flag));
1824 u32 changes = wanted_flags ^ priv->channels.params.pflags;
1827 if (!(changes & BIT(flag)))
1830 err = mlx5e_priv_flags[flag].handler(netdev, enable);
1832 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
1833 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
1837 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
1841 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1843 struct mlx5e_priv *priv = netdev_priv(netdev);
1844 enum mlx5e_priv_flag pflag;
1847 mutex_lock(&priv->state_lock);
1849 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
1850 err = mlx5e_handle_pflag(netdev, pflags, pflag);
1855 mutex_unlock(&priv->state_lock);
1857 /* Need to fix some features.. */
1858 netdev_update_features(netdev);
1863 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1865 struct mlx5e_priv *priv = netdev_priv(netdev);
1867 return priv->channels.params.pflags;
1870 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1871 struct ethtool_flash *flash)
1873 struct mlx5_core_dev *mdev = priv->mdev;
1874 struct net_device *dev = priv->netdev;
1875 const struct firmware *fw;
1878 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1881 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1888 err = mlx5_firmware_flash(mdev, fw);
1889 release_firmware(fw);
1896 static int mlx5e_flash_device(struct net_device *dev,
1897 struct ethtool_flash *flash)
1899 struct mlx5e_priv *priv = netdev_priv(dev);
1901 return mlx5e_ethtool_flash_device(priv, flash);
1904 const struct ethtool_ops mlx5e_ethtool_ops = {
1905 .get_drvinfo = mlx5e_get_drvinfo,
1906 .get_link = ethtool_op_get_link,
1907 .get_strings = mlx5e_get_strings,
1908 .get_sset_count = mlx5e_get_sset_count,
1909 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1910 .get_ringparam = mlx5e_get_ringparam,
1911 .set_ringparam = mlx5e_set_ringparam,
1912 .get_channels = mlx5e_get_channels,
1913 .set_channels = mlx5e_set_channels,
1914 .get_coalesce = mlx5e_get_coalesce,
1915 .set_coalesce = mlx5e_set_coalesce,
1916 .get_link_ksettings = mlx5e_get_link_ksettings,
1917 .set_link_ksettings = mlx5e_set_link_ksettings,
1918 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1919 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1920 .get_rxfh = mlx5e_get_rxfh,
1921 .set_rxfh = mlx5e_set_rxfh,
1922 #ifdef CONFIG_MLX5_EN_RXNFC
1923 .get_rxnfc = mlx5e_get_rxnfc,
1924 .set_rxnfc = mlx5e_set_rxnfc,
1926 .flash_device = mlx5e_flash_device,
1927 .get_tunable = mlx5e_get_tunable,
1928 .set_tunable = mlx5e_set_tunable,
1929 .get_pauseparam = mlx5e_get_pauseparam,
1930 .set_pauseparam = mlx5e_set_pauseparam,
1931 .get_ts_info = mlx5e_get_ts_info,
1932 .set_phys_id = mlx5e_set_phys_id,
1933 .get_wol = mlx5e_get_wol,
1934 .set_wol = mlx5e_set_wol,
1935 .get_module_info = mlx5e_get_module_info,
1936 .get_module_eeprom = mlx5e_get_module_eeprom,
1937 .get_priv_flags = mlx5e_get_priv_flags,
1938 .set_priv_flags = mlx5e_set_priv_flags,
1939 .self_test = mlx5e_self_test,
1940 .get_msglevel = mlx5e_get_msglevel,
1941 .set_msglevel = mlx5e_set_msglevel,
1942 .get_fecparam = mlx5e_get_fecparam,
1943 .set_fecparam = mlx5e_set_fecparam,