2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "lib/clock.h"
37 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
38 struct ethtool_drvinfo *drvinfo)
40 struct mlx5_core_dev *mdev = priv->mdev;
42 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
43 strlcpy(drvinfo->version, DRIVER_VERSION,
44 sizeof(drvinfo->version));
45 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
47 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
49 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
50 sizeof(drvinfo->bus_info));
53 static void mlx5e_get_drvinfo(struct net_device *dev,
54 struct ethtool_drvinfo *drvinfo)
56 struct mlx5e_priv *priv = netdev_priv(dev);
58 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
61 struct ptys2ethtool_config {
62 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
63 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
66 static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
68 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, ...) \
70 struct ptys2ethtool_config *cfg; \
71 const unsigned int modes[] = { __VA_ARGS__ }; \
73 cfg = &ptys2ethtool_table[reg_]; \
74 bitmap_zero(cfg->supported, \
75 __ETHTOOL_LINK_MODE_MASK_NBITS); \
76 bitmap_zero(cfg->advertised, \
77 __ETHTOOL_LINK_MODE_MASK_NBITS); \
78 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
79 __set_bit(modes[i], cfg->supported); \
80 __set_bit(modes[i], cfg->advertised); \
84 void mlx5e_build_ptys2ethtool_map(void)
86 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII,
87 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
88 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX,
89 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
90 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4,
91 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
92 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4,
93 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR,
95 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2,
97 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4,
99 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4,
101 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4,
103 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR,
105 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR,
107 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER,
109 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4,
111 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4,
113 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2,
115 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4,
117 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4,
119 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4,
121 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4,
123 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T,
125 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR,
127 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
128 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR,
129 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
130 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR,
131 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
132 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2,
133 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
134 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2,
135 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
138 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
143 "rx_no_csum_complete",
146 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
148 int i, num_stats = 0;
152 for (i = 0; i < mlx5e_num_stats_grps; i++)
153 num_stats += mlx5e_stats_grps[i].get_num_stats(priv);
155 case ETH_SS_PRIV_FLAGS:
156 return ARRAY_SIZE(mlx5e_priv_flags);
158 return mlx5e_self_test_num(priv);
165 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
167 struct mlx5e_priv *priv = netdev_priv(dev);
169 return mlx5e_ethtool_get_sset_count(priv, sset);
172 static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, u8 *data)
176 for (i = 0; i < mlx5e_num_stats_grps; i++)
177 idx = mlx5e_stats_grps[i].fill_strings(priv, data, idx);
180 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
185 case ETH_SS_PRIV_FLAGS:
186 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
187 strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
191 for (i = 0; i < mlx5e_self_test_num(priv); i++)
192 strcpy(data + i * ETH_GSTRING_LEN,
193 mlx5e_self_tests[i]);
197 mlx5e_fill_stats_strings(priv, data);
202 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
204 struct mlx5e_priv *priv = netdev_priv(dev);
206 mlx5e_ethtool_get_strings(priv, stringset, data);
209 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
210 struct ethtool_stats *stats, u64 *data)
214 mutex_lock(&priv->state_lock);
215 mlx5e_update_stats(priv);
216 mutex_unlock(&priv->state_lock);
218 for (i = 0; i < mlx5e_num_stats_grps; i++)
219 idx = mlx5e_stats_grps[i].fill_stats(priv, data, idx);
222 static void mlx5e_get_ethtool_stats(struct net_device *dev,
223 struct ethtool_stats *stats,
226 struct mlx5e_priv *priv = netdev_priv(dev);
228 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
231 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
232 struct ethtool_ringparam *param)
234 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
235 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
236 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
237 param->tx_pending = 1 << priv->channels.params.log_sq_size;
240 static void mlx5e_get_ringparam(struct net_device *dev,
241 struct ethtool_ringparam *param)
243 struct mlx5e_priv *priv = netdev_priv(dev);
245 mlx5e_ethtool_get_ringparam(priv, param);
248 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
249 struct ethtool_ringparam *param)
251 struct mlx5e_channels new_channels = {};
256 if (param->rx_jumbo_pending) {
257 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
261 if (param->rx_mini_pending) {
262 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
267 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
268 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
269 __func__, param->rx_pending,
270 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
274 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
275 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
276 __func__, param->tx_pending,
277 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
281 log_rq_size = order_base_2(param->rx_pending);
282 log_sq_size = order_base_2(param->tx_pending);
284 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
285 log_sq_size == priv->channels.params.log_sq_size)
288 mutex_lock(&priv->state_lock);
290 new_channels.params = priv->channels.params;
291 new_channels.params.log_rq_mtu_frames = log_rq_size;
292 new_channels.params.log_sq_size = log_sq_size;
294 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
295 priv->channels.params = new_channels.params;
299 err = mlx5e_open_channels(priv, &new_channels);
303 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
306 mutex_unlock(&priv->state_lock);
311 static int mlx5e_set_ringparam(struct net_device *dev,
312 struct ethtool_ringparam *param)
314 struct mlx5e_priv *priv = netdev_priv(dev);
316 return mlx5e_ethtool_set_ringparam(priv, param);
319 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
320 struct ethtool_channels *ch)
322 ch->max_combined = mlx5e_get_netdev_max_channels(priv->netdev);
323 ch->combined_count = priv->channels.params.num_channels;
326 static void mlx5e_get_channels(struct net_device *dev,
327 struct ethtool_channels *ch)
329 struct mlx5e_priv *priv = netdev_priv(dev);
331 mlx5e_ethtool_get_channels(priv, ch);
334 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
335 struct ethtool_channels *ch)
337 unsigned int count = ch->combined_count;
338 struct mlx5e_channels new_channels = {};
343 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
348 if (priv->channels.params.num_channels == count)
351 mutex_lock(&priv->state_lock);
353 new_channels.params = priv->channels.params;
354 new_channels.params.num_channels = count;
355 if (!netif_is_rxfh_configured(priv->netdev))
356 mlx5e_build_default_indir_rqt(new_channels.params.indirection_rqt,
357 MLX5E_INDIR_RQT_SIZE, count);
359 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
360 priv->channels.params = new_channels.params;
364 /* Create fresh channels with new parameters */
365 err = mlx5e_open_channels(priv, &new_channels);
369 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
371 mlx5e_arfs_disable(priv);
373 /* Switch to new channels, set new parameters and close old ones */
374 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
377 err = mlx5e_arfs_enable(priv);
379 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
384 mutex_unlock(&priv->state_lock);
389 static int mlx5e_set_channels(struct net_device *dev,
390 struct ethtool_channels *ch)
392 struct mlx5e_priv *priv = netdev_priv(dev);
394 return mlx5e_ethtool_set_channels(priv, ch);
397 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
398 struct ethtool_coalesce *coal)
400 struct net_dim_cq_moder *rx_moder, *tx_moder;
402 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
405 rx_moder = &priv->channels.params.rx_cq_moderation;
406 coal->rx_coalesce_usecs = rx_moder->usec;
407 coal->rx_max_coalesced_frames = rx_moder->pkts;
408 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
410 tx_moder = &priv->channels.params.tx_cq_moderation;
411 coal->tx_coalesce_usecs = tx_moder->usec;
412 coal->tx_max_coalesced_frames = tx_moder->pkts;
413 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
418 static int mlx5e_get_coalesce(struct net_device *netdev,
419 struct ethtool_coalesce *coal)
421 struct mlx5e_priv *priv = netdev_priv(netdev);
423 return mlx5e_ethtool_get_coalesce(priv, coal);
426 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
427 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
430 mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
432 struct mlx5_core_dev *mdev = priv->mdev;
436 for (i = 0; i < priv->channels.num; ++i) {
437 struct mlx5e_channel *c = priv->channels.c[i];
439 for (tc = 0; tc < c->num_tc; tc++) {
440 mlx5_core_modify_cq_moderation(mdev,
442 coal->tx_coalesce_usecs,
443 coal->tx_max_coalesced_frames);
446 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
447 coal->rx_coalesce_usecs,
448 coal->rx_max_coalesced_frames);
452 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
453 struct ethtool_coalesce *coal)
455 struct net_dim_cq_moder *rx_moder, *tx_moder;
456 struct mlx5_core_dev *mdev = priv->mdev;
457 struct mlx5e_channels new_channels = {};
461 if (!MLX5_CAP_GEN(mdev, cq_moderation))
464 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
465 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
466 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
467 __func__, MLX5E_MAX_COAL_TIME);
471 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
472 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
473 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
474 __func__, MLX5E_MAX_COAL_FRAMES);
478 mutex_lock(&priv->state_lock);
479 new_channels.params = priv->channels.params;
481 rx_moder = &new_channels.params.rx_cq_moderation;
482 rx_moder->usec = coal->rx_coalesce_usecs;
483 rx_moder->pkts = coal->rx_max_coalesced_frames;
484 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
486 tx_moder = &new_channels.params.tx_cq_moderation;
487 tx_moder->usec = coal->tx_coalesce_usecs;
488 tx_moder->pkts = coal->tx_max_coalesced_frames;
489 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
491 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
492 priv->channels.params = new_channels.params;
497 reset = (!!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled) ||
498 (!!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled);
501 mlx5e_set_priv_channels_coalesce(priv, coal);
502 priv->channels.params = new_channels.params;
506 /* open fresh channels with new coal parameters */
507 err = mlx5e_open_channels(priv, &new_channels);
511 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
514 mutex_unlock(&priv->state_lock);
518 static int mlx5e_set_coalesce(struct net_device *netdev,
519 struct ethtool_coalesce *coal)
521 struct mlx5e_priv *priv = netdev_priv(netdev);
523 return mlx5e_ethtool_set_coalesce(priv, coal);
526 static void ptys2ethtool_supported_link(unsigned long *supported_modes,
529 unsigned long proto_cap = eth_proto_cap;
532 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
533 bitmap_or(supported_modes, supported_modes,
534 ptys2ethtool_table[proto].supported,
535 __ETHTOOL_LINK_MODE_MASK_NBITS);
538 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
541 unsigned long proto_cap = eth_proto_cap;
544 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
545 bitmap_or(advertising_modes, advertising_modes,
546 ptys2ethtool_table[proto].advertised,
547 __ETHTOOL_LINK_MODE_MASK_NBITS);
550 static const u32 pplm_fec_2_ethtool[] = {
551 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
552 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
553 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
556 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
561 return ETHTOOL_FEC_AUTO;
563 mode = find_first_bit(&fec_mode, size);
565 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
566 return pplm_fec_2_ethtool[mode];
571 /* we use ETHTOOL_FEC_* offset and apply it to ETHTOOL_LINK_MODE_FEC_*_BIT */
572 static u32 ethtool_fec2ethtool_caps(u_long ethtool_fec_code)
576 offset = find_first_bit(ðtool_fec_code, sizeof(u32));
577 offset -= ETHTOOL_FEC_OFF_BIT;
578 offset += ETHTOOL_LINK_MODE_FEC_NONE_BIT;
583 static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
584 struct ethtool_link_ksettings *link_ksettings)
592 err = mlx5e_get_fec_caps(dev, (u8 *)&fec_caps);
594 return (err == -EOPNOTSUPP) ? 0 : err;
596 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
600 for_each_set_bit(bitn, &fec_caps, ARRAY_SIZE(pplm_fec_2_ethtool)) {
601 u_long ethtool_bitmask = pplm_fec_2_ethtool[bitn];
603 offset = ethtool_fec2ethtool_caps(ethtool_bitmask);
604 __set_bit(offset, link_ksettings->link_modes.supported);
607 active_fec = pplm2ethtool_fec(active_fec, sizeof(u32) * BITS_PER_BYTE);
608 offset = ethtool_fec2ethtool_caps(active_fec);
609 __set_bit(offset, link_ksettings->link_modes.advertising);
614 static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
618 if (!connector_type || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
619 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
620 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
621 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
622 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
623 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
624 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
625 ethtool_link_ksettings_add_link_mode(link_ksettings,
628 ethtool_link_ksettings_add_link_mode(link_ksettings,
633 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
634 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
635 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
636 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
637 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
638 ethtool_link_ksettings_add_link_mode(link_ksettings,
641 ethtool_link_ksettings_add_link_mode(link_ksettings,
648 switch (connector_type) {
650 ethtool_link_ksettings_add_link_mode(link_ksettings,
652 ethtool_link_ksettings_add_link_mode(link_ksettings,
656 ethtool_link_ksettings_add_link_mode(link_ksettings,
658 ethtool_link_ksettings_add_link_mode(link_ksettings,
662 ethtool_link_ksettings_add_link_mode(link_ksettings,
664 ethtool_link_ksettings_add_link_mode(link_ksettings,
668 ethtool_link_ksettings_add_link_mode(link_ksettings,
670 ethtool_link_ksettings_add_link_mode(link_ksettings,
673 case MLX5E_PORT_FIBRE:
674 ethtool_link_ksettings_add_link_mode(link_ksettings,
676 ethtool_link_ksettings_add_link_mode(link_ksettings,
680 ethtool_link_ksettings_add_link_mode(link_ksettings,
681 supported, Backplane);
682 ethtool_link_ksettings_add_link_mode(link_ksettings,
683 advertising, Backplane);
685 case MLX5E_PORT_NONE:
686 case MLX5E_PORT_OTHER:
692 static void get_speed_duplex(struct net_device *netdev,
694 struct ethtool_link_ksettings *link_ksettings)
696 u32 speed = SPEED_UNKNOWN;
697 u8 duplex = DUPLEX_UNKNOWN;
699 if (!netif_carrier_ok(netdev))
702 speed = mlx5e_port_ptys2speed(eth_proto_oper);
704 speed = SPEED_UNKNOWN;
708 duplex = DUPLEX_FULL;
711 link_ksettings->base.speed = speed;
712 link_ksettings->base.duplex = duplex;
715 static void get_supported(u32 eth_proto_cap,
716 struct ethtool_link_ksettings *link_ksettings)
718 unsigned long *supported = link_ksettings->link_modes.supported;
720 ptys2ethtool_supported_link(supported, eth_proto_cap);
721 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
724 static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
726 struct ethtool_link_ksettings *link_ksettings)
728 unsigned long *advertising = link_ksettings->link_modes.advertising;
730 ptys2ethtool_adver_link(advertising, eth_proto_cap);
732 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
733 if (tx_pause ^ rx_pause)
734 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
737 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
738 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
739 [MLX5E_PORT_NONE] = PORT_NONE,
740 [MLX5E_PORT_TP] = PORT_TP,
741 [MLX5E_PORT_AUI] = PORT_AUI,
742 [MLX5E_PORT_BNC] = PORT_BNC,
743 [MLX5E_PORT_MII] = PORT_MII,
744 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
745 [MLX5E_PORT_DA] = PORT_DA,
746 [MLX5E_PORT_OTHER] = PORT_OTHER,
749 static u8 get_connector_port(u32 eth_proto, u8 connector_type)
751 if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
752 return ptys2connector_type[connector_type];
755 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
756 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
757 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
758 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
763 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
764 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
765 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
770 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
771 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
772 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
773 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
780 static void get_lp_advertising(u32 eth_proto_lp,
781 struct ethtool_link_ksettings *link_ksettings)
783 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
785 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
788 static int mlx5e_get_link_ksettings(struct net_device *netdev,
789 struct ethtool_link_ksettings *link_ksettings)
791 struct mlx5e_priv *priv = netdev_priv(netdev);
792 struct mlx5_core_dev *mdev = priv->mdev;
793 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
805 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
807 netdev_err(netdev, "%s: query port ptys failed: %d\n",
812 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
813 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
814 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
815 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
816 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
817 an_status = MLX5_GET(ptys_reg, out, an_status);
818 connector_type = MLX5_GET(ptys_reg, out, connector_type);
820 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
822 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
823 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
825 get_supported(eth_proto_cap, link_ksettings);
826 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings);
827 get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
829 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
831 link_ksettings->base.port = get_connector_port(eth_proto_oper,
833 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
835 get_lp_advertising(eth_proto_lp, link_ksettings);
837 if (an_status == MLX5_AN_COMPLETE)
838 ethtool_link_ksettings_add_link_mode(link_ksettings,
839 lp_advertising, Autoneg);
841 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
843 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
846 err = get_fec_supported_advertised(mdev, link_ksettings);
848 netdev_dbg(netdev, "%s: FEC caps query failed: %d\n",
851 if (!an_disable_admin)
852 ethtool_link_ksettings_add_link_mode(link_ksettings,
853 advertising, Autoneg);
859 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
861 u32 i, ptys_modes = 0;
863 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
864 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
866 __ETHTOOL_LINK_MODE_MASK_NBITS))
867 ptys_modes |= MLX5E_PROT_MASK(i);
873 static int mlx5e_set_link_ksettings(struct net_device *netdev,
874 const struct ethtool_link_ksettings *link_ksettings)
876 struct mlx5e_priv *priv = netdev_priv(netdev);
877 struct mlx5_core_dev *mdev = priv->mdev;
878 u32 eth_proto_cap, eth_proto_admin;
879 bool an_changes = false;
888 speed = link_ksettings->base.speed;
890 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
891 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
892 mlx5e_port_speed2linkmodes(speed);
894 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
896 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
901 link_modes = link_modes & eth_proto_cap;
903 netdev_err(netdev, "%s: Not supported link mode(s) requested",
909 err = mlx5_query_port_proto_admin(mdev, ð_proto_admin, MLX5_PTYS_EN);
911 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
916 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
917 &an_disable_cap, &an_disable_admin);
919 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
920 an_changes = ((!an_disable && an_disable_admin) ||
921 (an_disable && !an_disable_admin));
923 if (!an_changes && link_modes == eth_proto_admin)
926 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
927 mlx5_toggle_port_link(mdev);
933 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
935 return sizeof(priv->channels.params.toeplitz_hash_key);
938 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
940 struct mlx5e_priv *priv = netdev_priv(netdev);
942 return mlx5e_ethtool_get_rxfh_key_size(priv);
945 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
947 return MLX5E_INDIR_RQT_SIZE;
950 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
952 struct mlx5e_priv *priv = netdev_priv(netdev);
954 return mlx5e_ethtool_get_rxfh_indir_size(priv);
957 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
960 struct mlx5e_priv *priv = netdev_priv(netdev);
963 memcpy(indir, priv->channels.params.indirection_rqt,
964 sizeof(priv->channels.params.indirection_rqt));
967 memcpy(key, priv->channels.params.toeplitz_hash_key,
968 sizeof(priv->channels.params.toeplitz_hash_key));
971 *hfunc = priv->channels.params.rss_hfunc;
976 static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
978 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
979 struct mlx5_core_dev *mdev = priv->mdev;
980 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
983 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
985 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
986 memset(tirc, 0, ctxlen);
987 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
988 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
991 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
994 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
995 memset(tirc, 0, ctxlen);
996 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
997 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in, inlen);
1001 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
1002 const u8 *key, const u8 hfunc)
1004 struct mlx5e_priv *priv = netdev_priv(dev);
1005 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1006 bool hash_changed = false;
1009 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1010 (hfunc != ETH_RSS_HASH_XOR) &&
1011 (hfunc != ETH_RSS_HASH_TOP))
1014 in = kvzalloc(inlen, GFP_KERNEL);
1018 mutex_lock(&priv->state_lock);
1020 if (hfunc != ETH_RSS_HASH_NO_CHANGE &&
1021 hfunc != priv->channels.params.rss_hfunc) {
1022 priv->channels.params.rss_hfunc = hfunc;
1023 hash_changed = true;
1027 memcpy(priv->channels.params.indirection_rqt, indir,
1028 sizeof(priv->channels.params.indirection_rqt));
1030 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1031 u32 rqtn = priv->indir_rqt.rqtn;
1032 struct mlx5e_redirect_rqt_param rrp = {
1036 .hfunc = priv->channels.params.rss_hfunc,
1037 .channels = &priv->channels,
1042 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1047 memcpy(priv->channels.params.toeplitz_hash_key, key,
1048 sizeof(priv->channels.params.toeplitz_hash_key));
1049 hash_changed = hash_changed ||
1050 priv->channels.params.rss_hfunc == ETH_RSS_HASH_TOP;
1054 mlx5e_modify_tirs_hash(priv, in, inlen);
1056 mutex_unlock(&priv->state_lock);
1063 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1064 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1065 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1066 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1067 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1068 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1069 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1071 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1072 u16 *pfc_prevention_tout)
1074 struct mlx5e_priv *priv = netdev_priv(netdev);
1075 struct mlx5_core_dev *mdev = priv->mdev;
1077 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1078 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1081 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1084 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1087 struct mlx5e_priv *priv = netdev_priv(netdev);
1088 struct mlx5_core_dev *mdev = priv->mdev;
1092 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1093 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1096 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1097 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1100 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1101 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1102 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1103 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1104 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1105 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1109 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1110 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1114 static int mlx5e_get_tunable(struct net_device *dev,
1115 const struct ethtool_tunable *tuna,
1121 case ETHTOOL_PFC_PREVENTION_TOUT:
1122 err = mlx5e_get_pfc_prevention_tout(dev, data);
1132 static int mlx5e_set_tunable(struct net_device *dev,
1133 const struct ethtool_tunable *tuna,
1136 struct mlx5e_priv *priv = netdev_priv(dev);
1139 mutex_lock(&priv->state_lock);
1142 case ETHTOOL_PFC_PREVENTION_TOUT:
1143 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1150 mutex_unlock(&priv->state_lock);
1154 static void mlx5e_get_pauseparam(struct net_device *netdev,
1155 struct ethtool_pauseparam *pauseparam)
1157 struct mlx5e_priv *priv = netdev_priv(netdev);
1158 struct mlx5_core_dev *mdev = priv->mdev;
1161 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1162 &pauseparam->tx_pause);
1164 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1169 static int mlx5e_set_pauseparam(struct net_device *netdev,
1170 struct ethtool_pauseparam *pauseparam)
1172 struct mlx5e_priv *priv = netdev_priv(netdev);
1173 struct mlx5_core_dev *mdev = priv->mdev;
1176 if (pauseparam->autoneg)
1179 err = mlx5_set_port_pause(mdev,
1180 pauseparam->rx_pause ? 1 : 0,
1181 pauseparam->tx_pause ? 1 : 0);
1183 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1190 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1191 struct ethtool_ts_info *info)
1193 struct mlx5_core_dev *mdev = priv->mdev;
1196 ret = ethtool_op_get_ts_info(priv->netdev, info);
1200 info->phc_index = mlx5_clock_get_ptp_index(mdev);
1202 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1203 info->phc_index == -1)
1206 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1207 SOF_TIMESTAMPING_RX_HARDWARE |
1208 SOF_TIMESTAMPING_RAW_HARDWARE;
1210 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1211 BIT(HWTSTAMP_TX_ON);
1213 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1214 BIT(HWTSTAMP_FILTER_ALL);
1219 static int mlx5e_get_ts_info(struct net_device *dev,
1220 struct ethtool_ts_info *info)
1222 struct mlx5e_priv *priv = netdev_priv(dev);
1224 return mlx5e_ethtool_get_ts_info(priv, info);
1227 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1231 if (MLX5_CAP_GEN(mdev, wol_g))
1234 if (MLX5_CAP_GEN(mdev, wol_s))
1235 ret |= WAKE_MAGICSECURE;
1237 if (MLX5_CAP_GEN(mdev, wol_a))
1240 if (MLX5_CAP_GEN(mdev, wol_b))
1243 if (MLX5_CAP_GEN(mdev, wol_m))
1246 if (MLX5_CAP_GEN(mdev, wol_u))
1249 if (MLX5_CAP_GEN(mdev, wol_p))
1255 static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1259 if (mode & MLX5_WOL_MAGIC)
1262 if (mode & MLX5_WOL_SECURED_MAGIC)
1263 ret |= WAKE_MAGICSECURE;
1265 if (mode & MLX5_WOL_ARP)
1268 if (mode & MLX5_WOL_BROADCAST)
1271 if (mode & MLX5_WOL_MULTICAST)
1274 if (mode & MLX5_WOL_UNICAST)
1277 if (mode & MLX5_WOL_PHY_ACTIVITY)
1283 static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1287 if (mode & WAKE_MAGIC)
1288 ret |= MLX5_WOL_MAGIC;
1290 if (mode & WAKE_MAGICSECURE)
1291 ret |= MLX5_WOL_SECURED_MAGIC;
1293 if (mode & WAKE_ARP)
1294 ret |= MLX5_WOL_ARP;
1296 if (mode & WAKE_BCAST)
1297 ret |= MLX5_WOL_BROADCAST;
1299 if (mode & WAKE_MCAST)
1300 ret |= MLX5_WOL_MULTICAST;
1302 if (mode & WAKE_UCAST)
1303 ret |= MLX5_WOL_UNICAST;
1305 if (mode & WAKE_PHY)
1306 ret |= MLX5_WOL_PHY_ACTIVITY;
1311 static void mlx5e_get_wol(struct net_device *netdev,
1312 struct ethtool_wolinfo *wol)
1314 struct mlx5e_priv *priv = netdev_priv(netdev);
1315 struct mlx5_core_dev *mdev = priv->mdev;
1319 memset(wol, 0, sizeof(*wol));
1321 wol->supported = mlx5e_get_wol_supported(mdev);
1322 if (!wol->supported)
1325 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1329 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1332 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1334 struct mlx5e_priv *priv = netdev_priv(netdev);
1335 struct mlx5_core_dev *mdev = priv->mdev;
1336 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1342 if (wol->wolopts & ~wol_supported)
1345 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1347 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1350 static int mlx5e_get_fecparam(struct net_device *netdev,
1351 struct ethtool_fecparam *fecparam)
1353 struct mlx5e_priv *priv = netdev_priv(netdev);
1354 struct mlx5_core_dev *mdev = priv->mdev;
1355 u8 fec_configured = 0;
1359 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1364 fecparam->active_fec = pplm2ethtool_fec((u_long)fec_active,
1365 sizeof(u32) * BITS_PER_BYTE);
1367 if (!fecparam->active_fec)
1370 fecparam->fec = pplm2ethtool_fec((u_long)fec_configured,
1371 sizeof(u8) * BITS_PER_BYTE);
1376 static int mlx5e_set_fecparam(struct net_device *netdev,
1377 struct ethtool_fecparam *fecparam)
1379 struct mlx5e_priv *priv = netdev_priv(netdev);
1380 struct mlx5_core_dev *mdev = priv->mdev;
1385 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1386 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1388 fec_policy |= (1 << mode);
1392 err = mlx5e_set_fec_mode(mdev, fec_policy);
1397 mlx5_toggle_port_link(mdev);
1402 static u32 mlx5e_get_msglevel(struct net_device *dev)
1404 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1407 static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1409 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1412 static int mlx5e_set_phys_id(struct net_device *dev,
1413 enum ethtool_phys_id_state state)
1415 struct mlx5e_priv *priv = netdev_priv(dev);
1416 struct mlx5_core_dev *mdev = priv->mdev;
1417 u16 beacon_duration;
1419 if (!MLX5_CAP_GEN(mdev, beacon_led))
1423 case ETHTOOL_ID_ACTIVE:
1424 beacon_duration = MLX5_BEACON_DURATION_INF;
1426 case ETHTOOL_ID_INACTIVE:
1427 beacon_duration = MLX5_BEACON_DURATION_OFF;
1433 return mlx5_set_port_beacon(mdev, beacon_duration);
1436 static int mlx5e_get_module_info(struct net_device *netdev,
1437 struct ethtool_modinfo *modinfo)
1439 struct mlx5e_priv *priv = netdev_priv(netdev);
1440 struct mlx5_core_dev *dev = priv->mdev;
1444 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1448 /* data[0] = identifier byte */
1450 case MLX5_MODULE_ID_QSFP:
1451 modinfo->type = ETH_MODULE_SFF_8436;
1452 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1454 case MLX5_MODULE_ID_QSFP_PLUS:
1455 case MLX5_MODULE_ID_QSFP28:
1456 /* data[1] = revision id */
1457 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1458 modinfo->type = ETH_MODULE_SFF_8636;
1459 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1461 modinfo->type = ETH_MODULE_SFF_8436;
1462 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1465 case MLX5_MODULE_ID_SFP:
1466 modinfo->type = ETH_MODULE_SFF_8472;
1467 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1470 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1478 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1479 struct ethtool_eeprom *ee,
1482 struct mlx5e_priv *priv = netdev_priv(netdev);
1483 struct mlx5_core_dev *mdev = priv->mdev;
1484 int offset = ee->offset;
1491 memset(data, 0, ee->len);
1493 while (i < ee->len) {
1494 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1501 if (size_read < 0) {
1502 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1503 __func__, size_read);
1508 offset += size_read;
1514 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1516 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1519 struct mlx5e_priv *priv = netdev_priv(netdev);
1520 struct mlx5_core_dev *mdev = priv->mdev;
1521 struct mlx5e_channels new_channels = {};
1523 u8 cq_period_mode, current_cq_period_mode;
1526 cq_period_mode = enable ?
1527 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1528 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1529 current_cq_period_mode = is_rx_cq ?
1530 priv->channels.params.rx_cq_moderation.cq_period_mode :
1531 priv->channels.params.tx_cq_moderation.cq_period_mode;
1532 mode_changed = cq_period_mode != current_cq_period_mode;
1534 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1535 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1541 new_channels.params = priv->channels.params;
1543 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1545 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
1547 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1548 priv->channels.params = new_channels.params;
1552 err = mlx5e_open_channels(priv, &new_channels);
1556 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1560 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1562 return set_pflag_cqe_based_moder(netdev, enable, false);
1565 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1567 return set_pflag_cqe_based_moder(netdev, enable, true);
1570 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1572 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1573 struct mlx5e_channels new_channels = {};
1576 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1577 return new_val ? -EOPNOTSUPP : 0;
1579 if (curr_val == new_val)
1582 new_channels.params = priv->channels.params;
1583 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1585 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1586 priv->channels.params = new_channels.params;
1590 err = mlx5e_open_channels(priv, &new_channels);
1594 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1595 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1596 MLX5E_GET_PFLAG(&priv->channels.params,
1597 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1602 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1605 struct mlx5e_priv *priv = netdev_priv(netdev);
1606 struct mlx5_core_dev *mdev = priv->mdev;
1608 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1611 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
1612 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1616 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
1617 priv->channels.params.rx_cqe_compress_def = enable;
1622 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1624 struct mlx5e_priv *priv = netdev_priv(netdev);
1625 struct mlx5_core_dev *mdev = priv->mdev;
1626 struct mlx5e_channels new_channels = {};
1630 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1632 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1634 } else if (priv->channels.params.lro_en) {
1635 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n");
1639 new_channels.params = priv->channels.params;
1641 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1642 mlx5e_set_rq_type(mdev, &new_channels.params);
1644 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1645 priv->channels.params = new_channels.params;
1649 err = mlx5e_open_channels(priv, &new_channels);
1653 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1657 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
1659 struct mlx5e_priv *priv = netdev_priv(netdev);
1660 struct mlx5e_channels *channels = &priv->channels;
1661 struct mlx5e_channel *c;
1664 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1667 for (i = 0; i < channels->num; i++) {
1670 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1672 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1678 static int mlx5e_handle_pflag(struct net_device *netdev,
1680 enum mlx5e_priv_flag flag,
1681 mlx5e_pflag_handler pflag_handler)
1683 struct mlx5e_priv *priv = netdev_priv(netdev);
1684 bool enable = !!(wanted_flags & flag);
1685 u32 changes = wanted_flags ^ priv->channels.params.pflags;
1688 if (!(changes & flag))
1691 err = pflag_handler(netdev, enable);
1693 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1694 enable ? "Enable" : "Disable", flag, err);
1698 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
1702 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1704 struct mlx5e_priv *priv = netdev_priv(netdev);
1707 mutex_lock(&priv->state_lock);
1708 err = mlx5e_handle_pflag(netdev, pflags,
1709 MLX5E_PFLAG_RX_CQE_BASED_MODER,
1710 set_pflag_rx_cqe_based_moder);
1714 err = mlx5e_handle_pflag(netdev, pflags,
1715 MLX5E_PFLAG_TX_CQE_BASED_MODER,
1716 set_pflag_tx_cqe_based_moder);
1720 err = mlx5e_handle_pflag(netdev, pflags,
1721 MLX5E_PFLAG_RX_CQE_COMPRESS,
1722 set_pflag_rx_cqe_compress);
1726 err = mlx5e_handle_pflag(netdev, pflags,
1727 MLX5E_PFLAG_RX_STRIDING_RQ,
1728 set_pflag_rx_striding_rq);
1732 err = mlx5e_handle_pflag(netdev, pflags,
1733 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
1734 set_pflag_rx_no_csum_complete);
1737 mutex_unlock(&priv->state_lock);
1739 /* Need to fix some features.. */
1740 netdev_update_features(netdev);
1745 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1747 struct mlx5e_priv *priv = netdev_priv(netdev);
1749 return priv->channels.params.pflags;
1752 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1753 struct ethtool_flash *flash)
1755 struct mlx5_core_dev *mdev = priv->mdev;
1756 struct net_device *dev = priv->netdev;
1757 const struct firmware *fw;
1760 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1763 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1770 err = mlx5_firmware_flash(mdev, fw);
1771 release_firmware(fw);
1778 static int mlx5e_flash_device(struct net_device *dev,
1779 struct ethtool_flash *flash)
1781 struct mlx5e_priv *priv = netdev_priv(dev);
1783 return mlx5e_ethtool_flash_device(priv, flash);
1786 const struct ethtool_ops mlx5e_ethtool_ops = {
1787 .get_drvinfo = mlx5e_get_drvinfo,
1788 .get_link = ethtool_op_get_link,
1789 .get_strings = mlx5e_get_strings,
1790 .get_sset_count = mlx5e_get_sset_count,
1791 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1792 .get_ringparam = mlx5e_get_ringparam,
1793 .set_ringparam = mlx5e_set_ringparam,
1794 .get_channels = mlx5e_get_channels,
1795 .set_channels = mlx5e_set_channels,
1796 .get_coalesce = mlx5e_get_coalesce,
1797 .set_coalesce = mlx5e_set_coalesce,
1798 .get_link_ksettings = mlx5e_get_link_ksettings,
1799 .set_link_ksettings = mlx5e_set_link_ksettings,
1800 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1801 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1802 .get_rxfh = mlx5e_get_rxfh,
1803 .set_rxfh = mlx5e_set_rxfh,
1804 #ifdef CONFIG_MLX5_EN_RXNFC
1805 .get_rxnfc = mlx5e_get_rxnfc,
1806 .set_rxnfc = mlx5e_set_rxnfc,
1808 .flash_device = mlx5e_flash_device,
1809 .get_tunable = mlx5e_get_tunable,
1810 .set_tunable = mlx5e_set_tunable,
1811 .get_pauseparam = mlx5e_get_pauseparam,
1812 .set_pauseparam = mlx5e_set_pauseparam,
1813 .get_ts_info = mlx5e_get_ts_info,
1814 .set_phys_id = mlx5e_set_phys_id,
1815 .get_wol = mlx5e_get_wol,
1816 .set_wol = mlx5e_set_wol,
1817 .get_module_info = mlx5e_get_module_info,
1818 .get_module_eeprom = mlx5e_get_module_eeprom,
1819 .get_priv_flags = mlx5e_get_priv_flags,
1820 .set_priv_flags = mlx5e_set_priv_flags,
1821 .self_test = mlx5e_self_test,
1822 .get_msglevel = mlx5e_get_msglevel,
1823 .set_msglevel = mlx5e_set_msglevel,
1824 .get_fecparam = mlx5e_get_fecparam,
1825 .set_fecparam = mlx5e_set_fecparam,