33a399a8b5d52297379ade73f37e61df266905fa
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
1 /*
2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include "en.h"
34
35 static void mlx5e_get_drvinfo(struct net_device *dev,
36                               struct ethtool_drvinfo *drvinfo)
37 {
38         struct mlx5e_priv *priv = netdev_priv(dev);
39         struct mlx5_core_dev *mdev = priv->mdev;
40
41         strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
42         strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")",
43                 sizeof(drvinfo->version));
44         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
45                  "%d.%d.%d",
46                  fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev));
47         strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
48                 sizeof(drvinfo->bus_info));
49 }
50
51 struct ptys2ethtool_config {
52         __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
53         __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
54         u32 speed;
55 };
56
57 static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
58
59 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...)               \
60         ({                                                              \
61                 struct ptys2ethtool_config *cfg;                        \
62                 const unsigned int modes[] = { __VA_ARGS__ };           \
63                 unsigned int i;                                         \
64                 cfg = &ptys2ethtool_table[reg_];                        \
65                 cfg->speed = speed_;                                    \
66                 bitmap_zero(cfg->supported,                             \
67                             __ETHTOOL_LINK_MODE_MASK_NBITS);            \
68                 bitmap_zero(cfg->advertised,                            \
69                             __ETHTOOL_LINK_MODE_MASK_NBITS);            \
70                 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) {             \
71                         __set_bit(modes[i], cfg->supported);            \
72                         __set_bit(modes[i], cfg->advertised);           \
73                 }                                                       \
74         })
75
76 void mlx5e_build_ptys2ethtool_map(void)
77 {
78         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000,
79                                        ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
80         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000,
81                                        ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
82         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000,
83                                        ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
84         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000,
85                                        ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
86         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000,
87                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
88         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000,
89                                        ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
90         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000,
91                                        ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
92         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000,
93                                        ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
94         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000,
95                                        ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
96         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000,
97                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
98         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000,
99                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
100         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000,
101                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
102         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000,
103                                        ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
104         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000,
105                                        ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
106         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000,
107                                        ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
108         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000,
109                                        ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
110         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000,
111                                        ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
112         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000,
113                                        ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
114         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000,
115                                        ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
116         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000,
117                                        ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
118         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000,
119                                        ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
120         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000,
121                                        ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
122         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000,
123                                        ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
124         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000,
125                                        ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
126         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000,
127                                        ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
128 }
129
130 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
131 {
132         struct mlx5_core_dev *mdev = priv->mdev;
133         u8 pfc_en_tx;
134         u8 pfc_en_rx;
135         int err;
136
137         err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
138
139         return err ? 0 : pfc_en_tx | pfc_en_rx;
140 }
141
142 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
143 {
144         struct mlx5_core_dev *mdev = priv->mdev;
145         u32 rx_pause;
146         u32 tx_pause;
147         int err;
148
149         err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
150
151         return err ? false : rx_pause | tx_pause;
152 }
153
154 #define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
155 #define MLX5E_NUM_RQ_STATS(priv) \
156         (NUM_RQ_STATS * priv->params.num_channels * \
157          test_bit(MLX5E_STATE_OPENED, &priv->state))
158 #define MLX5E_NUM_SQ_STATS(priv) \
159         (NUM_SQ_STATS * priv->params.num_channels * priv->params.num_tc * \
160          test_bit(MLX5E_STATE_OPENED, &priv->state))
161 #define MLX5E_NUM_PFC_COUNTERS(priv) \
162         ((mlx5e_query_global_pause_combined(priv) + hweight8(mlx5e_query_pfc_combined(priv))) * \
163           NUM_PPORT_PER_PRIO_PFC_COUNTERS)
164
165 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
166 {
167         struct mlx5e_priv *priv = netdev_priv(dev);
168
169         switch (sset) {
170         case ETH_SS_STATS:
171                 return NUM_SW_COUNTERS +
172                        MLX5E_NUM_Q_CNTRS(priv) +
173                        NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS +
174                        MLX5E_NUM_RQ_STATS(priv) +
175                        MLX5E_NUM_SQ_STATS(priv) +
176                        MLX5E_NUM_PFC_COUNTERS(priv) +
177                        ARRAY_SIZE(mlx5e_pme_status_desc) +
178                        ARRAY_SIZE(mlx5e_pme_error_desc);
179
180         case ETH_SS_PRIV_FLAGS:
181                 return ARRAY_SIZE(mlx5e_priv_flags);
182         case ETH_SS_TEST:
183                 return mlx5e_self_test_num(priv);
184         /* fallthrough */
185         default:
186                 return -EOPNOTSUPP;
187         }
188 }
189
190 static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
191 {
192         int i, j, tc, prio, idx = 0;
193         unsigned long pfc_combined;
194
195         /* SW counters */
196         for (i = 0; i < NUM_SW_COUNTERS; i++)
197                 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
198
199         /* Q counters */
200         for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
201                 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].format);
202
203         /* VPORT counters */
204         for (i = 0; i < NUM_VPORT_COUNTERS; i++)
205                 strcpy(data + (idx++) * ETH_GSTRING_LEN,
206                        vport_stats_desc[i].format);
207
208         /* PPORT counters */
209         for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
210                 strcpy(data + (idx++) * ETH_GSTRING_LEN,
211                        pport_802_3_stats_desc[i].format);
212
213         for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
214                 strcpy(data + (idx++) * ETH_GSTRING_LEN,
215                        pport_2863_stats_desc[i].format);
216
217         for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
218                 strcpy(data + (idx++) * ETH_GSTRING_LEN,
219                        pport_2819_stats_desc[i].format);
220
221         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
222                 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
223                         sprintf(data + (idx++) * ETH_GSTRING_LEN,
224                                 pport_per_prio_traffic_stats_desc[i].format, prio);
225         }
226
227         pfc_combined = mlx5e_query_pfc_combined(priv);
228         for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
229                 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
230                         char pfc_string[ETH_GSTRING_LEN];
231
232                         snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
233                         sprintf(data + (idx++) * ETH_GSTRING_LEN,
234                                 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
235                 }
236         }
237
238         if (mlx5e_query_global_pause_combined(priv)) {
239                 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
240                         sprintf(data + (idx++) * ETH_GSTRING_LEN,
241                                 pport_per_prio_pfc_stats_desc[i].format, "global");
242                 }
243         }
244
245         /* port module event counters */
246         for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
247                 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
248
249         for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
250                 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
251
252         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
253                 return;
254
255         /* per channel counters */
256         for (i = 0; i < priv->params.num_channels; i++)
257                 for (j = 0; j < NUM_RQ_STATS; j++)
258                         sprintf(data + (idx++) * ETH_GSTRING_LEN,
259                                 rq_stats_desc[j].format, i);
260
261         for (tc = 0; tc < priv->params.num_tc; tc++)
262                 for (i = 0; i < priv->params.num_channels; i++)
263                         for (j = 0; j < NUM_SQ_STATS; j++)
264                                 sprintf(data + (idx++) * ETH_GSTRING_LEN,
265                                         sq_stats_desc[j].format,
266                                         priv->channeltc_to_txq_map[i][tc]);
267 }
268
269 static void mlx5e_get_strings(struct net_device *dev,
270                               uint32_t stringset, uint8_t *data)
271 {
272         struct mlx5e_priv *priv = netdev_priv(dev);
273         int i;
274
275         switch (stringset) {
276         case ETH_SS_PRIV_FLAGS:
277                 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
278                         strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
279                 break;
280
281         case ETH_SS_TEST:
282                 for (i = 0; i < mlx5e_self_test_num(priv); i++)
283                         strcpy(data + i * ETH_GSTRING_LEN,
284                                mlx5e_self_tests[i]);
285                 break;
286
287         case ETH_SS_STATS:
288                 mlx5e_fill_stats_strings(priv, data);
289                 break;
290         }
291 }
292
293 static void mlx5e_get_ethtool_stats(struct net_device *dev,
294                                     struct ethtool_stats *stats, u64 *data)
295 {
296         struct mlx5e_priv *priv = netdev_priv(dev);
297         struct mlx5_priv *mlx5_priv;
298         int i, j, tc, prio, idx = 0;
299         unsigned long pfc_combined;
300
301         if (!data)
302                 return;
303
304         mutex_lock(&priv->state_lock);
305         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
306                 mlx5e_update_stats(priv);
307         mutex_unlock(&priv->state_lock);
308
309         for (i = 0; i < NUM_SW_COUNTERS; i++)
310                 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
311                                                    sw_stats_desc, i);
312
313         for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
314                 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
315                                                    q_stats_desc, i);
316
317         for (i = 0; i < NUM_VPORT_COUNTERS; i++)
318                 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
319                                                   vport_stats_desc, i);
320
321         for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
322                 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
323                                                   pport_802_3_stats_desc, i);
324
325         for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
326                 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
327                                                   pport_2863_stats_desc, i);
328
329         for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
330                 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
331                                                   pport_2819_stats_desc, i);
332
333         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
334                 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
335                         data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
336                                                  pport_per_prio_traffic_stats_desc, i);
337         }
338
339         pfc_combined = mlx5e_query_pfc_combined(priv);
340         for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
341                 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
342                         data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
343                                                           pport_per_prio_pfc_stats_desc, i);
344                 }
345         }
346
347         if (mlx5e_query_global_pause_combined(priv)) {
348                 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
349                         data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
350                                                           pport_per_prio_pfc_stats_desc, i);
351                 }
352         }
353
354         /* port module event counters */
355         mlx5_priv =  &priv->mdev->priv;
356         for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
357                 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
358                                                    mlx5e_pme_status_desc, i);
359
360         for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
361                 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
362                                                    mlx5e_pme_error_desc, i);
363
364         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
365                 return;
366
367         /* per channel counters */
368         for (i = 0; i < priv->params.num_channels; i++)
369                 for (j = 0; j < NUM_RQ_STATS; j++)
370                         data[idx++] =
371                                MLX5E_READ_CTR64_CPU(&priv->channel[i]->rq.stats,
372                                                     rq_stats_desc, j);
373
374         for (tc = 0; tc < priv->params.num_tc; tc++)
375                 for (i = 0; i < priv->params.num_channels; i++)
376                         for (j = 0; j < NUM_SQ_STATS; j++)
377                                 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->channel[i]->sq[tc].stats,
378                                                                    sq_stats_desc, j);
379 }
380
381 static u32 mlx5e_rx_wqes_to_packets(struct mlx5e_priv *priv, int rq_wq_type,
382                                     int num_wqe)
383 {
384         int packets_per_wqe;
385         int stride_size;
386         int num_strides;
387         int wqe_size;
388
389         if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
390                 return num_wqe;
391
392         stride_size = 1 << priv->params.mpwqe_log_stride_sz;
393         num_strides = 1 << priv->params.mpwqe_log_num_strides;
394         wqe_size = stride_size * num_strides;
395
396         packets_per_wqe = wqe_size /
397                           ALIGN(ETH_DATA_LEN, stride_size);
398         return (1 << (order_base_2(num_wqe * packets_per_wqe) - 1));
399 }
400
401 static u32 mlx5e_packets_to_rx_wqes(struct mlx5e_priv *priv, int rq_wq_type,
402                                     int num_packets)
403 {
404         int packets_per_wqe;
405         int stride_size;
406         int num_strides;
407         int wqe_size;
408         int num_wqes;
409
410         if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
411                 return num_packets;
412
413         stride_size = 1 << priv->params.mpwqe_log_stride_sz;
414         num_strides = 1 << priv->params.mpwqe_log_num_strides;
415         wqe_size = stride_size * num_strides;
416
417         num_packets = (1 << order_base_2(num_packets));
418
419         packets_per_wqe = wqe_size /
420                           ALIGN(ETH_DATA_LEN, stride_size);
421         num_wqes = DIV_ROUND_UP(num_packets, packets_per_wqe);
422         return 1 << (order_base_2(num_wqes));
423 }
424
425 static void mlx5e_get_ringparam(struct net_device *dev,
426                                 struct ethtool_ringparam *param)
427 {
428         struct mlx5e_priv *priv = netdev_priv(dev);
429         int rq_wq_type = priv->params.rq_wq_type;
430
431         param->rx_max_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
432                                                          1 << mlx5_max_log_rq_size(rq_wq_type));
433         param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
434         param->rx_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
435                                                      1 << priv->params.log_rq_size);
436         param->tx_pending     = 1 << priv->params.log_sq_size;
437 }
438
439 static int mlx5e_set_ringparam(struct net_device *dev,
440                                struct ethtool_ringparam *param)
441 {
442         struct mlx5e_priv *priv = netdev_priv(dev);
443         bool was_opened;
444         int rq_wq_type = priv->params.rq_wq_type;
445         u32 rx_pending_wqes;
446         u32 min_rq_size;
447         u32 max_rq_size;
448         u16 min_rx_wqes;
449         u8 log_rq_size;
450         u8 log_sq_size;
451         u32 num_mtts;
452         int err = 0;
453
454         if (param->rx_jumbo_pending) {
455                 netdev_info(dev, "%s: rx_jumbo_pending not supported\n",
456                             __func__);
457                 return -EINVAL;
458         }
459         if (param->rx_mini_pending) {
460                 netdev_info(dev, "%s: rx_mini_pending not supported\n",
461                             __func__);
462                 return -EINVAL;
463         }
464
465         min_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
466                                                1 << mlx5_min_log_rq_size(rq_wq_type));
467         max_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
468                                                1 << mlx5_max_log_rq_size(rq_wq_type));
469         rx_pending_wqes = mlx5e_packets_to_rx_wqes(priv, rq_wq_type,
470                                                    param->rx_pending);
471
472         if (param->rx_pending < min_rq_size) {
473                 netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n",
474                             __func__, param->rx_pending,
475                             min_rq_size);
476                 return -EINVAL;
477         }
478         if (param->rx_pending > max_rq_size) {
479                 netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n",
480                             __func__, param->rx_pending,
481                             max_rq_size);
482                 return -EINVAL;
483         }
484
485         num_mtts = MLX5E_REQUIRED_MTTS(rx_pending_wqes);
486         if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
487             !MLX5E_VALID_NUM_MTTS(num_mtts)) {
488                 netdev_info(dev, "%s: rx_pending (%d) request can't be satisfied, try to reduce.\n",
489                             __func__, param->rx_pending);
490                 return -EINVAL;
491         }
492
493         if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
494                 netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n",
495                             __func__, param->tx_pending,
496                             1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
497                 return -EINVAL;
498         }
499         if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
500                 netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n",
501                             __func__, param->tx_pending,
502                             1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
503                 return -EINVAL;
504         }
505
506         log_rq_size = order_base_2(rx_pending_wqes);
507         log_sq_size = order_base_2(param->tx_pending);
508         min_rx_wqes = mlx5_min_rx_wqes(rq_wq_type, rx_pending_wqes);
509
510         if (log_rq_size == priv->params.log_rq_size &&
511             log_sq_size == priv->params.log_sq_size &&
512             min_rx_wqes == priv->params.min_rx_wqes)
513                 return 0;
514
515         mutex_lock(&priv->state_lock);
516
517         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
518         if (was_opened)
519                 mlx5e_close_locked(dev);
520
521         priv->params.log_rq_size = log_rq_size;
522         priv->params.log_sq_size = log_sq_size;
523         priv->params.min_rx_wqes = min_rx_wqes;
524
525         if (was_opened)
526                 err = mlx5e_open_locked(dev);
527
528         mutex_unlock(&priv->state_lock);
529
530         return err;
531 }
532
533 static void mlx5e_get_channels(struct net_device *dev,
534                                struct ethtool_channels *ch)
535 {
536         struct mlx5e_priv *priv = netdev_priv(dev);
537
538         ch->max_combined   = mlx5e_get_max_num_channels(priv->mdev);
539         ch->combined_count = priv->params.num_channels;
540 }
541
542 static int mlx5e_set_channels(struct net_device *dev,
543                               struct ethtool_channels *ch)
544 {
545         struct mlx5e_priv *priv = netdev_priv(dev);
546         int ncv = mlx5e_get_max_num_channels(priv->mdev);
547         unsigned int count = ch->combined_count;
548         bool arfs_enabled;
549         bool was_opened;
550         int err = 0;
551
552         if (!count) {
553                 netdev_info(dev, "%s: combined_count=0 not supported\n",
554                             __func__);
555                 return -EINVAL;
556         }
557         if (ch->rx_count || ch->tx_count) {
558                 netdev_info(dev, "%s: separate rx/tx count not supported\n",
559                             __func__);
560                 return -EINVAL;
561         }
562         if (count > ncv) {
563                 netdev_info(dev, "%s: count (%d) > max (%d)\n",
564                             __func__, count, ncv);
565                 return -EINVAL;
566         }
567
568         if (priv->params.num_channels == count)
569                 return 0;
570
571         mutex_lock(&priv->state_lock);
572
573         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
574         if (was_opened)
575                 mlx5e_close_locked(dev);
576
577         arfs_enabled = dev->features & NETIF_F_NTUPLE;
578         if (arfs_enabled)
579                 mlx5e_arfs_disable(priv);
580
581         priv->params.num_channels = count;
582         mlx5e_build_default_indir_rqt(priv->mdev, priv->params.indirection_rqt,
583                                       MLX5E_INDIR_RQT_SIZE, count);
584
585         if (was_opened)
586                 err = mlx5e_open_locked(dev);
587         if (err)
588                 goto out;
589
590         if (arfs_enabled) {
591                 err = mlx5e_arfs_enable(priv);
592                 if (err)
593                         netdev_err(dev, "%s: mlx5e_arfs_enable failed: %d\n",
594                                    __func__, err);
595         }
596
597 out:
598         mutex_unlock(&priv->state_lock);
599
600         return err;
601 }
602
603 static int mlx5e_get_coalesce(struct net_device *netdev,
604                               struct ethtool_coalesce *coal)
605 {
606         struct mlx5e_priv *priv = netdev_priv(netdev);
607
608         if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
609                 return -ENOTSUPP;
610
611         coal->rx_coalesce_usecs       = priv->params.rx_cq_moderation.usec;
612         coal->rx_max_coalesced_frames = priv->params.rx_cq_moderation.pkts;
613         coal->tx_coalesce_usecs       = priv->params.tx_cq_moderation.usec;
614         coal->tx_max_coalesced_frames = priv->params.tx_cq_moderation.pkts;
615         coal->use_adaptive_rx_coalesce = priv->params.rx_am_enabled;
616
617         return 0;
618 }
619
620 static int mlx5e_set_coalesce(struct net_device *netdev,
621                               struct ethtool_coalesce *coal)
622 {
623         struct mlx5e_priv *priv    = netdev_priv(netdev);
624         struct mlx5_core_dev *mdev = priv->mdev;
625         struct mlx5e_channel *c;
626         bool restart =
627                 !!coal->use_adaptive_rx_coalesce != priv->params.rx_am_enabled;
628         bool was_opened;
629         int err = 0;
630         int tc;
631         int i;
632
633         if (!MLX5_CAP_GEN(mdev, cq_moderation))
634                 return -ENOTSUPP;
635
636         mutex_lock(&priv->state_lock);
637
638         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
639         if (was_opened && restart) {
640                 mlx5e_close_locked(netdev);
641                 priv->params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce;
642         }
643
644         priv->params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
645         priv->params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
646         priv->params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
647         priv->params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
648
649         if (!was_opened || restart)
650                 goto out;
651
652         for (i = 0; i < priv->params.num_channels; ++i) {
653                 c = priv->channel[i];
654
655                 for (tc = 0; tc < c->num_tc; tc++) {
656                         mlx5_core_modify_cq_moderation(mdev,
657                                                 &c->sq[tc].cq.mcq,
658                                                 coal->tx_coalesce_usecs,
659                                                 coal->tx_max_coalesced_frames);
660                 }
661
662                 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
663                                                coal->rx_coalesce_usecs,
664                                                coal->rx_max_coalesced_frames);
665         }
666
667 out:
668         if (was_opened && restart)
669                 err = mlx5e_open_locked(netdev);
670
671         mutex_unlock(&priv->state_lock);
672         return err;
673 }
674
675 static void ptys2ethtool_supported_link(unsigned long *supported_modes,
676                                         u32 eth_proto_cap)
677 {
678         unsigned long proto_cap = eth_proto_cap;
679         int proto;
680
681         for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
682                 bitmap_or(supported_modes, supported_modes,
683                           ptys2ethtool_table[proto].supported,
684                           __ETHTOOL_LINK_MODE_MASK_NBITS);
685 }
686
687 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
688                                     u32 eth_proto_cap)
689 {
690         unsigned long proto_cap = eth_proto_cap;
691         int proto;
692
693         for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
694                 bitmap_or(advertising_modes, advertising_modes,
695                           ptys2ethtool_table[proto].advertised,
696                           __ETHTOOL_LINK_MODE_MASK_NBITS);
697 }
698
699 static void ptys2ethtool_supported_port(struct ethtool_link_ksettings *link_ksettings,
700                                         u32 eth_proto_cap)
701 {
702         if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
703                            | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
704                            | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
705                            | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
706                            | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
707                            | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
708                 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, FIBRE);
709         }
710
711         if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
712                            | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
713                            | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
714                            | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
715                            | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
716                 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Backplane);
717         }
718 }
719
720 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
721 {
722         u32 max_speed = 0;
723         u32 proto_cap;
724         int err;
725         int i;
726
727         err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
728         if (err)
729                 return err;
730
731         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
732                 if (proto_cap & MLX5E_PROT_MASK(i))
733                         max_speed = max(max_speed, ptys2ethtool_table[i].speed);
734
735         *speed = max_speed;
736         return 0;
737 }
738
739 static void get_speed_duplex(struct net_device *netdev,
740                              u32 eth_proto_oper,
741                              struct ethtool_link_ksettings *link_ksettings)
742 {
743         int i;
744         u32 speed = SPEED_UNKNOWN;
745         u8 duplex = DUPLEX_UNKNOWN;
746
747         if (!netif_carrier_ok(netdev))
748                 goto out;
749
750         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
751                 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
752                         speed = ptys2ethtool_table[i].speed;
753                         duplex = DUPLEX_FULL;
754                         break;
755                 }
756         }
757 out:
758         link_ksettings->base.speed = speed;
759         link_ksettings->base.duplex = duplex;
760 }
761
762 static void get_supported(u32 eth_proto_cap,
763                           struct ethtool_link_ksettings *link_ksettings)
764 {
765         unsigned long *supported = link_ksettings->link_modes.supported;
766
767         ptys2ethtool_supported_port(link_ksettings, eth_proto_cap);
768         ptys2ethtool_supported_link(supported, eth_proto_cap);
769         ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
770         ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Asym_Pause);
771 }
772
773 static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
774                             u8 rx_pause,
775                             struct ethtool_link_ksettings *link_ksettings)
776 {
777         unsigned long *advertising = link_ksettings->link_modes.advertising;
778
779         ptys2ethtool_adver_link(advertising, eth_proto_cap);
780         if (tx_pause)
781                 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
782         if (tx_pause ^ rx_pause)
783                 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
784 }
785
786 static u8 get_connector_port(u32 eth_proto)
787 {
788         if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
789                          | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
790                          | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
791                          | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
792                         return PORT_FIBRE;
793         }
794
795         if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
796                          | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
797                          | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
798                         return PORT_DA;
799         }
800
801         if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
802                          | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
803                          | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
804                          | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
805                         return PORT_NONE;
806         }
807
808         return PORT_OTHER;
809 }
810
811 static void get_lp_advertising(u32 eth_proto_lp,
812                                struct ethtool_link_ksettings *link_ksettings)
813 {
814         unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
815
816         ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
817 }
818
819 static int mlx5e_get_link_ksettings(struct net_device *netdev,
820                                     struct ethtool_link_ksettings *link_ksettings)
821 {
822         struct mlx5e_priv *priv    = netdev_priv(netdev);
823         struct mlx5_core_dev *mdev = priv->mdev;
824         u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
825         u32 eth_proto_cap;
826         u32 eth_proto_admin;
827         u32 eth_proto_lp;
828         u32 eth_proto_oper;
829         u8 an_disable_admin;
830         u8 an_status;
831         int err;
832
833         err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
834         if (err) {
835                 netdev_err(netdev, "%s: query port ptys failed: %d\n",
836                            __func__, err);
837                 goto err_query_ptys;
838         }
839
840         eth_proto_cap    = MLX5_GET(ptys_reg, out, eth_proto_capability);
841         eth_proto_admin  = MLX5_GET(ptys_reg, out, eth_proto_admin);
842         eth_proto_oper   = MLX5_GET(ptys_reg, out, eth_proto_oper);
843         eth_proto_lp     = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
844         an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
845         an_status        = MLX5_GET(ptys_reg, out, an_status);
846
847         ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
848         ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
849
850         get_supported(eth_proto_cap, link_ksettings);
851         get_advertising(eth_proto_admin, 0, 0, link_ksettings);
852         get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
853
854         eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
855
856         link_ksettings->base.port = get_connector_port(eth_proto_oper);
857         get_lp_advertising(eth_proto_lp, link_ksettings);
858
859         if (an_status == MLX5_AN_COMPLETE)
860                 ethtool_link_ksettings_add_link_mode(link_ksettings,
861                                                      lp_advertising, Autoneg);
862
863         link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
864                                                           AUTONEG_ENABLE;
865         ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
866                                              Autoneg);
867         if (!an_disable_admin)
868                 ethtool_link_ksettings_add_link_mode(link_ksettings,
869                                                      advertising, Autoneg);
870
871 err_query_ptys:
872         return err;
873 }
874
875 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
876 {
877         u32 i, ptys_modes = 0;
878
879         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
880                 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
881                                       link_modes,
882                                       __ETHTOOL_LINK_MODE_MASK_NBITS))
883                         ptys_modes |= MLX5E_PROT_MASK(i);
884         }
885
886         return ptys_modes;
887 }
888
889 static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
890 {
891         u32 i, speed_links = 0;
892
893         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
894                 if (ptys2ethtool_table[i].speed == speed)
895                         speed_links |= MLX5E_PROT_MASK(i);
896         }
897
898         return speed_links;
899 }
900
901 static int mlx5e_set_link_ksettings(struct net_device *netdev,
902                                     const struct ethtool_link_ksettings *link_ksettings)
903 {
904         struct mlx5e_priv *priv    = netdev_priv(netdev);
905         struct mlx5_core_dev *mdev = priv->mdev;
906         u32 eth_proto_cap, eth_proto_admin;
907         bool an_changes = false;
908         u8 an_disable_admin;
909         u8 an_disable_cap;
910         bool an_disable;
911         u32 link_modes;
912         u8 an_status;
913         u32 speed;
914         int err;
915
916         speed = link_ksettings->base.speed;
917
918         link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
919                 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
920                 mlx5e_ethtool2ptys_speed_link(speed);
921
922         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
923         if (err) {
924                 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
925                            __func__, err);
926                 goto out;
927         }
928
929         link_modes = link_modes & eth_proto_cap;
930         if (!link_modes) {
931                 netdev_err(netdev, "%s: Not supported link mode(s) requested",
932                            __func__);
933                 err = -EINVAL;
934                 goto out;
935         }
936
937         err = mlx5_query_port_proto_admin(mdev, &eth_proto_admin, MLX5_PTYS_EN);
938         if (err) {
939                 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
940                            __func__, err);
941                 goto out;
942         }
943
944         mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
945                                 &an_disable_cap, &an_disable_admin);
946
947         an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
948         an_changes = ((!an_disable && an_disable_admin) ||
949                       (an_disable && !an_disable_admin));
950
951         if (!an_changes && link_modes == eth_proto_admin)
952                 goto out;
953
954         mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
955         mlx5_toggle_port_link(mdev);
956
957 out:
958         return err;
959 }
960
961 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
962 {
963         struct mlx5e_priv *priv = netdev_priv(netdev);
964
965         return sizeof(priv->params.toeplitz_hash_key);
966 }
967
968 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
969 {
970         return MLX5E_INDIR_RQT_SIZE;
971 }
972
973 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
974                           u8 *hfunc)
975 {
976         struct mlx5e_priv *priv = netdev_priv(netdev);
977
978         if (indir)
979                 memcpy(indir, priv->params.indirection_rqt,
980                        sizeof(priv->params.indirection_rqt));
981
982         if (key)
983                 memcpy(key, priv->params.toeplitz_hash_key,
984                        sizeof(priv->params.toeplitz_hash_key));
985
986         if (hfunc)
987                 *hfunc = priv->params.rss_hfunc;
988
989         return 0;
990 }
991
992 static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
993 {
994         struct mlx5_core_dev *mdev = priv->mdev;
995         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
996         int i;
997
998         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
999         mlx5e_build_tir_ctx_hash(tirc, priv);
1000
1001         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
1002                 mlx5_core_modify_tir(mdev, priv->indir_tir[i].tirn, in, inlen);
1003 }
1004
1005 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
1006                           const u8 *key, const u8 hfunc)
1007 {
1008         struct mlx5e_priv *priv = netdev_priv(dev);
1009         int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1010         void *in;
1011
1012         if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1013             (hfunc != ETH_RSS_HASH_XOR) &&
1014             (hfunc != ETH_RSS_HASH_TOP))
1015                 return -EINVAL;
1016
1017         in = mlx5_vzalloc(inlen);
1018         if (!in)
1019                 return -ENOMEM;
1020
1021         mutex_lock(&priv->state_lock);
1022
1023         if (indir) {
1024                 u32 rqtn = priv->indir_rqt.rqtn;
1025
1026                 memcpy(priv->params.indirection_rqt, indir,
1027                        sizeof(priv->params.indirection_rqt));
1028                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1029         }
1030
1031         if (key)
1032                 memcpy(priv->params.toeplitz_hash_key, key,
1033                        sizeof(priv->params.toeplitz_hash_key));
1034
1035         if (hfunc != ETH_RSS_HASH_NO_CHANGE)
1036                 priv->params.rss_hfunc = hfunc;
1037
1038         mlx5e_modify_tirs_hash(priv, in, inlen);
1039
1040         mutex_unlock(&priv->state_lock);
1041
1042         kvfree(in);
1043
1044         return 0;
1045 }
1046
1047 static int mlx5e_get_rxnfc(struct net_device *netdev,
1048                            struct ethtool_rxnfc *info, u32 *rule_locs)
1049 {
1050         struct mlx5e_priv *priv = netdev_priv(netdev);
1051         int err = 0;
1052
1053         switch (info->cmd) {
1054         case ETHTOOL_GRXRINGS:
1055                 info->data = priv->params.num_channels;
1056                 break;
1057         case ETHTOOL_GRXCLSRLCNT:
1058                 info->rule_cnt = priv->fs.ethtool.tot_num_rules;
1059                 break;
1060         case ETHTOOL_GRXCLSRULE:
1061                 err = mlx5e_ethtool_get_flow(priv, info, info->fs.location);
1062                 break;
1063         case ETHTOOL_GRXCLSRLALL:
1064                 err = mlx5e_ethtool_get_all_flows(priv, info, rule_locs);
1065                 break;
1066         default:
1067                 err = -EOPNOTSUPP;
1068                 break;
1069         }
1070
1071         return err;
1072 }
1073
1074 static int mlx5e_get_tunable(struct net_device *dev,
1075                              const struct ethtool_tunable *tuna,
1076                              void *data)
1077 {
1078         const struct mlx5e_priv *priv = netdev_priv(dev);
1079         int err = 0;
1080
1081         switch (tuna->id) {
1082         case ETHTOOL_TX_COPYBREAK:
1083                 *(u32 *)data = priv->params.tx_max_inline;
1084                 break;
1085         default:
1086                 err = -EINVAL;
1087                 break;
1088         }
1089
1090         return err;
1091 }
1092
1093 static int mlx5e_set_tunable(struct net_device *dev,
1094                              const struct ethtool_tunable *tuna,
1095                              const void *data)
1096 {
1097         struct mlx5e_priv *priv = netdev_priv(dev);
1098         struct mlx5_core_dev *mdev = priv->mdev;
1099         bool was_opened;
1100         u32 val;
1101         int err = 0;
1102
1103         switch (tuna->id) {
1104         case ETHTOOL_TX_COPYBREAK:
1105                 val = *(u32 *)data;
1106                 if (val > mlx5e_get_max_inline_cap(mdev)) {
1107                         err = -EINVAL;
1108                         break;
1109                 }
1110
1111                 mutex_lock(&priv->state_lock);
1112
1113                 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1114                 if (was_opened)
1115                         mlx5e_close_locked(dev);
1116
1117                 priv->params.tx_max_inline = val;
1118
1119                 if (was_opened)
1120                         err = mlx5e_open_locked(dev);
1121
1122                 mutex_unlock(&priv->state_lock);
1123                 break;
1124         default:
1125                 err = -EINVAL;
1126                 break;
1127         }
1128
1129         return err;
1130 }
1131
1132 static void mlx5e_get_pauseparam(struct net_device *netdev,
1133                                  struct ethtool_pauseparam *pauseparam)
1134 {
1135         struct mlx5e_priv *priv    = netdev_priv(netdev);
1136         struct mlx5_core_dev *mdev = priv->mdev;
1137         int err;
1138
1139         err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1140                                     &pauseparam->tx_pause);
1141         if (err) {
1142                 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1143                            __func__, err);
1144         }
1145 }
1146
1147 static int mlx5e_set_pauseparam(struct net_device *netdev,
1148                                 struct ethtool_pauseparam *pauseparam)
1149 {
1150         struct mlx5e_priv *priv    = netdev_priv(netdev);
1151         struct mlx5_core_dev *mdev = priv->mdev;
1152         int err;
1153
1154         if (pauseparam->autoneg)
1155                 return -EINVAL;
1156
1157         err = mlx5_set_port_pause(mdev,
1158                                   pauseparam->rx_pause ? 1 : 0,
1159                                   pauseparam->tx_pause ? 1 : 0);
1160         if (err) {
1161                 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1162                            __func__, err);
1163         }
1164
1165         return err;
1166 }
1167
1168 static int mlx5e_get_ts_info(struct net_device *dev,
1169                              struct ethtool_ts_info *info)
1170 {
1171         struct mlx5e_priv *priv = netdev_priv(dev);
1172         int ret;
1173
1174         ret = ethtool_op_get_ts_info(dev, info);
1175         if (ret)
1176                 return ret;
1177
1178         info->phc_index = priv->tstamp.ptp ?
1179                           ptp_clock_index(priv->tstamp.ptp) : -1;
1180
1181         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1182                 return 0;
1183
1184         info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1185                                  SOF_TIMESTAMPING_RX_HARDWARE |
1186                                  SOF_TIMESTAMPING_RAW_HARDWARE;
1187
1188         info->tx_types = (BIT(1) << HWTSTAMP_TX_OFF) |
1189                          (BIT(1) << HWTSTAMP_TX_ON);
1190
1191         info->rx_filters = (BIT(1) << HWTSTAMP_FILTER_NONE) |
1192                            (BIT(1) << HWTSTAMP_FILTER_ALL);
1193
1194         return 0;
1195 }
1196
1197 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1198 {
1199         __u32 ret = 0;
1200
1201         if (MLX5_CAP_GEN(mdev, wol_g))
1202                 ret |= WAKE_MAGIC;
1203
1204         if (MLX5_CAP_GEN(mdev, wol_s))
1205                 ret |= WAKE_MAGICSECURE;
1206
1207         if (MLX5_CAP_GEN(mdev, wol_a))
1208                 ret |= WAKE_ARP;
1209
1210         if (MLX5_CAP_GEN(mdev, wol_b))
1211                 ret |= WAKE_BCAST;
1212
1213         if (MLX5_CAP_GEN(mdev, wol_m))
1214                 ret |= WAKE_MCAST;
1215
1216         if (MLX5_CAP_GEN(mdev, wol_u))
1217                 ret |= WAKE_UCAST;
1218
1219         if (MLX5_CAP_GEN(mdev, wol_p))
1220                 ret |= WAKE_PHY;
1221
1222         return ret;
1223 }
1224
1225 static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1226 {
1227         __u32 ret = 0;
1228
1229         if (mode & MLX5_WOL_MAGIC)
1230                 ret |= WAKE_MAGIC;
1231
1232         if (mode & MLX5_WOL_SECURED_MAGIC)
1233                 ret |= WAKE_MAGICSECURE;
1234
1235         if (mode & MLX5_WOL_ARP)
1236                 ret |= WAKE_ARP;
1237
1238         if (mode & MLX5_WOL_BROADCAST)
1239                 ret |= WAKE_BCAST;
1240
1241         if (mode & MLX5_WOL_MULTICAST)
1242                 ret |= WAKE_MCAST;
1243
1244         if (mode & MLX5_WOL_UNICAST)
1245                 ret |= WAKE_UCAST;
1246
1247         if (mode & MLX5_WOL_PHY_ACTIVITY)
1248                 ret |= WAKE_PHY;
1249
1250         return ret;
1251 }
1252
1253 static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1254 {
1255         u8 ret = 0;
1256
1257         if (mode & WAKE_MAGIC)
1258                 ret |= MLX5_WOL_MAGIC;
1259
1260         if (mode & WAKE_MAGICSECURE)
1261                 ret |= MLX5_WOL_SECURED_MAGIC;
1262
1263         if (mode & WAKE_ARP)
1264                 ret |= MLX5_WOL_ARP;
1265
1266         if (mode & WAKE_BCAST)
1267                 ret |= MLX5_WOL_BROADCAST;
1268
1269         if (mode & WAKE_MCAST)
1270                 ret |= MLX5_WOL_MULTICAST;
1271
1272         if (mode & WAKE_UCAST)
1273                 ret |= MLX5_WOL_UNICAST;
1274
1275         if (mode & WAKE_PHY)
1276                 ret |= MLX5_WOL_PHY_ACTIVITY;
1277
1278         return ret;
1279 }
1280
1281 static void mlx5e_get_wol(struct net_device *netdev,
1282                           struct ethtool_wolinfo *wol)
1283 {
1284         struct mlx5e_priv *priv = netdev_priv(netdev);
1285         struct mlx5_core_dev *mdev = priv->mdev;
1286         u8 mlx5_wol_mode;
1287         int err;
1288
1289         memset(wol, 0, sizeof(*wol));
1290
1291         wol->supported = mlx5e_get_wol_supported(mdev);
1292         if (!wol->supported)
1293                 return;
1294
1295         err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1296         if (err)
1297                 return;
1298
1299         wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1300 }
1301
1302 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1303 {
1304         struct mlx5e_priv *priv = netdev_priv(netdev);
1305         struct mlx5_core_dev *mdev = priv->mdev;
1306         __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1307         u32 mlx5_wol_mode;
1308
1309         if (!wol_supported)
1310                 return -ENOTSUPP;
1311
1312         if (wol->wolopts & ~wol_supported)
1313                 return -EINVAL;
1314
1315         mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1316
1317         return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1318 }
1319
1320 static int mlx5e_set_phys_id(struct net_device *dev,
1321                              enum ethtool_phys_id_state state)
1322 {
1323         struct mlx5e_priv *priv = netdev_priv(dev);
1324         struct mlx5_core_dev *mdev = priv->mdev;
1325         u16 beacon_duration;
1326
1327         if (!MLX5_CAP_GEN(mdev, beacon_led))
1328                 return -EOPNOTSUPP;
1329
1330         switch (state) {
1331         case ETHTOOL_ID_ACTIVE:
1332                 beacon_duration = MLX5_BEACON_DURATION_INF;
1333                 break;
1334         case ETHTOOL_ID_INACTIVE:
1335                 beacon_duration = MLX5_BEACON_DURATION_OFF;
1336                 break;
1337         default:
1338                 return -EOPNOTSUPP;
1339         }
1340
1341         return mlx5_set_port_beacon(mdev, beacon_duration);
1342 }
1343
1344 static int mlx5e_get_module_info(struct net_device *netdev,
1345                                  struct ethtool_modinfo *modinfo)
1346 {
1347         struct mlx5e_priv *priv = netdev_priv(netdev);
1348         struct mlx5_core_dev *dev = priv->mdev;
1349         int size_read = 0;
1350         u8 data[4];
1351
1352         size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1353         if (size_read < 2)
1354                 return -EIO;
1355
1356         /* data[0] = identifier byte */
1357         switch (data[0]) {
1358         case MLX5_MODULE_ID_QSFP:
1359                 modinfo->type       = ETH_MODULE_SFF_8436;
1360                 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1361                 break;
1362         case MLX5_MODULE_ID_QSFP_PLUS:
1363         case MLX5_MODULE_ID_QSFP28:
1364                 /* data[1] = revision id */
1365                 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1366                         modinfo->type       = ETH_MODULE_SFF_8636;
1367                         modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1368                 } else {
1369                         modinfo->type       = ETH_MODULE_SFF_8436;
1370                         modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1371                 }
1372                 break;
1373         case MLX5_MODULE_ID_SFP:
1374                 modinfo->type       = ETH_MODULE_SFF_8472;
1375                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1376                 break;
1377         default:
1378                 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1379                            __func__, data[0]);
1380                 return -EINVAL;
1381         }
1382
1383         return 0;
1384 }
1385
1386 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1387                                    struct ethtool_eeprom *ee,
1388                                    u8 *data)
1389 {
1390         struct mlx5e_priv *priv = netdev_priv(netdev);
1391         struct mlx5_core_dev *mdev = priv->mdev;
1392         int offset = ee->offset;
1393         int size_read;
1394         int i = 0;
1395
1396         if (!ee->len)
1397                 return -EINVAL;
1398
1399         memset(data, 0, ee->len);
1400
1401         while (i < ee->len) {
1402                 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1403                                                      data + i);
1404
1405                 if (!size_read)
1406                         /* Done reading */
1407                         return 0;
1408
1409                 if (size_read < 0) {
1410                         netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1411                                    __func__, size_read);
1412                         return 0;
1413                 }
1414
1415                 i += size_read;
1416                 offset += size_read;
1417         }
1418
1419         return 0;
1420 }
1421
1422 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1423
1424 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1425 {
1426         struct mlx5e_priv *priv = netdev_priv(netdev);
1427         struct mlx5_core_dev *mdev = priv->mdev;
1428         bool rx_mode_changed;
1429         u8 rx_cq_period_mode;
1430         int err = 0;
1431         bool reset;
1432
1433         rx_cq_period_mode = enable ?
1434                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1435                 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1436         rx_mode_changed = rx_cq_period_mode != priv->params.rx_cq_period_mode;
1437
1438         if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1439             !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1440                 return -ENOTSUPP;
1441
1442         if (!rx_mode_changed)
1443                 return 0;
1444
1445         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
1446         if (reset)
1447                 mlx5e_close_locked(netdev);
1448
1449         mlx5e_set_rx_cq_mode_params(&priv->params, rx_cq_period_mode);
1450
1451         if (reset)
1452                 err = mlx5e_open_locked(netdev);
1453
1454         return err;
1455 }
1456
1457 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1458                                      bool enable)
1459 {
1460         struct mlx5e_priv *priv = netdev_priv(netdev);
1461         struct mlx5_core_dev *mdev = priv->mdev;
1462         int err = 0;
1463         bool reset;
1464
1465         if (!MLX5_CAP_GEN(mdev, cqe_compression))
1466                 return -ENOTSUPP;
1467
1468         if (enable && priv->tstamp.hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
1469                 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1470                 return -EINVAL;
1471         }
1472
1473         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
1474
1475         if (reset)
1476                 mlx5e_close_locked(netdev);
1477
1478         MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, enable);
1479         priv->params.rx_cqe_compress_def = enable;
1480
1481         if (reset)
1482                 err = mlx5e_open_locked(netdev);
1483         return err;
1484 }
1485
1486 static int mlx5e_handle_pflag(struct net_device *netdev,
1487                               u32 wanted_flags,
1488                               enum mlx5e_priv_flag flag,
1489                               mlx5e_pflag_handler pflag_handler)
1490 {
1491         struct mlx5e_priv *priv = netdev_priv(netdev);
1492         bool enable = !!(wanted_flags & flag);
1493         u32 changes = wanted_flags ^ priv->params.pflags;
1494         int err;
1495
1496         if (!(changes & flag))
1497                 return 0;
1498
1499         err = pflag_handler(netdev, enable);
1500         if (err) {
1501                 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1502                            enable ? "Enable" : "Disable", flag, err);
1503                 return err;
1504         }
1505
1506         MLX5E_SET_PFLAG(priv, flag, enable);
1507         return 0;
1508 }
1509
1510 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1511 {
1512         struct mlx5e_priv *priv = netdev_priv(netdev);
1513         int err;
1514
1515         mutex_lock(&priv->state_lock);
1516         err = mlx5e_handle_pflag(netdev, pflags,
1517                                  MLX5E_PFLAG_RX_CQE_BASED_MODER,
1518                                  set_pflag_rx_cqe_based_moder);
1519         if (err)
1520                 goto out;
1521
1522         err = mlx5e_handle_pflag(netdev, pflags,
1523                                  MLX5E_PFLAG_RX_CQE_COMPRESS,
1524                                  set_pflag_rx_cqe_compress);
1525
1526 out:
1527         mutex_unlock(&priv->state_lock);
1528         return err;
1529 }
1530
1531 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1532 {
1533         struct mlx5e_priv *priv = netdev_priv(netdev);
1534
1535         return priv->params.pflags;
1536 }
1537
1538 static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1539 {
1540         int err = 0;
1541         struct mlx5e_priv *priv = netdev_priv(dev);
1542
1543         switch (cmd->cmd) {
1544         case ETHTOOL_SRXCLSRLINS:
1545                 err = mlx5e_ethtool_flow_replace(priv, &cmd->fs);
1546                 break;
1547         case ETHTOOL_SRXCLSRLDEL:
1548                 err = mlx5e_ethtool_flow_remove(priv, cmd->fs.location);
1549                 break;
1550         default:
1551                 err = -EOPNOTSUPP;
1552                 break;
1553         }
1554
1555         return err;
1556 }
1557
1558 const struct ethtool_ops mlx5e_ethtool_ops = {
1559         .get_drvinfo       = mlx5e_get_drvinfo,
1560         .get_link          = ethtool_op_get_link,
1561         .get_strings       = mlx5e_get_strings,
1562         .get_sset_count    = mlx5e_get_sset_count,
1563         .get_ethtool_stats = mlx5e_get_ethtool_stats,
1564         .get_ringparam     = mlx5e_get_ringparam,
1565         .set_ringparam     = mlx5e_set_ringparam,
1566         .get_channels      = mlx5e_get_channels,
1567         .set_channels      = mlx5e_set_channels,
1568         .get_coalesce      = mlx5e_get_coalesce,
1569         .set_coalesce      = mlx5e_set_coalesce,
1570         .get_link_ksettings  = mlx5e_get_link_ksettings,
1571         .set_link_ksettings  = mlx5e_set_link_ksettings,
1572         .get_rxfh_key_size   = mlx5e_get_rxfh_key_size,
1573         .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1574         .get_rxfh          = mlx5e_get_rxfh,
1575         .set_rxfh          = mlx5e_set_rxfh,
1576         .get_rxnfc         = mlx5e_get_rxnfc,
1577         .set_rxnfc         = mlx5e_set_rxnfc,
1578         .get_tunable       = mlx5e_get_tunable,
1579         .set_tunable       = mlx5e_set_tunable,
1580         .get_pauseparam    = mlx5e_get_pauseparam,
1581         .set_pauseparam    = mlx5e_set_pauseparam,
1582         .get_ts_info       = mlx5e_get_ts_info,
1583         .set_phys_id       = mlx5e_set_phys_id,
1584         .get_wol           = mlx5e_get_wol,
1585         .set_wol           = mlx5e_set_wol,
1586         .get_module_info   = mlx5e_get_module_info,
1587         .get_module_eeprom = mlx5e_get_module_eeprom,
1588         .get_priv_flags    = mlx5e_get_priv_flags,
1589         .set_priv_flags    = mlx5e_set_priv_flags,
1590         .self_test         = mlx5e_self_test,
1591 };