2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #include <linux/device.h>
33 #include <linux/netdevice.h>
36 #include "en/port_buffer.h"
38 #define MLX5E_100MB (100000)
39 #define MLX5E_1GB (1000000)
41 #define MLX5E_CEE_STATE_UP 1
42 #define MLX5E_CEE_STATE_DOWN 0
44 /* Max supported cable length is 1000 meters */
45 #define MLX5E_MAX_CABLE_LENGTH 1000
48 MLX5E_VENDOR_TC_GROUP_NUM = 7,
49 MLX5E_LOWEST_PRIO_GROUP = 0,
52 #define MLX5_DSCP_SUPPORTED(mdev) (MLX5_CAP_GEN(mdev, qcam_reg) && \
53 MLX5_CAP_QCAM_REG(mdev, qpts) && \
54 MLX5_CAP_QCAM_REG(mdev, qpdpm))
56 static int mlx5e_set_trust_state(struct mlx5e_priv *priv, u8 trust_state);
57 static int mlx5e_set_dscp2prio(struct mlx5e_priv *priv, u8 dscp, u8 prio);
59 /* If dcbx mode is non-host set the dcbx mode to host.
61 static int mlx5e_dcbnl_set_dcbx_mode(struct mlx5e_priv *priv,
62 enum mlx5_dcbx_oper_mode mode)
64 struct mlx5_core_dev *mdev = priv->mdev;
65 u32 param[MLX5_ST_SZ_DW(dcbx_param)];
68 err = mlx5_query_port_dcbx_param(mdev, param);
72 MLX5_SET(dcbx_param, param, version_admin, mode);
73 if (mode != MLX5E_DCBX_PARAM_VER_OPER_HOST)
74 MLX5_SET(dcbx_param, param, willing_admin, 1);
76 return mlx5_set_port_dcbx_param(mdev, param);
79 static int mlx5e_dcbnl_switch_to_host_mode(struct mlx5e_priv *priv)
81 struct mlx5e_dcbx *dcbx = &priv->dcbx;
84 if (!MLX5_CAP_GEN(priv->mdev, dcbx))
87 if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_HOST)
90 err = mlx5e_dcbnl_set_dcbx_mode(priv, MLX5E_DCBX_PARAM_VER_OPER_HOST);
94 dcbx->mode = MLX5E_DCBX_PARAM_VER_OPER_HOST;
98 static int mlx5e_dcbnl_ieee_getets(struct net_device *netdev,
101 struct mlx5e_priv *priv = netdev_priv(netdev);
102 struct mlx5_core_dev *mdev = priv->mdev;
103 u8 tc_group[IEEE_8021QAZ_MAX_TCS];
104 bool is_tc_group_6_exist = false;
105 bool is_zero_bw_ets_tc = false;
109 if (!MLX5_CAP_GEN(priv->mdev, ets))
112 ets->ets_cap = mlx5_max_tc(priv->mdev) + 1;
113 for (i = 0; i < ets->ets_cap; i++) {
114 err = mlx5_query_port_prio_tc(mdev, i, &ets->prio_tc[i]);
118 err = mlx5_query_port_tc_group(mdev, i, &tc_group[i]);
122 err = mlx5_query_port_tc_bw_alloc(mdev, i, &ets->tc_tx_bw[i]);
126 if (ets->tc_tx_bw[i] < MLX5E_MAX_BW_ALLOC &&
127 tc_group[i] == (MLX5E_LOWEST_PRIO_GROUP + 1))
128 is_zero_bw_ets_tc = true;
130 if (tc_group[i] == (MLX5E_VENDOR_TC_GROUP_NUM - 1))
131 is_tc_group_6_exist = true;
134 /* Report 0% ets tc if exits*/
135 if (is_zero_bw_ets_tc) {
136 for (i = 0; i < ets->ets_cap; i++)
137 if (tc_group[i] == MLX5E_LOWEST_PRIO_GROUP)
138 ets->tc_tx_bw[i] = 0;
141 /* Update tc_tsa based on fw setting*/
142 for (i = 0; i < ets->ets_cap; i++) {
143 if (ets->tc_tx_bw[i] < MLX5E_MAX_BW_ALLOC)
144 priv->dcbx.tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
145 else if (tc_group[i] == MLX5E_VENDOR_TC_GROUP_NUM &&
146 !is_tc_group_6_exist)
147 priv->dcbx.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
149 memcpy(ets->tc_tsa, priv->dcbx.tc_tsa, sizeof(ets->tc_tsa));
154 static void mlx5e_build_tc_group(struct ieee_ets *ets, u8 *tc_group, int max_tc)
156 bool any_tc_mapped_to_ets = false;
157 bool ets_zero_bw = false;
161 for (i = 0; i <= max_tc; i++) {
162 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) {
163 any_tc_mapped_to_ets = true;
164 if (!ets->tc_tx_bw[i])
169 /* strict group has higher priority than ets group */
170 strict_group = MLX5E_LOWEST_PRIO_GROUP;
171 if (any_tc_mapped_to_ets)
176 for (i = 0; i <= max_tc; i++) {
177 switch (ets->tc_tsa[i]) {
178 case IEEE_8021QAZ_TSA_VENDOR:
179 tc_group[i] = MLX5E_VENDOR_TC_GROUP_NUM;
181 case IEEE_8021QAZ_TSA_STRICT:
182 tc_group[i] = strict_group++;
184 case IEEE_8021QAZ_TSA_ETS:
185 tc_group[i] = MLX5E_LOWEST_PRIO_GROUP;
186 if (ets->tc_tx_bw[i] && ets_zero_bw)
187 tc_group[i] = MLX5E_LOWEST_PRIO_GROUP + 1;
193 static void mlx5e_build_tc_tx_bw(struct ieee_ets *ets, u8 *tc_tx_bw,
194 u8 *tc_group, int max_tc)
196 int bw_for_ets_zero_bw_tc = 0;
197 int last_ets_zero_bw_tc = -1;
198 int num_ets_zero_bw = 0;
201 for (i = 0; i <= max_tc; i++) {
202 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS &&
205 last_ets_zero_bw_tc = i;
210 bw_for_ets_zero_bw_tc = MLX5E_MAX_BW_ALLOC / num_ets_zero_bw;
212 for (i = 0; i <= max_tc; i++) {
213 switch (ets->tc_tsa[i]) {
214 case IEEE_8021QAZ_TSA_VENDOR:
215 tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
217 case IEEE_8021QAZ_TSA_STRICT:
218 tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
220 case IEEE_8021QAZ_TSA_ETS:
221 tc_tx_bw[i] = ets->tc_tx_bw[i] ?
223 bw_for_ets_zero_bw_tc;
228 /* Make sure the total bw for ets zero bw group is 100% */
229 if (last_ets_zero_bw_tc != -1)
230 tc_tx_bw[last_ets_zero_bw_tc] +=
231 MLX5E_MAX_BW_ALLOC % num_ets_zero_bw;
234 /* If there are ETS BW 0,
235 * Set ETS group # to 1 for all ETS non zero BW tcs. Their sum must be 100%.
236 * Set group #0 to all the ETS BW 0 tcs and
237 * equally splits the 100% BW between them
238 * Report both group #0 and #1 as ETS type.
239 * All the tcs in group #0 will be reported with 0% BW.
241 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets)
243 struct mlx5_core_dev *mdev = priv->mdev;
244 u8 tc_tx_bw[IEEE_8021QAZ_MAX_TCS];
245 u8 tc_group[IEEE_8021QAZ_MAX_TCS];
246 int max_tc = mlx5_max_tc(mdev);
249 mlx5e_build_tc_group(ets, tc_group, max_tc);
250 mlx5e_build_tc_tx_bw(ets, tc_tx_bw, tc_group, max_tc);
252 err = mlx5_set_port_prio_tc(mdev, ets->prio_tc);
256 err = mlx5_set_port_tc_group(mdev, tc_group);
260 err = mlx5_set_port_tc_bw_alloc(mdev, tc_tx_bw);
265 memcpy(priv->dcbx.tc_tsa, ets->tc_tsa, sizeof(ets->tc_tsa));
267 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
268 mlx5e_dbg(HW, priv, "%s: prio_%d <=> tc_%d\n",
269 __func__, i, ets->prio_tc[i]);
270 mlx5e_dbg(HW, priv, "%s: tc_%d <=> tx_bw_%d%%, group_%d\n",
271 __func__, i, tc_tx_bw[i], tc_group[i]);
277 static int mlx5e_dbcnl_validate_ets(struct net_device *netdev,
278 struct ieee_ets *ets)
280 bool have_ets_tc = false;
284 /* Validate Priority */
285 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
286 if (ets->prio_tc[i] >= MLX5E_MAX_PRIORITY) {
288 "Failed to validate ETS: priority value greater than max(%d)\n",
294 /* Validate Bandwidth Sum */
295 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
296 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) {
298 bw_sum += ets->tc_tx_bw[i];
302 if (have_ets_tc && bw_sum != 100) {
304 "Failed to validate ETS: BW sum is illegal\n");
310 static int mlx5e_dcbnl_ieee_setets(struct net_device *netdev,
311 struct ieee_ets *ets)
313 struct mlx5e_priv *priv = netdev_priv(netdev);
316 if (!MLX5_CAP_GEN(priv->mdev, ets))
319 err = mlx5e_dbcnl_validate_ets(netdev, ets);
323 err = mlx5e_dcbnl_ieee_setets_core(priv, ets);
330 static int mlx5e_dcbnl_ieee_getpfc(struct net_device *dev,
331 struct ieee_pfc *pfc)
333 struct mlx5e_priv *priv = netdev_priv(dev);
334 struct mlx5_core_dev *mdev = priv->mdev;
335 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
338 pfc->pfc_cap = mlx5_max_tc(mdev) + 1;
339 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
340 pfc->requests[i] = PPORT_PER_PRIO_GET(pstats, i, tx_pause);
341 pfc->indications[i] = PPORT_PER_PRIO_GET(pstats, i, rx_pause);
344 if (MLX5_BUFFER_SUPPORTED(mdev))
345 pfc->delay = priv->dcbx.cable_len;
347 return mlx5_query_port_pfc(mdev, &pfc->pfc_en, NULL);
350 static int mlx5e_dcbnl_ieee_setpfc(struct net_device *dev,
351 struct ieee_pfc *pfc)
353 struct mlx5e_priv *priv = netdev_priv(dev);
354 struct mlx5_core_dev *mdev = priv->mdev;
355 u32 old_cable_len = priv->dcbx.cable_len;
356 struct ieee_pfc pfc_new;
362 mlx5_query_port_pfc(mdev, &curr_pfc_en, NULL);
363 if (pfc->pfc_en != curr_pfc_en) {
364 ret = mlx5_set_port_pfc(mdev, pfc->pfc_en, pfc->pfc_en);
367 mlx5_toggle_port_link(mdev);
368 changed |= MLX5E_PORT_BUFFER_PFC;
372 pfc->delay < MLX5E_MAX_CABLE_LENGTH &&
373 pfc->delay != priv->dcbx.cable_len) {
374 priv->dcbx.cable_len = pfc->delay;
375 changed |= MLX5E_PORT_BUFFER_CABLE_LEN;
378 if (MLX5_BUFFER_SUPPORTED(mdev)) {
379 pfc_new.pfc_en = (changed & MLX5E_PORT_BUFFER_PFC) ? pfc->pfc_en : curr_pfc_en;
380 if (priv->dcbx.manual_buffer)
381 ret = mlx5e_port_manual_buffer_config(priv, changed,
385 if (ret && (changed & MLX5E_PORT_BUFFER_CABLE_LEN))
386 priv->dcbx.cable_len = old_cable_len;
391 "%s: PFC per priority bit mask: 0x%x\n",
392 __func__, pfc->pfc_en);
397 static u8 mlx5e_dcbnl_getdcbx(struct net_device *dev)
399 struct mlx5e_priv *priv = netdev_priv(dev);
401 return priv->dcbx.cap;
404 static u8 mlx5e_dcbnl_setdcbx(struct net_device *dev, u8 mode)
406 struct mlx5e_priv *priv = netdev_priv(dev);
407 struct mlx5e_dcbx *dcbx = &priv->dcbx;
409 if (mode & DCB_CAP_DCBX_LLD_MANAGED)
412 if ((!mode) && MLX5_CAP_GEN(priv->mdev, dcbx)) {
413 if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_AUTO)
416 /* set dcbx to fw controlled */
417 if (!mlx5e_dcbnl_set_dcbx_mode(priv, MLX5E_DCBX_PARAM_VER_OPER_AUTO)) {
418 dcbx->mode = MLX5E_DCBX_PARAM_VER_OPER_AUTO;
419 dcbx->cap &= ~DCB_CAP_DCBX_HOST;
426 if (!(mode & DCB_CAP_DCBX_HOST))
429 if (mlx5e_dcbnl_switch_to_host_mode(netdev_priv(dev)))
437 static int mlx5e_dcbnl_ieee_setapp(struct net_device *dev, struct dcb_app *app)
439 struct mlx5e_priv *priv = netdev_priv(dev);
444 if (app->selector != IEEE_8021QAZ_APP_SEL_DSCP)
447 if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager))
450 if (!MLX5_DSCP_SUPPORTED(priv->mdev))
453 if (app->protocol >= MLX5E_MAX_DSCP)
456 /* Save the old entry info */
457 temp.selector = IEEE_8021QAZ_APP_SEL_DSCP;
458 temp.protocol = app->protocol;
459 temp.priority = priv->dcbx_dp.dscp2prio[app->protocol];
461 /* Check if need to switch to dscp trust state */
462 if (!priv->dcbx.dscp_app_cnt) {
463 err = mlx5e_set_trust_state(priv, MLX5_QPTS_TRUST_DSCP);
468 /* Skip the fw command if new and old mapping are the same */
469 if (app->priority != priv->dcbx_dp.dscp2prio[app->protocol]) {
470 err = mlx5e_set_dscp2prio(priv, app->protocol, app->priority);
475 /* Delete the old entry if exists */
477 err = dcb_ieee_delapp(dev, &temp);
481 /* Add new entry and update counter */
482 err = dcb_ieee_setapp(dev, app);
487 priv->dcbx.dscp_app_cnt++;
492 mlx5e_set_trust_state(priv, MLX5_QPTS_TRUST_PCP);
496 static int mlx5e_dcbnl_ieee_delapp(struct net_device *dev, struct dcb_app *app)
498 struct mlx5e_priv *priv = netdev_priv(dev);
501 if (app->selector != IEEE_8021QAZ_APP_SEL_DSCP)
504 if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager))
507 if (!MLX5_DSCP_SUPPORTED(priv->mdev))
510 if (app->protocol >= MLX5E_MAX_DSCP)
513 /* Skip if no dscp app entry */
514 if (!priv->dcbx.dscp_app_cnt)
517 /* Check if the entry matches fw setting */
518 if (app->priority != priv->dcbx_dp.dscp2prio[app->protocol])
521 /* Delete the app entry */
522 err = dcb_ieee_delapp(dev, app);
526 /* Reset the priority mapping back to zero */
527 err = mlx5e_set_dscp2prio(priv, app->protocol, 0);
531 priv->dcbx.dscp_app_cnt--;
533 /* Check if need to switch to pcp trust state */
534 if (!priv->dcbx.dscp_app_cnt)
535 err = mlx5e_set_trust_state(priv, MLX5_QPTS_TRUST_PCP);
540 mlx5e_set_trust_state(priv, MLX5_QPTS_TRUST_PCP);
544 static int mlx5e_dcbnl_ieee_getmaxrate(struct net_device *netdev,
545 struct ieee_maxrate *maxrate)
547 struct mlx5e_priv *priv = netdev_priv(netdev);
548 struct mlx5_core_dev *mdev = priv->mdev;
549 u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
550 u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
554 err = mlx5_query_port_ets_rate_limit(mdev, max_bw_value, max_bw_unit);
558 memset(maxrate->tc_maxrate, 0, sizeof(maxrate->tc_maxrate));
560 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
561 switch (max_bw_unit[i]) {
562 case MLX5_100_MBPS_UNIT:
563 maxrate->tc_maxrate[i] = max_bw_value[i] * MLX5E_100MB;
566 maxrate->tc_maxrate[i] = max_bw_value[i] * MLX5E_1GB;
568 case MLX5_BW_NO_LIMIT:
571 WARN(true, "non-supported BW unit");
579 static int mlx5e_dcbnl_ieee_setmaxrate(struct net_device *netdev,
580 struct ieee_maxrate *maxrate)
582 struct mlx5e_priv *priv = netdev_priv(netdev);
583 struct mlx5_core_dev *mdev = priv->mdev;
584 u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
585 u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
586 __u64 upper_limit_mbps = roundup(255 * MLX5E_100MB, MLX5E_1GB);
589 memset(max_bw_value, 0, sizeof(max_bw_value));
590 memset(max_bw_unit, 0, sizeof(max_bw_unit));
592 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
593 if (!maxrate->tc_maxrate[i]) {
594 max_bw_unit[i] = MLX5_BW_NO_LIMIT;
597 if (maxrate->tc_maxrate[i] < upper_limit_mbps) {
598 max_bw_value[i] = div_u64(maxrate->tc_maxrate[i],
600 max_bw_value[i] = max_bw_value[i] ? max_bw_value[i] : 1;
601 max_bw_unit[i] = MLX5_100_MBPS_UNIT;
603 max_bw_value[i] = div_u64(maxrate->tc_maxrate[i],
605 max_bw_unit[i] = MLX5_GBPS_UNIT;
609 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
610 mlx5e_dbg(HW, priv, "%s: tc_%d <=> max_bw %d Gbps\n",
611 __func__, i, max_bw_value[i]);
614 return mlx5_modify_port_ets_rate_limit(mdev, max_bw_value, max_bw_unit);
617 static u8 mlx5e_dcbnl_setall(struct net_device *netdev)
619 struct mlx5e_priv *priv = netdev_priv(netdev);
620 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
621 struct mlx5_core_dev *mdev = priv->mdev;
624 int err = -EOPNOTSUPP;
627 if (!MLX5_CAP_GEN(mdev, ets))
630 memset(&ets, 0, sizeof(ets));
631 memset(&pfc, 0, sizeof(pfc));
633 ets.ets_cap = IEEE_8021QAZ_MAX_TCS;
634 for (i = 0; i < CEE_DCBX_MAX_PGS; i++) {
635 ets.tc_tx_bw[i] = cee_cfg->pg_bw_pct[i];
636 ets.tc_rx_bw[i] = cee_cfg->pg_bw_pct[i];
637 ets.tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
638 ets.prio_tc[i] = cee_cfg->prio_to_pg_map[i];
640 "%s: Priority group %d: tx_bw %d, rx_bw %d, prio_tc %d\n",
641 __func__, i, ets.tc_tx_bw[i], ets.tc_rx_bw[i],
645 err = mlx5e_dbcnl_validate_ets(netdev, &ets);
648 "%s, Failed to validate ETS: %d\n", __func__, err);
652 err = mlx5e_dcbnl_ieee_setets_core(priv, &ets);
655 "%s, Failed to set ETS: %d\n", __func__, err);
660 pfc.pfc_cap = mlx5_max_tc(mdev) + 1;
661 if (!cee_cfg->pfc_enable)
664 for (i = 0; i < CEE_DCBX_MAX_PRIO; i++)
665 pfc.pfc_en |= cee_cfg->pfc_setting[i] << i;
667 err = mlx5e_dcbnl_ieee_setpfc(netdev, &pfc);
670 "%s, Failed to set PFC: %d\n", __func__, err);
674 return err ? MLX5_DCB_NO_CHG : MLX5_DCB_CHG_RESET;
677 static u8 mlx5e_dcbnl_getstate(struct net_device *netdev)
679 return MLX5E_CEE_STATE_UP;
682 static void mlx5e_dcbnl_getpermhwaddr(struct net_device *netdev,
685 struct mlx5e_priv *priv = netdev_priv(netdev);
690 memset(perm_addr, 0xff, MAX_ADDR_LEN);
692 mlx5_query_nic_vport_mac_address(priv->mdev, 0, perm_addr);
695 static void mlx5e_dcbnl_setpgtccfgtx(struct net_device *netdev,
696 int priority, u8 prio_type,
697 u8 pgid, u8 bw_pct, u8 up_map)
699 struct mlx5e_priv *priv = netdev_priv(netdev);
700 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
702 if (priority >= CEE_DCBX_MAX_PRIO) {
704 "%s, priority is out of range\n", __func__);
708 if (pgid >= CEE_DCBX_MAX_PGS) {
710 "%s, priority group is out of range\n", __func__);
714 cee_cfg->prio_to_pg_map[priority] = pgid;
717 static void mlx5e_dcbnl_setpgbwgcfgtx(struct net_device *netdev,
720 struct mlx5e_priv *priv = netdev_priv(netdev);
721 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
723 if (pgid >= CEE_DCBX_MAX_PGS) {
725 "%s, priority group is out of range\n", __func__);
729 cee_cfg->pg_bw_pct[pgid] = bw_pct;
732 static void mlx5e_dcbnl_getpgtccfgtx(struct net_device *netdev,
733 int priority, u8 *prio_type,
734 u8 *pgid, u8 *bw_pct, u8 *up_map)
736 struct mlx5e_priv *priv = netdev_priv(netdev);
737 struct mlx5_core_dev *mdev = priv->mdev;
739 if (!MLX5_CAP_GEN(priv->mdev, ets)) {
740 netdev_err(netdev, "%s, ets is not supported\n", __func__);
744 if (priority >= CEE_DCBX_MAX_PRIO) {
746 "%s, priority is out of range\n", __func__);
754 if (mlx5_query_port_prio_tc(mdev, priority, pgid))
758 static void mlx5e_dcbnl_getpgbwgcfgtx(struct net_device *netdev,
759 int pgid, u8 *bw_pct)
763 if (pgid >= CEE_DCBX_MAX_PGS) {
765 "%s, priority group is out of range\n", __func__);
769 mlx5e_dcbnl_ieee_getets(netdev, &ets);
770 *bw_pct = ets.tc_tx_bw[pgid];
773 static void mlx5e_dcbnl_setpfccfg(struct net_device *netdev,
774 int priority, u8 setting)
776 struct mlx5e_priv *priv = netdev_priv(netdev);
777 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
779 if (priority >= CEE_DCBX_MAX_PRIO) {
781 "%s, priority is out of range\n", __func__);
788 cee_cfg->pfc_setting[priority] = setting;
792 mlx5e_dcbnl_get_priority_pfc(struct net_device *netdev,
793 int priority, u8 *setting)
798 err = mlx5e_dcbnl_ieee_getpfc(netdev, &pfc);
803 *setting = (pfc.pfc_en >> priority) & 0x01;
808 static void mlx5e_dcbnl_getpfccfg(struct net_device *netdev,
809 int priority, u8 *setting)
811 if (priority >= CEE_DCBX_MAX_PRIO) {
813 "%s, priority is out of range\n", __func__);
820 mlx5e_dcbnl_get_priority_pfc(netdev, priority, setting);
823 static u8 mlx5e_dcbnl_getcap(struct net_device *netdev,
826 struct mlx5e_priv *priv = netdev_priv(netdev);
827 struct mlx5_core_dev *mdev = priv->mdev;
831 case DCB_CAP_ATTR_PG:
834 case DCB_CAP_ATTR_PFC:
837 case DCB_CAP_ATTR_UP2TC:
840 case DCB_CAP_ATTR_PG_TCS:
841 *cap = 1 << mlx5_max_tc(mdev);
843 case DCB_CAP_ATTR_PFC_TCS:
844 *cap = 1 << mlx5_max_tc(mdev);
846 case DCB_CAP_ATTR_GSP:
849 case DCB_CAP_ATTR_BCN:
852 case DCB_CAP_ATTR_DCBX:
853 *cap = priv->dcbx.cap |
854 DCB_CAP_DCBX_VER_CEE |
855 DCB_CAP_DCBX_VER_IEEE;
866 static int mlx5e_dcbnl_getnumtcs(struct net_device *netdev,
869 struct mlx5e_priv *priv = netdev_priv(netdev);
870 struct mlx5_core_dev *mdev = priv->mdev;
873 case DCB_NUMTCS_ATTR_PG:
874 case DCB_NUMTCS_ATTR_PFC:
875 *num = mlx5_max_tc(mdev) + 1;
884 static u8 mlx5e_dcbnl_getpfcstate(struct net_device *netdev)
888 if (mlx5e_dcbnl_ieee_getpfc(netdev, &pfc))
889 return MLX5E_CEE_STATE_DOWN;
891 return pfc.pfc_en ? MLX5E_CEE_STATE_UP : MLX5E_CEE_STATE_DOWN;
894 static void mlx5e_dcbnl_setpfcstate(struct net_device *netdev, u8 state)
896 struct mlx5e_priv *priv = netdev_priv(netdev);
897 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
899 if ((state != MLX5E_CEE_STATE_UP) && (state != MLX5E_CEE_STATE_DOWN))
902 cee_cfg->pfc_enable = state;
905 static int mlx5e_dcbnl_getbuffer(struct net_device *dev,
906 struct dcbnl_buffer *dcb_buffer)
908 struct mlx5e_priv *priv = netdev_priv(dev);
909 struct mlx5_core_dev *mdev = priv->mdev;
910 struct mlx5e_port_buffer port_buffer;
911 u8 buffer[MLX5E_MAX_PRIORITY];
914 if (!MLX5_BUFFER_SUPPORTED(mdev))
917 err = mlx5e_port_query_priority2buffer(mdev, buffer);
921 for (i = 0; i < MLX5E_MAX_PRIORITY; i++)
922 dcb_buffer->prio2buffer[i] = buffer[i];
924 err = mlx5e_port_query_buffer(priv, &port_buffer);
928 for (i = 0; i < MLX5E_MAX_BUFFER; i++)
929 dcb_buffer->buffer_size[i] = port_buffer.buffer[i].size;
930 dcb_buffer->total_size = port_buffer.port_buffer_size;
935 static int mlx5e_dcbnl_setbuffer(struct net_device *dev,
936 struct dcbnl_buffer *dcb_buffer)
938 struct mlx5e_priv *priv = netdev_priv(dev);
939 struct mlx5_core_dev *mdev = priv->mdev;
940 struct mlx5e_port_buffer port_buffer;
941 u8 old_prio2buffer[MLX5E_MAX_PRIORITY];
942 u32 *buffer_size = NULL;
943 u8 *prio2buffer = NULL;
947 if (!MLX5_BUFFER_SUPPORTED(mdev))
950 for (i = 0; i < DCBX_MAX_BUFFERS; i++)
951 mlx5_core_dbg(mdev, "buffer[%d]=%d\n", i, dcb_buffer->buffer_size[i]);
953 for (i = 0; i < MLX5E_MAX_PRIORITY; i++)
954 mlx5_core_dbg(mdev, "priority %d buffer%d\n", i, dcb_buffer->prio2buffer[i]);
956 err = mlx5e_port_query_priority2buffer(mdev, old_prio2buffer);
960 for (i = 0; i < MLX5E_MAX_PRIORITY; i++) {
961 if (dcb_buffer->prio2buffer[i] != old_prio2buffer[i]) {
962 changed |= MLX5E_PORT_BUFFER_PRIO2BUFFER;
963 prio2buffer = dcb_buffer->prio2buffer;
968 err = mlx5e_port_query_buffer(priv, &port_buffer);
972 for (i = 0; i < MLX5E_MAX_BUFFER; i++) {
973 if (port_buffer.buffer[i].size != dcb_buffer->buffer_size[i]) {
974 changed |= MLX5E_PORT_BUFFER_SIZE;
975 buffer_size = dcb_buffer->buffer_size;
983 priv->dcbx.manual_buffer = true;
984 err = mlx5e_port_manual_buffer_config(priv, changed, dev->mtu, NULL,
985 buffer_size, prio2buffer);
989 const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops = {
990 .ieee_getets = mlx5e_dcbnl_ieee_getets,
991 .ieee_setets = mlx5e_dcbnl_ieee_setets,
992 .ieee_getmaxrate = mlx5e_dcbnl_ieee_getmaxrate,
993 .ieee_setmaxrate = mlx5e_dcbnl_ieee_setmaxrate,
994 .ieee_getpfc = mlx5e_dcbnl_ieee_getpfc,
995 .ieee_setpfc = mlx5e_dcbnl_ieee_setpfc,
996 .ieee_setapp = mlx5e_dcbnl_ieee_setapp,
997 .ieee_delapp = mlx5e_dcbnl_ieee_delapp,
998 .getdcbx = mlx5e_dcbnl_getdcbx,
999 .setdcbx = mlx5e_dcbnl_setdcbx,
1000 .dcbnl_getbuffer = mlx5e_dcbnl_getbuffer,
1001 .dcbnl_setbuffer = mlx5e_dcbnl_setbuffer,
1003 /* CEE interfaces */
1004 .setall = mlx5e_dcbnl_setall,
1005 .getstate = mlx5e_dcbnl_getstate,
1006 .getpermhwaddr = mlx5e_dcbnl_getpermhwaddr,
1008 .setpgtccfgtx = mlx5e_dcbnl_setpgtccfgtx,
1009 .setpgbwgcfgtx = mlx5e_dcbnl_setpgbwgcfgtx,
1010 .getpgtccfgtx = mlx5e_dcbnl_getpgtccfgtx,
1011 .getpgbwgcfgtx = mlx5e_dcbnl_getpgbwgcfgtx,
1013 .setpfccfg = mlx5e_dcbnl_setpfccfg,
1014 .getpfccfg = mlx5e_dcbnl_getpfccfg,
1015 .getcap = mlx5e_dcbnl_getcap,
1016 .getnumtcs = mlx5e_dcbnl_getnumtcs,
1017 .getpfcstate = mlx5e_dcbnl_getpfcstate,
1018 .setpfcstate = mlx5e_dcbnl_setpfcstate,
1021 static void mlx5e_dcbnl_query_dcbx_mode(struct mlx5e_priv *priv,
1022 enum mlx5_dcbx_oper_mode *mode)
1024 u32 out[MLX5_ST_SZ_DW(dcbx_param)];
1026 *mode = MLX5E_DCBX_PARAM_VER_OPER_HOST;
1028 if (!mlx5_query_port_dcbx_param(priv->mdev, out))
1029 *mode = MLX5_GET(dcbx_param, out, version_oper);
1031 /* From driver's point of view, we only care if the mode
1032 * is host (HOST) or non-host (AUTO)
1034 if (*mode != MLX5E_DCBX_PARAM_VER_OPER_HOST)
1035 *mode = MLX5E_DCBX_PARAM_VER_OPER_AUTO;
1038 static void mlx5e_ets_init(struct mlx5e_priv *priv)
1040 struct ieee_ets ets;
1044 if (!MLX5_CAP_GEN(priv->mdev, ets))
1047 memset(&ets, 0, sizeof(ets));
1048 ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
1049 for (i = 0; i < ets.ets_cap; i++) {
1050 ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
1051 ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
1055 if (ets.ets_cap > 1) {
1056 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
1061 err = mlx5e_dcbnl_ieee_setets_core(priv, &ets);
1063 netdev_err(priv->netdev,
1064 "%s, Failed to init ETS: %d\n", __func__, err);
1072 static void mlx5e_dcbnl_dscp_app(struct mlx5e_priv *priv, int action)
1074 struct dcb_app temp;
1077 if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager))
1080 if (!MLX5_DSCP_SUPPORTED(priv->mdev))
1083 /* No SEL_DSCP entry in non DSCP state */
1084 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_DSCP)
1087 temp.selector = IEEE_8021QAZ_APP_SEL_DSCP;
1088 for (i = 0; i < MLX5E_MAX_DSCP; i++) {
1090 temp.priority = priv->dcbx_dp.dscp2prio[i];
1092 dcb_ieee_setapp(priv->netdev, &temp);
1094 dcb_ieee_delapp(priv->netdev, &temp);
1097 priv->dcbx.dscp_app_cnt = (action == INIT) ? MLX5E_MAX_DSCP : 0;
1100 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv)
1102 mlx5e_dcbnl_dscp_app(priv, INIT);
1105 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv)
1107 mlx5e_dcbnl_dscp_app(priv, DELETE);
1110 static void mlx5e_trust_update_tx_min_inline_mode(struct mlx5e_priv *priv,
1111 struct mlx5e_params *params)
1113 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(priv->mdev);
1114 if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_DSCP &&
1115 params->tx_min_inline_mode == MLX5_INLINE_MODE_L2)
1116 params->tx_min_inline_mode = MLX5_INLINE_MODE_IP;
1119 static void mlx5e_trust_update_sq_inline_mode(struct mlx5e_priv *priv)
1121 struct mlx5e_channels new_channels = {};
1123 mutex_lock(&priv->state_lock);
1125 new_channels.params = priv->channels.params;
1126 mlx5e_trust_update_tx_min_inline_mode(priv, &new_channels.params);
1128 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1129 priv->channels.params = new_channels.params;
1133 /* Skip if tx_min_inline is the same */
1134 if (new_channels.params.tx_min_inline_mode ==
1135 priv->channels.params.tx_min_inline_mode)
1138 if (mlx5e_open_channels(priv, &new_channels))
1140 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1143 mutex_unlock(&priv->state_lock);
1146 static int mlx5e_set_trust_state(struct mlx5e_priv *priv, u8 trust_state)
1150 err = mlx5_set_trust_state(priv->mdev, trust_state);
1153 priv->dcbx_dp.trust_state = trust_state;
1154 mlx5e_trust_update_sq_inline_mode(priv);
1159 static int mlx5e_set_dscp2prio(struct mlx5e_priv *priv, u8 dscp, u8 prio)
1163 err = mlx5_set_dscp2prio(priv->mdev, dscp, prio);
1167 priv->dcbx_dp.dscp2prio[dscp] = prio;
1171 static int mlx5e_trust_initialize(struct mlx5e_priv *priv)
1173 struct mlx5_core_dev *mdev = priv->mdev;
1176 if (!MLX5_DSCP_SUPPORTED(mdev))
1179 err = mlx5_query_trust_state(priv->mdev, &priv->dcbx_dp.trust_state);
1183 mlx5e_trust_update_tx_min_inline_mode(priv, &priv->channels.params);
1185 err = mlx5_query_dscp2prio(priv->mdev, priv->dcbx_dp.dscp2prio);
1192 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv)
1194 struct mlx5e_dcbx *dcbx = &priv->dcbx;
1196 mlx5e_trust_initialize(priv);
1198 if (!MLX5_CAP_GEN(priv->mdev, qos))
1201 if (MLX5_CAP_GEN(priv->mdev, dcbx))
1202 mlx5e_dcbnl_query_dcbx_mode(priv, &dcbx->mode);
1204 priv->dcbx.cap = DCB_CAP_DCBX_VER_CEE |
1205 DCB_CAP_DCBX_VER_IEEE;
1206 if (priv->dcbx.mode == MLX5E_DCBX_PARAM_VER_OPER_HOST)
1207 priv->dcbx.cap |= DCB_CAP_DCBX_HOST;
1209 priv->dcbx.manual_buffer = false;
1210 priv->dcbx.cable_len = MLX5E_DEFAULT_CABLE_LEN;
1212 mlx5e_ets_init(priv);