2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
47 #include <net/switchdev.h>
49 #include "mlx5_core.h"
52 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
54 #define MLX5E_MAX_NUM_TC 8
56 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
57 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
58 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
60 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
61 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
62 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
64 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
65 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3
66 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
68 #define MLX5_RX_HEADROOM NET_SKB_PAD
70 #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
71 #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */
72 #define MLX5_MPWRQ_LOG_WQE_SZ 18
73 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
74 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
75 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
76 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
77 MLX5_MPWRQ_WQE_PAGE_ORDER)
79 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
80 #define MLX5E_REQUIRED_MTTS(wqes) \
81 (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
82 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX)
84 #define MLX5_UMR_ALIGN (2048)
85 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
87 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
88 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
89 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
91 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
92 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
93 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
94 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
95 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
96 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
97 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
99 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
100 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
101 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
102 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
103 #define MLX5E_TX_CQ_POLL_BUDGET 128
104 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
105 #define MLX5E_SQ_BF_BUDGET 16
107 #define MLX5E_ICOSQ_MAX_WQEBBS \
108 (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))
110 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
111 #define MLX5E_XDP_IHS_DS_COUNT \
112 DIV_ROUND_UP(MLX5E_XDP_MIN_INLINE - 2, MLX5_SEND_WQE_DS)
113 #define MLX5E_XDP_TX_DS_COUNT \
114 (MLX5E_XDP_IHS_DS_COUNT + \
115 (sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)
116 #define MLX5E_XDP_TX_WQEBBS \
117 DIV_ROUND_UP(MLX5E_XDP_TX_DS_COUNT, MLX5_SEND_WQEBB_NUM_DS)
119 #define MLX5E_NUM_MAIN_GROUPS 9
121 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
124 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
125 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
128 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
133 static inline int mlx5_min_log_rq_size(int wq_type)
136 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
137 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
139 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
143 static inline int mlx5_max_log_rq_size(int wq_type)
146 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
147 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
149 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
153 struct mlx5e_tx_wqe {
154 struct mlx5_wqe_ctrl_seg ctrl;
155 struct mlx5_wqe_eth_seg eth;
158 struct mlx5e_rx_wqe {
159 struct mlx5_wqe_srq_next_seg next;
160 struct mlx5_wqe_data_seg data;
163 struct mlx5e_umr_wqe {
164 struct mlx5_wqe_ctrl_seg ctrl;
165 struct mlx5_wqe_umr_ctrl_seg uctrl;
166 struct mlx5_mkey_seg mkc;
167 struct mlx5_wqe_data_seg data;
170 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
172 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
177 enum mlx5e_priv_flag {
178 MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
179 MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1),
182 #define MLX5E_SET_PFLAG(priv, pflag, enable) \
185 (priv)->params.pflags |= (pflag); \
187 (priv)->params.pflags &= ~(pflag); \
190 #define MLX5E_GET_PFLAG(priv, pflag) (!!((priv)->params.pflags & (pflag)))
192 #ifdef CONFIG_MLX5_CORE_EN_DCB
193 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
196 struct mlx5e_cq_moder {
201 struct mlx5e_params {
204 u8 mpwqe_log_stride_sz;
205 u8 mpwqe_log_num_strides;
209 u8 rx_cq_period_mode;
210 bool rx_cqe_compress_def;
211 struct mlx5e_cq_moder rx_cq_moderation;
212 struct mlx5e_cq_moder tx_cq_moderation;
217 u8 tx_min_inline_mode;
219 u8 toeplitz_hash_key[40];
220 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
221 bool vlan_strip_disable;
227 #ifdef CONFIG_MLX5_CORE_EN_DCB
228 struct mlx5e_cee_config {
229 /* bw pct for priority group */
230 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
231 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
232 bool pfc_setting[CEE_DCBX_MAX_PRIO];
239 MLX5_DCB_CHG_NO_RESET,
243 enum mlx5_dcbx_oper_mode mode;
244 struct mlx5e_cee_config cee_cfg; /* pending configuration */
246 /* The only setting that cannot be read from FW */
247 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
251 struct mlx5e_tstamp {
253 struct cyclecounter cycles;
254 struct timecounter clock;
255 struct hwtstamp_config hwtstamp_config;
257 unsigned long overflow_period;
258 struct delayed_work overflow_work;
259 struct mlx5_core_dev *mdev;
260 struct ptp_clock *ptp;
261 struct ptp_clock_info ptp_info;
265 MLX5E_RQ_STATE_ENABLED,
266 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
271 /* data path - accessed per cqe */
274 /* data path - accessed per napi poll */
276 struct napi_struct *napi;
277 struct mlx5_core_cq mcq;
278 struct mlx5e_channel *channel;
279 struct mlx5e_priv *priv;
281 /* cqe decompression */
282 struct mlx5_cqe64 title;
283 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
286 u16 decmprs_wqe_counter;
289 struct mlx5_frag_wq_ctrl wq_ctrl;
290 } ____cacheline_aligned_in_smp;
293 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
294 struct mlx5_cqe64 *cqe);
295 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
298 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix);
300 struct mlx5e_dma_info {
305 struct mlx5e_rx_am_stats {
306 int ppms; /* packets per msec */
307 int epms; /* events per msec */
310 struct mlx5e_rx_am_sample {
312 unsigned int pkt_ctr;
316 struct mlx5e_rx_am { /* Adaptive Moderation */
318 struct mlx5e_rx_am_stats prev_stats;
319 struct mlx5e_rx_am_sample start_sample;
320 struct work_struct work;
329 /* a single cache unit is capable to serve one napi call (for non-striding rq)
330 * or a MPWQE (for striding rq).
332 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
333 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
334 #define MLX5E_CACHE_SIZE (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
335 struct mlx5e_page_cache {
338 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
343 struct mlx5_wq_ll wq;
346 struct mlx5e_dma_info *dma_info;
348 struct mlx5e_mpw_info *info;
354 u32 wqe_sz; /* wqe data buffer size */
355 u8 map_dir; /* dma map direction */
360 struct net_device *netdev;
361 struct mlx5e_tstamp *tstamp;
362 struct mlx5e_rq_stats stats;
364 struct mlx5e_page_cache page_cache;
366 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
367 mlx5e_fp_alloc_wqe alloc_wqe;
368 mlx5e_fp_dealloc_wqe dealloc_wqe;
373 struct mlx5e_rx_am am; /* Adaptive Moderation */
374 struct bpf_prog *xdp_prog;
377 struct mlx5_wq_ctrl wq_ctrl;
380 u32 mpwqe_num_strides;
382 struct mlx5e_channel *channel;
383 struct mlx5e_priv *priv;
384 struct mlx5_core_mkey umr_mkey;
385 } ____cacheline_aligned_in_smp;
387 struct mlx5e_umr_dma_info {
390 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
391 struct mlx5e_umr_wqe wqe;
394 struct mlx5e_mpw_info {
395 struct mlx5e_umr_dma_info umr;
396 u16 consumed_strides;
397 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
400 struct mlx5e_tx_wqe_info {
406 enum mlx5e_dma_map_type {
407 MLX5E_DMA_MAP_SINGLE,
411 struct mlx5e_sq_dma {
414 enum mlx5e_dma_map_type type;
418 MLX5E_SQ_STATE_ENABLED,
419 MLX5E_SQ_STATE_BF_ENABLE,
422 struct mlx5e_sq_wqe_info {
436 /* dirtied @completion */
441 u16 pc ____cacheline_aligned_in_smp;
446 struct mlx5e_sq_stats stats;
450 /* pointers to per tx element info: write@xmit, read@completion */
453 struct sk_buff **skb;
454 struct mlx5e_sq_dma *dma_fifo;
455 struct mlx5e_tx_wqe_info *wqe_info;
457 struct mlx5e_sq_wqe_info *ico_wqe;
459 struct mlx5e_sq_wqe_info *wqe_info;
460 struct mlx5e_dma_info *di;
466 struct mlx5_wq_cyc wq;
468 void __iomem *uar_map;
469 struct netdev_queue *txq;
476 struct mlx5e_tstamp *tstamp;
481 struct mlx5_wq_ctrl wq_ctrl;
483 struct mlx5e_channel *channel;
487 } ____cacheline_aligned_in_smp;
489 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
491 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
496 MLX5E_CHANNEL_NAPI_SCHED = 1,
499 struct mlx5e_channel {
502 struct mlx5e_sq xdp_sq;
503 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
504 struct mlx5e_sq icosq; /* internal control operations */
506 struct napi_struct napi;
508 struct net_device *netdev;
514 struct mlx5e_priv *priv;
519 enum mlx5e_traffic_types {
524 MLX5E_TT_IPV4_IPSEC_AH,
525 MLX5E_TT_IPV6_IPSEC_AH,
526 MLX5E_TT_IPV4_IPSEC_ESP,
527 MLX5E_TT_IPV6_IPSEC_ESP,
532 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
536 MLX5E_STATE_ASYNC_EVENTS_ENABLED,
538 MLX5E_STATE_DESTROYING,
541 struct mlx5e_vxlan_db {
542 spinlock_t lock; /* protect vxlan table */
543 struct radix_tree_root tree;
546 struct mlx5e_l2_rule {
547 u8 addr[ETH_ALEN + 2];
548 struct mlx5_flow_handle *rule;
551 struct mlx5e_flow_table {
553 struct mlx5_flow_table *t;
554 struct mlx5_flow_group **g;
557 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
559 struct mlx5e_tc_table {
560 struct mlx5_flow_table *t;
562 struct rhashtable_params ht_params;
563 struct rhashtable ht;
566 struct mlx5e_vlan_table {
567 struct mlx5e_flow_table ft;
568 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
569 struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID];
570 struct mlx5_flow_handle *untagged_rule;
571 struct mlx5_flow_handle *any_vlan_rule;
572 bool filter_disabled;
575 struct mlx5e_l2_table {
576 struct mlx5e_flow_table ft;
577 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
578 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
579 struct mlx5e_l2_rule broadcast;
580 struct mlx5e_l2_rule allmulti;
581 struct mlx5e_l2_rule promisc;
582 bool broadcast_enabled;
583 bool allmulti_enabled;
584 bool promisc_enabled;
587 /* L3/L4 traffic type classifier */
588 struct mlx5e_ttc_table {
589 struct mlx5e_flow_table ft;
590 struct mlx5_flow_handle *rules[MLX5E_NUM_TT];
593 #define ARFS_HASH_SHIFT BITS_PER_BYTE
594 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
596 struct mlx5e_flow_table ft;
597 struct mlx5_flow_handle *default_rule;
598 struct hlist_head rules_hash[ARFS_HASH_SIZE];
609 struct mlx5e_arfs_tables {
610 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
611 /* Protect aRFS rules list */
612 spinlock_t arfs_lock;
613 struct list_head rules;
615 struct workqueue_struct *wq;
620 MLX5E_VLAN_FT_LEVEL = 0,
626 struct mlx5e_ethtool_table {
627 struct mlx5_flow_table *ft;
631 #define ETHTOOL_NUM_L3_L4_FTS 7
632 #define ETHTOOL_NUM_L2_FTS 4
634 struct mlx5e_ethtool_steering {
635 struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
636 struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS];
637 struct list_head rules;
641 struct mlx5e_flow_steering {
642 struct mlx5_flow_namespace *ns;
643 struct mlx5e_ethtool_steering ethtool;
644 struct mlx5e_tc_table tc;
645 struct mlx5e_vlan_table vlan;
646 struct mlx5e_l2_table l2;
647 struct mlx5e_ttc_table ttc;
648 struct mlx5e_arfs_tables arfs;
658 struct mlx5e_rqt rqt;
659 struct list_head list;
667 struct mlx5e_profile {
668 void (*init)(struct mlx5_core_dev *mdev,
669 struct net_device *netdev,
670 const struct mlx5e_profile *profile, void *ppriv);
671 void (*cleanup)(struct mlx5e_priv *priv);
672 int (*init_rx)(struct mlx5e_priv *priv);
673 void (*cleanup_rx)(struct mlx5e_priv *priv);
674 int (*init_tx)(struct mlx5e_priv *priv);
675 void (*cleanup_tx)(struct mlx5e_priv *priv);
676 void (*enable)(struct mlx5e_priv *priv);
677 void (*disable)(struct mlx5e_priv *priv);
678 void (*update_stats)(struct mlx5e_priv *priv);
679 int (*max_nch)(struct mlx5_core_dev *mdev);
684 /* priv data path fields - start */
685 struct mlx5e_sq **txq_to_sq_map;
686 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
687 struct bpf_prog *xdp_prog;
688 /* priv data path fields - end */
691 struct mutex state_lock; /* Protects Interface state */
692 struct mlx5e_rq drop_rq;
694 struct mlx5e_channel **channel;
695 u32 tisn[MLX5E_MAX_NUM_TC];
696 struct mlx5e_rqt indir_rqt;
697 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
698 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
699 u32 tx_rates[MLX5E_MAX_NUM_SQS];
701 struct mlx5e_flow_steering fs;
702 struct mlx5e_vxlan_db vxlan;
704 struct mlx5e_params params;
705 struct workqueue_struct *wq;
706 struct work_struct update_carrier_work;
707 struct work_struct set_rx_mode_work;
708 struct work_struct tx_timeout_work;
709 struct delayed_work update_stats_work;
711 struct mlx5_core_dev *mdev;
712 struct net_device *netdev;
713 struct mlx5e_stats stats;
714 struct mlx5e_tstamp tstamp;
716 #ifdef CONFIG_MLX5_CORE_EN_DCB
717 struct mlx5e_dcbx dcbx;
720 const struct mlx5e_profile *profile;
724 void mlx5e_build_ptys2ethtool_map(void);
726 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
727 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
728 void *accel_priv, select_queue_fallback_t fallback);
729 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
731 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
732 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
733 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
734 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
735 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
736 void mlx5e_free_sq_descs(struct mlx5e_sq *sq);
738 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
740 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
741 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
742 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
743 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
744 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
745 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
746 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
747 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq);
748 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
749 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
751 void mlx5e_rx_am(struct mlx5e_rq *rq);
752 void mlx5e_rx_am_work(struct work_struct *work);
753 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
755 void mlx5e_update_stats(struct mlx5e_priv *priv);
757 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
758 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
759 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
760 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
761 int mlx5e_self_test_num(struct mlx5e_priv *priv);
762 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
764 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
766 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
767 struct ethtool_rxnfc *info, u32 *rule_locs);
768 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
769 struct ethtool_rx_flow_spec *fs);
770 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
772 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
773 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
774 void mlx5e_set_rx_mode_work(struct work_struct *work);
776 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
777 struct skb_shared_hwtstamps *hwts);
778 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
779 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
780 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
781 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
782 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val);
784 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
786 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
788 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
789 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
791 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
793 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
794 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
796 int mlx5e_open_locked(struct net_device *netdev);
797 int mlx5e_close_locked(struct net_device *netdev);
798 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
799 u32 *indirection_rqt, int len,
801 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
803 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
806 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
807 struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
809 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
811 /* ensure wqe is visible to device before updating doorbell record */
814 *sq->wq.db = cpu_to_be32(sq->pc);
816 /* ensure doorbell record is visible to device before ringing the
821 __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
823 mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
824 /* flush the write-combining mapped buffer */
827 sq->bf_offset ^= sq->bf_buf_size;
830 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
832 struct mlx5_core_cq *mcq;
835 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
838 static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
840 return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
843 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
845 return min_t(int, mdev->priv.eq_table.num_comp_vectors,
846 MLX5E_MAX_NUM_CHANNELS);
849 extern const struct ethtool_ops mlx5e_ethtool_ops;
850 #ifdef CONFIG_MLX5_CORE_EN_DCB
851 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
852 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
853 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
856 #ifndef CONFIG_RFS_ACCEL
857 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
862 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
864 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
869 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
874 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
875 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
876 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
877 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
878 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
879 u16 rxq_index, u32 flow_id);
882 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
883 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
884 struct mlx5e_tir *tir, u32 *in, int inlen);
885 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
886 struct mlx5e_tir *tir);
887 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
888 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
889 int mlx5e_refresh_tirs_self_loopback(struct mlx5_core_dev *mdev,
892 struct mlx5_eswitch_rep;
893 int mlx5e_vport_rep_load(struct mlx5_eswitch *esw,
894 struct mlx5_eswitch_rep *rep);
895 void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw,
896 struct mlx5_eswitch_rep *rep);
897 int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep);
898 void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw,
899 struct mlx5_eswitch_rep *rep);
900 int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv);
901 void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv);
902 int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr);
903 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
904 void mlx5e_update_hw_rep_counters(struct mlx5e_priv *priv);
906 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
907 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
908 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
909 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
910 int mlx5e_create_tises(struct mlx5e_priv *priv);
911 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
912 int mlx5e_close(struct net_device *netdev);
913 int mlx5e_open(struct net_device *netdev);
914 void mlx5e_update_stats_work(struct work_struct *work);
915 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
916 const struct mlx5e_profile *profile,
918 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv);
919 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
920 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
921 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout);
922 void mlx5e_add_vxlan_port(struct net_device *netdev,
923 struct udp_tunnel_info *ti);
924 void mlx5e_del_vxlan_port(struct net_device *netdev,
925 struct udp_tunnel_info *ti);
927 int mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
929 bool mlx5e_has_offload_stats(const struct net_device *dev, int attr_id);
931 bool mlx5e_is_uplink_rep(struct mlx5e_priv *priv);
932 bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv);
933 #endif /* __MLX5_EN_H__ */