2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/rhashtable.h>
48 #include <net/switchdev.h>
50 #include "mlx5_core.h"
53 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
55 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
57 #define MLX5E_HW2SW_MTU(priv, hwmtu) ((hwmtu) - ((priv)->hard_mtu))
58 #define MLX5E_SW2HW_MTU(priv, swmtu) ((swmtu) + ((priv)->hard_mtu))
60 #define MLX5E_MAX_DSCP 64
61 #define MLX5E_MAX_NUM_TC 8
63 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
64 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
65 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
67 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
68 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
69 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
71 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
72 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3
73 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
75 #define MLX5_RX_HEADROOM NET_SKB_PAD
76 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
77 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
79 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
80 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
81 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
82 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
83 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6)
84 #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8)
85 #define MLX5E_MPWQE_STRIDE_SZ(mdev, cqe_cmprs) \
86 (cqe_cmprs ? MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) : \
87 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev))
89 #define MLX5_MPWRQ_LOG_WQE_SZ 18
90 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
91 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
92 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
93 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
94 MLX5_MPWRQ_WQE_PAGE_ORDER)
96 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
97 #define MLX5E_REQUIRED_MTTS(wqes) \
98 (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
99 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX)
101 #define MLX5_UMR_ALIGN (2048)
102 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (256)
104 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
105 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
106 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
108 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
109 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
110 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
111 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
112 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
113 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
114 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
115 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
117 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
118 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
119 #define MLX5E_MIN_NUM_CHANNELS 0x1
120 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
121 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
122 #define MLX5E_TX_CQ_POLL_BUDGET 128
123 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
125 #define MLX5E_ICOSQ_MAX_WQEBBS \
126 (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))
128 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
129 #define MLX5E_XDP_TX_DS_COUNT \
130 ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)
132 #define MLX5E_NUM_MAIN_GROUPS 9
134 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
136 #define mlx5e_dbg(mlevel, priv, format, ...) \
138 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
139 netdev_warn(priv->netdev, format, \
144 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
147 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
148 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
151 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
156 static inline int mlx5_min_log_rq_size(int wq_type)
159 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
160 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
162 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
166 static inline int mlx5_max_log_rq_size(int wq_type)
169 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
170 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
172 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
176 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
178 return is_kdump_kernel() ?
179 MLX5E_MIN_NUM_CHANNELS :
180 min_t(int, mdev->priv.eq_table.num_comp_vectors,
181 MLX5E_MAX_NUM_CHANNELS);
184 struct mlx5e_tx_wqe {
185 struct mlx5_wqe_ctrl_seg ctrl;
186 struct mlx5_wqe_eth_seg eth;
189 struct mlx5e_rx_wqe {
190 struct mlx5_wqe_srq_next_seg next;
191 struct mlx5_wqe_data_seg data;
194 struct mlx5e_umr_wqe {
195 struct mlx5_wqe_ctrl_seg ctrl;
196 struct mlx5_wqe_umr_ctrl_seg uctrl;
197 struct mlx5_mkey_seg mkc;
198 struct mlx5_wqe_data_seg data;
201 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
203 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
209 enum mlx5e_priv_flag {
210 MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
211 MLX5E_PFLAG_TX_CQE_BASED_MODER = (1 << 1),
212 MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 2),
215 #define MLX5E_SET_PFLAG(params, pflag, enable) \
218 (params)->pflags |= (pflag); \
220 (params)->pflags &= ~(pflag); \
223 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag)))
225 #ifdef CONFIG_MLX5_CORE_EN_DCB
226 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
229 struct mlx5e_cq_moder {
235 struct mlx5e_params {
239 u8 mpwqe_log_stride_sz;
240 u8 mpwqe_log_num_strides;
244 bool rx_cqe_compress_def;
245 struct mlx5e_cq_moder rx_cq_moderation;
246 struct mlx5e_cq_moder tx_cq_moderation;
250 u8 tx_min_inline_mode;
252 u8 toeplitz_hash_key[40];
253 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
254 bool vlan_strip_disable;
259 struct bpf_prog *xdp_prog;
262 #ifdef CONFIG_MLX5_CORE_EN_DCB
263 struct mlx5e_cee_config {
264 /* bw pct for priority group */
265 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
266 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
267 bool pfc_setting[CEE_DCBX_MAX_PRIO];
274 MLX5_DCB_CHG_NO_RESET,
278 enum mlx5_dcbx_oper_mode mode;
279 struct mlx5e_cee_config cee_cfg; /* pending configuration */
282 /* The only setting that cannot be read from FW */
283 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
287 struct mlx5e_dcbx_dp {
288 u8 dscp2prio[MLX5E_MAX_DSCP];
294 MLX5E_RQ_STATE_ENABLED,
298 #define MLX5E_TEST_BIT(state, nr) (state & BIT(nr))
301 /* data path - accessed per cqe */
304 /* data path - accessed per napi poll */
306 struct napi_struct *napi;
307 struct mlx5_core_cq mcq;
308 struct mlx5e_channel *channel;
310 /* cqe decompression */
311 struct mlx5_cqe64 title;
312 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
315 u16 decmprs_wqe_counter;
318 struct mlx5_core_dev *mdev;
319 struct mlx5_frag_wq_ctrl wq_ctrl;
320 } ____cacheline_aligned_in_smp;
322 struct mlx5e_tx_wqe_info {
329 enum mlx5e_dma_map_type {
330 MLX5E_DMA_MAP_SINGLE,
334 struct mlx5e_sq_dma {
337 enum mlx5e_dma_map_type type;
341 MLX5E_SQ_STATE_ENABLED,
342 MLX5E_SQ_STATE_IPSEC,
345 struct mlx5e_sq_wqe_info {
352 /* dirtied @completion */
357 u16 pc ____cacheline_aligned_in_smp;
359 struct mlx5e_sq_stats stats;
363 /* write@xmit, read@completion */
365 struct mlx5e_sq_dma *dma_fifo;
366 struct mlx5e_tx_wqe_info *wqe_info;
370 struct mlx5_wq_cyc wq;
372 void __iomem *uar_map;
373 struct netdev_queue *txq;
381 struct hwtstamp_config *tstamp;
382 struct mlx5_clock *clock;
385 struct mlx5_wq_ctrl wq_ctrl;
386 struct mlx5e_channel *channel;
389 } ____cacheline_aligned_in_smp;
394 /* dirtied @rx completion */
400 /* write@xmit, read@completion */
402 struct mlx5e_dma_info *di;
407 struct mlx5_wq_cyc wq;
408 void __iomem *uar_map;
416 struct mlx5_wq_ctrl wq_ctrl;
417 struct mlx5e_channel *channel;
418 } ____cacheline_aligned_in_smp;
424 u16 pc ____cacheline_aligned_in_smp;
428 /* write@xmit, read@completion */
430 struct mlx5e_sq_wqe_info *ico_wqe;
434 struct mlx5_wq_cyc wq;
435 void __iomem *uar_map;
442 struct mlx5_wq_ctrl wq_ctrl;
443 struct mlx5e_channel *channel;
444 } ____cacheline_aligned_in_smp;
447 mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n)
449 return (((wq->sz_m1 & (cc - pc)) >= n) || (cc == pc));
452 struct mlx5e_dma_info {
457 struct mlx5e_wqe_frag_info {
458 struct mlx5e_dma_info di;
462 struct mlx5e_umr_dma_info {
465 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
466 struct mlx5e_umr_wqe wqe;
469 struct mlx5e_mpw_info {
470 struct mlx5e_umr_dma_info umr;
471 u16 consumed_strides;
472 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
475 struct mlx5e_rx_am_stats {
476 int ppms; /* packets per msec */
477 int bpms; /* bytes per msec */
478 int epms; /* events per msec */
481 struct mlx5e_rx_am_sample {
488 struct mlx5e_rx_am { /* Adaptive Moderation */
490 struct mlx5e_rx_am_stats prev_stats;
491 struct mlx5e_rx_am_sample start_sample;
492 struct work_struct work;
501 /* a single cache unit is capable to serve one napi call (for non-striding rq)
502 * or a MPWQE (for striding rq).
504 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
505 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
506 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
507 struct mlx5e_page_cache {
510 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
514 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
515 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
516 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
520 struct mlx5_wq_ll wq;
524 struct mlx5e_wqe_frag_info *frag_info;
525 u32 frag_sz; /* max possible skb frag_sz */
532 struct mlx5e_mpw_info *info;
536 bool umr_in_progress;
542 u8 map_dir; /* dma map direction */
545 struct mlx5e_channel *channel;
547 struct net_device *netdev;
548 struct mlx5e_rq_stats stats;
550 struct mlx5e_page_cache page_cache;
551 struct hwtstamp_config *tstamp;
552 struct mlx5_clock *clock;
554 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
555 mlx5e_fp_post_rx_wqes post_wqes;
556 mlx5e_fp_dealloc_wqe dealloc_wqe;
561 struct mlx5e_rx_am am; /* Adaptive Moderation */
564 struct bpf_prog *xdp_prog;
565 struct mlx5e_xdpsq xdpsq;
568 struct mlx5_wq_ctrl wq_ctrl;
572 struct mlx5_core_dev *mdev;
573 struct mlx5_core_mkey umr_mkey;
574 } ____cacheline_aligned_in_smp;
576 struct mlx5e_channel {
579 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
580 struct mlx5e_icosq icosq; /* internal control operations */
582 struct napi_struct napi;
584 struct net_device *netdev;
588 /* data path - accessed per napi poll */
589 struct irq_desc *irq_desc;
592 struct mlx5e_priv *priv;
593 struct mlx5_core_dev *mdev;
594 struct hwtstamp_config *tstamp;
599 struct mlx5e_channels {
600 struct mlx5e_channel **c;
602 struct mlx5e_params params;
605 enum mlx5e_traffic_types {
610 MLX5E_TT_IPV4_IPSEC_AH,
611 MLX5E_TT_IPV6_IPSEC_AH,
612 MLX5E_TT_IPV4_IPSEC_ESP,
613 MLX5E_TT_IPV6_IPSEC_ESP,
618 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
621 enum mlx5e_tunnel_types {
628 MLX5E_STATE_ASYNC_EVENTS_ENABLED,
630 MLX5E_STATE_DESTROYING,
633 struct mlx5e_vxlan_db {
634 spinlock_t lock; /* protect vxlan table */
635 struct radix_tree_root tree;
638 struct mlx5e_l2_rule {
639 u8 addr[ETH_ALEN + 2];
640 struct mlx5_flow_handle *rule;
643 struct mlx5e_flow_table {
645 struct mlx5_flow_table *t;
646 struct mlx5_flow_group **g;
649 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
651 struct mlx5e_tc_table {
652 struct mlx5_flow_table *t;
654 struct rhashtable_params ht_params;
655 struct rhashtable ht;
657 DECLARE_HASHTABLE(mod_hdr_tbl, 8);
660 struct mlx5e_vlan_table {
661 struct mlx5e_flow_table ft;
662 DECLARE_BITMAP(active_cvlans, VLAN_N_VID);
663 DECLARE_BITMAP(active_svlans, VLAN_N_VID);
664 struct mlx5_flow_handle *active_cvlans_rule[VLAN_N_VID];
665 struct mlx5_flow_handle *active_svlans_rule[VLAN_N_VID];
666 struct mlx5_flow_handle *untagged_rule;
667 struct mlx5_flow_handle *any_cvlan_rule;
668 struct mlx5_flow_handle *any_svlan_rule;
669 bool cvlan_filter_disabled;
672 struct mlx5e_l2_table {
673 struct mlx5e_flow_table ft;
674 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
675 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
676 struct mlx5e_l2_rule broadcast;
677 struct mlx5e_l2_rule allmulti;
678 struct mlx5e_l2_rule promisc;
679 bool broadcast_enabled;
680 bool allmulti_enabled;
681 bool promisc_enabled;
684 /* L3/L4 traffic type classifier */
685 struct mlx5e_ttc_table {
686 struct mlx5e_flow_table ft;
687 struct mlx5_flow_handle *rules[MLX5E_NUM_TT];
688 struct mlx5_flow_handle *tunnel_rules[MLX5E_NUM_TUNNEL_TT];
691 #define ARFS_HASH_SHIFT BITS_PER_BYTE
692 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
694 struct mlx5e_flow_table ft;
695 struct mlx5_flow_handle *default_rule;
696 struct hlist_head rules_hash[ARFS_HASH_SIZE];
707 struct mlx5e_arfs_tables {
708 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
709 /* Protect aRFS rules list */
710 spinlock_t arfs_lock;
711 struct list_head rules;
713 struct workqueue_struct *wq;
718 MLX5E_VLAN_FT_LEVEL = 0,
721 MLX5E_INNER_TTC_FT_LEVEL,
725 struct mlx5e_ethtool_table {
726 struct mlx5_flow_table *ft;
730 #define ETHTOOL_NUM_L3_L4_FTS 7
731 #define ETHTOOL_NUM_L2_FTS 4
733 struct mlx5e_ethtool_steering {
734 struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
735 struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS];
736 struct list_head rules;
740 struct mlx5e_flow_steering {
741 struct mlx5_flow_namespace *ns;
742 struct mlx5e_ethtool_steering ethtool;
743 struct mlx5e_tc_table tc;
744 struct mlx5e_vlan_table vlan;
745 struct mlx5e_l2_table l2;
746 struct mlx5e_ttc_table ttc;
747 struct mlx5e_ttc_table inner_ttc;
748 struct mlx5e_arfs_tables arfs;
758 struct mlx5e_rqt rqt;
759 struct list_head list;
768 /* priv data path fields - start */
769 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
770 int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
771 #ifdef CONFIG_MLX5_CORE_EN_DCB
772 struct mlx5e_dcbx_dp dcbx_dp;
774 /* priv data path fields - end */
778 struct mutex state_lock; /* Protects Interface state */
779 struct mlx5e_rq drop_rq;
781 struct mlx5e_channels channels;
782 u32 tisn[MLX5E_MAX_NUM_TC];
783 struct mlx5e_rqt indir_rqt;
784 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
785 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
786 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
787 u32 tx_rates[MLX5E_MAX_NUM_SQS];
790 struct mlx5e_flow_steering fs;
791 struct mlx5e_vxlan_db vxlan;
793 struct workqueue_struct *wq;
794 struct work_struct update_carrier_work;
795 struct work_struct set_rx_mode_work;
796 struct work_struct tx_timeout_work;
797 struct delayed_work update_stats_work;
799 struct mlx5_core_dev *mdev;
800 struct net_device *netdev;
801 struct mlx5e_stats stats;
802 struct hwtstamp_config tstamp;
804 #ifdef CONFIG_MLX5_CORE_EN_DCB
805 struct mlx5e_dcbx dcbx;
808 const struct mlx5e_profile *profile;
810 #ifdef CONFIG_MLX5_EN_IPSEC
811 struct mlx5e_ipsec *ipsec;
815 struct mlx5e_profile {
816 void (*init)(struct mlx5_core_dev *mdev,
817 struct net_device *netdev,
818 const struct mlx5e_profile *profile, void *ppriv);
819 void (*cleanup)(struct mlx5e_priv *priv);
820 int (*init_rx)(struct mlx5e_priv *priv);
821 void (*cleanup_rx)(struct mlx5e_priv *priv);
822 int (*init_tx)(struct mlx5e_priv *priv);
823 void (*cleanup_tx)(struct mlx5e_priv *priv);
824 void (*enable)(struct mlx5e_priv *priv);
825 void (*disable)(struct mlx5e_priv *priv);
826 void (*update_stats)(struct mlx5e_priv *priv);
827 void (*update_carrier)(struct mlx5e_priv *priv);
828 int (*max_nch)(struct mlx5_core_dev *mdev);
830 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
831 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
833 void (*netdev_registered_init)(struct mlx5e_priv *priv);
834 void (*netdev_registered_remove)(struct mlx5e_priv *priv);
838 void mlx5e_build_ptys2ethtool_map(void);
840 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
841 void *accel_priv, select_queue_fallback_t fallback);
842 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
844 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
845 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
846 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
847 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
848 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
849 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq);
850 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
851 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq);
853 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
855 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
856 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
857 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
858 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq);
859 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
860 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
861 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
863 void mlx5e_rx_am(struct mlx5e_rq *rq);
864 void mlx5e_rx_am_work(struct work_struct *work);
865 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
867 void mlx5e_update_stats(struct mlx5e_priv *priv, bool full);
869 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
870 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
871 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
872 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
873 int mlx5e_self_test_num(struct mlx5e_priv *priv);
874 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
876 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
878 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
879 struct ethtool_rxnfc *info, u32 *rule_locs);
880 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
881 struct ethtool_rx_flow_spec *fs);
882 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
884 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
885 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
886 void mlx5e_set_rx_mode_work(struct work_struct *work);
888 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
889 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
890 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
892 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
894 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
896 void mlx5e_enable_cvlan_filter(struct mlx5e_priv *priv);
897 void mlx5e_disable_cvlan_filter(struct mlx5e_priv *priv);
898 void mlx5e_timestamp_set(struct mlx5e_priv *priv);
900 struct mlx5e_redirect_rqt_param {
903 u32 rqn; /* Direct RQN (Non-RSS) */
906 struct mlx5e_channels *channels;
907 } rss; /* RSS data */
911 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
912 struct mlx5e_redirect_rqt_param rrp);
913 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
914 enum mlx5e_traffic_types tt,
915 void *tirc, bool inner);
917 int mlx5e_open_locked(struct net_device *netdev);
918 int mlx5e_close_locked(struct net_device *netdev);
920 int mlx5e_open_channels(struct mlx5e_priv *priv,
921 struct mlx5e_channels *chs);
922 void mlx5e_close_channels(struct mlx5e_channels *chs);
924 /* Function pointer to be used to modify WH settings while
927 typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv);
928 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
929 struct mlx5e_channels *new_chs,
930 mlx5e_fp_hw_modify hw_modify);
931 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
932 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
934 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
936 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
938 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,
940 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
942 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
943 struct mlx5e_params *params,
946 static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev)
948 return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) &&
949 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version));
953 struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)
955 u16 pi = *pc & wq->sz_m1;
956 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
957 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
959 memset(cseg, 0, sizeof(*cseg));
961 cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP);
962 cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01);
970 void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc,
971 void __iomem *uar_map,
972 struct mlx5_wqe_ctrl_seg *ctrl)
974 ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
975 /* ensure wqe is visible to device before updating doorbell record */
978 *wq->db = cpu_to_be32(pc);
980 /* ensure doorbell record is visible to device before ringing the
985 mlx5_write64((__be32 *)ctrl, uar_map, NULL);
988 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
990 struct mlx5_core_cq *mcq;
993 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
996 static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
998 return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
1001 extern const struct ethtool_ops mlx5e_ethtool_ops;
1002 #ifdef CONFIG_MLX5_CORE_EN_DCB
1003 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
1004 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
1005 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
1006 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
1007 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
1010 #ifndef CONFIG_RFS_ACCEL
1011 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
1016 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
1018 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
1023 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
1028 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
1029 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
1030 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
1031 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
1032 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1033 u16 rxq_index, u32 flow_id);
1036 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
1037 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
1038 struct mlx5e_tir *tir, u32 *in, int inlen);
1039 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
1040 struct mlx5e_tir *tir);
1041 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1042 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1043 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
1045 /* common netdev helpers */
1046 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
1048 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv);
1049 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv);
1051 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
1052 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv);
1053 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
1054 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
1055 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
1057 int mlx5e_create_ttc_table(struct mlx5e_priv *priv);
1058 void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv);
1060 int mlx5e_create_inner_ttc_table(struct mlx5e_priv *priv);
1061 void mlx5e_destroy_inner_ttc_table(struct mlx5e_priv *priv);
1063 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
1064 u32 underlay_qpn, u32 *tisn);
1065 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1067 int mlx5e_create_tises(struct mlx5e_priv *priv);
1068 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
1069 int mlx5e_close(struct net_device *netdev);
1070 int mlx5e_open(struct net_device *netdev);
1071 void mlx5e_update_stats_work(struct work_struct *work);
1072 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout);
1074 /* ethtool helpers */
1075 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1076 struct ethtool_drvinfo *drvinfo);
1077 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1078 uint32_t stringset, uint8_t *data);
1079 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1080 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1081 struct ethtool_stats *stats, u64 *data);
1082 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1083 struct ethtool_ringparam *param);
1084 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1085 struct ethtool_ringparam *param);
1086 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1087 struct ethtool_channels *ch);
1088 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1089 struct ethtool_channels *ch);
1090 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1091 struct ethtool_coalesce *coal);
1092 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1093 struct ethtool_coalesce *coal);
1094 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1095 struct ethtool_ts_info *info);
1096 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1097 struct ethtool_flash *flash);
1099 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
1102 /* mlx5e generic netdev management API */
1104 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1106 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1107 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1108 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1109 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
1110 struct mlx5e_params *params,
1112 u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev);
1113 #endif /* __MLX5_EN_H__ */