2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/mlx5/fs.h>
48 #include <linux/rhashtable.h>
49 #include <net/switchdev.h>
51 #include <linux/net_dim.h>
53 #include "mlx5_core.h"
58 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
59 #define MLX5E_METADATA_ETHER_LEN 8
61 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
63 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
65 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
66 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
68 #define MLX5E_MAX_PRIORITY 8
69 #define MLX5E_MAX_DSCP 64
70 #define MLX5E_MAX_NUM_TC 8
72 #define MLX5_RX_HEADROOM NET_SKB_PAD
73 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
74 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
76 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
77 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
78 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
79 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
80 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6)
81 #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8)
82 #define MLX5E_MPWQE_STRIDE_SZ(mdev, cqe_cmprs) \
83 (cqe_cmprs ? MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) : \
84 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev))
86 #define MLX5_MPWRQ_LOG_WQE_SZ 18
87 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
88 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
89 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
91 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
92 #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
93 #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS))
94 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
95 #define MLX5E_MAX_RQ_NUM_MTTS \
96 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
97 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
98 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
99 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
100 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
101 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
102 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
104 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
105 #define MLX5E_LOG_MAX_RX_WQE_BULK \
106 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
108 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
109 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
110 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
112 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
113 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
114 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
115 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
117 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
119 #define MLX5E_RX_MAX_HEAD (256)
121 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
122 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
123 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
125 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
126 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
127 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
128 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
129 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
130 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
131 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
132 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
134 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
135 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
136 #define MLX5E_MIN_NUM_CHANNELS 0x1
137 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
138 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
139 #define MLX5E_TX_CQ_POLL_BUDGET 128
140 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
142 #define MLX5E_UMR_WQE_INLINE_SZ \
143 (sizeof(struct mlx5e_umr_wqe) + \
144 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
145 MLX5_UMR_MTT_ALIGNMENT))
146 #define MLX5E_UMR_WQEBBS \
147 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
148 #define MLX5E_ICOSQ_MAX_WQEBBS MLX5E_UMR_WQEBBS
150 #define MLX5E_NUM_MAIN_GROUPS 9
152 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
154 #define mlx5e_dbg(mlevel, priv, format, ...) \
156 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
157 netdev_warn(priv->netdev, format, \
162 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
165 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
166 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
169 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
174 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
176 return is_kdump_kernel() ?
177 MLX5E_MIN_NUM_CHANNELS :
178 min_t(int, mdev->priv.eq_table.num_comp_vectors,
179 MLX5E_MAX_NUM_CHANNELS);
182 struct mlx5e_tx_wqe {
183 struct mlx5_wqe_ctrl_seg ctrl;
184 struct mlx5_wqe_eth_seg eth;
185 struct mlx5_wqe_data_seg data[0];
188 struct mlx5e_rx_wqe_ll {
189 struct mlx5_wqe_srq_next_seg next;
190 struct mlx5_wqe_data_seg data[0];
193 struct mlx5e_rx_wqe_cyc {
194 struct mlx5_wqe_data_seg data[0];
197 struct mlx5e_umr_wqe {
198 struct mlx5_wqe_ctrl_seg ctrl;
199 struct mlx5_wqe_umr_ctrl_seg uctrl;
200 struct mlx5_mkey_seg mkc;
201 struct mlx5_mtt inline_mtts[0];
204 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
206 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
213 enum mlx5e_priv_flag {
214 MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
215 MLX5E_PFLAG_TX_CQE_BASED_MODER = (1 << 1),
216 MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 2),
217 MLX5E_PFLAG_RX_STRIDING_RQ = (1 << 3),
220 #define MLX5E_SET_PFLAG(params, pflag, enable) \
223 (params)->pflags |= (pflag); \
225 (params)->pflags &= ~(pflag); \
228 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag)))
230 #ifdef CONFIG_MLX5_CORE_EN_DCB
231 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
234 struct mlx5e_params {
237 u8 log_rq_mtu_frames;
240 bool rx_cqe_compress_def;
241 struct net_dim_cq_moder rx_cq_moderation;
242 struct net_dim_cq_moder tx_cq_moderation;
245 u8 tx_min_inline_mode;
247 u8 toeplitz_hash_key[40];
248 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
249 bool vlan_strip_disable;
255 struct bpf_prog *xdp_prog;
260 #ifdef CONFIG_MLX5_CORE_EN_DCB
261 struct mlx5e_cee_config {
262 /* bw pct for priority group */
263 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
264 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
265 bool pfc_setting[CEE_DCBX_MAX_PRIO];
272 MLX5_DCB_CHG_NO_RESET,
276 enum mlx5_dcbx_oper_mode mode;
277 struct mlx5e_cee_config cee_cfg; /* pending configuration */
280 /* The only setting that cannot be read from FW */
281 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
284 /* Buffer configuration */
290 struct mlx5e_dcbx_dp {
291 u8 dscp2prio[MLX5E_MAX_DSCP];
297 MLX5E_RQ_STATE_ENABLED,
302 /* data path - accessed per cqe */
305 /* data path - accessed per napi poll */
307 struct napi_struct *napi;
308 struct mlx5_core_cq mcq;
309 struct mlx5e_channel *channel;
311 /* cqe decompression */
312 struct mlx5_cqe64 title;
313 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
316 u16 decmprs_wqe_counter;
319 struct mlx5_core_dev *mdev;
320 struct mlx5_wq_ctrl wq_ctrl;
321 } ____cacheline_aligned_in_smp;
323 struct mlx5e_tx_wqe_info {
330 enum mlx5e_dma_map_type {
331 MLX5E_DMA_MAP_SINGLE,
335 struct mlx5e_sq_dma {
338 enum mlx5e_dma_map_type type;
342 MLX5E_SQ_STATE_ENABLED,
343 MLX5E_SQ_STATE_RECOVERING,
344 MLX5E_SQ_STATE_IPSEC,
347 MLX5E_SQ_STATE_REDIRECT,
350 struct mlx5e_sq_wqe_info {
357 /* dirtied @completion */
360 struct net_dim dim; /* Adaptive Moderation */
363 u16 pc ____cacheline_aligned_in_smp;
369 struct mlx5_wq_cyc wq;
371 struct mlx5e_sq_stats *stats;
373 struct mlx5e_sq_dma *dma_fifo;
374 struct mlx5e_tx_wqe_info *wqe_info;
376 void __iomem *uar_map;
377 struct netdev_queue *txq;
383 struct hwtstamp_config *tstamp;
384 struct mlx5_clock *clock;
387 struct mlx5_wq_ctrl wq_ctrl;
388 struct mlx5e_channel *channel;
391 struct mlx5e_txqsq_recover {
392 struct work_struct recover_work;
395 } ____cacheline_aligned_in_smp;
397 struct mlx5e_dma_info {
402 struct mlx5e_xdp_info {
403 struct xdp_frame *xdpf;
405 struct mlx5e_dma_info di;
411 /* dirtied @completion */
416 u16 pc ____cacheline_aligned_in_smp;
422 struct mlx5_wq_cyc wq;
423 struct mlx5e_xdpsq_stats *stats;
425 struct mlx5e_xdp_info *xdpi;
427 void __iomem *uar_map;
436 struct mlx5_wq_ctrl wq_ctrl;
437 struct mlx5e_channel *channel;
438 } ____cacheline_aligned_in_smp;
444 u16 pc ____cacheline_aligned_in_smp;
448 /* write@xmit, read@completion */
450 struct mlx5e_sq_wqe_info *ico_wqe;
454 struct mlx5_wq_cyc wq;
455 void __iomem *uar_map;
460 struct mlx5_wq_ctrl wq_ctrl;
461 struct mlx5e_channel *channel;
462 } ____cacheline_aligned_in_smp;
465 mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n)
467 return (mlx5_wq_cyc_ctr2ix(wq, cc - pc) >= n) || (cc == pc);
470 struct mlx5e_wqe_frag_info {
471 struct mlx5e_dma_info *di;
476 struct mlx5e_umr_dma_info {
477 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
480 struct mlx5e_mpw_info {
481 struct mlx5e_umr_dma_info umr;
482 u16 consumed_strides;
483 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
486 #define MLX5E_MAX_RX_FRAGS 4
488 /* a single cache unit is capable to serve one napi call (for non-striding rq)
489 * or a MPWQE (for striding rq).
491 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
492 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
493 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
494 struct mlx5e_page_cache {
497 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
501 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
502 typedef struct sk_buff *
503 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
504 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
505 typedef struct sk_buff *
506 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
507 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
508 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
509 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
512 MLX5E_RQ_FLAG_XDP_XMIT = BIT(0),
515 struct mlx5e_rq_frag_info {
520 struct mlx5e_rq_frags_info {
521 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
531 struct mlx5_wq_cyc wq;
532 struct mlx5e_wqe_frag_info *frags;
533 struct mlx5e_dma_info *di;
534 struct mlx5e_rq_frags_info info;
535 mlx5e_fp_skb_from_cqe skb_from_cqe;
538 struct mlx5_wq_ll wq;
539 struct mlx5e_umr_wqe umr_wqe;
540 struct mlx5e_mpw_info *info;
541 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
544 bool umr_in_progress;
549 u8 map_dir; /* dma map direction */
552 struct mlx5e_channel *channel;
554 struct net_device *netdev;
555 struct mlx5e_rq_stats *stats;
557 struct mlx5e_page_cache page_cache;
558 struct hwtstamp_config *tstamp;
559 struct mlx5_clock *clock;
561 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
562 mlx5e_fp_post_rx_wqes post_wqes;
563 mlx5e_fp_dealloc_wqe dealloc_wqe;
568 struct net_dim dim; /* Dynamic Interrupt Moderation */
571 struct bpf_prog *xdp_prog;
572 struct mlx5e_xdpsq xdpsq;
573 DECLARE_BITMAP(flags, 8);
574 struct page_pool *page_pool;
577 struct mlx5_wq_ctrl wq_ctrl;
581 struct mlx5_core_dev *mdev;
582 struct mlx5_core_mkey umr_mkey;
584 /* XDP read-mostly */
585 struct xdp_rxq_info xdp_rxq;
586 } ____cacheline_aligned_in_smp;
588 struct mlx5e_channel {
591 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
592 struct mlx5e_icosq icosq; /* internal control operations */
594 struct napi_struct napi;
596 struct net_device *netdev;
601 struct mlx5e_xdpsq xdpsq;
603 /* data path - accessed per napi poll */
604 struct irq_desc *irq_desc;
605 struct mlx5e_ch_stats *stats;
608 struct mlx5e_priv *priv;
609 struct mlx5_core_dev *mdev;
610 struct hwtstamp_config *tstamp;
615 struct mlx5e_channels {
616 struct mlx5e_channel **c;
618 struct mlx5e_params params;
621 struct mlx5e_channel_stats {
622 struct mlx5e_ch_stats ch;
623 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
624 struct mlx5e_rq_stats rq;
625 struct mlx5e_xdpsq_stats rq_xdpsq;
626 struct mlx5e_xdpsq_stats xdpsq;
627 } ____cacheline_aligned_in_smp;
629 enum mlx5e_traffic_types {
634 MLX5E_TT_IPV4_IPSEC_AH,
635 MLX5E_TT_IPV6_IPSEC_AH,
636 MLX5E_TT_IPV4_IPSEC_ESP,
637 MLX5E_TT_IPV6_IPSEC_ESP,
642 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
645 enum mlx5e_tunnel_types {
652 MLX5E_STATE_ASYNC_EVENTS_ENABLED,
654 MLX5E_STATE_DESTROYING,
657 struct mlx5e_l2_rule {
658 u8 addr[ETH_ALEN + 2];
659 struct mlx5_flow_handle *rule;
662 struct mlx5e_flow_table {
664 struct mlx5_flow_table *t;
665 struct mlx5_flow_group **g;
668 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
670 struct mlx5e_tc_table {
671 struct mlx5_flow_table *t;
673 struct rhashtable ht;
675 DECLARE_HASHTABLE(mod_hdr_tbl, 8);
676 DECLARE_HASHTABLE(hairpin_tbl, 8);
679 struct mlx5e_vlan_table {
680 struct mlx5e_flow_table ft;
681 DECLARE_BITMAP(active_cvlans, VLAN_N_VID);
682 DECLARE_BITMAP(active_svlans, VLAN_N_VID);
683 struct mlx5_flow_handle *active_cvlans_rule[VLAN_N_VID];
684 struct mlx5_flow_handle *active_svlans_rule[VLAN_N_VID];
685 struct mlx5_flow_handle *untagged_rule;
686 struct mlx5_flow_handle *any_cvlan_rule;
687 struct mlx5_flow_handle *any_svlan_rule;
688 bool cvlan_filter_disabled;
691 struct mlx5e_l2_table {
692 struct mlx5e_flow_table ft;
693 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
694 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
695 struct mlx5e_l2_rule broadcast;
696 struct mlx5e_l2_rule allmulti;
697 struct mlx5e_l2_rule promisc;
698 bool broadcast_enabled;
699 bool allmulti_enabled;
700 bool promisc_enabled;
703 /* L3/L4 traffic type classifier */
704 struct mlx5e_ttc_table {
705 struct mlx5e_flow_table ft;
706 struct mlx5_flow_handle *rules[MLX5E_NUM_TT];
707 struct mlx5_flow_handle *tunnel_rules[MLX5E_NUM_TUNNEL_TT];
710 #define ARFS_HASH_SHIFT BITS_PER_BYTE
711 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
713 struct mlx5e_flow_table ft;
714 struct mlx5_flow_handle *default_rule;
715 struct hlist_head rules_hash[ARFS_HASH_SIZE];
726 struct mlx5e_arfs_tables {
727 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
728 /* Protect aRFS rules list */
729 spinlock_t arfs_lock;
730 struct list_head rules;
732 struct workqueue_struct *wq;
737 MLX5E_VLAN_FT_LEVEL = 0,
740 MLX5E_INNER_TTC_FT_LEVEL,
745 MLX5E_TC_FT_LEVEL = 0,
746 MLX5E_TC_TTC_FT_LEVEL,
749 struct mlx5e_ethtool_table {
750 struct mlx5_flow_table *ft;
754 #define ETHTOOL_NUM_L3_L4_FTS 7
755 #define ETHTOOL_NUM_L2_FTS 4
757 struct mlx5e_ethtool_steering {
758 struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
759 struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS];
760 struct list_head rules;
764 struct mlx5e_flow_steering {
765 struct mlx5_flow_namespace *ns;
766 struct mlx5e_ethtool_steering ethtool;
767 struct mlx5e_tc_table tc;
768 struct mlx5e_vlan_table vlan;
769 struct mlx5e_l2_table l2;
770 struct mlx5e_ttc_table ttc;
771 struct mlx5e_ttc_table inner_ttc;
772 struct mlx5e_arfs_tables arfs;
782 struct mlx5e_rqt rqt;
783 struct list_head list;
792 /* priv data path fields - start */
793 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
794 int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
795 #ifdef CONFIG_MLX5_CORE_EN_DCB
796 struct mlx5e_dcbx_dp dcbx_dp;
798 /* priv data path fields - end */
802 struct mutex state_lock; /* Protects Interface state */
803 struct mlx5e_rq drop_rq;
805 struct mlx5e_channels channels;
806 u32 tisn[MLX5E_MAX_NUM_TC];
807 struct mlx5e_rqt indir_rqt;
808 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
809 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
810 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
811 u32 tx_rates[MLX5E_MAX_NUM_SQS];
813 struct mlx5e_flow_steering fs;
815 struct workqueue_struct *wq;
816 struct work_struct update_carrier_work;
817 struct work_struct set_rx_mode_work;
818 struct work_struct tx_timeout_work;
819 struct delayed_work update_stats_work;
821 struct mlx5_core_dev *mdev;
822 struct net_device *netdev;
823 struct mlx5e_stats stats;
824 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
826 struct hwtstamp_config tstamp;
828 u16 drop_rq_q_counter;
829 #ifdef CONFIG_MLX5_CORE_EN_DCB
830 struct mlx5e_dcbx dcbx;
833 const struct mlx5e_profile *profile;
835 #ifdef CONFIG_MLX5_EN_IPSEC
836 struct mlx5e_ipsec *ipsec;
838 #ifdef CONFIG_MLX5_EN_TLS
839 struct mlx5e_tls *tls;
843 struct mlx5e_profile {
844 void (*init)(struct mlx5_core_dev *mdev,
845 struct net_device *netdev,
846 const struct mlx5e_profile *profile, void *ppriv);
847 void (*cleanup)(struct mlx5e_priv *priv);
848 int (*init_rx)(struct mlx5e_priv *priv);
849 void (*cleanup_rx)(struct mlx5e_priv *priv);
850 int (*init_tx)(struct mlx5e_priv *priv);
851 void (*cleanup_tx)(struct mlx5e_priv *priv);
852 void (*enable)(struct mlx5e_priv *priv);
853 void (*disable)(struct mlx5e_priv *priv);
854 void (*update_stats)(struct mlx5e_priv *priv);
855 void (*update_carrier)(struct mlx5e_priv *priv);
856 int (*max_nch)(struct mlx5_core_dev *mdev);
858 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
859 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
861 void (*netdev_registered_init)(struct mlx5e_priv *priv);
862 void (*netdev_registered_remove)(struct mlx5e_priv *priv);
866 void mlx5e_build_ptys2ethtool_map(void);
868 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
869 struct net_device *sb_dev,
870 select_queue_fallback_t fallback);
871 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
872 netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
873 struct mlx5e_tx_wqe *wqe, u16 pi);
875 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
876 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
877 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
878 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
879 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
880 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
882 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
883 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
884 struct mlx5e_params *params);
886 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info);
887 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
889 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
890 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
891 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
892 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq);
893 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
894 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
896 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
897 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
899 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
900 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
902 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
903 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
905 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
906 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
908 void mlx5e_update_stats(struct mlx5e_priv *priv);
910 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
911 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
912 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
913 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
914 int mlx5e_self_test_num(struct mlx5e_priv *priv);
915 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
917 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
919 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
920 struct ethtool_rxnfc *info, u32 *rule_locs);
921 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
922 struct ethtool_rx_flow_spec *fs);
923 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
925 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
926 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
927 void mlx5e_set_rx_mode_work(struct work_struct *work);
929 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
930 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
931 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
933 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
935 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
937 void mlx5e_enable_cvlan_filter(struct mlx5e_priv *priv);
938 void mlx5e_disable_cvlan_filter(struct mlx5e_priv *priv);
939 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
941 struct mlx5e_redirect_rqt_param {
944 u32 rqn; /* Direct RQN (Non-RSS) */
947 struct mlx5e_channels *channels;
948 } rss; /* RSS data */
952 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
953 struct mlx5e_redirect_rqt_param rrp);
954 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
955 enum mlx5e_traffic_types tt,
956 void *tirc, bool inner);
958 int mlx5e_open_locked(struct net_device *netdev);
959 int mlx5e_close_locked(struct net_device *netdev);
961 int mlx5e_open_channels(struct mlx5e_priv *priv,
962 struct mlx5e_channels *chs);
963 void mlx5e_close_channels(struct mlx5e_channels *chs);
965 /* Function pointer to be used to modify WH settings while
968 typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv);
969 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
970 struct mlx5e_channels *new_chs,
971 mlx5e_fp_hw_modify hw_modify);
972 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
973 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
975 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
977 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,
979 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
981 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
982 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
983 struct mlx5e_params *params);
985 static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev)
987 return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) &&
988 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version));
991 static inline void mlx5e_sq_fetch_wqe(struct mlx5e_txqsq *sq,
992 struct mlx5e_tx_wqe **wqe,
995 struct mlx5_wq_cyc *wq = &sq->wq;
997 *pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
998 *wqe = mlx5_wq_cyc_get_wqe(wq, *pi);
999 memset(*wqe, 0, sizeof(**wqe));
1003 struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)
1005 u16 pi = mlx5_wq_cyc_ctr2ix(wq, *pc);
1006 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
1007 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1009 memset(cseg, 0, sizeof(*cseg));
1011 cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP);
1012 cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01);
1020 void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc,
1021 void __iomem *uar_map,
1022 struct mlx5_wqe_ctrl_seg *ctrl)
1024 ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
1025 /* ensure wqe is visible to device before updating doorbell record */
1028 *wq->db = cpu_to_be32(pc);
1030 /* ensure doorbell record is visible to device before ringing the
1035 mlx5_write64((__be32 *)ctrl, uar_map, NULL);
1038 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
1040 struct mlx5_core_cq *mcq;
1043 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
1046 extern const struct ethtool_ops mlx5e_ethtool_ops;
1047 #ifdef CONFIG_MLX5_CORE_EN_DCB
1048 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
1049 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
1050 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
1051 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
1052 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
1055 #ifndef CONFIG_RFS_ACCEL
1056 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
1061 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
1063 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
1068 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
1073 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
1074 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
1075 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
1076 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
1077 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1078 u16 rxq_index, u32 flow_id);
1081 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
1082 struct mlx5e_tir *tir, u32 *in, int inlen);
1083 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
1084 struct mlx5e_tir *tir);
1085 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1086 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1087 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
1089 /* common netdev helpers */
1090 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
1092 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv);
1093 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv);
1095 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
1096 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv);
1097 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
1098 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
1099 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
1102 struct mlx5_flow_table_attr ft_attr;
1104 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
1105 struct mlx5e_ttc_table *inner_ttc;
1108 void mlx5e_set_ttc_basic_params(struct mlx5e_priv *priv, struct ttc_params *ttc_params);
1109 void mlx5e_set_ttc_ft_params(struct ttc_params *ttc_params);
1110 void mlx5e_set_inner_ttc_ft_params(struct ttc_params *ttc_params);
1112 int mlx5e_create_ttc_table(struct mlx5e_priv *priv, struct ttc_params *params,
1113 struct mlx5e_ttc_table *ttc);
1114 void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv,
1115 struct mlx5e_ttc_table *ttc);
1117 int mlx5e_create_inner_ttc_table(struct mlx5e_priv *priv, struct ttc_params *params,
1118 struct mlx5e_ttc_table *ttc);
1119 void mlx5e_destroy_inner_ttc_table(struct mlx5e_priv *priv,
1120 struct mlx5e_ttc_table *ttc);
1122 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
1123 u32 underlay_qpn, u32 *tisn);
1124 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1126 int mlx5e_create_tises(struct mlx5e_priv *priv);
1127 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
1128 int mlx5e_close(struct net_device *netdev);
1129 int mlx5e_open(struct net_device *netdev);
1130 void mlx5e_update_stats_work(struct work_struct *work);
1132 int mlx5e_bits_invert(unsigned long a, int size);
1134 typedef int (*change_hw_mtu_cb)(struct mlx5e_priv *priv);
1135 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1136 change_hw_mtu_cb set_mtu_cb);
1138 /* ethtool helpers */
1139 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1140 struct ethtool_drvinfo *drvinfo);
1141 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1142 uint32_t stringset, uint8_t *data);
1143 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1144 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1145 struct ethtool_stats *stats, u64 *data);
1146 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1147 struct ethtool_ringparam *param);
1148 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1149 struct ethtool_ringparam *param);
1150 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1151 struct ethtool_channels *ch);
1152 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1153 struct ethtool_channels *ch);
1154 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1155 struct ethtool_coalesce *coal);
1156 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1157 struct ethtool_coalesce *coal);
1158 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1159 struct ethtool_ts_info *info);
1160 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1161 struct ethtool_flash *flash);
1163 /* mlx5e generic netdev management API */
1165 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1167 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1168 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1169 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1170 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
1171 struct mlx5e_params *params,
1172 u16 max_channels, u16 mtu);
1173 u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev);
1174 void mlx5e_rx_dim_work(struct work_struct *work);
1175 void mlx5e_tx_dim_work(struct work_struct *work);
1176 #endif /* __MLX5_EN_H__ */