2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/mlx5/fs.h>
48 #include <linux/rhashtable.h>
49 #include <net/switchdev.h>
51 #include <linux/net_dim.h>
53 #include "mlx5_core.h"
59 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
60 #define MLX5E_METADATA_ETHER_LEN 8
62 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
64 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
66 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
67 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
69 #define MLX5E_MAX_PRIORITY 8
70 #define MLX5E_MAX_DSCP 64
71 #define MLX5E_MAX_NUM_TC 8
73 #define MLX5_RX_HEADROOM NET_SKB_PAD
74 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
75 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
77 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
78 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
79 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
80 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
81 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6)
82 #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8)
83 #define MLX5E_MPWQE_STRIDE_SZ(mdev, cqe_cmprs) \
84 (cqe_cmprs ? MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) : \
85 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev))
87 #define MLX5_MPWRQ_LOG_WQE_SZ 18
88 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
89 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
90 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
92 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
93 #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
94 #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS))
95 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
96 #define MLX5E_MAX_RQ_NUM_MTTS \
97 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
98 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
99 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
100 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
101 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
102 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
103 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
105 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
106 #define MLX5E_LOG_MAX_RX_WQE_BULK \
107 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
109 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
110 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
111 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
113 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
114 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
115 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
116 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
118 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
120 #define MLX5E_RX_MAX_HEAD (256)
122 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
123 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
124 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
126 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
127 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
128 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
129 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
130 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
131 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
132 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
133 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
135 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
136 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
137 #define MLX5E_MIN_NUM_CHANNELS 0x1
138 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
139 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
140 #define MLX5E_TX_CQ_POLL_BUDGET 128
141 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
143 #define MLX5E_UMR_WQE_INLINE_SZ \
144 (sizeof(struct mlx5e_umr_wqe) + \
145 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
146 MLX5_UMR_MTT_ALIGNMENT))
147 #define MLX5E_UMR_WQEBBS \
148 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
149 #define MLX5E_ICOSQ_MAX_WQEBBS MLX5E_UMR_WQEBBS
151 #define MLX5E_NUM_MAIN_GROUPS 9
153 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
155 #define mlx5e_dbg(mlevel, priv, format, ...) \
157 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
158 netdev_warn(priv->netdev, format, \
163 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
166 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
167 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
170 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
175 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
177 return is_kdump_kernel() ?
178 MLX5E_MIN_NUM_CHANNELS :
179 min_t(int, mdev->priv.eq_table.num_comp_vectors,
180 MLX5E_MAX_NUM_CHANNELS);
183 struct mlx5e_tx_wqe {
184 struct mlx5_wqe_ctrl_seg ctrl;
185 struct mlx5_wqe_eth_seg eth;
186 struct mlx5_wqe_data_seg data[0];
189 struct mlx5e_rx_wqe_ll {
190 struct mlx5_wqe_srq_next_seg next;
191 struct mlx5_wqe_data_seg data[0];
194 struct mlx5e_rx_wqe_cyc {
195 struct mlx5_wqe_data_seg data[0];
198 struct mlx5e_umr_wqe {
199 struct mlx5_wqe_ctrl_seg ctrl;
200 struct mlx5_wqe_umr_ctrl_seg uctrl;
201 struct mlx5_mkey_seg mkc;
202 struct mlx5_mtt inline_mtts[0];
205 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
207 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
214 enum mlx5e_priv_flag {
215 MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
216 MLX5E_PFLAG_TX_CQE_BASED_MODER = (1 << 1),
217 MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 2),
218 MLX5E_PFLAG_RX_STRIDING_RQ = (1 << 3),
221 #define MLX5E_SET_PFLAG(params, pflag, enable) \
224 (params)->pflags |= (pflag); \
226 (params)->pflags &= ~(pflag); \
229 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag)))
231 #ifdef CONFIG_MLX5_CORE_EN_DCB
232 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
235 struct mlx5e_params {
238 u8 log_rq_mtu_frames;
241 bool rx_cqe_compress_def;
242 struct net_dim_cq_moder rx_cq_moderation;
243 struct net_dim_cq_moder tx_cq_moderation;
246 u8 tx_min_inline_mode;
248 u8 toeplitz_hash_key[40];
249 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
250 bool vlan_strip_disable;
256 struct bpf_prog *xdp_prog;
261 #ifdef CONFIG_MLX5_CORE_EN_DCB
262 struct mlx5e_cee_config {
263 /* bw pct for priority group */
264 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
265 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
266 bool pfc_setting[CEE_DCBX_MAX_PRIO];
273 MLX5_DCB_CHG_NO_RESET,
277 enum mlx5_dcbx_oper_mode mode;
278 struct mlx5e_cee_config cee_cfg; /* pending configuration */
281 /* The only setting that cannot be read from FW */
282 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
285 /* Buffer configuration */
291 struct mlx5e_dcbx_dp {
292 u8 dscp2prio[MLX5E_MAX_DSCP];
298 MLX5E_RQ_STATE_ENABLED,
303 /* data path - accessed per cqe */
306 /* data path - accessed per napi poll */
308 struct napi_struct *napi;
309 struct mlx5_core_cq mcq;
310 struct mlx5e_channel *channel;
312 /* cqe decompression */
313 struct mlx5_cqe64 title;
314 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
317 u16 decmprs_wqe_counter;
320 struct mlx5_core_dev *mdev;
321 struct mlx5_wq_ctrl wq_ctrl;
322 } ____cacheline_aligned_in_smp;
324 struct mlx5e_tx_wqe_info {
331 enum mlx5e_dma_map_type {
332 MLX5E_DMA_MAP_SINGLE,
336 struct mlx5e_sq_dma {
339 enum mlx5e_dma_map_type type;
343 MLX5E_SQ_STATE_ENABLED,
344 MLX5E_SQ_STATE_RECOVERING,
345 MLX5E_SQ_STATE_IPSEC,
348 MLX5E_SQ_STATE_REDIRECT,
351 struct mlx5e_sq_wqe_info {
358 /* dirtied @completion */
361 struct net_dim dim; /* Adaptive Moderation */
364 u16 pc ____cacheline_aligned_in_smp;
370 struct mlx5_wq_cyc wq;
372 struct mlx5e_sq_stats *stats;
374 struct mlx5e_sq_dma *dma_fifo;
375 struct mlx5e_tx_wqe_info *wqe_info;
377 void __iomem *uar_map;
378 struct netdev_queue *txq;
384 struct hwtstamp_config *tstamp;
385 struct mlx5_clock *clock;
388 struct mlx5_wq_ctrl wq_ctrl;
389 struct mlx5e_channel *channel;
392 struct mlx5e_txqsq_recover {
393 struct work_struct recover_work;
396 } ____cacheline_aligned_in_smp;
398 struct mlx5e_dma_info {
403 struct mlx5e_xdp_info {
404 struct xdp_frame *xdpf;
406 struct mlx5e_dma_info di;
412 /* dirtied @completion */
417 u16 pc ____cacheline_aligned_in_smp;
423 struct mlx5_wq_cyc wq;
424 struct mlx5e_xdpsq_stats *stats;
426 struct mlx5e_xdp_info *xdpi;
428 void __iomem *uar_map;
437 struct mlx5_wq_ctrl wq_ctrl;
438 struct mlx5e_channel *channel;
439 } ____cacheline_aligned_in_smp;
445 u16 pc ____cacheline_aligned_in_smp;
449 /* write@xmit, read@completion */
451 struct mlx5e_sq_wqe_info *ico_wqe;
455 struct mlx5_wq_cyc wq;
456 void __iomem *uar_map;
461 struct mlx5_wq_ctrl wq_ctrl;
462 struct mlx5e_channel *channel;
463 } ____cacheline_aligned_in_smp;
466 mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n)
468 return (mlx5_wq_cyc_ctr2ix(wq, cc - pc) >= n) || (cc == pc);
471 struct mlx5e_wqe_frag_info {
472 struct mlx5e_dma_info *di;
477 struct mlx5e_umr_dma_info {
478 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
481 struct mlx5e_mpw_info {
482 struct mlx5e_umr_dma_info umr;
483 u16 consumed_strides;
484 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
487 #define MLX5E_MAX_RX_FRAGS 4
489 /* a single cache unit is capable to serve one napi call (for non-striding rq)
490 * or a MPWQE (for striding rq).
492 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
493 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
494 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
495 struct mlx5e_page_cache {
498 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
502 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
503 typedef struct sk_buff *
504 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
505 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
506 typedef struct sk_buff *
507 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
508 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
509 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
510 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
513 MLX5E_RQ_FLAG_XDP_XMIT = BIT(0),
516 struct mlx5e_rq_frag_info {
521 struct mlx5e_rq_frags_info {
522 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
532 struct mlx5_wq_cyc wq;
533 struct mlx5e_wqe_frag_info *frags;
534 struct mlx5e_dma_info *di;
535 struct mlx5e_rq_frags_info info;
536 mlx5e_fp_skb_from_cqe skb_from_cqe;
539 struct mlx5_wq_ll wq;
540 struct mlx5e_umr_wqe umr_wqe;
541 struct mlx5e_mpw_info *info;
542 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
545 bool umr_in_progress;
550 u8 map_dir; /* dma map direction */
553 struct mlx5e_channel *channel;
555 struct net_device *netdev;
556 struct mlx5e_rq_stats *stats;
558 struct mlx5e_page_cache page_cache;
559 struct hwtstamp_config *tstamp;
560 struct mlx5_clock *clock;
562 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
563 mlx5e_fp_post_rx_wqes post_wqes;
564 mlx5e_fp_dealloc_wqe dealloc_wqe;
569 struct net_dim dim; /* Dynamic Interrupt Moderation */
572 struct bpf_prog *xdp_prog;
573 struct mlx5e_xdpsq xdpsq;
574 DECLARE_BITMAP(flags, 8);
575 struct page_pool *page_pool;
578 struct mlx5_wq_ctrl wq_ctrl;
582 struct mlx5_core_dev *mdev;
583 struct mlx5_core_mkey umr_mkey;
585 /* XDP read-mostly */
586 struct xdp_rxq_info xdp_rxq;
587 } ____cacheline_aligned_in_smp;
589 struct mlx5e_channel {
592 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
593 struct mlx5e_icosq icosq; /* internal control operations */
595 struct napi_struct napi;
597 struct net_device *netdev;
602 struct mlx5e_xdpsq xdpsq;
604 /* data path - accessed per napi poll */
605 struct irq_desc *irq_desc;
606 struct mlx5e_ch_stats *stats;
609 struct mlx5e_priv *priv;
610 struct mlx5_core_dev *mdev;
611 struct hwtstamp_config *tstamp;
616 struct mlx5e_channels {
617 struct mlx5e_channel **c;
619 struct mlx5e_params params;
622 struct mlx5e_channel_stats {
623 struct mlx5e_ch_stats ch;
624 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
625 struct mlx5e_rq_stats rq;
626 struct mlx5e_xdpsq_stats rq_xdpsq;
627 struct mlx5e_xdpsq_stats xdpsq;
628 } ____cacheline_aligned_in_smp;
631 MLX5E_STATE_ASYNC_EVENTS_ENABLED,
633 MLX5E_STATE_DESTROYING,
643 struct mlx5e_rqt rqt;
644 struct list_head list;
653 /* priv data path fields - start */
654 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
655 int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
656 #ifdef CONFIG_MLX5_CORE_EN_DCB
657 struct mlx5e_dcbx_dp dcbx_dp;
659 /* priv data path fields - end */
663 struct mutex state_lock; /* Protects Interface state */
664 struct mlx5e_rq drop_rq;
666 struct mlx5e_channels channels;
667 u32 tisn[MLX5E_MAX_NUM_TC];
668 struct mlx5e_rqt indir_rqt;
669 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
670 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
671 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
672 u32 tx_rates[MLX5E_MAX_NUM_SQS];
674 struct mlx5e_flow_steering fs;
676 struct workqueue_struct *wq;
677 struct work_struct update_carrier_work;
678 struct work_struct set_rx_mode_work;
679 struct work_struct tx_timeout_work;
680 struct delayed_work update_stats_work;
682 struct mlx5_core_dev *mdev;
683 struct net_device *netdev;
684 struct mlx5e_stats stats;
685 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
687 struct hwtstamp_config tstamp;
689 u16 drop_rq_q_counter;
690 #ifdef CONFIG_MLX5_CORE_EN_DCB
691 struct mlx5e_dcbx dcbx;
694 const struct mlx5e_profile *profile;
696 #ifdef CONFIG_MLX5_EN_IPSEC
697 struct mlx5e_ipsec *ipsec;
699 #ifdef CONFIG_MLX5_EN_TLS
700 struct mlx5e_tls *tls;
704 struct mlx5e_profile {
705 void (*init)(struct mlx5_core_dev *mdev,
706 struct net_device *netdev,
707 const struct mlx5e_profile *profile, void *ppriv);
708 void (*cleanup)(struct mlx5e_priv *priv);
709 int (*init_rx)(struct mlx5e_priv *priv);
710 void (*cleanup_rx)(struct mlx5e_priv *priv);
711 int (*init_tx)(struct mlx5e_priv *priv);
712 void (*cleanup_tx)(struct mlx5e_priv *priv);
713 void (*enable)(struct mlx5e_priv *priv);
714 void (*disable)(struct mlx5e_priv *priv);
715 void (*update_stats)(struct mlx5e_priv *priv);
716 void (*update_carrier)(struct mlx5e_priv *priv);
717 int (*max_nch)(struct mlx5_core_dev *mdev);
719 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
720 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
725 void mlx5e_build_ptys2ethtool_map(void);
727 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
728 struct net_device *sb_dev,
729 select_queue_fallback_t fallback);
730 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
731 netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
732 struct mlx5e_tx_wqe *wqe, u16 pi);
734 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
735 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
736 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
737 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
738 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
739 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
741 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
742 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
743 struct mlx5e_params *params);
745 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info);
746 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
748 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
749 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
750 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
751 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq);
752 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
753 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
755 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
756 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
758 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
759 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
761 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
762 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
764 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
765 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
767 void mlx5e_update_stats(struct mlx5e_priv *priv);
769 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
770 int mlx5e_self_test_num(struct mlx5e_priv *priv);
771 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
773 void mlx5e_set_rx_mode_work(struct work_struct *work);
775 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
776 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
777 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
779 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
781 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
783 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
785 struct mlx5e_redirect_rqt_param {
788 u32 rqn; /* Direct RQN (Non-RSS) */
791 struct mlx5e_channels *channels;
792 } rss; /* RSS data */
796 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
797 struct mlx5e_redirect_rqt_param rrp);
798 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
799 enum mlx5e_traffic_types tt,
800 void *tirc, bool inner);
802 int mlx5e_open_locked(struct net_device *netdev);
803 int mlx5e_close_locked(struct net_device *netdev);
805 int mlx5e_open_channels(struct mlx5e_priv *priv,
806 struct mlx5e_channels *chs);
807 void mlx5e_close_channels(struct mlx5e_channels *chs);
809 /* Function pointer to be used to modify WH settings while
812 typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv);
813 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
814 struct mlx5e_channels *new_chs,
815 mlx5e_fp_hw_modify hw_modify);
816 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
817 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
819 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
821 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,
823 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
825 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
826 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
827 struct mlx5e_params *params);
829 static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev)
831 return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) &&
832 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version));
835 static inline void mlx5e_sq_fetch_wqe(struct mlx5e_txqsq *sq,
836 struct mlx5e_tx_wqe **wqe,
839 struct mlx5_wq_cyc *wq = &sq->wq;
841 *pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
842 *wqe = mlx5_wq_cyc_get_wqe(wq, *pi);
843 memset(*wqe, 0, sizeof(**wqe));
847 struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)
849 u16 pi = mlx5_wq_cyc_ctr2ix(wq, *pc);
850 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
851 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
853 memset(cseg, 0, sizeof(*cseg));
855 cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP);
856 cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01);
864 void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc,
865 void __iomem *uar_map,
866 struct mlx5_wqe_ctrl_seg *ctrl)
868 ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
869 /* ensure wqe is visible to device before updating doorbell record */
872 *wq->db = cpu_to_be32(pc);
874 /* ensure doorbell record is visible to device before ringing the
879 mlx5_write64((__be32 *)ctrl, uar_map, NULL);
882 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
884 struct mlx5_core_cq *mcq;
887 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
890 extern const struct ethtool_ops mlx5e_ethtool_ops;
891 #ifdef CONFIG_MLX5_CORE_EN_DCB
892 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
893 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
894 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
895 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
896 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
899 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
900 struct mlx5e_tir *tir, u32 *in, int inlen);
901 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
902 struct mlx5e_tir *tir);
903 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
904 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
905 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
907 /* common netdev helpers */
908 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
910 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv);
911 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv);
913 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
914 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv);
915 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
916 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
917 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
919 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
920 u32 underlay_qpn, u32 *tisn);
921 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
923 int mlx5e_create_tises(struct mlx5e_priv *priv);
924 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
925 int mlx5e_close(struct net_device *netdev);
926 int mlx5e_open(struct net_device *netdev);
927 void mlx5e_update_stats_work(struct work_struct *work);
929 int mlx5e_bits_invert(unsigned long a, int size);
931 typedef int (*change_hw_mtu_cb)(struct mlx5e_priv *priv);
932 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
933 change_hw_mtu_cb set_mtu_cb);
935 /* ethtool helpers */
936 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
937 struct ethtool_drvinfo *drvinfo);
938 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
939 uint32_t stringset, uint8_t *data);
940 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
941 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
942 struct ethtool_stats *stats, u64 *data);
943 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
944 struct ethtool_ringparam *param);
945 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
946 struct ethtool_ringparam *param);
947 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
948 struct ethtool_channels *ch);
949 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
950 struct ethtool_channels *ch);
951 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
952 struct ethtool_coalesce *coal);
953 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
954 struct ethtool_coalesce *coal);
955 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
956 struct ethtool_ts_info *info);
957 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
958 struct ethtool_flash *flash);
960 /* mlx5e generic netdev management API */
962 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
964 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
965 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
966 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
967 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
968 struct mlx5e_params *params,
969 u16 max_channels, u16 mtu);
970 u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev);
971 void mlx5e_rx_dim_work(struct work_struct *work);
972 void mlx5e_tx_dim_work(struct work_struct *work);
973 #endif /* __MLX5_EN_H__ */