2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/mlx5/fs.h>
48 #include <linux/rhashtable.h>
49 #include <net/switchdev.h>
51 #include <linux/net_dim.h>
53 #include "mlx5_core.h"
59 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
60 #define MLX5E_METADATA_ETHER_LEN 8
62 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
64 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
66 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
67 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
69 #define MLX5E_MAX_PRIORITY 8
70 #define MLX5E_MAX_DSCP 64
71 #define MLX5E_MAX_NUM_TC 8
73 #define MLX5_RX_HEADROOM NET_SKB_PAD
74 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
75 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
77 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
78 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
79 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
80 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
81 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6)
82 #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8)
83 #define MLX5E_MPWQE_STRIDE_SZ(mdev, cqe_cmprs) \
84 (cqe_cmprs ? MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) : \
85 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev))
87 #define MLX5_MPWRQ_LOG_WQE_SZ 18
88 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
89 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
90 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
92 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
93 #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
94 #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS))
95 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
96 #define MLX5E_MAX_RQ_NUM_MTTS \
97 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
98 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
99 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
100 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
101 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
102 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
103 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
105 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
106 #define MLX5E_LOG_MAX_RX_WQE_BULK \
107 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
109 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
110 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
111 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
113 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
114 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
115 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
116 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
118 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
120 #define MLX5E_RX_MAX_HEAD (256)
122 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
123 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
124 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
126 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
127 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
128 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
129 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
130 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
131 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
132 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
133 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
135 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
136 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
137 #define MLX5E_MIN_NUM_CHANNELS 0x1
138 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
139 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
140 #define MLX5E_TX_CQ_POLL_BUDGET 128
141 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
143 #define MLX5E_UMR_WQE_INLINE_SZ \
144 (sizeof(struct mlx5e_umr_wqe) + \
145 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
146 MLX5_UMR_MTT_ALIGNMENT))
147 #define MLX5E_UMR_WQEBBS \
148 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
149 #define MLX5E_ICOSQ_MAX_WQEBBS MLX5E_UMR_WQEBBS
151 #define MLX5E_NUM_MAIN_GROUPS 9
153 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
155 #define mlx5e_dbg(mlevel, priv, format, ...) \
157 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
158 netdev_warn(priv->netdev, format, \
163 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
166 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
167 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
170 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
175 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
177 return is_kdump_kernel() ?
178 MLX5E_MIN_NUM_CHANNELS :
179 min_t(int, mdev->priv.eq_table.num_comp_vectors,
180 MLX5E_MAX_NUM_CHANNELS);
183 struct mlx5e_tx_wqe {
184 struct mlx5_wqe_ctrl_seg ctrl;
185 struct mlx5_wqe_eth_seg eth;
186 struct mlx5_wqe_data_seg data[0];
189 struct mlx5e_rx_wqe_ll {
190 struct mlx5_wqe_srq_next_seg next;
191 struct mlx5_wqe_data_seg data[0];
194 struct mlx5e_rx_wqe_cyc {
195 struct mlx5_wqe_data_seg data[0];
198 struct mlx5e_umr_wqe {
199 struct mlx5_wqe_ctrl_seg ctrl;
200 struct mlx5_wqe_umr_ctrl_seg uctrl;
201 struct mlx5_mkey_seg mkc;
202 struct mlx5_mtt inline_mtts[0];
205 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
207 enum mlx5e_priv_flag {
208 MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
209 MLX5E_PFLAG_TX_CQE_BASED_MODER = (1 << 1),
210 MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 2),
211 MLX5E_PFLAG_RX_STRIDING_RQ = (1 << 3),
214 #define MLX5E_SET_PFLAG(params, pflag, enable) \
217 (params)->pflags |= (pflag); \
219 (params)->pflags &= ~(pflag); \
222 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag)))
224 #ifdef CONFIG_MLX5_CORE_EN_DCB
225 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
228 struct mlx5e_params {
231 u8 log_rq_mtu_frames;
234 bool rx_cqe_compress_def;
235 struct net_dim_cq_moder rx_cq_moderation;
236 struct net_dim_cq_moder tx_cq_moderation;
239 u8 tx_min_inline_mode;
241 u8 toeplitz_hash_key[40];
242 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
243 bool vlan_strip_disable;
249 struct bpf_prog *xdp_prog;
254 #ifdef CONFIG_MLX5_CORE_EN_DCB
255 struct mlx5e_cee_config {
256 /* bw pct for priority group */
257 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
258 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
259 bool pfc_setting[CEE_DCBX_MAX_PRIO];
266 MLX5_DCB_CHG_NO_RESET,
270 enum mlx5_dcbx_oper_mode mode;
271 struct mlx5e_cee_config cee_cfg; /* pending configuration */
274 /* The only setting that cannot be read from FW */
275 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
278 /* Buffer configuration */
284 struct mlx5e_dcbx_dp {
285 u8 dscp2prio[MLX5E_MAX_DSCP];
291 MLX5E_RQ_STATE_ENABLED,
296 /* data path - accessed per cqe */
299 /* data path - accessed per napi poll */
301 struct napi_struct *napi;
302 struct mlx5_core_cq mcq;
303 struct mlx5e_channel *channel;
305 /* cqe decompression */
306 struct mlx5_cqe64 title;
307 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
310 u16 decmprs_wqe_counter;
313 struct mlx5_core_dev *mdev;
314 struct mlx5_wq_ctrl wq_ctrl;
315 } ____cacheline_aligned_in_smp;
317 struct mlx5e_tx_wqe_info {
324 enum mlx5e_dma_map_type {
325 MLX5E_DMA_MAP_SINGLE,
329 struct mlx5e_sq_dma {
332 enum mlx5e_dma_map_type type;
336 MLX5E_SQ_STATE_ENABLED,
337 MLX5E_SQ_STATE_RECOVERING,
338 MLX5E_SQ_STATE_IPSEC,
341 MLX5E_SQ_STATE_REDIRECT,
344 struct mlx5e_sq_wqe_info {
351 /* dirtied @completion */
354 struct net_dim dim; /* Adaptive Moderation */
357 u16 pc ____cacheline_aligned_in_smp;
363 struct mlx5_wq_cyc wq;
365 struct mlx5e_sq_stats *stats;
367 struct mlx5e_sq_dma *dma_fifo;
368 struct mlx5e_tx_wqe_info *wqe_info;
370 void __iomem *uar_map;
371 struct netdev_queue *txq;
377 struct hwtstamp_config *tstamp;
378 struct mlx5_clock *clock;
381 struct mlx5_wq_ctrl wq_ctrl;
382 struct mlx5e_channel *channel;
385 struct mlx5e_txqsq_recover {
386 struct work_struct recover_work;
389 } ____cacheline_aligned_in_smp;
391 struct mlx5e_dma_info {
396 struct mlx5e_xdp_info {
397 struct xdp_frame *xdpf;
399 struct mlx5e_dma_info di;
405 /* dirtied @completion */
410 u16 pc ____cacheline_aligned_in_smp;
416 struct mlx5_wq_cyc wq;
417 struct mlx5e_xdpsq_stats *stats;
419 struct mlx5e_xdp_info *xdpi;
421 void __iomem *uar_map;
430 struct mlx5_wq_ctrl wq_ctrl;
431 struct mlx5e_channel *channel;
432 } ____cacheline_aligned_in_smp;
438 u16 pc ____cacheline_aligned_in_smp;
442 /* write@xmit, read@completion */
444 struct mlx5e_sq_wqe_info *ico_wqe;
448 struct mlx5_wq_cyc wq;
449 void __iomem *uar_map;
454 struct mlx5_wq_ctrl wq_ctrl;
455 struct mlx5e_channel *channel;
456 } ____cacheline_aligned_in_smp;
459 mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n)
461 return (mlx5_wq_cyc_ctr2ix(wq, cc - pc) >= n) || (cc == pc);
464 struct mlx5e_wqe_frag_info {
465 struct mlx5e_dma_info *di;
470 struct mlx5e_umr_dma_info {
471 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
474 struct mlx5e_mpw_info {
475 struct mlx5e_umr_dma_info umr;
476 u16 consumed_strides;
477 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
480 #define MLX5E_MAX_RX_FRAGS 4
482 /* a single cache unit is capable to serve one napi call (for non-striding rq)
483 * or a MPWQE (for striding rq).
485 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
486 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
487 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
488 struct mlx5e_page_cache {
491 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
495 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
496 typedef struct sk_buff *
497 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
498 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
499 typedef struct sk_buff *
500 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
501 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
502 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
503 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
506 MLX5E_RQ_FLAG_XDP_XMIT = BIT(0),
509 struct mlx5e_rq_frag_info {
514 struct mlx5e_rq_frags_info {
515 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
525 struct mlx5_wq_cyc wq;
526 struct mlx5e_wqe_frag_info *frags;
527 struct mlx5e_dma_info *di;
528 struct mlx5e_rq_frags_info info;
529 mlx5e_fp_skb_from_cqe skb_from_cqe;
532 struct mlx5_wq_ll wq;
533 struct mlx5e_umr_wqe umr_wqe;
534 struct mlx5e_mpw_info *info;
535 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
538 bool umr_in_progress;
543 u8 map_dir; /* dma map direction */
546 struct mlx5e_channel *channel;
548 struct net_device *netdev;
549 struct mlx5e_rq_stats *stats;
551 struct mlx5e_page_cache page_cache;
552 struct hwtstamp_config *tstamp;
553 struct mlx5_clock *clock;
555 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
556 mlx5e_fp_post_rx_wqes post_wqes;
557 mlx5e_fp_dealloc_wqe dealloc_wqe;
562 struct net_dim dim; /* Dynamic Interrupt Moderation */
565 struct bpf_prog *xdp_prog;
566 struct mlx5e_xdpsq xdpsq;
567 DECLARE_BITMAP(flags, 8);
568 struct page_pool *page_pool;
571 struct mlx5_wq_ctrl wq_ctrl;
575 struct mlx5_core_dev *mdev;
576 struct mlx5_core_mkey umr_mkey;
578 /* XDP read-mostly */
579 struct xdp_rxq_info xdp_rxq;
580 } ____cacheline_aligned_in_smp;
582 struct mlx5e_channel {
585 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
586 struct mlx5e_icosq icosq; /* internal control operations */
588 struct napi_struct napi;
590 struct net_device *netdev;
595 struct mlx5e_xdpsq xdpsq;
597 /* data path - accessed per napi poll */
598 struct irq_desc *irq_desc;
599 struct mlx5e_ch_stats *stats;
602 struct mlx5e_priv *priv;
603 struct mlx5_core_dev *mdev;
604 struct hwtstamp_config *tstamp;
609 struct mlx5e_channels {
610 struct mlx5e_channel **c;
612 struct mlx5e_params params;
615 struct mlx5e_channel_stats {
616 struct mlx5e_ch_stats ch;
617 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
618 struct mlx5e_rq_stats rq;
619 struct mlx5e_xdpsq_stats rq_xdpsq;
620 struct mlx5e_xdpsq_stats xdpsq;
621 } ____cacheline_aligned_in_smp;
624 MLX5E_STATE_ASYNC_EVENTS_ENABLED,
626 MLX5E_STATE_DESTROYING,
636 struct mlx5e_rqt rqt;
637 struct list_head list;
646 /* priv data path fields - start */
647 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
648 int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
649 #ifdef CONFIG_MLX5_CORE_EN_DCB
650 struct mlx5e_dcbx_dp dcbx_dp;
652 /* priv data path fields - end */
656 struct mutex state_lock; /* Protects Interface state */
657 struct mlx5e_rq drop_rq;
659 struct mlx5e_channels channels;
660 u32 tisn[MLX5E_MAX_NUM_TC];
661 struct mlx5e_rqt indir_rqt;
662 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
663 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
664 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
665 u32 tx_rates[MLX5E_MAX_NUM_SQS];
667 struct mlx5e_flow_steering fs;
669 struct workqueue_struct *wq;
670 struct work_struct update_carrier_work;
671 struct work_struct set_rx_mode_work;
672 struct work_struct tx_timeout_work;
673 struct delayed_work update_stats_work;
675 struct mlx5_core_dev *mdev;
676 struct net_device *netdev;
677 struct mlx5e_stats stats;
678 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
680 struct hwtstamp_config tstamp;
682 u16 drop_rq_q_counter;
683 #ifdef CONFIG_MLX5_CORE_EN_DCB
684 struct mlx5e_dcbx dcbx;
687 const struct mlx5e_profile *profile;
689 #ifdef CONFIG_MLX5_EN_IPSEC
690 struct mlx5e_ipsec *ipsec;
692 #ifdef CONFIG_MLX5_EN_TLS
693 struct mlx5e_tls *tls;
697 struct mlx5e_profile {
698 void (*init)(struct mlx5_core_dev *mdev,
699 struct net_device *netdev,
700 const struct mlx5e_profile *profile, void *ppriv);
701 void (*cleanup)(struct mlx5e_priv *priv);
702 int (*init_rx)(struct mlx5e_priv *priv);
703 void (*cleanup_rx)(struct mlx5e_priv *priv);
704 int (*init_tx)(struct mlx5e_priv *priv);
705 void (*cleanup_tx)(struct mlx5e_priv *priv);
706 void (*enable)(struct mlx5e_priv *priv);
707 void (*disable)(struct mlx5e_priv *priv);
708 void (*update_stats)(struct mlx5e_priv *priv);
709 void (*update_carrier)(struct mlx5e_priv *priv);
710 int (*max_nch)(struct mlx5_core_dev *mdev);
712 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
713 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
718 void mlx5e_build_ptys2ethtool_map(void);
720 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
721 struct net_device *sb_dev,
722 select_queue_fallback_t fallback);
723 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
724 netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
725 struct mlx5e_tx_wqe *wqe, u16 pi);
727 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
728 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
729 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
730 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
731 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
732 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
734 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
735 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
736 struct mlx5e_params *params);
738 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info);
739 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
741 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
742 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
743 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
744 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq);
745 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
746 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
748 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
749 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
751 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
752 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
754 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
755 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
757 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
758 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
760 void mlx5e_update_stats(struct mlx5e_priv *priv);
762 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
763 int mlx5e_self_test_num(struct mlx5e_priv *priv);
764 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
766 void mlx5e_set_rx_mode_work(struct work_struct *work);
768 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
769 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
770 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
772 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
774 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
776 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
778 struct mlx5e_redirect_rqt_param {
781 u32 rqn; /* Direct RQN (Non-RSS) */
784 struct mlx5e_channels *channels;
785 } rss; /* RSS data */
789 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
790 struct mlx5e_redirect_rqt_param rrp);
791 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
792 enum mlx5e_traffic_types tt,
793 void *tirc, bool inner);
795 int mlx5e_open_locked(struct net_device *netdev);
796 int mlx5e_close_locked(struct net_device *netdev);
798 int mlx5e_open_channels(struct mlx5e_priv *priv,
799 struct mlx5e_channels *chs);
800 void mlx5e_close_channels(struct mlx5e_channels *chs);
802 /* Function pointer to be used to modify WH settings while
805 typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv);
806 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
807 struct mlx5e_channels *new_chs,
808 mlx5e_fp_hw_modify hw_modify);
809 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
810 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
812 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
814 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,
816 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
818 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
819 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
820 struct mlx5e_params *params);
822 static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev)
824 return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) &&
825 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version));
828 static inline void mlx5e_sq_fetch_wqe(struct mlx5e_txqsq *sq,
829 struct mlx5e_tx_wqe **wqe,
832 struct mlx5_wq_cyc *wq = &sq->wq;
834 *pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
835 *wqe = mlx5_wq_cyc_get_wqe(wq, *pi);
836 memset(*wqe, 0, sizeof(**wqe));
840 struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)
842 u16 pi = mlx5_wq_cyc_ctr2ix(wq, *pc);
843 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
844 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
846 memset(cseg, 0, sizeof(*cseg));
848 cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP);
849 cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01);
857 void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc,
858 void __iomem *uar_map,
859 struct mlx5_wqe_ctrl_seg *ctrl)
861 ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
862 /* ensure wqe is visible to device before updating doorbell record */
865 *wq->db = cpu_to_be32(pc);
867 /* ensure doorbell record is visible to device before ringing the
872 mlx5_write64((__be32 *)ctrl, uar_map, NULL);
875 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
877 struct mlx5_core_cq *mcq;
880 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
883 extern const struct ethtool_ops mlx5e_ethtool_ops;
884 #ifdef CONFIG_MLX5_CORE_EN_DCB
885 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
886 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
887 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
888 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
889 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
892 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
893 struct mlx5e_tir *tir, u32 *in, int inlen);
894 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
895 struct mlx5e_tir *tir);
896 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
897 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
898 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
900 /* common netdev helpers */
901 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
902 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
903 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
904 struct mlx5e_rq *drop_rq);
905 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
907 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
909 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv);
910 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv);
912 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
913 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv);
914 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
915 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
916 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
918 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
919 u32 underlay_qpn, u32 *tisn);
920 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
922 int mlx5e_create_tises(struct mlx5e_priv *priv);
923 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
924 int mlx5e_close(struct net_device *netdev);
925 int mlx5e_open(struct net_device *netdev);
926 void mlx5e_update_stats_work(struct work_struct *work);
928 int mlx5e_bits_invert(unsigned long a, int size);
930 typedef int (*change_hw_mtu_cb)(struct mlx5e_priv *priv);
931 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
932 change_hw_mtu_cb set_mtu_cb);
934 /* ethtool helpers */
935 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
936 struct ethtool_drvinfo *drvinfo);
937 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
938 uint32_t stringset, uint8_t *data);
939 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
940 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
941 struct ethtool_stats *stats, u64 *data);
942 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
943 struct ethtool_ringparam *param);
944 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
945 struct ethtool_ringparam *param);
946 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
947 struct ethtool_channels *ch);
948 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
949 struct ethtool_channels *ch);
950 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
951 struct ethtool_coalesce *coal);
952 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
953 struct ethtool_coalesce *coal);
954 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
955 struct ethtool_ts_info *info);
956 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
957 struct ethtool_flash *flash);
959 /* mlx5e generic netdev management API */
961 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
963 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
964 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
965 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
966 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
967 struct mlx5e_params *params,
968 u16 max_channels, u16 mtu);
969 u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev);
970 void mlx5e_rx_dim_work(struct work_struct *work);
971 void mlx5e_tx_dim_work(struct work_struct *work);
972 #endif /* __MLX5_EN_H__ */