drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/debugfs.h>
  44
  45 #include "mlx5_core.h"
  46
  47 enum {
  48         CMD_IF_REV = 5,
  49 };
  50
  51 enum {
  52         CMD_MODE_POLLING,
  53         CMD_MODE_EVENTS
  54 };
  55
  56 enum {
  57         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  58         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  59         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  60         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  61         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  62         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  63         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  64         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  65         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  66         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  67         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  68 };
  69
  70 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  71                                            struct mlx5_cmd_msg *in,
  72                                            struct mlx5_cmd_msg *out,
  73                                            void *uout, int uout_size,
  74                                            mlx5_cmd_cbk_t cbk,
  75                                            void *context, int page_queue)
  76 {
  77         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
  78         struct mlx5_cmd_work_ent *ent;
  79
  80         ent = kzalloc(sizeof(*ent), alloc_flags);
  81         if (!ent)
  82                 return ERR_PTR(-ENOMEM);
  83
  84         ent->in         = in;
  85         ent->out        = out;
  86         ent->uout       = uout;
  87         ent->uout_size  = uout_size;
  88         ent->callback   = cbk;
  89         ent->context    = context;
  90         ent->cmd        = cmd;
  91         ent->page_queue = page_queue;
  92
  93         return ent;
  94 }
  95
  96 static u8 alloc_token(struct mlx5_cmd *cmd)
  97 {
  98         u8 token;
  99
 100         spin_lock(&cmd->token_lock);
 101         cmd->token++;
 102         if (cmd->token == 0)
 103                 cmd->token++;
 104         token = cmd->token;
 105         spin_unlock(&cmd->token_lock);
 106
 107         return token;
 108 }
 109
 110 static int alloc_ent(struct mlx5_cmd *cmd)
 111 {
 112         unsigned long flags;
 113         int ret;
 114
 115         spin_lock_irqsave(&cmd->alloc_lock, flags);
 116         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 117         if (ret < cmd->max_reg_cmds)
 118                 clear_bit(ret, &cmd->bitmask);
 119         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 120
 121         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 122 }
 123
 124 static void free_ent(struct mlx5_cmd *cmd, int idx)
 125 {
 126         unsigned long flags;
 127
 128         spin_lock_irqsave(&cmd->alloc_lock, flags);
 129         set_bit(idx, &cmd->bitmask);
 130         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 131 }
 132
 133 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 134 {
 135         return cmd->cmd_buf + (idx << cmd->log_stride);
 136 }
 137
 138 static u8 xor8_buf(void *buf, size_t offset, int len)
 139 {
 140         u8 *ptr = buf;
 141         u8 sum = 0;
 142         int i;
 143         int end = len + offset;
 144
 145         for (i = offset; i < end; i++)
 146                 sum ^= ptr[i];
 147
 148         return sum;
 149 }
 150
 151 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 152 {
 153         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 154         int xor_len = sizeof(*block) - sizeof(block->data) - 1;
 155
 156         if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
 157                 return -EINVAL;
 158
 159         if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
 160                 return -EINVAL;
 161
 162         return 0;
 163 }
 164
 165 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
 166 {
 167         int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
 168         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 169
 170         block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
 171         block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
 172 }
 173
 174 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
 175 {
 176         struct mlx5_cmd_mailbox *next = msg->next;
 177         int size = msg->len;
 178         int blen = size - min_t(int, sizeof(msg->first.data), size);
 179         int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
 180                 / MLX5_CMD_DATA_BLOCK_SIZE;
 181         int i = 0;
 182
 183         for (i = 0; i < n && next; i++)  {
 184                 calc_block_sig(next->buf);
 185                 next = next->next;
 186         }
 187 }
 188
 189 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 190 {
 191         ent->lay->sig = ~xor8_buf(ent->lay, 0,  sizeof(*ent->lay));
 192         if (csum) {
 193                 calc_chain_sig(ent->in);
 194                 calc_chain_sig(ent->out);
 195         }
 196 }
 197
 198 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 199 {
 200         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 201         u8 own;
 202
 203         do {
 204                 own = ent->lay->status_own;
 205                 if (!(own & CMD_OWNER_HW)) {
 206                         ent->ret = 0;
 207                         return;
 208                 }
 209                 usleep_range(5000, 10000);
 210         } while (time_before(jiffies, poll_end));
 211
 212         ent->ret = -ETIMEDOUT;
 213 }
 214
 215 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 216 {
 217         kfree(ent);
 218 }
 219
 220
 221 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 222 {
 223         struct mlx5_cmd_mailbox *next = ent->out->next;
 224         int err;
 225         u8 sig;
 226         int size = ent->out->len;
 227         int blen = size - min_t(int, sizeof(ent->out->first.data), size);
 228         int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
 229                 / MLX5_CMD_DATA_BLOCK_SIZE;
 230         int i = 0;
 231
 232         sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
 233         if (sig != 0xff)
 234                 return -EINVAL;
 235
 236         for (i = 0; i < n && next; i++) {
 237                 err = verify_block_sig(next->buf);
 238                 if (err)
 239                         return err;
 240
 241                 next = next->next;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static void dump_buf(void *buf, int size, int data_only, int offset)
 248 {
 249         __be32 *p = buf;
 250         int i;
 251
 252         for (i = 0; i < size; i += 16) {
 253                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 254                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 255                          be32_to_cpu(p[3]));
 256                 p += 4;
 257                 offset += 16;
 258         }
 259         if (!data_only)
 260                 pr_debug("\n");
 261 }
 262
 263 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
 264                                        u32 *synd, u8 *status)
 265 {
 266         *synd = 0;
 267         *status = 0;
 268
 269         switch (op) {
 270         case MLX5_CMD_OP_TEARDOWN_HCA:
 271         case MLX5_CMD_OP_DISABLE_HCA:
 272         case MLX5_CMD_OP_MANAGE_PAGES:
 273         case MLX5_CMD_OP_DESTROY_MKEY:
 274         case MLX5_CMD_OP_DESTROY_EQ:
 275         case MLX5_CMD_OP_DESTROY_CQ:
 276         case MLX5_CMD_OP_DESTROY_QP:
 277         case MLX5_CMD_OP_DESTROY_PSV:
 278         case MLX5_CMD_OP_DESTROY_SRQ:
 279         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 280         case MLX5_CMD_OP_DESTROY_DCT:
 281         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 282         case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
 283         case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
 284         case MLX5_CMD_OP_DEALLOC_PD:
 285         case MLX5_CMD_OP_DEALLOC_UAR:
 286         case MLX5_CMD_OP_DETACH_FROM_MCG:
 287         case MLX5_CMD_OP_DEALLOC_XRCD:
 288         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 289         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 290         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 291         case MLX5_CMD_OP_DESTROY_LAG:
 292         case MLX5_CMD_OP_DESTROY_VPORT_LAG:
 293         case MLX5_CMD_OP_DESTROY_TIR:
 294         case MLX5_CMD_OP_DESTROY_SQ:
 295         case MLX5_CMD_OP_DESTROY_RQ:
 296         case MLX5_CMD_OP_DESTROY_RMP:
 297         case MLX5_CMD_OP_DESTROY_TIS:
 298         case MLX5_CMD_OP_DESTROY_RQT:
 299         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 300         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 301         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 302         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
 303         case MLX5_CMD_OP_2ERR_QP:
 304         case MLX5_CMD_OP_2RST_QP:
 305         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 306         case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
 307         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 308         case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
 309         case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
 310         case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
 311                 return MLX5_CMD_STAT_OK;
 312
 313         case MLX5_CMD_OP_QUERY_HCA_CAP:
 314         case MLX5_CMD_OP_QUERY_ADAPTER:
 315         case MLX5_CMD_OP_INIT_HCA:
 316         case MLX5_CMD_OP_ENABLE_HCA:
 317         case MLX5_CMD_OP_QUERY_PAGES:
 318         case MLX5_CMD_OP_SET_HCA_CAP:
 319         case MLX5_CMD_OP_QUERY_ISSI:
 320         case MLX5_CMD_OP_SET_ISSI:
 321         case MLX5_CMD_OP_CREATE_MKEY:
 322         case MLX5_CMD_OP_QUERY_MKEY:
 323         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 324         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 325         case MLX5_CMD_OP_CREATE_EQ:
 326         case MLX5_CMD_OP_QUERY_EQ:
 327         case MLX5_CMD_OP_GEN_EQE:
 328         case MLX5_CMD_OP_CREATE_CQ:
 329         case MLX5_CMD_OP_QUERY_CQ:
 330         case MLX5_CMD_OP_MODIFY_CQ:
 331         case MLX5_CMD_OP_CREATE_QP:
 332         case MLX5_CMD_OP_RST2INIT_QP:
 333         case MLX5_CMD_OP_INIT2RTR_QP:
 334         case MLX5_CMD_OP_RTR2RTS_QP:
 335         case MLX5_CMD_OP_RTS2RTS_QP:
 336         case MLX5_CMD_OP_SQERR2RTS_QP:
 337         case MLX5_CMD_OP_QUERY_QP:
 338         case MLX5_CMD_OP_SQD_RTS_QP:
 339         case MLX5_CMD_OP_INIT2INIT_QP:
 340         case MLX5_CMD_OP_CREATE_PSV:
 341         case MLX5_CMD_OP_CREATE_SRQ:
 342         case MLX5_CMD_OP_QUERY_SRQ:
 343         case MLX5_CMD_OP_ARM_RQ:
 344         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 345         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 346         case MLX5_CMD_OP_ARM_XRC_SRQ:
 347         case MLX5_CMD_OP_CREATE_DCT:
 348         case MLX5_CMD_OP_DRAIN_DCT:
 349         case MLX5_CMD_OP_QUERY_DCT:
 350         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 351         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 352         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 353         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 354         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 355         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 356         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 357         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 358         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 359         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 360         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 361         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 362         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 363         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 364         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 365         case MLX5_CMD_OP_SET_RATE_LIMIT:
 366         case MLX5_CMD_OP_QUERY_RATE_LIMIT:
 367         case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
 368         case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
 369         case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
 370         case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
 371         case MLX5_CMD_OP_ALLOC_PD:
 372         case MLX5_CMD_OP_ALLOC_UAR:
 373         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 374         case MLX5_CMD_OP_ACCESS_REG:
 375         case MLX5_CMD_OP_ATTACH_TO_MCG:
 376         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 377         case MLX5_CMD_OP_MAD_IFC:
 378         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 379         case MLX5_CMD_OP_SET_MAD_DEMUX:
 380         case MLX5_CMD_OP_NOP:
 381         case MLX5_CMD_OP_ALLOC_XRCD:
 382         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 383         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 384         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 385         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 386         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 387         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 388         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 389         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 390         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 391         case MLX5_CMD_OP_CREATE_LAG:
 392         case MLX5_CMD_OP_MODIFY_LAG:
 393         case MLX5_CMD_OP_QUERY_LAG:
 394         case MLX5_CMD_OP_CREATE_VPORT_LAG:
 395         case MLX5_CMD_OP_CREATE_TIR:
 396         case MLX5_CMD_OP_MODIFY_TIR:
 397         case MLX5_CMD_OP_QUERY_TIR:
 398         case MLX5_CMD_OP_CREATE_SQ:
 399         case MLX5_CMD_OP_MODIFY_SQ:
 400         case MLX5_CMD_OP_QUERY_SQ:
 401         case MLX5_CMD_OP_CREATE_RQ:
 402         case MLX5_CMD_OP_MODIFY_RQ:
 403         case MLX5_CMD_OP_QUERY_RQ:
 404         case MLX5_CMD_OP_CREATE_RMP:
 405         case MLX5_CMD_OP_MODIFY_RMP:
 406         case MLX5_CMD_OP_QUERY_RMP:
 407         case MLX5_CMD_OP_CREATE_TIS:
 408         case MLX5_CMD_OP_MODIFY_TIS:
 409         case MLX5_CMD_OP_QUERY_TIS:
 410         case MLX5_CMD_OP_CREATE_RQT:
 411         case MLX5_CMD_OP_MODIFY_RQT:
 412         case MLX5_CMD_OP_QUERY_RQT:
 413
 414         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 415         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 416         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 417         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 418         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 419         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
 420         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
 421         case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
 422         case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
 423                 *status = MLX5_DRIVER_STATUS_ABORTED;
 424                 *synd = MLX5_DRIVER_SYND;
 425                 return -EIO;
 426         default:
 427                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
 428                 return -EINVAL;
 429         }
 430 }
 431
 432 const char *mlx5_command_str(int command)
 433 {
 434 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
 435
 436         switch (command) {
 437         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
 438         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
 439         MLX5_COMMAND_STR_CASE(INIT_HCA);
 440         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
 441         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
 442         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
 443         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
 444         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
 445         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
 446         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
 447         MLX5_COMMAND_STR_CASE(SET_ISSI);
 448         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
 449         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
 450         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
 451         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
 452         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
 453         MLX5_COMMAND_STR_CASE(CREATE_EQ);
 454         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
 455         MLX5_COMMAND_STR_CASE(QUERY_EQ);
 456         MLX5_COMMAND_STR_CASE(GEN_EQE);
 457         MLX5_COMMAND_STR_CASE(CREATE_CQ);
 458         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
 459         MLX5_COMMAND_STR_CASE(QUERY_CQ);
 460         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
 461         MLX5_COMMAND_STR_CASE(CREATE_QP);
 462         MLX5_COMMAND_STR_CASE(DESTROY_QP);
 463         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
 464         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
 465         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
 466         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
 467         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
 468         MLX5_COMMAND_STR_CASE(2ERR_QP);
 469         MLX5_COMMAND_STR_CASE(2RST_QP);
 470         MLX5_COMMAND_STR_CASE(QUERY_QP);
 471         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
 472         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
 473         MLX5_COMMAND_STR_CASE(CREATE_PSV);
 474         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
 475         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
 476         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
 477         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
 478         MLX5_COMMAND_STR_CASE(ARM_RQ);
 479         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
 480         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
 481         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
 482         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
 483         MLX5_COMMAND_STR_CASE(CREATE_DCT);
 484         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
 485         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
 486         MLX5_COMMAND_STR_CASE(QUERY_DCT);
 487         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
 488         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
 489         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
 490         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
 491         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
 492         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
 493         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
 494         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
 495         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
 496         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
 497         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
 498         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
 499         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
 500         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
 501         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
 502         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
 503         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
 504         MLX5_COMMAND_STR_CASE(SET_RATE_LIMIT);
 505         MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
 506         MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
 507         MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
 508         MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
 509         MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
 510         MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
 511         MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
 512         MLX5_COMMAND_STR_CASE(ALLOC_PD);
 513         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
 514         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
 515         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
 516         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
 517         MLX5_COMMAND_STR_CASE(ACCESS_REG);
 518         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
 519         MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
 520         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
 521         MLX5_COMMAND_STR_CASE(MAD_IFC);
 522         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
 523         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
 524         MLX5_COMMAND_STR_CASE(NOP);
 525         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
 526         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
 527         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
 528         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
 529         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
 530         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
 531         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
 532         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
 533         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
 534         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
 535         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
 536         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
 537         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
 538         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
 539         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
 540         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
 541         MLX5_COMMAND_STR_CASE(CREATE_LAG);
 542         MLX5_COMMAND_STR_CASE(MODIFY_LAG);
 543         MLX5_COMMAND_STR_CASE(QUERY_LAG);
 544         MLX5_COMMAND_STR_CASE(DESTROY_LAG);
 545         MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
 546         MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
 547         MLX5_COMMAND_STR_CASE(CREATE_TIR);
 548         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
 549         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
 550         MLX5_COMMAND_STR_CASE(QUERY_TIR);
 551         MLX5_COMMAND_STR_CASE(CREATE_SQ);
 552         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
 553         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
 554         MLX5_COMMAND_STR_CASE(QUERY_SQ);
 555         MLX5_COMMAND_STR_CASE(CREATE_RQ);
 556         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
 557         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
 558         MLX5_COMMAND_STR_CASE(QUERY_RQ);
 559         MLX5_COMMAND_STR_CASE(CREATE_RMP);
 560         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
 561         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
 562         MLX5_COMMAND_STR_CASE(QUERY_RMP);
 563         MLX5_COMMAND_STR_CASE(CREATE_TIS);
 564         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
 565         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
 566         MLX5_COMMAND_STR_CASE(QUERY_TIS);
 567         MLX5_COMMAND_STR_CASE(CREATE_RQT);
 568         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
 569         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
 570         MLX5_COMMAND_STR_CASE(QUERY_RQT);
 571         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
 572         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
 573         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
 574         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
 575         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
 576         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
 577         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
 578         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
 579         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
 580         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
 581         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
 582         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
 583         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
 584         MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
 585         MLX5_COMMAND_STR_CASE(ALLOC_ENCAP_HEADER);
 586         MLX5_COMMAND_STR_CASE(DEALLOC_ENCAP_HEADER);
 587         MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
 588         MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
 589         default: return "unknown command opcode";
 590         }
 591 }
 592
 593 static const char *cmd_status_str(u8 status)
 594 {
 595         switch (status) {
 596         case MLX5_CMD_STAT_OK:
 597                 return "OK";
 598         case MLX5_CMD_STAT_INT_ERR:
 599                 return "internal error";
 600         case MLX5_CMD_STAT_BAD_OP_ERR:
 601                 return "bad operation";
 602         case MLX5_CMD_STAT_BAD_PARAM_ERR:
 603                 return "bad parameter";
 604         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
 605                 return "bad system state";
 606         case MLX5_CMD_STAT_BAD_RES_ERR:
 607                 return "bad resource";
 608         case MLX5_CMD_STAT_RES_BUSY:
 609                 return "resource busy";
 610         case MLX5_CMD_STAT_LIM_ERR:
 611                 return "limits exceeded";
 612         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
 613                 return "bad resource state";
 614         case MLX5_CMD_STAT_IX_ERR:
 615                 return "bad index";
 616         case MLX5_CMD_STAT_NO_RES_ERR:
 617                 return "no resources";
 618         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
 619                 return "bad input length";
 620         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
 621                 return "bad output length";
 622         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
 623                 return "bad QP state";
 624         case MLX5_CMD_STAT_BAD_PKT_ERR:
 625                 return "bad packet (discarded)";
 626         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
 627                 return "bad size too many outstanding CQEs";
 628         default:
 629                 return "unknown status";
 630         }
 631 }
 632
 633 static int cmd_status_to_err(u8 status)
 634 {
 635         switch (status) {
 636         case MLX5_CMD_STAT_OK:                          return 0;
 637         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
 638         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
 639         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
 640         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
 641         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
 642         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
 643         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
 644         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
 645         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
 646         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
 647         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
 648         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
 649         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
 650         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
 651         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
 652         default:                                        return -EIO;
 653         }
 654 }
 655
 656 struct mlx5_ifc_mbox_out_bits {
 657         u8         status[0x8];
 658         u8         reserved_at_8[0x18];
 659
 660         u8         syndrome[0x20];
 661
 662         u8         reserved_at_40[0x40];
 663 };
 664
 665 struct mlx5_ifc_mbox_in_bits {
 666         u8         opcode[0x10];
 667         u8         reserved_at_10[0x10];
 668
 669         u8         reserved_at_20[0x10];
 670         u8         op_mod[0x10];
 671
 672         u8         reserved_at_40[0x40];
 673 };
 674
 675 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
 676 {
 677         *status = MLX5_GET(mbox_out, out, status);
 678         *syndrome = MLX5_GET(mbox_out, out, syndrome);
 679 }
 680
 681 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
 682 {
 683         u32 syndrome;
 684         u8  status;
 685         u16 opcode;
 686         u16 op_mod;
 687
 688         mlx5_cmd_mbox_status(out, &status, &syndrome);
 689         if (!status)
 690                 return 0;
 691
 692         opcode = MLX5_GET(mbox_in, in, opcode);
 693         op_mod = MLX5_GET(mbox_in, in, op_mod);
 694
 695         mlx5_core_err(dev,
 696                       "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
 697                       mlx5_command_str(opcode),
 698                       opcode, op_mod,
 699                       cmd_status_str(status),
 700                       status,
 701                       syndrome);
 702
 703         return cmd_status_to_err(status);
 704 }
 705
 706 static void dump_command(struct mlx5_core_dev *dev,
 707                          struct mlx5_cmd_work_ent *ent, int input)
 708 {
 709         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 710         u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
 711         struct mlx5_cmd_mailbox *next = msg->next;
 712         int data_only;
 713         u32 offset = 0;
 714         int dump_len;
 715
 716         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 717
 718         if (data_only)
 719                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 720                                    "dump command data %s(0x%x) %s\n",
 721                                    mlx5_command_str(op), op,
 722                                    input ? "INPUT" : "OUTPUT");
 723         else
 724                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 725                               mlx5_command_str(op), op,
 726                               input ? "INPUT" : "OUTPUT");
 727
 728         if (data_only) {
 729                 if (input) {
 730                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 731                         offset += sizeof(ent->lay->in);
 732                 } else {
 733                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 734                         offset += sizeof(ent->lay->out);
 735                 }
 736         } else {
 737                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 738                 offset += sizeof(*ent->lay);
 739         }
 740
 741         while (next && offset < msg->len) {
 742                 if (data_only) {
 743                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 744                         dump_buf(next->buf, dump_len, 1, offset);
 745                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 746                 } else {
 747                         mlx5_core_dbg(dev, "command block:\n");
 748                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 749                         offset += sizeof(struct mlx5_cmd_prot_block);
 750                 }
 751                 next = next->next;
 752         }
 753
 754         if (data_only)
 755                 pr_debug("\n");
 756 }
 757
 758 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 759 {
 760         return MLX5_GET(mbox_in, in->first.data, opcode);
 761 }
 762
 763 static void cb_timeout_handler(struct work_struct *work)
 764 {
 765         struct delayed_work *dwork = container_of(work, struct delayed_work,
 766                                                   work);
 767         struct mlx5_cmd_work_ent *ent = container_of(dwork,
 768                                                      struct mlx5_cmd_work_ent,
 769                                                      cb_timeout_work);
 770         struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
 771                                                  cmd);
 772
 773         ent->ret = -ETIMEDOUT;
 774         mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 775                        mlx5_command_str(msg_to_opcode(ent->in)),
 776                        msg_to_opcode(ent->in));
 777         mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 778 }
 779
 780 static void cmd_work_handler(struct work_struct *work)
 781 {
 782         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 783         struct mlx5_cmd *cmd = ent->cmd;
 784         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 785         unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 786         struct mlx5_cmd_layout *lay;
 787         struct semaphore *sem;
 788         unsigned long flags;
 789
 790         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 791         down(sem);
 792         if (!ent->page_queue) {
 793                 ent->idx = alloc_ent(cmd);
 794                 if (ent->idx < 0) {
 795                         mlx5_core_err(dev, "failed to allocate command entry\n");
 796                         up(sem);
 797                         return;
 798                 }
 799         } else {
 800                 ent->idx = cmd->max_reg_cmds;
 801                 spin_lock_irqsave(&cmd->alloc_lock, flags);
 802                 clear_bit(ent->idx, &cmd->bitmask);
 803                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 804         }
 805
 806         cmd->ent_arr[ent->idx] = ent;
 807         set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
 808         lay = get_inst(cmd, ent->idx);
 809         ent->lay = lay;
 810         memset(lay, 0, sizeof(*lay));
 811         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 812         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 813         if (ent->in->next)
 814                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 815         lay->inlen = cpu_to_be32(ent->in->len);
 816         if (ent->out->next)
 817                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 818         lay->outlen = cpu_to_be32(ent->out->len);
 819         lay->type = MLX5_PCI_CMD_XPORT;
 820         lay->token = ent->token;
 821         lay->status_own = CMD_OWNER_HW;
 822         set_signature(ent, !cmd->checksum_disabled);
 823         dump_command(dev, ent, 1);
 824         ent->ts1 = ktime_get_ns();
 825
 826         if (ent->callback)
 827                 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
 828
 829         /* Skip sending command to fw if internal error */
 830         if (pci_channel_offline(dev->pdev) ||
 831             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
 832                 u8 status = 0;
 833                 u32 drv_synd;
 834
 835                 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
 836                 MLX5_SET(mbox_out, ent->out, status, status);
 837                 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
 838
 839                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 840                 return;
 841         }
 842
 843         /* ring doorbell after the descriptor is valid */
 844         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
 845         wmb();
 846         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 847         mmiowb();
 848         /* if not in polling don't use ent after this point */
 849         if (cmd->mode == CMD_MODE_POLLING) {
 850                 poll_timeout(ent);
 851                 /* make sure we read the descriptor after ownership is SW */
 852                 rmb();
 853                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
 854         }
 855 }
 856
 857 static const char *deliv_status_to_str(u8 status)
 858 {
 859         switch (status) {
 860         case MLX5_CMD_DELIVERY_STAT_OK:
 861                 return "no errors";
 862         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 863                 return "signature error";
 864         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 865                 return "token error";
 866         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 867                 return "bad block number";
 868         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 869                 return "output pointer not aligned to block size";
 870         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 871                 return "input pointer not aligned to block size";
 872         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 873                 return "firmware internal error";
 874         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 875                 return "command input length error";
 876         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 877                 return "command ouput length error";
 878         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 879                 return "reserved fields not cleared";
 880         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 881                 return "bad command descriptor type";
 882         default:
 883                 return "unknown status code";
 884         }
 885 }
 886
 887 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 888 {
 889         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 890         struct mlx5_cmd *cmd = &dev->cmd;
 891         int err;
 892
 893         if (cmd->mode == CMD_MODE_POLLING) {
 894                 wait_for_completion(&ent->done);
 895         } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
 896                 ent->ret = -ETIMEDOUT;
 897                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 898         }
 899
 900         err = ent->ret;
 901
 902         if (err == -ETIMEDOUT) {
 903                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 904                                mlx5_command_str(msg_to_opcode(ent->in)),
 905                                msg_to_opcode(ent->in));
 906         }
 907         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
 908                       err, deliv_status_to_str(ent->status), ent->status);
 909
 910         return err;
 911 }
 912
 913 /*  Notes:
 914  *    1. Callback functions may not sleep
 915  *    2. page queue commands do not support asynchrous completion
 916  */
 917 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 918                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
 919                            mlx5_cmd_cbk_t callback,
 920                            void *context, int page_queue, u8 *status,
 921                            u8 token)
 922 {
 923         struct mlx5_cmd *cmd = &dev->cmd;
 924         struct mlx5_cmd_work_ent *ent;
 925         struct mlx5_cmd_stats *stats;
 926         int err = 0;
 927         s64 ds;
 928         u16 op;
 929
 930         if (callback && page_queue)
 931                 return -EINVAL;
 932
 933         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
 934                         page_queue);
 935         if (IS_ERR(ent))
 936                 return PTR_ERR(ent);
 937
 938         ent->token = token;
 939
 940         if (!callback)
 941                 init_completion(&ent->done);
 942
 943         INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
 944         INIT_WORK(&ent->work, cmd_work_handler);
 945         if (page_queue) {
 946                 cmd_work_handler(&ent->work);
 947         } else if (!queue_work(cmd->wq, &ent->work)) {
 948                 mlx5_core_warn(dev, "failed to queue work\n");
 949                 err = -ENOMEM;
 950                 goto out_free;
 951         }
 952
 953         if (callback)
 954                 goto out;
 955
 956         err = wait_func(dev, ent);
 957         if (err == -ETIMEDOUT)
 958                 goto out_free;
 959
 960         ds = ent->ts2 - ent->ts1;
 961         op = MLX5_GET(mbox_in, in->first.data, opcode);
 962         if (op < ARRAY_SIZE(cmd->stats)) {
 963                 stats = &cmd->stats[op];
 964                 spin_lock_irq(&stats->lock);
 965                 stats->sum += ds;
 966                 ++stats->n;
 967                 spin_unlock_irq(&stats->lock);
 968         }
 969         mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
 970                            "fw exec time for %s is %lld nsec\n",
 971                            mlx5_command_str(op), ds);
 972         *status = ent->status;
 973
 974 out_free:
 975         free_cmd(ent);
 976 out:
 977         return err;
 978 }
 979
 980 static ssize_t dbg_write(struct file *filp, const char __user *buf,
 981                          size_t count, loff_t *pos)
 982 {
 983         struct mlx5_core_dev *dev = filp->private_data;
 984         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 985         char lbuf[3];
 986         int err;
 987
 988         if (!dbg->in_msg || !dbg->out_msg)
 989                 return -ENOMEM;
 990
 991         if (copy_from_user(lbuf, buf, sizeof(lbuf)))
 992                 return -EFAULT;
 993
 994         lbuf[sizeof(lbuf) - 1] = 0;
 995
 996         if (strcmp(lbuf, "go"))
 997                 return -EINVAL;
 998
 999         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1000
1001         return err ? err : count;
1002 }
1003
1004
1005 static const struct file_operations fops = {
1006         .owner  = THIS_MODULE,
1007         .open   = simple_open,
1008         .write  = dbg_write,
1009 };
1010
1011 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1012                             u8 token)
1013 {
1014         struct mlx5_cmd_prot_block *block;
1015         struct mlx5_cmd_mailbox *next;
1016         int copy;
1017
1018         if (!to || !from)
1019                 return -ENOMEM;
1020
1021         copy = min_t(int, size, sizeof(to->first.data));
1022         memcpy(to->first.data, from, copy);
1023         size -= copy;
1024         from += copy;
1025
1026         next = to->next;
1027         while (size) {
1028                 if (!next) {
1029                         /* this is a BUG */
1030                         return -ENOMEM;
1031                 }
1032
1033                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1034                 block = next->buf;
1035                 memcpy(block->data, from, copy);
1036                 from += copy;
1037                 size -= copy;
1038                 block->token = token;
1039                 next = next->next;
1040         }
1041
1042         return 0;
1043 }
1044
1045 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1046 {
1047         struct mlx5_cmd_prot_block *block;
1048         struct mlx5_cmd_mailbox *next;
1049         int copy;
1050
1051         if (!to || !from)
1052                 return -ENOMEM;
1053
1054         copy = min_t(int, size, sizeof(from->first.data));
1055         memcpy(to, from->first.data, copy);
1056         size -= copy;
1057         to += copy;
1058
1059         next = from->next;
1060         while (size) {
1061                 if (!next) {
1062                         /* this is a BUG */
1063                         return -ENOMEM;
1064                 }
1065
1066                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1067                 block = next->buf;
1068
1069                 memcpy(to, block->data, copy);
1070                 to += copy;
1071                 size -= copy;
1072                 next = next->next;
1073         }
1074
1075         return 0;
1076 }
1077
1078 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1079                                               gfp_t flags)
1080 {
1081         struct mlx5_cmd_mailbox *mailbox;
1082
1083         mailbox = kmalloc(sizeof(*mailbox), flags);
1084         if (!mailbox)
1085                 return ERR_PTR(-ENOMEM);
1086
1087         mailbox->buf = pci_pool_zalloc(dev->cmd.pool, flags,
1088                                        &mailbox->dma);
1089         if (!mailbox->buf) {
1090                 mlx5_core_dbg(dev, "failed allocation\n");
1091                 kfree(mailbox);
1092                 return ERR_PTR(-ENOMEM);
1093         }
1094         mailbox->next = NULL;
1095
1096         return mailbox;
1097 }
1098
1099 static void free_cmd_box(struct mlx5_core_dev *dev,
1100                          struct mlx5_cmd_mailbox *mailbox)
1101 {
1102         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1103         kfree(mailbox);
1104 }
1105
1106 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1107                                                gfp_t flags, int size,
1108                                                u8 token)
1109 {
1110         struct mlx5_cmd_mailbox *tmp, *head = NULL;
1111         struct mlx5_cmd_prot_block *block;
1112         struct mlx5_cmd_msg *msg;
1113         int blen;
1114         int err;
1115         int n;
1116         int i;
1117
1118         msg = kzalloc(sizeof(*msg), flags);
1119         if (!msg)
1120                 return ERR_PTR(-ENOMEM);
1121
1122         blen = size - min_t(int, sizeof(msg->first.data), size);
1123         n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
1124
1125         for (i = 0; i < n; i++) {
1126                 tmp = alloc_cmd_box(dev, flags);
1127                 if (IS_ERR(tmp)) {
1128                         mlx5_core_warn(dev, "failed allocating block\n");
1129                         err = PTR_ERR(tmp);
1130                         goto err_alloc;
1131                 }
1132
1133                 block = tmp->buf;
1134                 tmp->next = head;
1135                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1136                 block->block_num = cpu_to_be32(n - i - 1);
1137                 block->token = token;
1138                 head = tmp;
1139         }
1140         msg->next = head;
1141         msg->len = size;
1142         return msg;
1143
1144 err_alloc:
1145         while (head) {
1146                 tmp = head->next;
1147                 free_cmd_box(dev, head);
1148                 head = tmp;
1149         }
1150         kfree(msg);
1151
1152         return ERR_PTR(err);
1153 }
1154
1155 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1156                                   struct mlx5_cmd_msg *msg)
1157 {
1158         struct mlx5_cmd_mailbox *head = msg->next;
1159         struct mlx5_cmd_mailbox *next;
1160
1161         while (head) {
1162                 next = head->next;
1163                 free_cmd_box(dev, head);
1164                 head = next;
1165         }
1166         kfree(msg);
1167 }
1168
1169 static ssize_t data_write(struct file *filp, const char __user *buf,
1170                           size_t count, loff_t *pos)
1171 {
1172         struct mlx5_core_dev *dev = filp->private_data;
1173         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1174         void *ptr;
1175
1176         if (*pos != 0)
1177                 return -EINVAL;
1178
1179         kfree(dbg->in_msg);
1180         dbg->in_msg = NULL;
1181         dbg->inlen = 0;
1182         ptr = memdup_user(buf, count);
1183         if (IS_ERR(ptr))
1184                 return PTR_ERR(ptr);
1185         dbg->in_msg = ptr;
1186         dbg->inlen = count;
1187
1188         *pos = count;
1189
1190         return count;
1191 }
1192
1193 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1194                          loff_t *pos)
1195 {
1196         struct mlx5_core_dev *dev = filp->private_data;
1197         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1198         int copy;
1199
1200         if (*pos)
1201                 return 0;
1202
1203         if (!dbg->out_msg)
1204                 return -ENOMEM;
1205
1206         copy = min_t(int, count, dbg->outlen);
1207         if (copy_to_user(buf, dbg->out_msg, copy))
1208                 return -EFAULT;
1209
1210         *pos += copy;
1211
1212         return copy;
1213 }
1214
1215 static const struct file_operations dfops = {
1216         .owner  = THIS_MODULE,
1217         .open   = simple_open,
1218         .write  = data_write,
1219         .read   = data_read,
1220 };
1221
1222 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1223                            loff_t *pos)
1224 {
1225         struct mlx5_core_dev *dev = filp->private_data;
1226         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1227         char outlen[8];
1228         int err;
1229
1230         if (*pos)
1231                 return 0;
1232
1233         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1234         if (err < 0)
1235                 return err;
1236
1237         if (copy_to_user(buf, &outlen, err))
1238                 return -EFAULT;
1239
1240         *pos += err;
1241
1242         return err;
1243 }
1244
1245 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1246                             size_t count, loff_t *pos)
1247 {
1248         struct mlx5_core_dev *dev = filp->private_data;
1249         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1250         char outlen_str[8];
1251         int outlen;
1252         void *ptr;
1253         int err;
1254
1255         if (*pos != 0 || count > 6)
1256                 return -EINVAL;
1257
1258         kfree(dbg->out_msg);
1259         dbg->out_msg = NULL;
1260         dbg->outlen = 0;
1261
1262         if (copy_from_user(outlen_str, buf, count))
1263                 return -EFAULT;
1264
1265         outlen_str[7] = 0;
1266
1267         err = sscanf(outlen_str, "%d", &outlen);
1268         if (err < 0)
1269                 return err;
1270
1271         ptr = kzalloc(outlen, GFP_KERNEL);
1272         if (!ptr)
1273                 return -ENOMEM;
1274
1275         dbg->out_msg = ptr;
1276         dbg->outlen = outlen;
1277
1278         *pos = count;
1279
1280         return count;
1281 }
1282
1283 static const struct file_operations olfops = {
1284         .owner  = THIS_MODULE,
1285         .open   = simple_open,
1286         .write  = outlen_write,
1287         .read   = outlen_read,
1288 };
1289
1290 static void set_wqname(struct mlx5_core_dev *dev)
1291 {
1292         struct mlx5_cmd *cmd = &dev->cmd;
1293
1294         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1295                  dev_name(&dev->pdev->dev));
1296 }
1297
1298 static void clean_debug_files(struct mlx5_core_dev *dev)
1299 {
1300         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1301
1302         if (!mlx5_debugfs_root)
1303                 return;
1304
1305         mlx5_cmdif_debugfs_cleanup(dev);
1306         debugfs_remove_recursive(dbg->dbg_root);
1307 }
1308
1309 static int create_debugfs_files(struct mlx5_core_dev *dev)
1310 {
1311         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1312         int err = -ENOMEM;
1313
1314         if (!mlx5_debugfs_root)
1315                 return 0;
1316
1317         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1318         if (!dbg->dbg_root)
1319                 return err;
1320
1321         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1322                                           dev, &dfops);
1323         if (!dbg->dbg_in)
1324                 goto err_dbg;
1325
1326         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1327                                            dev, &dfops);
1328         if (!dbg->dbg_out)
1329                 goto err_dbg;
1330
1331         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1332                                               dev, &olfops);
1333         if (!dbg->dbg_outlen)
1334                 goto err_dbg;
1335
1336         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1337                                             &dbg->status);
1338         if (!dbg->dbg_status)
1339                 goto err_dbg;
1340
1341         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1342         if (!dbg->dbg_run)
1343                 goto err_dbg;
1344
1345         mlx5_cmdif_debugfs_init(dev);
1346
1347         return 0;
1348
1349 err_dbg:
1350         clean_debug_files(dev);
1351         return err;
1352 }
1353
1354 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1355 {
1356         struct mlx5_cmd *cmd = &dev->cmd;
1357         int i;
1358
1359         for (i = 0; i < cmd->max_reg_cmds; i++)
1360                 down(&cmd->sem);
1361         down(&cmd->pages_sem);
1362
1363         cmd->mode = mode;
1364
1365         up(&cmd->pages_sem);
1366         for (i = 0; i < cmd->max_reg_cmds; i++)
1367                 up(&cmd->sem);
1368 }
1369
1370 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1371 {
1372         mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1373 }
1374
1375 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1376 {
1377         mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1378 }
1379
1380 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1381 {
1382         unsigned long flags;
1383
1384         if (msg->parent) {
1385                 spin_lock_irqsave(&msg->parent->lock, flags);
1386                 list_add_tail(&msg->list, &msg->parent->head);
1387                 spin_unlock_irqrestore(&msg->parent->lock, flags);
1388         } else {
1389                 mlx5_free_cmd_msg(dev, msg);
1390         }
1391 }
1392
1393 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1394 {
1395         struct mlx5_cmd *cmd = &dev->cmd;
1396         struct mlx5_cmd_work_ent *ent;
1397         mlx5_cmd_cbk_t callback;
1398         void *context;
1399         int err;
1400         int i;
1401         s64 ds;
1402         struct mlx5_cmd_stats *stats;
1403         unsigned long flags;
1404         unsigned long vector;
1405
1406         /* there can be at most 32 command queues */
1407         vector = vec & 0xffffffff;
1408         for (i = 0; i < (1 << cmd->log_sz); i++) {
1409                 if (test_bit(i, &vector)) {
1410                         struct semaphore *sem;
1411
1412                         ent = cmd->ent_arr[i];
1413
1414                         /* if we already completed the command, ignore it */
1415                         if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1416                                                 &ent->state)) {
1417                                 /* only real completion can free the cmd slot */
1418                                 if (!forced) {
1419                                         mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1420                                                       ent->idx);
1421                                         free_ent(cmd, ent->idx);
1422                                 }
1423                                 continue;
1424                         }
1425
1426                         if (ent->callback)
1427                                 cancel_delayed_work(&ent->cb_timeout_work);
1428                         if (ent->page_queue)
1429                                 sem = &cmd->pages_sem;
1430                         else
1431                                 sem = &cmd->sem;
1432                         ent->ts2 = ktime_get_ns();
1433                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1434                         dump_command(dev, ent, 0);
1435                         if (!ent->ret) {
1436                                 if (!cmd->checksum_disabled)
1437                                         ent->ret = verify_signature(ent);
1438                                 else
1439                                         ent->ret = 0;
1440                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1441                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1442                                 else
1443                                         ent->status = ent->lay->status_own >> 1;
1444
1445                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1446                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1447                         }
1448
1449                         /* only real completion will free the entry slot */
1450                         if (!forced)
1451                                 free_ent(cmd, ent->idx);
1452
1453                         if (ent->callback) {
1454                                 ds = ent->ts2 - ent->ts1;
1455                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1456                                         stats = &cmd->stats[ent->op];
1457                                         spin_lock_irqsave(&stats->lock, flags);
1458                                         stats->sum += ds;
1459                                         ++stats->n;
1460                                         spin_unlock_irqrestore(&stats->lock, flags);
1461                                 }
1462
1463                                 callback = ent->callback;
1464                                 context = ent->context;
1465                                 err = ent->ret;
1466                                 if (!err) {
1467                                         err = mlx5_copy_from_msg(ent->uout,
1468                                                                  ent->out,
1469                                                                  ent->uout_size);
1470
1471                                         err = err ? err : mlx5_cmd_check(dev,
1472                                                                         ent->in->first.data,
1473                                                                         ent->uout);
1474                                 }
1475
1476                                 mlx5_free_cmd_msg(dev, ent->out);
1477                                 free_msg(dev, ent->in);
1478
1479                                 err = err ? err : ent->status;
1480                                 free_cmd(ent);
1481                                 callback(err, context);
1482                         } else {
1483                                 complete(&ent->done);
1484                         }
1485                         up(sem);
1486                 }
1487         }
1488 }
1489 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1490
1491 static int status_to_err(u8 status)
1492 {
1493         return status ? -1 : 0; /* TBD more meaningful codes */
1494 }
1495
1496 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1497                                       gfp_t gfp)
1498 {
1499         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1500         struct cmd_msg_cache *ch = NULL;
1501         struct mlx5_cmd *cmd = &dev->cmd;
1502         int i;
1503
1504         if (in_size <= 16)
1505                 goto cache_miss;
1506
1507         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1508                 ch = &cmd->cache[i];
1509                 if (in_size > ch->max_inbox_size)
1510                         continue;
1511                 spin_lock_irq(&ch->lock);
1512                 if (list_empty(&ch->head)) {
1513                         spin_unlock_irq(&ch->lock);
1514                         continue;
1515                 }
1516                 msg = list_entry(ch->head.next, typeof(*msg), list);
1517                 /* For cached lists, we must explicitly state what is
1518                  * the real size
1519                  */
1520                 msg->len = in_size;
1521                 list_del(&msg->list);
1522                 spin_unlock_irq(&ch->lock);
1523                 break;
1524         }
1525
1526         if (!IS_ERR(msg))
1527                 return msg;
1528
1529 cache_miss:
1530         msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1531         return msg;
1532 }
1533
1534 static int is_manage_pages(void *in)
1535 {
1536         return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1537 }
1538
1539 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1540                     int out_size, mlx5_cmd_cbk_t callback, void *context)
1541 {
1542         struct mlx5_cmd_msg *inb;
1543         struct mlx5_cmd_msg *outb;
1544         int pages_queue;
1545         gfp_t gfp;
1546         int err;
1547         u8 status = 0;
1548         u32 drv_synd;
1549         u8 token;
1550
1551         if (pci_channel_offline(dev->pdev) ||
1552             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1553                 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1554
1555                 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1556                 MLX5_SET(mbox_out, out, status, status);
1557                 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1558                 return err;
1559         }
1560
1561         pages_queue = is_manage_pages(in);
1562         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1563
1564         inb = alloc_msg(dev, in_size, gfp);
1565         if (IS_ERR(inb)) {
1566                 err = PTR_ERR(inb);
1567                 return err;
1568         }
1569
1570         token = alloc_token(&dev->cmd);
1571
1572         err = mlx5_copy_to_msg(inb, in, in_size, token);
1573         if (err) {
1574                 mlx5_core_warn(dev, "err %d\n", err);
1575                 goto out_in;
1576         }
1577
1578         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1579         if (IS_ERR(outb)) {
1580                 err = PTR_ERR(outb);
1581                 goto out_in;
1582         }
1583
1584         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1585                               pages_queue, &status, token);
1586         if (err)
1587                 goto out_out;
1588
1589         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1590         if (status) {
1591                 err = status_to_err(status);
1592                 goto out_out;
1593         }
1594
1595         if (!callback)
1596                 err = mlx5_copy_from_msg(out, outb, out_size);
1597
1598 out_out:
1599         if (!callback)
1600                 mlx5_free_cmd_msg(dev, outb);
1601
1602 out_in:
1603         if (!callback)
1604                 free_msg(dev, inb);
1605         return err;
1606 }
1607
1608 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1609                   int out_size)
1610 {
1611         int err;
1612
1613         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1614         return err ? : mlx5_cmd_check(dev, in, out);
1615 }
1616 EXPORT_SYMBOL(mlx5_cmd_exec);
1617
1618 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1619                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1620                      void *context)
1621 {
1622         return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1623 }
1624 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1625
1626 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1627 {
1628         struct cmd_msg_cache *ch;
1629         struct mlx5_cmd_msg *msg;
1630         struct mlx5_cmd_msg *n;
1631         int i;
1632
1633         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1634                 ch = &dev->cmd.cache[i];
1635                 list_for_each_entry_safe(msg, n, &ch->head, list) {
1636                         list_del(&msg->list);
1637                         mlx5_free_cmd_msg(dev, msg);
1638                 }
1639         }
1640 }
1641
1642 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1643         512, 32, 16, 8, 2
1644 };
1645
1646 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1647         16 + MLX5_CMD_DATA_BLOCK_SIZE,
1648         16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1649         16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1650         16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1651         16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1652 };
1653
1654 static void create_msg_cache(struct mlx5_core_dev *dev)
1655 {
1656         struct mlx5_cmd *cmd = &dev->cmd;
1657         struct cmd_msg_cache *ch;
1658         struct mlx5_cmd_msg *msg;
1659         int i;
1660         int k;
1661
1662         /* Initialize and fill the caches with initial entries */
1663         for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1664                 ch = &cmd->cache[k];
1665                 spin_lock_init(&ch->lock);
1666                 INIT_LIST_HEAD(&ch->head);
1667                 ch->num_ent = cmd_cache_num_ent[k];
1668                 ch->max_inbox_size = cmd_cache_ent_size[k];
1669                 for (i = 0; i < ch->num_ent; i++) {
1670                         msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1671                                                  ch->max_inbox_size, 0);
1672                         if (IS_ERR(msg))
1673                                 break;
1674                         msg->parent = ch;
1675                         list_add_tail(&msg->list, &ch->head);
1676                 }
1677         }
1678 }
1679
1680 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1681 {
1682         struct device *ddev = &dev->pdev->dev;
1683
1684         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1685                                                  &cmd->alloc_dma, GFP_KERNEL);
1686         if (!cmd->cmd_alloc_buf)
1687                 return -ENOMEM;
1688
1689         /* make sure it is aligned to 4K */
1690         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1691                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1692                 cmd->dma = cmd->alloc_dma;
1693                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1694                 return 0;
1695         }
1696
1697         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1698                           cmd->alloc_dma);
1699         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1700                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1701                                                  &cmd->alloc_dma, GFP_KERNEL);
1702         if (!cmd->cmd_alloc_buf)
1703                 return -ENOMEM;
1704
1705         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1706         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1707         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1708         return 0;
1709 }
1710
1711 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1712 {
1713         struct device *ddev = &dev->pdev->dev;
1714
1715         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1716                           cmd->alloc_dma);
1717 }
1718
1719 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1720 {
1721         int size = sizeof(struct mlx5_cmd_prot_block);
1722         int align = roundup_pow_of_two(size);
1723         struct mlx5_cmd *cmd = &dev->cmd;
1724         u32 cmd_h, cmd_l;
1725         u16 cmd_if_rev;
1726         int err;
1727         int i;
1728
1729         memset(cmd, 0, sizeof(*cmd));
1730         cmd_if_rev = cmdif_rev(dev);
1731         if (cmd_if_rev != CMD_IF_REV) {
1732                 dev_err(&dev->pdev->dev,
1733                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1734                         CMD_IF_REV, cmd_if_rev);
1735                 return -EINVAL;
1736         }
1737
1738         cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1739         if (!cmd->pool)
1740                 return -ENOMEM;
1741
1742         err = alloc_cmd_page(dev, cmd);
1743         if (err)
1744                 goto err_free_pool;
1745
1746         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1747         cmd->log_sz = cmd_l >> 4 & 0xf;
1748         cmd->log_stride = cmd_l & 0xf;
1749         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1750                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1751                         1 << cmd->log_sz);
1752                 err = -EINVAL;
1753                 goto err_free_page;
1754         }
1755
1756         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1757                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1758                 err = -EINVAL;
1759                 goto err_free_page;
1760         }
1761
1762         cmd->checksum_disabled = 1;
1763         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1764         cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1765
1766         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1767         if (cmd->cmdif_rev > CMD_IF_REV) {
1768                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1769                         CMD_IF_REV, cmd->cmdif_rev);
1770                 err = -EOPNOTSUPP;
1771                 goto err_free_page;
1772         }
1773
1774         spin_lock_init(&cmd->alloc_lock);
1775         spin_lock_init(&cmd->token_lock);
1776         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1777                 spin_lock_init(&cmd->stats[i].lock);
1778
1779         sema_init(&cmd->sem, cmd->max_reg_cmds);
1780         sema_init(&cmd->pages_sem, 1);
1781
1782         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1783         cmd_l = (u32)(cmd->dma);
1784         if (cmd_l & 0xfff) {
1785                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1786                 err = -ENOMEM;
1787                 goto err_free_page;
1788         }
1789
1790         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1791         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1792
1793         /* Make sure firmware sees the complete address before we proceed */
1794         wmb();
1795
1796         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1797
1798         cmd->mode = CMD_MODE_POLLING;
1799
1800         create_msg_cache(dev);
1801
1802         set_wqname(dev);
1803         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1804         if (!cmd->wq) {
1805                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1806                 err = -ENOMEM;
1807                 goto err_cache;
1808         }
1809
1810         err = create_debugfs_files(dev);
1811         if (err) {
1812                 err = -ENOMEM;
1813                 goto err_wq;
1814         }
1815
1816         return 0;
1817
1818 err_wq:
1819         destroy_workqueue(cmd->wq);
1820
1821 err_cache:
1822         destroy_msg_cache(dev);
1823
1824 err_free_page:
1825         free_cmd_page(dev, cmd);
1826
1827 err_free_pool:
1828         pci_pool_destroy(cmd->pool);
1829
1830         return err;
1831 }
1832 EXPORT_SYMBOL(mlx5_cmd_init);
1833
1834 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1835 {
1836         struct mlx5_cmd *cmd = &dev->cmd;
1837
1838         clean_debug_files(dev);
1839         destroy_workqueue(cmd->wq);
1840         destroy_msg_cache(dev);
1841         free_cmd_page(dev, cmd);
1842         pci_pool_destroy(cmd->pool);
1843 }
1844 EXPORT_SYMBOL(mlx5_cmd_cleanup);