drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/debugfs.h>
  44
  45 #include "mlx5_core.h"
  46
  47 enum {
  48         CMD_IF_REV = 5,
  49 };
  50
  51 enum {
  52         CMD_MODE_POLLING,
  53         CMD_MODE_EVENTS
  54 };
  55
  56 enum {
  57         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  58         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  59         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  60         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  61         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  62         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  63         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  64         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  65         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  66         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  67         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  68 };
  69
  70 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  71                                            struct mlx5_cmd_msg *in,
  72                                            struct mlx5_cmd_msg *out,
  73                                            void *uout, int uout_size,
  74                                            mlx5_cmd_cbk_t cbk,
  75                                            void *context, int page_queue)
  76 {
  77         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
  78         struct mlx5_cmd_work_ent *ent;
  79
  80         ent = kzalloc(sizeof(*ent), alloc_flags);
  81         if (!ent)
  82                 return ERR_PTR(-ENOMEM);
  83
  84         ent->in         = in;
  85         ent->out        = out;
  86         ent->uout       = uout;
  87         ent->uout_size  = uout_size;
  88         ent->callback   = cbk;
  89         ent->context    = context;
  90         ent->cmd        = cmd;
  91         ent->page_queue = page_queue;
  92
  93         return ent;
  94 }
  95
  96 static u8 alloc_token(struct mlx5_cmd *cmd)
  97 {
  98         u8 token;
  99
 100         spin_lock(&cmd->token_lock);
 101         cmd->token++;
 102         if (cmd->token == 0)
 103                 cmd->token++;
 104         token = cmd->token;
 105         spin_unlock(&cmd->token_lock);
 106
 107         return token;
 108 }
 109
 110 static int alloc_ent(struct mlx5_cmd *cmd)
 111 {
 112         unsigned long flags;
 113         int ret;
 114
 115         spin_lock_irqsave(&cmd->alloc_lock, flags);
 116         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 117         if (ret < cmd->max_reg_cmds)
 118                 clear_bit(ret, &cmd->bitmask);
 119         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 120
 121         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 122 }
 123
 124 static void free_ent(struct mlx5_cmd *cmd, int idx)
 125 {
 126         unsigned long flags;
 127
 128         spin_lock_irqsave(&cmd->alloc_lock, flags);
 129         set_bit(idx, &cmd->bitmask);
 130         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 131 }
 132
 133 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 134 {
 135         return cmd->cmd_buf + (idx << cmd->log_stride);
 136 }
 137
 138 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
 139 {
 140         int size = msg->len;
 141         int blen = size - min_t(int, sizeof(msg->first.data), size);
 142
 143         return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
 144 }
 145
 146 static u8 xor8_buf(void *buf, size_t offset, int len)
 147 {
 148         u8 *ptr = buf;
 149         u8 sum = 0;
 150         int i;
 151         int end = len + offset;
 152
 153         for (i = offset; i < end; i++)
 154                 sum ^= ptr[i];
 155
 156         return sum;
 157 }
 158
 159 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 160 {
 161         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 162         int xor_len = sizeof(*block) - sizeof(block->data) - 1;
 163
 164         if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
 165                 return -EINVAL;
 166
 167         if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
 168                 return -EINVAL;
 169
 170         return 0;
 171 }
 172
 173 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
 174 {
 175         int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
 176         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 177
 178         block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
 179         block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
 180 }
 181
 182 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
 183 {
 184         struct mlx5_cmd_mailbox *next = msg->next;
 185         int n = mlx5_calc_cmd_blocks(msg);
 186         int i = 0;
 187
 188         for (i = 0; i < n && next; i++)  {
 189                 calc_block_sig(next->buf);
 190                 next = next->next;
 191         }
 192 }
 193
 194 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 195 {
 196         ent->lay->sig = ~xor8_buf(ent->lay, 0,  sizeof(*ent->lay));
 197         if (csum) {
 198                 calc_chain_sig(ent->in);
 199                 calc_chain_sig(ent->out);
 200         }
 201 }
 202
 203 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 204 {
 205         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 206         u8 own;
 207
 208         do {
 209                 own = ent->lay->status_own;
 210                 if (!(own & CMD_OWNER_HW)) {
 211                         ent->ret = 0;
 212                         return;
 213                 }
 214                 usleep_range(5000, 10000);
 215         } while (time_before(jiffies, poll_end));
 216
 217         ent->ret = -ETIMEDOUT;
 218 }
 219
 220 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 221 {
 222         kfree(ent);
 223 }
 224
 225 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 226 {
 227         struct mlx5_cmd_mailbox *next = ent->out->next;
 228         int n = mlx5_calc_cmd_blocks(ent->out);
 229         int err;
 230         u8 sig;
 231         int i = 0;
 232
 233         sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
 234         if (sig != 0xff)
 235                 return -EINVAL;
 236
 237         for (i = 0; i < n && next; i++) {
 238                 err = verify_block_sig(next->buf);
 239                 if (err)
 240                         return err;
 241
 242                 next = next->next;
 243         }
 244
 245         return 0;
 246 }
 247
 248 static void dump_buf(void *buf, int size, int data_only, int offset)
 249 {
 250         __be32 *p = buf;
 251         int i;
 252
 253         for (i = 0; i < size; i += 16) {
 254                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 255                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 256                          be32_to_cpu(p[3]));
 257                 p += 4;
 258                 offset += 16;
 259         }
 260         if (!data_only)
 261                 pr_debug("\n");
 262 }
 263
 264 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
 265                                        u32 *synd, u8 *status)
 266 {
 267         *synd = 0;
 268         *status = 0;
 269
 270         switch (op) {
 271         case MLX5_CMD_OP_TEARDOWN_HCA:
 272         case MLX5_CMD_OP_DISABLE_HCA:
 273         case MLX5_CMD_OP_MANAGE_PAGES:
 274         case MLX5_CMD_OP_DESTROY_MKEY:
 275         case MLX5_CMD_OP_DESTROY_EQ:
 276         case MLX5_CMD_OP_DESTROY_CQ:
 277         case MLX5_CMD_OP_DESTROY_QP:
 278         case MLX5_CMD_OP_DESTROY_PSV:
 279         case MLX5_CMD_OP_DESTROY_SRQ:
 280         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 281         case MLX5_CMD_OP_DESTROY_DCT:
 282         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 283         case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
 284         case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
 285         case MLX5_CMD_OP_DEALLOC_PD:
 286         case MLX5_CMD_OP_DEALLOC_UAR:
 287         case MLX5_CMD_OP_DETACH_FROM_MCG:
 288         case MLX5_CMD_OP_DEALLOC_XRCD:
 289         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 290         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 291         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 292         case MLX5_CMD_OP_DESTROY_LAG:
 293         case MLX5_CMD_OP_DESTROY_VPORT_LAG:
 294         case MLX5_CMD_OP_DESTROY_TIR:
 295         case MLX5_CMD_OP_DESTROY_SQ:
 296         case MLX5_CMD_OP_DESTROY_RQ:
 297         case MLX5_CMD_OP_DESTROY_RMP:
 298         case MLX5_CMD_OP_DESTROY_TIS:
 299         case MLX5_CMD_OP_DESTROY_RQT:
 300         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 301         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 302         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 303         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
 304         case MLX5_CMD_OP_2ERR_QP:
 305         case MLX5_CMD_OP_2RST_QP:
 306         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 307         case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
 308         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 309         case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
 310         case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
 311         case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
 312         case MLX5_CMD_OP_FPGA_DESTROY_QP:
 313                 return MLX5_CMD_STAT_OK;
 314
 315         case MLX5_CMD_OP_QUERY_HCA_CAP:
 316         case MLX5_CMD_OP_QUERY_ADAPTER:
 317         case MLX5_CMD_OP_INIT_HCA:
 318         case MLX5_CMD_OP_ENABLE_HCA:
 319         case MLX5_CMD_OP_QUERY_PAGES:
 320         case MLX5_CMD_OP_SET_HCA_CAP:
 321         case MLX5_CMD_OP_QUERY_ISSI:
 322         case MLX5_CMD_OP_SET_ISSI:
 323         case MLX5_CMD_OP_CREATE_MKEY:
 324         case MLX5_CMD_OP_QUERY_MKEY:
 325         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 326         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 327         case MLX5_CMD_OP_CREATE_EQ:
 328         case MLX5_CMD_OP_QUERY_EQ:
 329         case MLX5_CMD_OP_GEN_EQE:
 330         case MLX5_CMD_OP_CREATE_CQ:
 331         case MLX5_CMD_OP_QUERY_CQ:
 332         case MLX5_CMD_OP_MODIFY_CQ:
 333         case MLX5_CMD_OP_CREATE_QP:
 334         case MLX5_CMD_OP_RST2INIT_QP:
 335         case MLX5_CMD_OP_INIT2RTR_QP:
 336         case MLX5_CMD_OP_RTR2RTS_QP:
 337         case MLX5_CMD_OP_RTS2RTS_QP:
 338         case MLX5_CMD_OP_SQERR2RTS_QP:
 339         case MLX5_CMD_OP_QUERY_QP:
 340         case MLX5_CMD_OP_SQD_RTS_QP:
 341         case MLX5_CMD_OP_INIT2INIT_QP:
 342         case MLX5_CMD_OP_CREATE_PSV:
 343         case MLX5_CMD_OP_CREATE_SRQ:
 344         case MLX5_CMD_OP_QUERY_SRQ:
 345         case MLX5_CMD_OP_ARM_RQ:
 346         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 347         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 348         case MLX5_CMD_OP_ARM_XRC_SRQ:
 349         case MLX5_CMD_OP_CREATE_DCT:
 350         case MLX5_CMD_OP_DRAIN_DCT:
 351         case MLX5_CMD_OP_QUERY_DCT:
 352         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 353         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 354         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 355         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 356         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 357         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 358         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 359         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 360         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 361         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 362         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 363         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 364         case MLX5_CMD_OP_QUERY_VNIC_ENV:
 365         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 366         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 367         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 368         case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
 369         case MLX5_CMD_OP_QUERY_RATE_LIMIT:
 370         case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
 371         case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
 372         case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
 373         case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
 374         case MLX5_CMD_OP_ALLOC_PD:
 375         case MLX5_CMD_OP_ALLOC_UAR:
 376         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 377         case MLX5_CMD_OP_ACCESS_REG:
 378         case MLX5_CMD_OP_ATTACH_TO_MCG:
 379         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 380         case MLX5_CMD_OP_MAD_IFC:
 381         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 382         case MLX5_CMD_OP_SET_MAD_DEMUX:
 383         case MLX5_CMD_OP_NOP:
 384         case MLX5_CMD_OP_ALLOC_XRCD:
 385         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 386         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 387         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 388         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 389         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 390         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 391         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 392         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 393         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 394         case MLX5_CMD_OP_CREATE_LAG:
 395         case MLX5_CMD_OP_MODIFY_LAG:
 396         case MLX5_CMD_OP_QUERY_LAG:
 397         case MLX5_CMD_OP_CREATE_VPORT_LAG:
 398         case MLX5_CMD_OP_CREATE_TIR:
 399         case MLX5_CMD_OP_MODIFY_TIR:
 400         case MLX5_CMD_OP_QUERY_TIR:
 401         case MLX5_CMD_OP_CREATE_SQ:
 402         case MLX5_CMD_OP_MODIFY_SQ:
 403         case MLX5_CMD_OP_QUERY_SQ:
 404         case MLX5_CMD_OP_CREATE_RQ:
 405         case MLX5_CMD_OP_MODIFY_RQ:
 406         case MLX5_CMD_OP_QUERY_RQ:
 407         case MLX5_CMD_OP_CREATE_RMP:
 408         case MLX5_CMD_OP_MODIFY_RMP:
 409         case MLX5_CMD_OP_QUERY_RMP:
 410         case MLX5_CMD_OP_CREATE_TIS:
 411         case MLX5_CMD_OP_MODIFY_TIS:
 412         case MLX5_CMD_OP_QUERY_TIS:
 413         case MLX5_CMD_OP_CREATE_RQT:
 414         case MLX5_CMD_OP_MODIFY_RQT:
 415         case MLX5_CMD_OP_QUERY_RQT:
 416
 417         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 418         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 419         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 420         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 421         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 422         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
 423         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
 424         case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
 425         case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
 426         case MLX5_CMD_OP_FPGA_CREATE_QP:
 427         case MLX5_CMD_OP_FPGA_MODIFY_QP:
 428         case MLX5_CMD_OP_FPGA_QUERY_QP:
 429         case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
 430                 *status = MLX5_DRIVER_STATUS_ABORTED;
 431                 *synd = MLX5_DRIVER_SYND;
 432                 return -EIO;
 433         default:
 434                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
 435                 return -EINVAL;
 436         }
 437 }
 438
 439 const char *mlx5_command_str(int command)
 440 {
 441 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
 442
 443         switch (command) {
 444         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
 445         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
 446         MLX5_COMMAND_STR_CASE(INIT_HCA);
 447         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
 448         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
 449         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
 450         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
 451         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
 452         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
 453         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
 454         MLX5_COMMAND_STR_CASE(SET_ISSI);
 455         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
 456         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
 457         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
 458         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
 459         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
 460         MLX5_COMMAND_STR_CASE(CREATE_EQ);
 461         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
 462         MLX5_COMMAND_STR_CASE(QUERY_EQ);
 463         MLX5_COMMAND_STR_CASE(GEN_EQE);
 464         MLX5_COMMAND_STR_CASE(CREATE_CQ);
 465         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
 466         MLX5_COMMAND_STR_CASE(QUERY_CQ);
 467         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
 468         MLX5_COMMAND_STR_CASE(CREATE_QP);
 469         MLX5_COMMAND_STR_CASE(DESTROY_QP);
 470         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
 471         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
 472         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
 473         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
 474         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
 475         MLX5_COMMAND_STR_CASE(2ERR_QP);
 476         MLX5_COMMAND_STR_CASE(2RST_QP);
 477         MLX5_COMMAND_STR_CASE(QUERY_QP);
 478         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
 479         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
 480         MLX5_COMMAND_STR_CASE(CREATE_PSV);
 481         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
 482         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
 483         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
 484         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
 485         MLX5_COMMAND_STR_CASE(ARM_RQ);
 486         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
 487         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
 488         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
 489         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
 490         MLX5_COMMAND_STR_CASE(CREATE_DCT);
 491         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
 492         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
 493         MLX5_COMMAND_STR_CASE(QUERY_DCT);
 494         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
 495         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
 496         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
 497         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
 498         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
 499         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
 500         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
 501         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
 502         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
 503         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
 504         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
 505         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
 506         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
 507         MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
 508         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
 509         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
 510         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
 511         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
 512         MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
 513         MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
 514         MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
 515         MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
 516         MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
 517         MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
 518         MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
 519         MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
 520         MLX5_COMMAND_STR_CASE(ALLOC_PD);
 521         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
 522         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
 523         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
 524         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
 525         MLX5_COMMAND_STR_CASE(ACCESS_REG);
 526         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
 527         MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
 528         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
 529         MLX5_COMMAND_STR_CASE(MAD_IFC);
 530         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
 531         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
 532         MLX5_COMMAND_STR_CASE(NOP);
 533         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
 534         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
 535         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
 536         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
 537         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
 538         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
 539         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
 540         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
 541         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
 542         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
 543         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
 544         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
 545         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
 546         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
 547         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
 548         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
 549         MLX5_COMMAND_STR_CASE(CREATE_LAG);
 550         MLX5_COMMAND_STR_CASE(MODIFY_LAG);
 551         MLX5_COMMAND_STR_CASE(QUERY_LAG);
 552         MLX5_COMMAND_STR_CASE(DESTROY_LAG);
 553         MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
 554         MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
 555         MLX5_COMMAND_STR_CASE(CREATE_TIR);
 556         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
 557         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
 558         MLX5_COMMAND_STR_CASE(QUERY_TIR);
 559         MLX5_COMMAND_STR_CASE(CREATE_SQ);
 560         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
 561         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
 562         MLX5_COMMAND_STR_CASE(QUERY_SQ);
 563         MLX5_COMMAND_STR_CASE(CREATE_RQ);
 564         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
 565         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
 566         MLX5_COMMAND_STR_CASE(QUERY_RQ);
 567         MLX5_COMMAND_STR_CASE(CREATE_RMP);
 568         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
 569         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
 570         MLX5_COMMAND_STR_CASE(QUERY_RMP);
 571         MLX5_COMMAND_STR_CASE(CREATE_TIS);
 572         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
 573         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
 574         MLX5_COMMAND_STR_CASE(QUERY_TIS);
 575         MLX5_COMMAND_STR_CASE(CREATE_RQT);
 576         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
 577         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
 578         MLX5_COMMAND_STR_CASE(QUERY_RQT);
 579         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
 580         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
 581         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
 582         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
 583         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
 584         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
 585         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
 586         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
 587         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
 588         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
 589         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
 590         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
 591         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
 592         MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
 593         MLX5_COMMAND_STR_CASE(ALLOC_ENCAP_HEADER);
 594         MLX5_COMMAND_STR_CASE(DEALLOC_ENCAP_HEADER);
 595         MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
 596         MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
 597         MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
 598         MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
 599         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
 600         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
 601         MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
 602         default: return "unknown command opcode";
 603         }
 604 }
 605
 606 static const char *cmd_status_str(u8 status)
 607 {
 608         switch (status) {
 609         case MLX5_CMD_STAT_OK:
 610                 return "OK";
 611         case MLX5_CMD_STAT_INT_ERR:
 612                 return "internal error";
 613         case MLX5_CMD_STAT_BAD_OP_ERR:
 614                 return "bad operation";
 615         case MLX5_CMD_STAT_BAD_PARAM_ERR:
 616                 return "bad parameter";
 617         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
 618                 return "bad system state";
 619         case MLX5_CMD_STAT_BAD_RES_ERR:
 620                 return "bad resource";
 621         case MLX5_CMD_STAT_RES_BUSY:
 622                 return "resource busy";
 623         case MLX5_CMD_STAT_LIM_ERR:
 624                 return "limits exceeded";
 625         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
 626                 return "bad resource state";
 627         case MLX5_CMD_STAT_IX_ERR:
 628                 return "bad index";
 629         case MLX5_CMD_STAT_NO_RES_ERR:
 630                 return "no resources";
 631         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
 632                 return "bad input length";
 633         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
 634                 return "bad output length";
 635         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
 636                 return "bad QP state";
 637         case MLX5_CMD_STAT_BAD_PKT_ERR:
 638                 return "bad packet (discarded)";
 639         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
 640                 return "bad size too many outstanding CQEs";
 641         default:
 642                 return "unknown status";
 643         }
 644 }
 645
 646 static int cmd_status_to_err(u8 status)
 647 {
 648         switch (status) {
 649         case MLX5_CMD_STAT_OK:                          return 0;
 650         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
 651         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
 652         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
 653         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
 654         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
 655         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
 656         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
 657         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
 658         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
 659         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
 660         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
 661         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
 662         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
 663         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
 664         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
 665         default:                                        return -EIO;
 666         }
 667 }
 668
 669 struct mlx5_ifc_mbox_out_bits {
 670         u8         status[0x8];
 671         u8         reserved_at_8[0x18];
 672
 673         u8         syndrome[0x20];
 674
 675         u8         reserved_at_40[0x40];
 676 };
 677
 678 struct mlx5_ifc_mbox_in_bits {
 679         u8         opcode[0x10];
 680         u8         reserved_at_10[0x10];
 681
 682         u8         reserved_at_20[0x10];
 683         u8         op_mod[0x10];
 684
 685         u8         reserved_at_40[0x40];
 686 };
 687
 688 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
 689 {
 690         *status = MLX5_GET(mbox_out, out, status);
 691         *syndrome = MLX5_GET(mbox_out, out, syndrome);
 692 }
 693
 694 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
 695 {
 696         u32 syndrome;
 697         u8  status;
 698         u16 opcode;
 699         u16 op_mod;
 700
 701         mlx5_cmd_mbox_status(out, &status, &syndrome);
 702         if (!status)
 703                 return 0;
 704
 705         opcode = MLX5_GET(mbox_in, in, opcode);
 706         op_mod = MLX5_GET(mbox_in, in, op_mod);
 707
 708         mlx5_core_err(dev,
 709                       "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
 710                       mlx5_command_str(opcode),
 711                       opcode, op_mod,
 712                       cmd_status_str(status),
 713                       status,
 714                       syndrome);
 715
 716         return cmd_status_to_err(status);
 717 }
 718
 719 static void dump_command(struct mlx5_core_dev *dev,
 720                          struct mlx5_cmd_work_ent *ent, int input)
 721 {
 722         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 723         u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
 724         struct mlx5_cmd_mailbox *next = msg->next;
 725         int n = mlx5_calc_cmd_blocks(msg);
 726         int data_only;
 727         u32 offset = 0;
 728         int dump_len;
 729         int i;
 730
 731         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 732
 733         if (data_only)
 734                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 735                                    "dump command data %s(0x%x) %s\n",
 736                                    mlx5_command_str(op), op,
 737                                    input ? "INPUT" : "OUTPUT");
 738         else
 739                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 740                               mlx5_command_str(op), op,
 741                               input ? "INPUT" : "OUTPUT");
 742
 743         if (data_only) {
 744                 if (input) {
 745                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 746                         offset += sizeof(ent->lay->in);
 747                 } else {
 748                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 749                         offset += sizeof(ent->lay->out);
 750                 }
 751         } else {
 752                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 753                 offset += sizeof(*ent->lay);
 754         }
 755
 756         for (i = 0; i < n && next; i++)  {
 757                 if (data_only) {
 758                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 759                         dump_buf(next->buf, dump_len, 1, offset);
 760                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 761                 } else {
 762                         mlx5_core_dbg(dev, "command block:\n");
 763                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 764                         offset += sizeof(struct mlx5_cmd_prot_block);
 765                 }
 766                 next = next->next;
 767         }
 768
 769         if (data_only)
 770                 pr_debug("\n");
 771 }
 772
 773 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 774 {
 775         return MLX5_GET(mbox_in, in->first.data, opcode);
 776 }
 777
 778 static void cb_timeout_handler(struct work_struct *work)
 779 {
 780         struct delayed_work *dwork = container_of(work, struct delayed_work,
 781                                                   work);
 782         struct mlx5_cmd_work_ent *ent = container_of(dwork,
 783                                                      struct mlx5_cmd_work_ent,
 784                                                      cb_timeout_work);
 785         struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
 786                                                  cmd);
 787
 788         ent->ret = -ETIMEDOUT;
 789         mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 790                        mlx5_command_str(msg_to_opcode(ent->in)),
 791                        msg_to_opcode(ent->in));
 792         mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 793 }
 794
 795 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
 796 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
 797                               struct mlx5_cmd_msg *msg);
 798
 799 static void cmd_work_handler(struct work_struct *work)
 800 {
 801         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 802         struct mlx5_cmd *cmd = ent->cmd;
 803         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 804         unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 805         struct mlx5_cmd_layout *lay;
 806         struct semaphore *sem;
 807         unsigned long flags;
 808         bool poll_cmd = ent->polling;
 809         int alloc_ret;
 810
 811         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 812         down(sem);
 813         if (!ent->page_queue) {
 814                 alloc_ret = alloc_ent(cmd);
 815                 if (alloc_ret < 0) {
 816                         mlx5_core_err(dev, "failed to allocate command entry\n");
 817                         if (ent->callback) {
 818                                 ent->callback(-EAGAIN, ent->context);
 819                                 mlx5_free_cmd_msg(dev, ent->out);
 820                                 free_msg(dev, ent->in);
 821                                 free_cmd(ent);
 822                         } else {
 823                                 ent->ret = -EAGAIN;
 824                                 complete(&ent->done);
 825                         }
 826                         up(sem);
 827                         return;
 828                 }
 829                 ent->idx = alloc_ret;
 830         } else {
 831                 ent->idx = cmd->max_reg_cmds;
 832                 spin_lock_irqsave(&cmd->alloc_lock, flags);
 833                 clear_bit(ent->idx, &cmd->bitmask);
 834                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 835         }
 836
 837         cmd->ent_arr[ent->idx] = ent;
 838         set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
 839         lay = get_inst(cmd, ent->idx);
 840         ent->lay = lay;
 841         memset(lay, 0, sizeof(*lay));
 842         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 843         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 844         if (ent->in->next)
 845                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 846         lay->inlen = cpu_to_be32(ent->in->len);
 847         if (ent->out->next)
 848                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 849         lay->outlen = cpu_to_be32(ent->out->len);
 850         lay->type = MLX5_PCI_CMD_XPORT;
 851         lay->token = ent->token;
 852         lay->status_own = CMD_OWNER_HW;
 853         set_signature(ent, !cmd->checksum_disabled);
 854         dump_command(dev, ent, 1);
 855         ent->ts1 = ktime_get_ns();
 856
 857         if (ent->callback)
 858                 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
 859
 860         /* Skip sending command to fw if internal error */
 861         if (pci_channel_offline(dev->pdev) ||
 862             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
 863                 u8 status = 0;
 864                 u32 drv_synd;
 865
 866                 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
 867                 MLX5_SET(mbox_out, ent->out, status, status);
 868                 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
 869
 870                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 871                 return;
 872         }
 873
 874         /* ring doorbell after the descriptor is valid */
 875         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
 876         wmb();
 877         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 878         mmiowb();
 879         /* if not in polling don't use ent after this point */
 880         if (cmd->mode == CMD_MODE_POLLING || poll_cmd) {
 881                 poll_timeout(ent);
 882                 /* make sure we read the descriptor after ownership is SW */
 883                 rmb();
 884                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
 885         }
 886 }
 887
 888 static const char *deliv_status_to_str(u8 status)
 889 {
 890         switch (status) {
 891         case MLX5_CMD_DELIVERY_STAT_OK:
 892                 return "no errors";
 893         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 894                 return "signature error";
 895         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 896                 return "token error";
 897         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 898                 return "bad block number";
 899         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 900                 return "output pointer not aligned to block size";
 901         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 902                 return "input pointer not aligned to block size";
 903         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 904                 return "firmware internal error";
 905         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 906                 return "command input length error";
 907         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 908                 return "command output length error";
 909         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 910                 return "reserved fields not cleared";
 911         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 912                 return "bad command descriptor type";
 913         default:
 914                 return "unknown status code";
 915         }
 916 }
 917
 918 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 919 {
 920         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 921         struct mlx5_cmd *cmd = &dev->cmd;
 922         int err;
 923
 924         if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
 925                 wait_for_completion(&ent->done);
 926         } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
 927                 ent->ret = -ETIMEDOUT;
 928                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 929         }
 930
 931         err = ent->ret;
 932
 933         if (err == -ETIMEDOUT) {
 934                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 935                                mlx5_command_str(msg_to_opcode(ent->in)),
 936                                msg_to_opcode(ent->in));
 937         }
 938         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
 939                       err, deliv_status_to_str(ent->status), ent->status);
 940
 941         return err;
 942 }
 943
 944 /*  Notes:
 945  *    1. Callback functions may not sleep
 946  *    2. page queue commands do not support asynchrous completion
 947  */
 948 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 949                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
 950                            mlx5_cmd_cbk_t callback,
 951                            void *context, int page_queue, u8 *status,
 952                            u8 token, bool force_polling)
 953 {
 954         struct mlx5_cmd *cmd = &dev->cmd;
 955         struct mlx5_cmd_work_ent *ent;
 956         struct mlx5_cmd_stats *stats;
 957         int err = 0;
 958         s64 ds;
 959         u16 op;
 960
 961         if (callback && page_queue)
 962                 return -EINVAL;
 963
 964         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
 965                         page_queue);
 966         if (IS_ERR(ent))
 967                 return PTR_ERR(ent);
 968
 969         ent->token = token;
 970         ent->polling = force_polling;
 971
 972         if (!callback)
 973                 init_completion(&ent->done);
 974
 975         INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
 976         INIT_WORK(&ent->work, cmd_work_handler);
 977         if (page_queue) {
 978                 cmd_work_handler(&ent->work);
 979         } else if (!queue_work(cmd->wq, &ent->work)) {
 980                 mlx5_core_warn(dev, "failed to queue work\n");
 981                 err = -ENOMEM;
 982                 goto out_free;
 983         }
 984
 985         if (callback)
 986                 goto out;
 987
 988         err = wait_func(dev, ent);
 989         if (err == -ETIMEDOUT)
 990                 goto out;
 991
 992         ds = ent->ts2 - ent->ts1;
 993         op = MLX5_GET(mbox_in, in->first.data, opcode);
 994         if (op < ARRAY_SIZE(cmd->stats)) {
 995                 stats = &cmd->stats[op];
 996                 spin_lock_irq(&stats->lock);
 997                 stats->sum += ds;
 998                 ++stats->n;
 999                 spin_unlock_irq(&stats->lock);
1000         }
1001         mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1002                            "fw exec time for %s is %lld nsec\n",
1003                            mlx5_command_str(op), ds);
1004         *status = ent->status;
1005
1006 out_free:
1007         free_cmd(ent);
1008 out:
1009         return err;
1010 }
1011
1012 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1013                          size_t count, loff_t *pos)
1014 {
1015         struct mlx5_core_dev *dev = filp->private_data;
1016         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1017         char lbuf[3];
1018         int err;
1019
1020         if (!dbg->in_msg || !dbg->out_msg)
1021                 return -ENOMEM;
1022
1023         if (copy_from_user(lbuf, buf, sizeof(lbuf)))
1024                 return -EFAULT;
1025
1026         lbuf[sizeof(lbuf) - 1] = 0;
1027
1028         if (strcmp(lbuf, "go"))
1029                 return -EINVAL;
1030
1031         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1032
1033         return err ? err : count;
1034 }
1035
1036 static const struct file_operations fops = {
1037         .owner  = THIS_MODULE,
1038         .open   = simple_open,
1039         .write  = dbg_write,
1040 };
1041
1042 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1043                             u8 token)
1044 {
1045         struct mlx5_cmd_prot_block *block;
1046         struct mlx5_cmd_mailbox *next;
1047         int copy;
1048
1049         if (!to || !from)
1050                 return -ENOMEM;
1051
1052         copy = min_t(int, size, sizeof(to->first.data));
1053         memcpy(to->first.data, from, copy);
1054         size -= copy;
1055         from += copy;
1056
1057         next = to->next;
1058         while (size) {
1059                 if (!next) {
1060                         /* this is a BUG */
1061                         return -ENOMEM;
1062                 }
1063
1064                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1065                 block = next->buf;
1066                 memcpy(block->data, from, copy);
1067                 from += copy;
1068                 size -= copy;
1069                 block->token = token;
1070                 next = next->next;
1071         }
1072
1073         return 0;
1074 }
1075
1076 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1077 {
1078         struct mlx5_cmd_prot_block *block;
1079         struct mlx5_cmd_mailbox *next;
1080         int copy;
1081
1082         if (!to || !from)
1083                 return -ENOMEM;
1084
1085         copy = min_t(int, size, sizeof(from->first.data));
1086         memcpy(to, from->first.data, copy);
1087         size -= copy;
1088         to += copy;
1089
1090         next = from->next;
1091         while (size) {
1092                 if (!next) {
1093                         /* this is a BUG */
1094                         return -ENOMEM;
1095                 }
1096
1097                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1098                 block = next->buf;
1099
1100                 memcpy(to, block->data, copy);
1101                 to += copy;
1102                 size -= copy;
1103                 next = next->next;
1104         }
1105
1106         return 0;
1107 }
1108
1109 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1110                                               gfp_t flags)
1111 {
1112         struct mlx5_cmd_mailbox *mailbox;
1113
1114         mailbox = kmalloc(sizeof(*mailbox), flags);
1115         if (!mailbox)
1116                 return ERR_PTR(-ENOMEM);
1117
1118         mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1119                                        &mailbox->dma);
1120         if (!mailbox->buf) {
1121                 mlx5_core_dbg(dev, "failed allocation\n");
1122                 kfree(mailbox);
1123                 return ERR_PTR(-ENOMEM);
1124         }
1125         mailbox->next = NULL;
1126
1127         return mailbox;
1128 }
1129
1130 static void free_cmd_box(struct mlx5_core_dev *dev,
1131                          struct mlx5_cmd_mailbox *mailbox)
1132 {
1133         dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1134         kfree(mailbox);
1135 }
1136
1137 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1138                                                gfp_t flags, int size,
1139                                                u8 token)
1140 {
1141         struct mlx5_cmd_mailbox *tmp, *head = NULL;
1142         struct mlx5_cmd_prot_block *block;
1143         struct mlx5_cmd_msg *msg;
1144         int err;
1145         int n;
1146         int i;
1147
1148         msg = kzalloc(sizeof(*msg), flags);
1149         if (!msg)
1150                 return ERR_PTR(-ENOMEM);
1151
1152         msg->len = size;
1153         n = mlx5_calc_cmd_blocks(msg);
1154
1155         for (i = 0; i < n; i++) {
1156                 tmp = alloc_cmd_box(dev, flags);
1157                 if (IS_ERR(tmp)) {
1158                         mlx5_core_warn(dev, "failed allocating block\n");
1159                         err = PTR_ERR(tmp);
1160                         goto err_alloc;
1161                 }
1162
1163                 block = tmp->buf;
1164                 tmp->next = head;
1165                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1166                 block->block_num = cpu_to_be32(n - i - 1);
1167                 block->token = token;
1168                 head = tmp;
1169         }
1170         msg->next = head;
1171         return msg;
1172
1173 err_alloc:
1174         while (head) {
1175                 tmp = head->next;
1176                 free_cmd_box(dev, head);
1177                 head = tmp;
1178         }
1179         kfree(msg);
1180
1181         return ERR_PTR(err);
1182 }
1183
1184 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1185                               struct mlx5_cmd_msg *msg)
1186 {
1187         struct mlx5_cmd_mailbox *head = msg->next;
1188         struct mlx5_cmd_mailbox *next;
1189
1190         while (head) {
1191                 next = head->next;
1192                 free_cmd_box(dev, head);
1193                 head = next;
1194         }
1195         kfree(msg);
1196 }
1197
1198 static ssize_t data_write(struct file *filp, const char __user *buf,
1199                           size_t count, loff_t *pos)
1200 {
1201         struct mlx5_core_dev *dev = filp->private_data;
1202         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1203         void *ptr;
1204
1205         if (*pos != 0)
1206                 return -EINVAL;
1207
1208         kfree(dbg->in_msg);
1209         dbg->in_msg = NULL;
1210         dbg->inlen = 0;
1211         ptr = memdup_user(buf, count);
1212         if (IS_ERR(ptr))
1213                 return PTR_ERR(ptr);
1214         dbg->in_msg = ptr;
1215         dbg->inlen = count;
1216
1217         *pos = count;
1218
1219         return count;
1220 }
1221
1222 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1223                          loff_t *pos)
1224 {
1225         struct mlx5_core_dev *dev = filp->private_data;
1226         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1227         int copy;
1228
1229         if (*pos)
1230                 return 0;
1231
1232         if (!dbg->out_msg)
1233                 return -ENOMEM;
1234
1235         copy = min_t(int, count, dbg->outlen);
1236         if (copy_to_user(buf, dbg->out_msg, copy))
1237                 return -EFAULT;
1238
1239         *pos += copy;
1240
1241         return copy;
1242 }
1243
1244 static const struct file_operations dfops = {
1245         .owner  = THIS_MODULE,
1246         .open   = simple_open,
1247         .write  = data_write,
1248         .read   = data_read,
1249 };
1250
1251 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1252                            loff_t *pos)
1253 {
1254         struct mlx5_core_dev *dev = filp->private_data;
1255         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1256         char outlen[8];
1257         int err;
1258
1259         if (*pos)
1260                 return 0;
1261
1262         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1263         if (err < 0)
1264                 return err;
1265
1266         if (copy_to_user(buf, &outlen, err))
1267                 return -EFAULT;
1268
1269         *pos += err;
1270
1271         return err;
1272 }
1273
1274 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1275                             size_t count, loff_t *pos)
1276 {
1277         struct mlx5_core_dev *dev = filp->private_data;
1278         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1279         char outlen_str[8];
1280         int outlen;
1281         void *ptr;
1282         int err;
1283
1284         if (*pos != 0 || count > 6)
1285                 return -EINVAL;
1286
1287         kfree(dbg->out_msg);
1288         dbg->out_msg = NULL;
1289         dbg->outlen = 0;
1290
1291         if (copy_from_user(outlen_str, buf, count))
1292                 return -EFAULT;
1293
1294         outlen_str[7] = 0;
1295
1296         err = sscanf(outlen_str, "%d", &outlen);
1297         if (err < 0)
1298                 return err;
1299
1300         ptr = kzalloc(outlen, GFP_KERNEL);
1301         if (!ptr)
1302                 return -ENOMEM;
1303
1304         dbg->out_msg = ptr;
1305         dbg->outlen = outlen;
1306
1307         *pos = count;
1308
1309         return count;
1310 }
1311
1312 static const struct file_operations olfops = {
1313         .owner  = THIS_MODULE,
1314         .open   = simple_open,
1315         .write  = outlen_write,
1316         .read   = outlen_read,
1317 };
1318
1319 static void set_wqname(struct mlx5_core_dev *dev)
1320 {
1321         struct mlx5_cmd *cmd = &dev->cmd;
1322
1323         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1324                  dev_name(&dev->pdev->dev));
1325 }
1326
1327 static void clean_debug_files(struct mlx5_core_dev *dev)
1328 {
1329         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1330
1331         if (!mlx5_debugfs_root)
1332                 return;
1333
1334         mlx5_cmdif_debugfs_cleanup(dev);
1335         debugfs_remove_recursive(dbg->dbg_root);
1336 }
1337
1338 static int create_debugfs_files(struct mlx5_core_dev *dev)
1339 {
1340         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1341         int err = -ENOMEM;
1342
1343         if (!mlx5_debugfs_root)
1344                 return 0;
1345
1346         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1347         if (!dbg->dbg_root)
1348                 return err;
1349
1350         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1351                                           dev, &dfops);
1352         if (!dbg->dbg_in)
1353                 goto err_dbg;
1354
1355         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1356                                            dev, &dfops);
1357         if (!dbg->dbg_out)
1358                 goto err_dbg;
1359
1360         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1361                                               dev, &olfops);
1362         if (!dbg->dbg_outlen)
1363                 goto err_dbg;
1364
1365         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1366                                             &dbg->status);
1367         if (!dbg->dbg_status)
1368                 goto err_dbg;
1369
1370         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1371         if (!dbg->dbg_run)
1372                 goto err_dbg;
1373
1374         mlx5_cmdif_debugfs_init(dev);
1375
1376         return 0;
1377
1378 err_dbg:
1379         clean_debug_files(dev);
1380         return err;
1381 }
1382
1383 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1384 {
1385         struct mlx5_cmd *cmd = &dev->cmd;
1386         int i;
1387
1388         for (i = 0; i < cmd->max_reg_cmds; i++)
1389                 down(&cmd->sem);
1390         down(&cmd->pages_sem);
1391
1392         cmd->mode = mode;
1393
1394         up(&cmd->pages_sem);
1395         for (i = 0; i < cmd->max_reg_cmds; i++)
1396                 up(&cmd->sem);
1397 }
1398
1399 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1400 {
1401         mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1402 }
1403
1404 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1405 {
1406         mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1407 }
1408
1409 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1410 {
1411         unsigned long flags;
1412
1413         if (msg->parent) {
1414                 spin_lock_irqsave(&msg->parent->lock, flags);
1415                 list_add_tail(&msg->list, &msg->parent->head);
1416                 spin_unlock_irqrestore(&msg->parent->lock, flags);
1417         } else {
1418                 mlx5_free_cmd_msg(dev, msg);
1419         }
1420 }
1421
1422 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1423 {
1424         struct mlx5_cmd *cmd = &dev->cmd;
1425         struct mlx5_cmd_work_ent *ent;
1426         mlx5_cmd_cbk_t callback;
1427         void *context;
1428         int err;
1429         int i;
1430         s64 ds;
1431         struct mlx5_cmd_stats *stats;
1432         unsigned long flags;
1433         unsigned long vector;
1434
1435         /* there can be at most 32 command queues */
1436         vector = vec & 0xffffffff;
1437         for (i = 0; i < (1 << cmd->log_sz); i++) {
1438                 if (test_bit(i, &vector)) {
1439                         struct semaphore *sem;
1440
1441                         ent = cmd->ent_arr[i];
1442
1443                         /* if we already completed the command, ignore it */
1444                         if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1445                                                 &ent->state)) {
1446                                 /* only real completion can free the cmd slot */
1447                                 if (!forced) {
1448                                         mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1449                                                       ent->idx);
1450                                         free_ent(cmd, ent->idx);
1451                                         free_cmd(ent);
1452                                 }
1453                                 continue;
1454                         }
1455
1456                         if (ent->callback)
1457                                 cancel_delayed_work(&ent->cb_timeout_work);
1458                         if (ent->page_queue)
1459                                 sem = &cmd->pages_sem;
1460                         else
1461                                 sem = &cmd->sem;
1462                         ent->ts2 = ktime_get_ns();
1463                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1464                         dump_command(dev, ent, 0);
1465                         if (!ent->ret) {
1466                                 if (!cmd->checksum_disabled)
1467                                         ent->ret = verify_signature(ent);
1468                                 else
1469                                         ent->ret = 0;
1470                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1471                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1472                                 else
1473                                         ent->status = ent->lay->status_own >> 1;
1474
1475                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1476                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1477                         }
1478
1479                         /* only real completion will free the entry slot */
1480                         if (!forced)
1481                                 free_ent(cmd, ent->idx);
1482
1483                         if (ent->callback) {
1484                                 ds = ent->ts2 - ent->ts1;
1485                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1486                                         stats = &cmd->stats[ent->op];
1487                                         spin_lock_irqsave(&stats->lock, flags);
1488                                         stats->sum += ds;
1489                                         ++stats->n;
1490                                         spin_unlock_irqrestore(&stats->lock, flags);
1491                                 }
1492
1493                                 callback = ent->callback;
1494                                 context = ent->context;
1495                                 err = ent->ret;
1496                                 if (!err) {
1497                                         err = mlx5_copy_from_msg(ent->uout,
1498                                                                  ent->out,
1499                                                                  ent->uout_size);
1500
1501                                         err = err ? err : mlx5_cmd_check(dev,
1502                                                                         ent->in->first.data,
1503                                                                         ent->uout);
1504                                 }
1505
1506                                 mlx5_free_cmd_msg(dev, ent->out);
1507                                 free_msg(dev, ent->in);
1508
1509                                 err = err ? err : ent->status;
1510                                 if (!forced)
1511                                         free_cmd(ent);
1512                                 callback(err, context);
1513                         } else {
1514                                 complete(&ent->done);
1515                         }
1516                         up(sem);
1517                 }
1518         }
1519 }
1520 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1521
1522 static int status_to_err(u8 status)
1523 {
1524         return status ? -1 : 0; /* TBD more meaningful codes */
1525 }
1526
1527 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1528                                       gfp_t gfp)
1529 {
1530         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1531         struct cmd_msg_cache *ch = NULL;
1532         struct mlx5_cmd *cmd = &dev->cmd;
1533         int i;
1534
1535         if (in_size <= 16)
1536                 goto cache_miss;
1537
1538         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1539                 ch = &cmd->cache[i];
1540                 if (in_size > ch->max_inbox_size)
1541                         continue;
1542                 spin_lock_irq(&ch->lock);
1543                 if (list_empty(&ch->head)) {
1544                         spin_unlock_irq(&ch->lock);
1545                         continue;
1546                 }
1547                 msg = list_entry(ch->head.next, typeof(*msg), list);
1548                 /* For cached lists, we must explicitly state what is
1549                  * the real size
1550                  */
1551                 msg->len = in_size;
1552                 list_del(&msg->list);
1553                 spin_unlock_irq(&ch->lock);
1554                 break;
1555         }
1556
1557         if (!IS_ERR(msg))
1558                 return msg;
1559
1560 cache_miss:
1561         msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1562         return msg;
1563 }
1564
1565 static int is_manage_pages(void *in)
1566 {
1567         return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1568 }
1569
1570 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1571                     int out_size, mlx5_cmd_cbk_t callback, void *context,
1572                     bool force_polling)
1573 {
1574         struct mlx5_cmd_msg *inb;
1575         struct mlx5_cmd_msg *outb;
1576         int pages_queue;
1577         gfp_t gfp;
1578         int err;
1579         u8 status = 0;
1580         u32 drv_synd;
1581         u8 token;
1582
1583         if (pci_channel_offline(dev->pdev) ||
1584             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1585                 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1586
1587                 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1588                 MLX5_SET(mbox_out, out, status, status);
1589                 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1590                 return err;
1591         }
1592
1593         pages_queue = is_manage_pages(in);
1594         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1595
1596         inb = alloc_msg(dev, in_size, gfp);
1597         if (IS_ERR(inb)) {
1598                 err = PTR_ERR(inb);
1599                 return err;
1600         }
1601
1602         token = alloc_token(&dev->cmd);
1603
1604         err = mlx5_copy_to_msg(inb, in, in_size, token);
1605         if (err) {
1606                 mlx5_core_warn(dev, "err %d\n", err);
1607                 goto out_in;
1608         }
1609
1610         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1611         if (IS_ERR(outb)) {
1612                 err = PTR_ERR(outb);
1613                 goto out_in;
1614         }
1615
1616         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1617                               pages_queue, &status, token, force_polling);
1618         if (err)
1619                 goto out_out;
1620
1621         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1622         if (status) {
1623                 err = status_to_err(status);
1624                 goto out_out;
1625         }
1626
1627         if (!callback)
1628                 err = mlx5_copy_from_msg(out, outb, out_size);
1629
1630 out_out:
1631         if (!callback)
1632                 mlx5_free_cmd_msg(dev, outb);
1633
1634 out_in:
1635         if (!callback)
1636                 free_msg(dev, inb);
1637         return err;
1638 }
1639
1640 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1641                   int out_size)
1642 {
1643         int err;
1644
1645         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1646         return err ? : mlx5_cmd_check(dev, in, out);
1647 }
1648 EXPORT_SYMBOL(mlx5_cmd_exec);
1649
1650 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1651                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1652                      void *context)
1653 {
1654         return cmd_exec(dev, in, in_size, out, out_size, callback, context,
1655                         false);
1656 }
1657 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1658
1659 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1660                           void *out, int out_size)
1661 {
1662         int err;
1663
1664         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1665
1666         return err ? : mlx5_cmd_check(dev, in, out);
1667 }
1668 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1669
1670 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1671 {
1672         struct cmd_msg_cache *ch;
1673         struct mlx5_cmd_msg *msg;
1674         struct mlx5_cmd_msg *n;
1675         int i;
1676
1677         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1678                 ch = &dev->cmd.cache[i];
1679                 list_for_each_entry_safe(msg, n, &ch->head, list) {
1680                         list_del(&msg->list);
1681                         mlx5_free_cmd_msg(dev, msg);
1682                 }
1683         }
1684 }
1685
1686 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1687         512, 32, 16, 8, 2
1688 };
1689
1690 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1691         16 + MLX5_CMD_DATA_BLOCK_SIZE,
1692         16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1693         16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1694         16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1695         16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1696 };
1697
1698 static void create_msg_cache(struct mlx5_core_dev *dev)
1699 {
1700         struct mlx5_cmd *cmd = &dev->cmd;
1701         struct cmd_msg_cache *ch;
1702         struct mlx5_cmd_msg *msg;
1703         int i;
1704         int k;
1705
1706         /* Initialize and fill the caches with initial entries */
1707         for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1708                 ch = &cmd->cache[k];
1709                 spin_lock_init(&ch->lock);
1710                 INIT_LIST_HEAD(&ch->head);
1711                 ch->num_ent = cmd_cache_num_ent[k];
1712                 ch->max_inbox_size = cmd_cache_ent_size[k];
1713                 for (i = 0; i < ch->num_ent; i++) {
1714                         msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1715                                                  ch->max_inbox_size, 0);
1716                         if (IS_ERR(msg))
1717                                 break;
1718                         msg->parent = ch;
1719                         list_add_tail(&msg->list, &ch->head);
1720                 }
1721         }
1722 }
1723
1724 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1725 {
1726         struct device *ddev = &dev->pdev->dev;
1727
1728         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1729                                                  &cmd->alloc_dma, GFP_KERNEL);
1730         if (!cmd->cmd_alloc_buf)
1731                 return -ENOMEM;
1732
1733         /* make sure it is aligned to 4K */
1734         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1735                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1736                 cmd->dma = cmd->alloc_dma;
1737                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1738                 return 0;
1739         }
1740
1741         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1742                           cmd->alloc_dma);
1743         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1744                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1745                                                  &cmd->alloc_dma, GFP_KERNEL);
1746         if (!cmd->cmd_alloc_buf)
1747                 return -ENOMEM;
1748
1749         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1750         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1751         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1752         return 0;
1753 }
1754
1755 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1756 {
1757         struct device *ddev = &dev->pdev->dev;
1758
1759         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1760                           cmd->alloc_dma);
1761 }
1762
1763 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1764 {
1765         int size = sizeof(struct mlx5_cmd_prot_block);
1766         int align = roundup_pow_of_two(size);
1767         struct mlx5_cmd *cmd = &dev->cmd;
1768         u32 cmd_h, cmd_l;
1769         u16 cmd_if_rev;
1770         int err;
1771         int i;
1772
1773         memset(cmd, 0, sizeof(*cmd));
1774         cmd_if_rev = cmdif_rev(dev);
1775         if (cmd_if_rev != CMD_IF_REV) {
1776                 dev_err(&dev->pdev->dev,
1777                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1778                         CMD_IF_REV, cmd_if_rev);
1779                 return -EINVAL;
1780         }
1781
1782         cmd->pool = dma_pool_create("mlx5_cmd", &dev->pdev->dev, size, align,
1783                                     0);
1784         if (!cmd->pool)
1785                 return -ENOMEM;
1786
1787         err = alloc_cmd_page(dev, cmd);
1788         if (err)
1789                 goto err_free_pool;
1790
1791         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1792         cmd->log_sz = cmd_l >> 4 & 0xf;
1793         cmd->log_stride = cmd_l & 0xf;
1794         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1795                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1796                         1 << cmd->log_sz);
1797                 err = -EINVAL;
1798                 goto err_free_page;
1799         }
1800
1801         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1802                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1803                 err = -EINVAL;
1804                 goto err_free_page;
1805         }
1806
1807         cmd->checksum_disabled = 1;
1808         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1809         cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
1810
1811         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1812         if (cmd->cmdif_rev > CMD_IF_REV) {
1813                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1814                         CMD_IF_REV, cmd->cmdif_rev);
1815                 err = -EOPNOTSUPP;
1816                 goto err_free_page;
1817         }
1818
1819         spin_lock_init(&cmd->alloc_lock);
1820         spin_lock_init(&cmd->token_lock);
1821         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1822                 spin_lock_init(&cmd->stats[i].lock);
1823
1824         sema_init(&cmd->sem, cmd->max_reg_cmds);
1825         sema_init(&cmd->pages_sem, 1);
1826
1827         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1828         cmd_l = (u32)(cmd->dma);
1829         if (cmd_l & 0xfff) {
1830                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1831                 err = -ENOMEM;
1832                 goto err_free_page;
1833         }
1834
1835         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1836         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1837
1838         /* Make sure firmware sees the complete address before we proceed */
1839         wmb();
1840
1841         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1842
1843         cmd->mode = CMD_MODE_POLLING;
1844
1845         create_msg_cache(dev);
1846
1847         set_wqname(dev);
1848         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1849         if (!cmd->wq) {
1850                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1851                 err = -ENOMEM;
1852                 goto err_cache;
1853         }
1854
1855         err = create_debugfs_files(dev);
1856         if (err) {
1857                 err = -ENOMEM;
1858                 goto err_wq;
1859         }
1860
1861         return 0;
1862
1863 err_wq:
1864         destroy_workqueue(cmd->wq);
1865
1866 err_cache:
1867         destroy_msg_cache(dev);
1868
1869 err_free_page:
1870         free_cmd_page(dev, cmd);
1871
1872 err_free_pool:
1873         dma_pool_destroy(cmd->pool);
1874
1875         return err;
1876 }
1877 EXPORT_SYMBOL(mlx5_cmd_init);
1878
1879 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1880 {
1881         struct mlx5_cmd *cmd = &dev->cmd;
1882
1883         clean_debug_files(dev);
1884         destroy_workqueue(cmd->wq);
1885         destroy_msg_cache(dev);
1886         free_cmd_page(dev, cmd);
1887         dma_pool_destroy(cmd->pool);
1888 }
1889 EXPORT_SYMBOL(mlx5_cmd_cleanup);