Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox...
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / cmd.c
1 /*
2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/debugfs.h>
44
45 #include "mlx5_core.h"
46
47 enum {
48         CMD_IF_REV = 5,
49 };
50
51 enum {
52         CMD_MODE_POLLING,
53         CMD_MODE_EVENTS
54 };
55
56 enum {
57         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
58         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
59         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
60         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
61         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
62         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
63         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
64         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
65         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
66         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
67         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
68 };
69
70 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
71                                            struct mlx5_cmd_msg *in,
72                                            struct mlx5_cmd_msg *out,
73                                            void *uout, int uout_size,
74                                            mlx5_cmd_cbk_t cbk,
75                                            void *context, int page_queue)
76 {
77         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
78         struct mlx5_cmd_work_ent *ent;
79
80         ent = kzalloc(sizeof(*ent), alloc_flags);
81         if (!ent)
82                 return ERR_PTR(-ENOMEM);
83
84         ent->in         = in;
85         ent->out        = out;
86         ent->uout       = uout;
87         ent->uout_size  = uout_size;
88         ent->callback   = cbk;
89         ent->context    = context;
90         ent->cmd        = cmd;
91         ent->page_queue = page_queue;
92
93         return ent;
94 }
95
96 static u8 alloc_token(struct mlx5_cmd *cmd)
97 {
98         u8 token;
99
100         spin_lock(&cmd->token_lock);
101         cmd->token++;
102         if (cmd->token == 0)
103                 cmd->token++;
104         token = cmd->token;
105         spin_unlock(&cmd->token_lock);
106
107         return token;
108 }
109
110 static int alloc_ent(struct mlx5_cmd *cmd)
111 {
112         unsigned long flags;
113         int ret;
114
115         spin_lock_irqsave(&cmd->alloc_lock, flags);
116         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
117         if (ret < cmd->max_reg_cmds)
118                 clear_bit(ret, &cmd->bitmask);
119         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
120
121         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
122 }
123
124 static void free_ent(struct mlx5_cmd *cmd, int idx)
125 {
126         unsigned long flags;
127
128         spin_lock_irqsave(&cmd->alloc_lock, flags);
129         set_bit(idx, &cmd->bitmask);
130         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
131 }
132
133 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
134 {
135         return cmd->cmd_buf + (idx << cmd->log_stride);
136 }
137
138 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
139 {
140         int size = msg->len;
141         int blen = size - min_t(int, sizeof(msg->first.data), size);
142
143         return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
144 }
145
146 static u8 xor8_buf(void *buf, size_t offset, int len)
147 {
148         u8 *ptr = buf;
149         u8 sum = 0;
150         int i;
151         int end = len + offset;
152
153         for (i = offset; i < end; i++)
154                 sum ^= ptr[i];
155
156         return sum;
157 }
158
159 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
160 {
161         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
162         int xor_len = sizeof(*block) - sizeof(block->data) - 1;
163
164         if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
165                 return -EINVAL;
166
167         if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
168                 return -EINVAL;
169
170         return 0;
171 }
172
173 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
174 {
175         int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
176         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
177
178         block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
179         block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
180 }
181
182 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
183 {
184         struct mlx5_cmd_mailbox *next = msg->next;
185         int n = mlx5_calc_cmd_blocks(msg);
186         int i = 0;
187
188         for (i = 0; i < n && next; i++)  {
189                 calc_block_sig(next->buf);
190                 next = next->next;
191         }
192 }
193
194 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
195 {
196         ent->lay->sig = ~xor8_buf(ent->lay, 0,  sizeof(*ent->lay));
197         if (csum) {
198                 calc_chain_sig(ent->in);
199                 calc_chain_sig(ent->out);
200         }
201 }
202
203 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
204 {
205         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
206         u8 own;
207
208         do {
209                 own = ent->lay->status_own;
210                 if (!(own & CMD_OWNER_HW)) {
211                         ent->ret = 0;
212                         return;
213                 }
214                 usleep_range(5000, 10000);
215         } while (time_before(jiffies, poll_end));
216
217         ent->ret = -ETIMEDOUT;
218 }
219
220 static void free_cmd(struct mlx5_cmd_work_ent *ent)
221 {
222         kfree(ent);
223 }
224
225 static int verify_signature(struct mlx5_cmd_work_ent *ent)
226 {
227         struct mlx5_cmd_mailbox *next = ent->out->next;
228         int n = mlx5_calc_cmd_blocks(ent->out);
229         int err;
230         u8 sig;
231         int i = 0;
232
233         sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
234         if (sig != 0xff)
235                 return -EINVAL;
236
237         for (i = 0; i < n && next; i++) {
238                 err = verify_block_sig(next->buf);
239                 if (err)
240                         return err;
241
242                 next = next->next;
243         }
244
245         return 0;
246 }
247
248 static void dump_buf(void *buf, int size, int data_only, int offset)
249 {
250         __be32 *p = buf;
251         int i;
252
253         for (i = 0; i < size; i += 16) {
254                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
255                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
256                          be32_to_cpu(p[3]));
257                 p += 4;
258                 offset += 16;
259         }
260         if (!data_only)
261                 pr_debug("\n");
262 }
263
264 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
265                                        u32 *synd, u8 *status)
266 {
267         *synd = 0;
268         *status = 0;
269
270         switch (op) {
271         case MLX5_CMD_OP_TEARDOWN_HCA:
272         case MLX5_CMD_OP_DISABLE_HCA:
273         case MLX5_CMD_OP_MANAGE_PAGES:
274         case MLX5_CMD_OP_DESTROY_MKEY:
275         case MLX5_CMD_OP_DESTROY_EQ:
276         case MLX5_CMD_OP_DESTROY_CQ:
277         case MLX5_CMD_OP_DESTROY_QP:
278         case MLX5_CMD_OP_DESTROY_PSV:
279         case MLX5_CMD_OP_DESTROY_SRQ:
280         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
281         case MLX5_CMD_OP_DESTROY_XRQ:
282         case MLX5_CMD_OP_DESTROY_DCT:
283         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
284         case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
285         case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
286         case MLX5_CMD_OP_DEALLOC_PD:
287         case MLX5_CMD_OP_DEALLOC_UAR:
288         case MLX5_CMD_OP_DETACH_FROM_MCG:
289         case MLX5_CMD_OP_DEALLOC_XRCD:
290         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
291         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
292         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
293         case MLX5_CMD_OP_DESTROY_LAG:
294         case MLX5_CMD_OP_DESTROY_VPORT_LAG:
295         case MLX5_CMD_OP_DESTROY_TIR:
296         case MLX5_CMD_OP_DESTROY_SQ:
297         case MLX5_CMD_OP_DESTROY_RQ:
298         case MLX5_CMD_OP_DESTROY_RMP:
299         case MLX5_CMD_OP_DESTROY_TIS:
300         case MLX5_CMD_OP_DESTROY_RQT:
301         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
302         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
303         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
304         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
305         case MLX5_CMD_OP_2ERR_QP:
306         case MLX5_CMD_OP_2RST_QP:
307         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
308         case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
309         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
310         case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
311         case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
312         case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
313         case MLX5_CMD_OP_FPGA_DESTROY_QP:
314         case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
315                 return MLX5_CMD_STAT_OK;
316
317         case MLX5_CMD_OP_QUERY_HCA_CAP:
318         case MLX5_CMD_OP_QUERY_ADAPTER:
319         case MLX5_CMD_OP_INIT_HCA:
320         case MLX5_CMD_OP_ENABLE_HCA:
321         case MLX5_CMD_OP_QUERY_PAGES:
322         case MLX5_CMD_OP_SET_HCA_CAP:
323         case MLX5_CMD_OP_QUERY_ISSI:
324         case MLX5_CMD_OP_SET_ISSI:
325         case MLX5_CMD_OP_CREATE_MKEY:
326         case MLX5_CMD_OP_QUERY_MKEY:
327         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
328         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
329         case MLX5_CMD_OP_CREATE_EQ:
330         case MLX5_CMD_OP_QUERY_EQ:
331         case MLX5_CMD_OP_GEN_EQE:
332         case MLX5_CMD_OP_CREATE_CQ:
333         case MLX5_CMD_OP_QUERY_CQ:
334         case MLX5_CMD_OP_MODIFY_CQ:
335         case MLX5_CMD_OP_CREATE_QP:
336         case MLX5_CMD_OP_RST2INIT_QP:
337         case MLX5_CMD_OP_INIT2RTR_QP:
338         case MLX5_CMD_OP_RTR2RTS_QP:
339         case MLX5_CMD_OP_RTS2RTS_QP:
340         case MLX5_CMD_OP_SQERR2RTS_QP:
341         case MLX5_CMD_OP_QUERY_QP:
342         case MLX5_CMD_OP_SQD_RTS_QP:
343         case MLX5_CMD_OP_INIT2INIT_QP:
344         case MLX5_CMD_OP_CREATE_PSV:
345         case MLX5_CMD_OP_CREATE_SRQ:
346         case MLX5_CMD_OP_QUERY_SRQ:
347         case MLX5_CMD_OP_ARM_RQ:
348         case MLX5_CMD_OP_CREATE_XRC_SRQ:
349         case MLX5_CMD_OP_QUERY_XRC_SRQ:
350         case MLX5_CMD_OP_ARM_XRC_SRQ:
351         case MLX5_CMD_OP_CREATE_XRQ:
352         case MLX5_CMD_OP_QUERY_XRQ:
353         case MLX5_CMD_OP_ARM_XRQ:
354         case MLX5_CMD_OP_CREATE_DCT:
355         case MLX5_CMD_OP_DRAIN_DCT:
356         case MLX5_CMD_OP_QUERY_DCT:
357         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
358         case MLX5_CMD_OP_QUERY_VPORT_STATE:
359         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
360         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
361         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
362         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
363         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
364         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
365         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
366         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
367         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
368         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
369         case MLX5_CMD_OP_QUERY_VNIC_ENV:
370         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
371         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
372         case MLX5_CMD_OP_QUERY_Q_COUNTER:
373         case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
374         case MLX5_CMD_OP_QUERY_RATE_LIMIT:
375         case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
376         case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
377         case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
378         case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
379         case MLX5_CMD_OP_ALLOC_PD:
380         case MLX5_CMD_OP_ALLOC_UAR:
381         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
382         case MLX5_CMD_OP_ACCESS_REG:
383         case MLX5_CMD_OP_ATTACH_TO_MCG:
384         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
385         case MLX5_CMD_OP_MAD_IFC:
386         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
387         case MLX5_CMD_OP_SET_MAD_DEMUX:
388         case MLX5_CMD_OP_NOP:
389         case MLX5_CMD_OP_ALLOC_XRCD:
390         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
391         case MLX5_CMD_OP_QUERY_CONG_STATUS:
392         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
393         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
394         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
395         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
396         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
397         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
398         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
399         case MLX5_CMD_OP_CREATE_LAG:
400         case MLX5_CMD_OP_MODIFY_LAG:
401         case MLX5_CMD_OP_QUERY_LAG:
402         case MLX5_CMD_OP_CREATE_VPORT_LAG:
403         case MLX5_CMD_OP_CREATE_TIR:
404         case MLX5_CMD_OP_MODIFY_TIR:
405         case MLX5_CMD_OP_QUERY_TIR:
406         case MLX5_CMD_OP_CREATE_SQ:
407         case MLX5_CMD_OP_MODIFY_SQ:
408         case MLX5_CMD_OP_QUERY_SQ:
409         case MLX5_CMD_OP_CREATE_RQ:
410         case MLX5_CMD_OP_MODIFY_RQ:
411         case MLX5_CMD_OP_QUERY_RQ:
412         case MLX5_CMD_OP_CREATE_RMP:
413         case MLX5_CMD_OP_MODIFY_RMP:
414         case MLX5_CMD_OP_QUERY_RMP:
415         case MLX5_CMD_OP_CREATE_TIS:
416         case MLX5_CMD_OP_MODIFY_TIS:
417         case MLX5_CMD_OP_QUERY_TIS:
418         case MLX5_CMD_OP_CREATE_RQT:
419         case MLX5_CMD_OP_MODIFY_RQT:
420         case MLX5_CMD_OP_QUERY_RQT:
421
422         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
423         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
424         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
425         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
426         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
427         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
428         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
429         case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
430         case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
431         case MLX5_CMD_OP_FPGA_CREATE_QP:
432         case MLX5_CMD_OP_FPGA_MODIFY_QP:
433         case MLX5_CMD_OP_FPGA_QUERY_QP:
434         case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
435         case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
436                 *status = MLX5_DRIVER_STATUS_ABORTED;
437                 *synd = MLX5_DRIVER_SYND;
438                 return -EIO;
439         default:
440                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
441                 return -EINVAL;
442         }
443 }
444
445 const char *mlx5_command_str(int command)
446 {
447 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
448
449         switch (command) {
450         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
451         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
452         MLX5_COMMAND_STR_CASE(INIT_HCA);
453         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
454         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
455         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
456         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
457         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
458         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
459         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
460         MLX5_COMMAND_STR_CASE(SET_ISSI);
461         MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
462         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
463         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
464         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
465         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
466         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
467         MLX5_COMMAND_STR_CASE(CREATE_EQ);
468         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
469         MLX5_COMMAND_STR_CASE(QUERY_EQ);
470         MLX5_COMMAND_STR_CASE(GEN_EQE);
471         MLX5_COMMAND_STR_CASE(CREATE_CQ);
472         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
473         MLX5_COMMAND_STR_CASE(QUERY_CQ);
474         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
475         MLX5_COMMAND_STR_CASE(CREATE_QP);
476         MLX5_COMMAND_STR_CASE(DESTROY_QP);
477         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
478         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
479         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
480         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
481         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
482         MLX5_COMMAND_STR_CASE(2ERR_QP);
483         MLX5_COMMAND_STR_CASE(2RST_QP);
484         MLX5_COMMAND_STR_CASE(QUERY_QP);
485         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
486         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
487         MLX5_COMMAND_STR_CASE(CREATE_PSV);
488         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
489         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
490         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
491         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
492         MLX5_COMMAND_STR_CASE(ARM_RQ);
493         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
494         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
495         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
496         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
497         MLX5_COMMAND_STR_CASE(CREATE_DCT);
498         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
499         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
500         MLX5_COMMAND_STR_CASE(QUERY_DCT);
501         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
502         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
503         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
504         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
505         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
506         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
507         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
508         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
509         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
510         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
511         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
512         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
513         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
514         MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
515         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
516         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
517         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
518         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
519         MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
520         MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
521         MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
522         MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
523         MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
524         MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
525         MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
526         MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
527         MLX5_COMMAND_STR_CASE(ALLOC_PD);
528         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
529         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
530         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
531         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
532         MLX5_COMMAND_STR_CASE(ACCESS_REG);
533         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
534         MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
535         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
536         MLX5_COMMAND_STR_CASE(MAD_IFC);
537         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
538         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
539         MLX5_COMMAND_STR_CASE(NOP);
540         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
541         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
542         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
543         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
544         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
545         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
546         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
547         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
548         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
549         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
550         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
551         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
552         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
553         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
554         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
555         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
556         MLX5_COMMAND_STR_CASE(CREATE_LAG);
557         MLX5_COMMAND_STR_CASE(MODIFY_LAG);
558         MLX5_COMMAND_STR_CASE(QUERY_LAG);
559         MLX5_COMMAND_STR_CASE(DESTROY_LAG);
560         MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
561         MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
562         MLX5_COMMAND_STR_CASE(CREATE_TIR);
563         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
564         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
565         MLX5_COMMAND_STR_CASE(QUERY_TIR);
566         MLX5_COMMAND_STR_CASE(CREATE_SQ);
567         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
568         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
569         MLX5_COMMAND_STR_CASE(QUERY_SQ);
570         MLX5_COMMAND_STR_CASE(CREATE_RQ);
571         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
572         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
573         MLX5_COMMAND_STR_CASE(QUERY_RQ);
574         MLX5_COMMAND_STR_CASE(CREATE_RMP);
575         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
576         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
577         MLX5_COMMAND_STR_CASE(QUERY_RMP);
578         MLX5_COMMAND_STR_CASE(CREATE_TIS);
579         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
580         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
581         MLX5_COMMAND_STR_CASE(QUERY_TIS);
582         MLX5_COMMAND_STR_CASE(CREATE_RQT);
583         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
584         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
585         MLX5_COMMAND_STR_CASE(QUERY_RQT);
586         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
587         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
588         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
589         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
590         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
591         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
592         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
593         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
594         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
595         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
596         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
597         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
598         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
599         MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
600         MLX5_COMMAND_STR_CASE(ALLOC_ENCAP_HEADER);
601         MLX5_COMMAND_STR_CASE(DEALLOC_ENCAP_HEADER);
602         MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
603         MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
604         MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
605         MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
606         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
607         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
608         MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
609         MLX5_COMMAND_STR_CASE(CREATE_XRQ);
610         MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
611         MLX5_COMMAND_STR_CASE(QUERY_XRQ);
612         MLX5_COMMAND_STR_CASE(ARM_XRQ);
613         MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
614         MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
615         default: return "unknown command opcode";
616         }
617 }
618
619 static const char *cmd_status_str(u8 status)
620 {
621         switch (status) {
622         case MLX5_CMD_STAT_OK:
623                 return "OK";
624         case MLX5_CMD_STAT_INT_ERR:
625                 return "internal error";
626         case MLX5_CMD_STAT_BAD_OP_ERR:
627                 return "bad operation";
628         case MLX5_CMD_STAT_BAD_PARAM_ERR:
629                 return "bad parameter";
630         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
631                 return "bad system state";
632         case MLX5_CMD_STAT_BAD_RES_ERR:
633                 return "bad resource";
634         case MLX5_CMD_STAT_RES_BUSY:
635                 return "resource busy";
636         case MLX5_CMD_STAT_LIM_ERR:
637                 return "limits exceeded";
638         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
639                 return "bad resource state";
640         case MLX5_CMD_STAT_IX_ERR:
641                 return "bad index";
642         case MLX5_CMD_STAT_NO_RES_ERR:
643                 return "no resources";
644         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
645                 return "bad input length";
646         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
647                 return "bad output length";
648         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
649                 return "bad QP state";
650         case MLX5_CMD_STAT_BAD_PKT_ERR:
651                 return "bad packet (discarded)";
652         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
653                 return "bad size too many outstanding CQEs";
654         default:
655                 return "unknown status";
656         }
657 }
658
659 static int cmd_status_to_err(u8 status)
660 {
661         switch (status) {
662         case MLX5_CMD_STAT_OK:                          return 0;
663         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
664         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
665         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
666         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
667         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
668         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
669         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
670         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
671         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
672         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
673         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
674         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
675         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
676         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
677         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
678         default:                                        return -EIO;
679         }
680 }
681
682 struct mlx5_ifc_mbox_out_bits {
683         u8         status[0x8];
684         u8         reserved_at_8[0x18];
685
686         u8         syndrome[0x20];
687
688         u8         reserved_at_40[0x40];
689 };
690
691 struct mlx5_ifc_mbox_in_bits {
692         u8         opcode[0x10];
693         u8         uid[0x10];
694
695         u8         reserved_at_20[0x10];
696         u8         op_mod[0x10];
697
698         u8         reserved_at_40[0x40];
699 };
700
701 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
702 {
703         *status = MLX5_GET(mbox_out, out, status);
704         *syndrome = MLX5_GET(mbox_out, out, syndrome);
705 }
706
707 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
708 {
709         u32 syndrome;
710         u8  status;
711         u16 opcode;
712         u16 op_mod;
713         u16 uid;
714
715         mlx5_cmd_mbox_status(out, &status, &syndrome);
716         if (!status)
717                 return 0;
718
719         opcode = MLX5_GET(mbox_in, in, opcode);
720         op_mod = MLX5_GET(mbox_in, in, op_mod);
721         uid    = MLX5_GET(mbox_in, in, uid);
722
723         if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
724                 mlx5_core_err_rl(dev,
725                         "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
726                         mlx5_command_str(opcode), opcode, op_mod,
727                         cmd_status_str(status), status, syndrome);
728         else
729                 mlx5_core_dbg(dev,
730                       "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
731                       mlx5_command_str(opcode),
732                       opcode, op_mod,
733                       cmd_status_str(status),
734                       status,
735                       syndrome);
736
737         return cmd_status_to_err(status);
738 }
739
740 static void dump_command(struct mlx5_core_dev *dev,
741                          struct mlx5_cmd_work_ent *ent, int input)
742 {
743         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
744         u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
745         struct mlx5_cmd_mailbox *next = msg->next;
746         int n = mlx5_calc_cmd_blocks(msg);
747         int data_only;
748         u32 offset = 0;
749         int dump_len;
750         int i;
751
752         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
753
754         if (data_only)
755                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
756                                    "dump command data %s(0x%x) %s\n",
757                                    mlx5_command_str(op), op,
758                                    input ? "INPUT" : "OUTPUT");
759         else
760                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
761                               mlx5_command_str(op), op,
762                               input ? "INPUT" : "OUTPUT");
763
764         if (data_only) {
765                 if (input) {
766                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
767                         offset += sizeof(ent->lay->in);
768                 } else {
769                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
770                         offset += sizeof(ent->lay->out);
771                 }
772         } else {
773                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
774                 offset += sizeof(*ent->lay);
775         }
776
777         for (i = 0; i < n && next; i++)  {
778                 if (data_only) {
779                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
780                         dump_buf(next->buf, dump_len, 1, offset);
781                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
782                 } else {
783                         mlx5_core_dbg(dev, "command block:\n");
784                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
785                         offset += sizeof(struct mlx5_cmd_prot_block);
786                 }
787                 next = next->next;
788         }
789
790         if (data_only)
791                 pr_debug("\n");
792 }
793
794 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
795 {
796         return MLX5_GET(mbox_in, in->first.data, opcode);
797 }
798
799 static void cb_timeout_handler(struct work_struct *work)
800 {
801         struct delayed_work *dwork = container_of(work, struct delayed_work,
802                                                   work);
803         struct mlx5_cmd_work_ent *ent = container_of(dwork,
804                                                      struct mlx5_cmd_work_ent,
805                                                      cb_timeout_work);
806         struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
807                                                  cmd);
808
809         ent->ret = -ETIMEDOUT;
810         mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
811                        mlx5_command_str(msg_to_opcode(ent->in)),
812                        msg_to_opcode(ent->in));
813         mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
814 }
815
816 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
817 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
818                               struct mlx5_cmd_msg *msg);
819
820 static void cmd_work_handler(struct work_struct *work)
821 {
822         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
823         struct mlx5_cmd *cmd = ent->cmd;
824         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
825         unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
826         struct mlx5_cmd_layout *lay;
827         struct semaphore *sem;
828         unsigned long flags;
829         bool poll_cmd = ent->polling;
830         int alloc_ret;
831         int cmd_mode;
832
833         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
834         down(sem);
835         if (!ent->page_queue) {
836                 alloc_ret = alloc_ent(cmd);
837                 if (alloc_ret < 0) {
838                         mlx5_core_err(dev, "failed to allocate command entry\n");
839                         if (ent->callback) {
840                                 ent->callback(-EAGAIN, ent->context);
841                                 mlx5_free_cmd_msg(dev, ent->out);
842                                 free_msg(dev, ent->in);
843                                 free_cmd(ent);
844                         } else {
845                                 ent->ret = -EAGAIN;
846                                 complete(&ent->done);
847                         }
848                         up(sem);
849                         return;
850                 }
851                 ent->idx = alloc_ret;
852         } else {
853                 ent->idx = cmd->max_reg_cmds;
854                 spin_lock_irqsave(&cmd->alloc_lock, flags);
855                 clear_bit(ent->idx, &cmd->bitmask);
856                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
857         }
858
859         cmd->ent_arr[ent->idx] = ent;
860         set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
861         lay = get_inst(cmd, ent->idx);
862         ent->lay = lay;
863         memset(lay, 0, sizeof(*lay));
864         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
865         ent->op = be32_to_cpu(lay->in[0]) >> 16;
866         if (ent->in->next)
867                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
868         lay->inlen = cpu_to_be32(ent->in->len);
869         if (ent->out->next)
870                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
871         lay->outlen = cpu_to_be32(ent->out->len);
872         lay->type = MLX5_PCI_CMD_XPORT;
873         lay->token = ent->token;
874         lay->status_own = CMD_OWNER_HW;
875         set_signature(ent, !cmd->checksum_disabled);
876         dump_command(dev, ent, 1);
877         ent->ts1 = ktime_get_ns();
878         cmd_mode = cmd->mode;
879
880         if (ent->callback)
881                 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
882
883         /* Skip sending command to fw if internal error */
884         if (pci_channel_offline(dev->pdev) ||
885             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
886                 u8 status = 0;
887                 u32 drv_synd;
888
889                 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
890                 MLX5_SET(mbox_out, ent->out, status, status);
891                 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
892
893                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
894                 return;
895         }
896
897         /* ring doorbell after the descriptor is valid */
898         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
899         wmb();
900         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
901         mmiowb();
902         /* if not in polling don't use ent after this point */
903         if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
904                 poll_timeout(ent);
905                 /* make sure we read the descriptor after ownership is SW */
906                 rmb();
907                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
908         }
909 }
910
911 static const char *deliv_status_to_str(u8 status)
912 {
913         switch (status) {
914         case MLX5_CMD_DELIVERY_STAT_OK:
915                 return "no errors";
916         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
917                 return "signature error";
918         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
919                 return "token error";
920         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
921                 return "bad block number";
922         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
923                 return "output pointer not aligned to block size";
924         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
925                 return "input pointer not aligned to block size";
926         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
927                 return "firmware internal error";
928         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
929                 return "command input length error";
930         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
931                 return "command output length error";
932         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
933                 return "reserved fields not cleared";
934         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
935                 return "bad command descriptor type";
936         default:
937                 return "unknown status code";
938         }
939 }
940
941 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
942 {
943         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
944         struct mlx5_cmd *cmd = &dev->cmd;
945         int err;
946
947         if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
948                 wait_for_completion(&ent->done);
949         } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
950                 ent->ret = -ETIMEDOUT;
951                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
952         }
953
954         err = ent->ret;
955
956         if (err == -ETIMEDOUT) {
957                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
958                                mlx5_command_str(msg_to_opcode(ent->in)),
959                                msg_to_opcode(ent->in));
960         }
961         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
962                       err, deliv_status_to_str(ent->status), ent->status);
963
964         return err;
965 }
966
967 /*  Notes:
968  *    1. Callback functions may not sleep
969  *    2. page queue commands do not support asynchrous completion
970  */
971 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
972                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
973                            mlx5_cmd_cbk_t callback,
974                            void *context, int page_queue, u8 *status,
975                            u8 token, bool force_polling)
976 {
977         struct mlx5_cmd *cmd = &dev->cmd;
978         struct mlx5_cmd_work_ent *ent;
979         struct mlx5_cmd_stats *stats;
980         int err = 0;
981         s64 ds;
982         u16 op;
983
984         if (callback && page_queue)
985                 return -EINVAL;
986
987         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
988                         page_queue);
989         if (IS_ERR(ent))
990                 return PTR_ERR(ent);
991
992         ent->token = token;
993         ent->polling = force_polling;
994
995         if (!callback)
996                 init_completion(&ent->done);
997
998         INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
999         INIT_WORK(&ent->work, cmd_work_handler);
1000         if (page_queue) {
1001                 cmd_work_handler(&ent->work);
1002         } else if (!queue_work(cmd->wq, &ent->work)) {
1003                 mlx5_core_warn(dev, "failed to queue work\n");
1004                 err = -ENOMEM;
1005                 goto out_free;
1006         }
1007
1008         if (callback)
1009                 goto out;
1010
1011         err = wait_func(dev, ent);
1012         if (err == -ETIMEDOUT)
1013                 goto out;
1014
1015         ds = ent->ts2 - ent->ts1;
1016         op = MLX5_GET(mbox_in, in->first.data, opcode);
1017         if (op < ARRAY_SIZE(cmd->stats)) {
1018                 stats = &cmd->stats[op];
1019                 spin_lock_irq(&stats->lock);
1020                 stats->sum += ds;
1021                 ++stats->n;
1022                 spin_unlock_irq(&stats->lock);
1023         }
1024         mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1025                            "fw exec time for %s is %lld nsec\n",
1026                            mlx5_command_str(op), ds);
1027         *status = ent->status;
1028
1029 out_free:
1030         free_cmd(ent);
1031 out:
1032         return err;
1033 }
1034
1035 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1036                          size_t count, loff_t *pos)
1037 {
1038         struct mlx5_core_dev *dev = filp->private_data;
1039         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1040         char lbuf[3];
1041         int err;
1042
1043         if (!dbg->in_msg || !dbg->out_msg)
1044                 return -ENOMEM;
1045
1046         if (count < sizeof(lbuf) - 1)
1047                 return -EINVAL;
1048
1049         if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1050                 return -EFAULT;
1051
1052         lbuf[sizeof(lbuf) - 1] = 0;
1053
1054         if (strcmp(lbuf, "go"))
1055                 return -EINVAL;
1056
1057         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1058
1059         return err ? err : count;
1060 }
1061
1062 static const struct file_operations fops = {
1063         .owner  = THIS_MODULE,
1064         .open   = simple_open,
1065         .write  = dbg_write,
1066 };
1067
1068 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1069                             u8 token)
1070 {
1071         struct mlx5_cmd_prot_block *block;
1072         struct mlx5_cmd_mailbox *next;
1073         int copy;
1074
1075         if (!to || !from)
1076                 return -ENOMEM;
1077
1078         copy = min_t(int, size, sizeof(to->first.data));
1079         memcpy(to->first.data, from, copy);
1080         size -= copy;
1081         from += copy;
1082
1083         next = to->next;
1084         while (size) {
1085                 if (!next) {
1086                         /* this is a BUG */
1087                         return -ENOMEM;
1088                 }
1089
1090                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1091                 block = next->buf;
1092                 memcpy(block->data, from, copy);
1093                 from += copy;
1094                 size -= copy;
1095                 block->token = token;
1096                 next = next->next;
1097         }
1098
1099         return 0;
1100 }
1101
1102 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1103 {
1104         struct mlx5_cmd_prot_block *block;
1105         struct mlx5_cmd_mailbox *next;
1106         int copy;
1107
1108         if (!to || !from)
1109                 return -ENOMEM;
1110
1111         copy = min_t(int, size, sizeof(from->first.data));
1112         memcpy(to, from->first.data, copy);
1113         size -= copy;
1114         to += copy;
1115
1116         next = from->next;
1117         while (size) {
1118                 if (!next) {
1119                         /* this is a BUG */
1120                         return -ENOMEM;
1121                 }
1122
1123                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1124                 block = next->buf;
1125
1126                 memcpy(to, block->data, copy);
1127                 to += copy;
1128                 size -= copy;
1129                 next = next->next;
1130         }
1131
1132         return 0;
1133 }
1134
1135 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1136                                               gfp_t flags)
1137 {
1138         struct mlx5_cmd_mailbox *mailbox;
1139
1140         mailbox = kmalloc(sizeof(*mailbox), flags);
1141         if (!mailbox)
1142                 return ERR_PTR(-ENOMEM);
1143
1144         mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1145                                        &mailbox->dma);
1146         if (!mailbox->buf) {
1147                 mlx5_core_dbg(dev, "failed allocation\n");
1148                 kfree(mailbox);
1149                 return ERR_PTR(-ENOMEM);
1150         }
1151         mailbox->next = NULL;
1152
1153         return mailbox;
1154 }
1155
1156 static void free_cmd_box(struct mlx5_core_dev *dev,
1157                          struct mlx5_cmd_mailbox *mailbox)
1158 {
1159         dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1160         kfree(mailbox);
1161 }
1162
1163 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1164                                                gfp_t flags, int size,
1165                                                u8 token)
1166 {
1167         struct mlx5_cmd_mailbox *tmp, *head = NULL;
1168         struct mlx5_cmd_prot_block *block;
1169         struct mlx5_cmd_msg *msg;
1170         int err;
1171         int n;
1172         int i;
1173
1174         msg = kzalloc(sizeof(*msg), flags);
1175         if (!msg)
1176                 return ERR_PTR(-ENOMEM);
1177
1178         msg->len = size;
1179         n = mlx5_calc_cmd_blocks(msg);
1180
1181         for (i = 0; i < n; i++) {
1182                 tmp = alloc_cmd_box(dev, flags);
1183                 if (IS_ERR(tmp)) {
1184                         mlx5_core_warn(dev, "failed allocating block\n");
1185                         err = PTR_ERR(tmp);
1186                         goto err_alloc;
1187                 }
1188
1189                 block = tmp->buf;
1190                 tmp->next = head;
1191                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1192                 block->block_num = cpu_to_be32(n - i - 1);
1193                 block->token = token;
1194                 head = tmp;
1195         }
1196         msg->next = head;
1197         return msg;
1198
1199 err_alloc:
1200         while (head) {
1201                 tmp = head->next;
1202                 free_cmd_box(dev, head);
1203                 head = tmp;
1204         }
1205         kfree(msg);
1206
1207         return ERR_PTR(err);
1208 }
1209
1210 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1211                               struct mlx5_cmd_msg *msg)
1212 {
1213         struct mlx5_cmd_mailbox *head = msg->next;
1214         struct mlx5_cmd_mailbox *next;
1215
1216         while (head) {
1217                 next = head->next;
1218                 free_cmd_box(dev, head);
1219                 head = next;
1220         }
1221         kfree(msg);
1222 }
1223
1224 static ssize_t data_write(struct file *filp, const char __user *buf,
1225                           size_t count, loff_t *pos)
1226 {
1227         struct mlx5_core_dev *dev = filp->private_data;
1228         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1229         void *ptr;
1230
1231         if (*pos != 0)
1232                 return -EINVAL;
1233
1234         kfree(dbg->in_msg);
1235         dbg->in_msg = NULL;
1236         dbg->inlen = 0;
1237         ptr = memdup_user(buf, count);
1238         if (IS_ERR(ptr))
1239                 return PTR_ERR(ptr);
1240         dbg->in_msg = ptr;
1241         dbg->inlen = count;
1242
1243         *pos = count;
1244
1245         return count;
1246 }
1247
1248 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1249                          loff_t *pos)
1250 {
1251         struct mlx5_core_dev *dev = filp->private_data;
1252         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1253
1254         if (!dbg->out_msg)
1255                 return -ENOMEM;
1256
1257         return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1258                                        dbg->outlen);
1259 }
1260
1261 static const struct file_operations dfops = {
1262         .owner  = THIS_MODULE,
1263         .open   = simple_open,
1264         .write  = data_write,
1265         .read   = data_read,
1266 };
1267
1268 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1269                            loff_t *pos)
1270 {
1271         struct mlx5_core_dev *dev = filp->private_data;
1272         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1273         char outlen[8];
1274         int err;
1275
1276         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1277         if (err < 0)
1278                 return err;
1279
1280         return simple_read_from_buffer(buf, count, pos, outlen, err);
1281 }
1282
1283 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1284                             size_t count, loff_t *pos)
1285 {
1286         struct mlx5_core_dev *dev = filp->private_data;
1287         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1288         char outlen_str[8] = {0};
1289         int outlen;
1290         void *ptr;
1291         int err;
1292
1293         if (*pos != 0 || count > 6)
1294                 return -EINVAL;
1295
1296         kfree(dbg->out_msg);
1297         dbg->out_msg = NULL;
1298         dbg->outlen = 0;
1299
1300         if (copy_from_user(outlen_str, buf, count))
1301                 return -EFAULT;
1302
1303         err = sscanf(outlen_str, "%d", &outlen);
1304         if (err < 0)
1305                 return err;
1306
1307         ptr = kzalloc(outlen, GFP_KERNEL);
1308         if (!ptr)
1309                 return -ENOMEM;
1310
1311         dbg->out_msg = ptr;
1312         dbg->outlen = outlen;
1313
1314         *pos = count;
1315
1316         return count;
1317 }
1318
1319 static const struct file_operations olfops = {
1320         .owner  = THIS_MODULE,
1321         .open   = simple_open,
1322         .write  = outlen_write,
1323         .read   = outlen_read,
1324 };
1325
1326 static void set_wqname(struct mlx5_core_dev *dev)
1327 {
1328         struct mlx5_cmd *cmd = &dev->cmd;
1329
1330         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1331                  dev_name(&dev->pdev->dev));
1332 }
1333
1334 static void clean_debug_files(struct mlx5_core_dev *dev)
1335 {
1336         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1337
1338         if (!mlx5_debugfs_root)
1339                 return;
1340
1341         mlx5_cmdif_debugfs_cleanup(dev);
1342         debugfs_remove_recursive(dbg->dbg_root);
1343 }
1344
1345 static int create_debugfs_files(struct mlx5_core_dev *dev)
1346 {
1347         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1348         int err = -ENOMEM;
1349
1350         if (!mlx5_debugfs_root)
1351                 return 0;
1352
1353         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1354         if (!dbg->dbg_root)
1355                 return err;
1356
1357         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1358                                           dev, &dfops);
1359         if (!dbg->dbg_in)
1360                 goto err_dbg;
1361
1362         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1363                                            dev, &dfops);
1364         if (!dbg->dbg_out)
1365                 goto err_dbg;
1366
1367         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1368                                               dev, &olfops);
1369         if (!dbg->dbg_outlen)
1370                 goto err_dbg;
1371
1372         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1373                                             &dbg->status);
1374         if (!dbg->dbg_status)
1375                 goto err_dbg;
1376
1377         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1378         if (!dbg->dbg_run)
1379                 goto err_dbg;
1380
1381         mlx5_cmdif_debugfs_init(dev);
1382
1383         return 0;
1384
1385 err_dbg:
1386         clean_debug_files(dev);
1387         return err;
1388 }
1389
1390 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1391 {
1392         struct mlx5_cmd *cmd = &dev->cmd;
1393         int i;
1394
1395         for (i = 0; i < cmd->max_reg_cmds; i++)
1396                 down(&cmd->sem);
1397         down(&cmd->pages_sem);
1398
1399         cmd->mode = mode;
1400
1401         up(&cmd->pages_sem);
1402         for (i = 0; i < cmd->max_reg_cmds; i++)
1403                 up(&cmd->sem);
1404 }
1405
1406 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1407 {
1408         mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1409 }
1410
1411 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1412 {
1413         mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1414 }
1415
1416 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1417 {
1418         unsigned long flags;
1419
1420         if (msg->parent) {
1421                 spin_lock_irqsave(&msg->parent->lock, flags);
1422                 list_add_tail(&msg->list, &msg->parent->head);
1423                 spin_unlock_irqrestore(&msg->parent->lock, flags);
1424         } else {
1425                 mlx5_free_cmd_msg(dev, msg);
1426         }
1427 }
1428
1429 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1430 {
1431         struct mlx5_cmd *cmd = &dev->cmd;
1432         struct mlx5_cmd_work_ent *ent;
1433         mlx5_cmd_cbk_t callback;
1434         void *context;
1435         int err;
1436         int i;
1437         s64 ds;
1438         struct mlx5_cmd_stats *stats;
1439         unsigned long flags;
1440         unsigned long vector;
1441
1442         /* there can be at most 32 command queues */
1443         vector = vec & 0xffffffff;
1444         for (i = 0; i < (1 << cmd->log_sz); i++) {
1445                 if (test_bit(i, &vector)) {
1446                         struct semaphore *sem;
1447
1448                         ent = cmd->ent_arr[i];
1449
1450                         /* if we already completed the command, ignore it */
1451                         if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1452                                                 &ent->state)) {
1453                                 /* only real completion can free the cmd slot */
1454                                 if (!forced) {
1455                                         mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1456                                                       ent->idx);
1457                                         free_ent(cmd, ent->idx);
1458                                         free_cmd(ent);
1459                                 }
1460                                 continue;
1461                         }
1462
1463                         if (ent->callback)
1464                                 cancel_delayed_work(&ent->cb_timeout_work);
1465                         if (ent->page_queue)
1466                                 sem = &cmd->pages_sem;
1467                         else
1468                                 sem = &cmd->sem;
1469                         ent->ts2 = ktime_get_ns();
1470                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1471                         dump_command(dev, ent, 0);
1472                         if (!ent->ret) {
1473                                 if (!cmd->checksum_disabled)
1474                                         ent->ret = verify_signature(ent);
1475                                 else
1476                                         ent->ret = 0;
1477                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1478                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1479                                 else
1480                                         ent->status = ent->lay->status_own >> 1;
1481
1482                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1483                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1484                         }
1485
1486                         /* only real completion will free the entry slot */
1487                         if (!forced)
1488                                 free_ent(cmd, ent->idx);
1489
1490                         if (ent->callback) {
1491                                 ds = ent->ts2 - ent->ts1;
1492                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1493                                         stats = &cmd->stats[ent->op];
1494                                         spin_lock_irqsave(&stats->lock, flags);
1495                                         stats->sum += ds;
1496                                         ++stats->n;
1497                                         spin_unlock_irqrestore(&stats->lock, flags);
1498                                 }
1499
1500                                 callback = ent->callback;
1501                                 context = ent->context;
1502                                 err = ent->ret;
1503                                 if (!err) {
1504                                         err = mlx5_copy_from_msg(ent->uout,
1505                                                                  ent->out,
1506                                                                  ent->uout_size);
1507
1508                                         err = err ? err : mlx5_cmd_check(dev,
1509                                                                         ent->in->first.data,
1510                                                                         ent->uout);
1511                                 }
1512
1513                                 mlx5_free_cmd_msg(dev, ent->out);
1514                                 free_msg(dev, ent->in);
1515
1516                                 err = err ? err : ent->status;
1517                                 if (!forced)
1518                                         free_cmd(ent);
1519                                 callback(err, context);
1520                         } else {
1521                                 complete(&ent->done);
1522                         }
1523                         up(sem);
1524                 }
1525         }
1526 }
1527 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1528
1529 static int status_to_err(u8 status)
1530 {
1531         return status ? -1 : 0; /* TBD more meaningful codes */
1532 }
1533
1534 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1535                                       gfp_t gfp)
1536 {
1537         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1538         struct cmd_msg_cache *ch = NULL;
1539         struct mlx5_cmd *cmd = &dev->cmd;
1540         int i;
1541
1542         if (in_size <= 16)
1543                 goto cache_miss;
1544
1545         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1546                 ch = &cmd->cache[i];
1547                 if (in_size > ch->max_inbox_size)
1548                         continue;
1549                 spin_lock_irq(&ch->lock);
1550                 if (list_empty(&ch->head)) {
1551                         spin_unlock_irq(&ch->lock);
1552                         continue;
1553                 }
1554                 msg = list_entry(ch->head.next, typeof(*msg), list);
1555                 /* For cached lists, we must explicitly state what is
1556                  * the real size
1557                  */
1558                 msg->len = in_size;
1559                 list_del(&msg->list);
1560                 spin_unlock_irq(&ch->lock);
1561                 break;
1562         }
1563
1564         if (!IS_ERR(msg))
1565                 return msg;
1566
1567 cache_miss:
1568         msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1569         return msg;
1570 }
1571
1572 static int is_manage_pages(void *in)
1573 {
1574         return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1575 }
1576
1577 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1578                     int out_size, mlx5_cmd_cbk_t callback, void *context,
1579                     bool force_polling)
1580 {
1581         struct mlx5_cmd_msg *inb;
1582         struct mlx5_cmd_msg *outb;
1583         int pages_queue;
1584         gfp_t gfp;
1585         int err;
1586         u8 status = 0;
1587         u32 drv_synd;
1588         u8 token;
1589
1590         if (pci_channel_offline(dev->pdev) ||
1591             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1592                 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1593
1594                 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1595                 MLX5_SET(mbox_out, out, status, status);
1596                 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1597                 return err;
1598         }
1599
1600         pages_queue = is_manage_pages(in);
1601         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1602
1603         inb = alloc_msg(dev, in_size, gfp);
1604         if (IS_ERR(inb)) {
1605                 err = PTR_ERR(inb);
1606                 return err;
1607         }
1608
1609         token = alloc_token(&dev->cmd);
1610
1611         err = mlx5_copy_to_msg(inb, in, in_size, token);
1612         if (err) {
1613                 mlx5_core_warn(dev, "err %d\n", err);
1614                 goto out_in;
1615         }
1616
1617         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1618         if (IS_ERR(outb)) {
1619                 err = PTR_ERR(outb);
1620                 goto out_in;
1621         }
1622
1623         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1624                               pages_queue, &status, token, force_polling);
1625         if (err)
1626                 goto out_out;
1627
1628         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1629         if (status) {
1630                 err = status_to_err(status);
1631                 goto out_out;
1632         }
1633
1634         if (!callback)
1635                 err = mlx5_copy_from_msg(out, outb, out_size);
1636
1637 out_out:
1638         if (!callback)
1639                 mlx5_free_cmd_msg(dev, outb);
1640
1641 out_in:
1642         if (!callback)
1643                 free_msg(dev, inb);
1644         return err;
1645 }
1646
1647 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1648                   int out_size)
1649 {
1650         int err;
1651
1652         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1653         return err ? : mlx5_cmd_check(dev, in, out);
1654 }
1655 EXPORT_SYMBOL(mlx5_cmd_exec);
1656
1657 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1658                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1659                      void *context)
1660 {
1661         return cmd_exec(dev, in, in_size, out, out_size, callback, context,
1662                         false);
1663 }
1664 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1665
1666 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1667                           void *out, int out_size)
1668 {
1669         int err;
1670
1671         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1672
1673         return err ? : mlx5_cmd_check(dev, in, out);
1674 }
1675 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1676
1677 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1678 {
1679         struct cmd_msg_cache *ch;
1680         struct mlx5_cmd_msg *msg;
1681         struct mlx5_cmd_msg *n;
1682         int i;
1683
1684         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1685                 ch = &dev->cmd.cache[i];
1686                 list_for_each_entry_safe(msg, n, &ch->head, list) {
1687                         list_del(&msg->list);
1688                         mlx5_free_cmd_msg(dev, msg);
1689                 }
1690         }
1691 }
1692
1693 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1694         512, 32, 16, 8, 2
1695 };
1696
1697 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1698         16 + MLX5_CMD_DATA_BLOCK_SIZE,
1699         16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1700         16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1701         16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1702         16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1703 };
1704
1705 static void create_msg_cache(struct mlx5_core_dev *dev)
1706 {
1707         struct mlx5_cmd *cmd = &dev->cmd;
1708         struct cmd_msg_cache *ch;
1709         struct mlx5_cmd_msg *msg;
1710         int i;
1711         int k;
1712
1713         /* Initialize and fill the caches with initial entries */
1714         for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1715                 ch = &cmd->cache[k];
1716                 spin_lock_init(&ch->lock);
1717                 INIT_LIST_HEAD(&ch->head);
1718                 ch->num_ent = cmd_cache_num_ent[k];
1719                 ch->max_inbox_size = cmd_cache_ent_size[k];
1720                 for (i = 0; i < ch->num_ent; i++) {
1721                         msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1722                                                  ch->max_inbox_size, 0);
1723                         if (IS_ERR(msg))
1724                                 break;
1725                         msg->parent = ch;
1726                         list_add_tail(&msg->list, &ch->head);
1727                 }
1728         }
1729 }
1730
1731 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1732 {
1733         struct device *ddev = &dev->pdev->dev;
1734
1735         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1736                                                  &cmd->alloc_dma, GFP_KERNEL);
1737         if (!cmd->cmd_alloc_buf)
1738                 return -ENOMEM;
1739
1740         /* make sure it is aligned to 4K */
1741         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1742                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1743                 cmd->dma = cmd->alloc_dma;
1744                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1745                 return 0;
1746         }
1747
1748         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1749                           cmd->alloc_dma);
1750         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1751                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1752                                                  &cmd->alloc_dma, GFP_KERNEL);
1753         if (!cmd->cmd_alloc_buf)
1754                 return -ENOMEM;
1755
1756         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1757         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1758         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1759         return 0;
1760 }
1761
1762 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1763 {
1764         struct device *ddev = &dev->pdev->dev;
1765
1766         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1767                           cmd->alloc_dma);
1768 }
1769
1770 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1771 {
1772         int size = sizeof(struct mlx5_cmd_prot_block);
1773         int align = roundup_pow_of_two(size);
1774         struct mlx5_cmd *cmd = &dev->cmd;
1775         u32 cmd_h, cmd_l;
1776         u16 cmd_if_rev;
1777         int err;
1778         int i;
1779
1780         memset(cmd, 0, sizeof(*cmd));
1781         cmd_if_rev = cmdif_rev(dev);
1782         if (cmd_if_rev != CMD_IF_REV) {
1783                 dev_err(&dev->pdev->dev,
1784                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1785                         CMD_IF_REV, cmd_if_rev);
1786                 return -EINVAL;
1787         }
1788
1789         cmd->pool = dma_pool_create("mlx5_cmd", &dev->pdev->dev, size, align,
1790                                     0);
1791         if (!cmd->pool)
1792                 return -ENOMEM;
1793
1794         err = alloc_cmd_page(dev, cmd);
1795         if (err)
1796                 goto err_free_pool;
1797
1798         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1799         cmd->log_sz = cmd_l >> 4 & 0xf;
1800         cmd->log_stride = cmd_l & 0xf;
1801         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1802                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1803                         1 << cmd->log_sz);
1804                 err = -EINVAL;
1805                 goto err_free_page;
1806         }
1807
1808         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1809                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1810                 err = -EINVAL;
1811                 goto err_free_page;
1812         }
1813
1814         cmd->checksum_disabled = 1;
1815         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1816         cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
1817
1818         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1819         if (cmd->cmdif_rev > CMD_IF_REV) {
1820                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1821                         CMD_IF_REV, cmd->cmdif_rev);
1822                 err = -EOPNOTSUPP;
1823                 goto err_free_page;
1824         }
1825
1826         spin_lock_init(&cmd->alloc_lock);
1827         spin_lock_init(&cmd->token_lock);
1828         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1829                 spin_lock_init(&cmd->stats[i].lock);
1830
1831         sema_init(&cmd->sem, cmd->max_reg_cmds);
1832         sema_init(&cmd->pages_sem, 1);
1833
1834         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1835         cmd_l = (u32)(cmd->dma);
1836         if (cmd_l & 0xfff) {
1837                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1838                 err = -ENOMEM;
1839                 goto err_free_page;
1840         }
1841
1842         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1843         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1844
1845         /* Make sure firmware sees the complete address before we proceed */
1846         wmb();
1847
1848         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1849
1850         cmd->mode = CMD_MODE_POLLING;
1851
1852         create_msg_cache(dev);
1853
1854         set_wqname(dev);
1855         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1856         if (!cmd->wq) {
1857                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1858                 err = -ENOMEM;
1859                 goto err_cache;
1860         }
1861
1862         err = create_debugfs_files(dev);
1863         if (err) {
1864                 err = -ENOMEM;
1865                 goto err_wq;
1866         }
1867
1868         return 0;
1869
1870 err_wq:
1871         destroy_workqueue(cmd->wq);
1872
1873 err_cache:
1874         destroy_msg_cache(dev);
1875
1876 err_free_page:
1877         free_cmd_page(dev, cmd);
1878
1879 err_free_pool:
1880         dma_pool_destroy(cmd->pool);
1881
1882         return err;
1883 }
1884 EXPORT_SYMBOL(mlx5_cmd_init);
1885
1886 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1887 {
1888         struct mlx5_cmd *cmd = &dev->cmd;
1889
1890         clean_debug_files(dev);
1891         destroy_workqueue(cmd->wq);
1892         destroy_msg_cache(dev);
1893         free_cmd_page(dev, cmd);
1894         dma_pool_destroy(cmd->pool);
1895 }
1896 EXPORT_SYMBOL(mlx5_cmd_cleanup);