drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/debugfs.h>
  44
  45 #include "mlx5_core.h"
  46
  47 enum {
  48         CMD_IF_REV = 5,
  49 };
  50
  51 enum {
  52         CMD_MODE_POLLING,
  53         CMD_MODE_EVENTS
  54 };
  55
  56 enum {
  57         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  58         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  59         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  60         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  61         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  62         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  63         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  64         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  65         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  66         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  67         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  68 };
  69
  70 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  71                                            struct mlx5_cmd_msg *in,
  72                                            struct mlx5_cmd_msg *out,
  73                                            void *uout, int uout_size,
  74                                            mlx5_cmd_cbk_t cbk,
  75                                            void *context, int page_queue)
  76 {
  77         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
  78         struct mlx5_cmd_work_ent *ent;
  79
  80         ent = kzalloc(sizeof(*ent), alloc_flags);
  81         if (!ent)
  82                 return ERR_PTR(-ENOMEM);
  83
  84         ent->in         = in;
  85         ent->out        = out;
  86         ent->uout       = uout;
  87         ent->uout_size  = uout_size;
  88         ent->callback   = cbk;
  89         ent->context    = context;
  90         ent->cmd        = cmd;
  91         ent->page_queue = page_queue;
  92
  93         return ent;
  94 }
  95
  96 static u8 alloc_token(struct mlx5_cmd *cmd)
  97 {
  98         u8 token;
  99
 100         spin_lock(&cmd->token_lock);
 101         cmd->token++;
 102         if (cmd->token == 0)
 103                 cmd->token++;
 104         token = cmd->token;
 105         spin_unlock(&cmd->token_lock);
 106
 107         return token;
 108 }
 109
 110 static int alloc_ent(struct mlx5_cmd *cmd)
 111 {
 112         unsigned long flags;
 113         int ret;
 114
 115         spin_lock_irqsave(&cmd->alloc_lock, flags);
 116         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 117         if (ret < cmd->max_reg_cmds)
 118                 clear_bit(ret, &cmd->bitmask);
 119         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 120
 121         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 122 }
 123
 124 static void free_ent(struct mlx5_cmd *cmd, int idx)
 125 {
 126         unsigned long flags;
 127
 128         spin_lock_irqsave(&cmd->alloc_lock, flags);
 129         set_bit(idx, &cmd->bitmask);
 130         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 131 }
 132
 133 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 134 {
 135         return cmd->cmd_buf + (idx << cmd->log_stride);
 136 }
 137
 138 static u8 xor8_buf(void *buf, size_t offset, int len)
 139 {
 140         u8 *ptr = buf;
 141         u8 sum = 0;
 142         int i;
 143         int end = len + offset;
 144
 145         for (i = offset; i < end; i++)
 146                 sum ^= ptr[i];
 147
 148         return sum;
 149 }
 150
 151 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 152 {
 153         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 154         int xor_len = sizeof(*block) - sizeof(block->data) - 1;
 155
 156         if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
 157                 return -EINVAL;
 158
 159         if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
 160                 return -EINVAL;
 161
 162         return 0;
 163 }
 164
 165 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
 166 {
 167         int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
 168         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 169
 170         block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
 171         block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
 172 }
 173
 174 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
 175 {
 176         struct mlx5_cmd_mailbox *next = msg->next;
 177         int size = msg->len;
 178         int blen = size - min_t(int, sizeof(msg->first.data), size);
 179         int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
 180                 / MLX5_CMD_DATA_BLOCK_SIZE;
 181         int i = 0;
 182
 183         for (i = 0; i < n && next; i++)  {
 184                 calc_block_sig(next->buf);
 185                 next = next->next;
 186         }
 187 }
 188
 189 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 190 {
 191         ent->lay->sig = ~xor8_buf(ent->lay, 0,  sizeof(*ent->lay));
 192         if (csum) {
 193                 calc_chain_sig(ent->in);
 194                 calc_chain_sig(ent->out);
 195         }
 196 }
 197
 198 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 199 {
 200         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 201         u8 own;
 202
 203         do {
 204                 own = ent->lay->status_own;
 205                 if (!(own & CMD_OWNER_HW)) {
 206                         ent->ret = 0;
 207                         return;
 208                 }
 209                 usleep_range(5000, 10000);
 210         } while (time_before(jiffies, poll_end));
 211
 212         ent->ret = -ETIMEDOUT;
 213 }
 214
 215 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 216 {
 217         kfree(ent);
 218 }
 219
 220 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 221 {
 222         struct mlx5_cmd_mailbox *next = ent->out->next;
 223         int err;
 224         u8 sig;
 225         int size = ent->out->len;
 226         int blen = size - min_t(int, sizeof(ent->out->first.data), size);
 227         int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
 228                 / MLX5_CMD_DATA_BLOCK_SIZE;
 229         int i = 0;
 230
 231         sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
 232         if (sig != 0xff)
 233                 return -EINVAL;
 234
 235         for (i = 0; i < n && next; i++) {
 236                 err = verify_block_sig(next->buf);
 237                 if (err)
 238                         return err;
 239
 240                 next = next->next;
 241         }
 242
 243         return 0;
 244 }
 245
 246 static void dump_buf(void *buf, int size, int data_only, int offset)
 247 {
 248         __be32 *p = buf;
 249         int i;
 250
 251         for (i = 0; i < size; i += 16) {
 252                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 253                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 254                          be32_to_cpu(p[3]));
 255                 p += 4;
 256                 offset += 16;
 257         }
 258         if (!data_only)
 259                 pr_debug("\n");
 260 }
 261
 262 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
 263                                        u32 *synd, u8 *status)
 264 {
 265         *synd = 0;
 266         *status = 0;
 267
 268         switch (op) {
 269         case MLX5_CMD_OP_TEARDOWN_HCA:
 270         case MLX5_CMD_OP_DISABLE_HCA:
 271         case MLX5_CMD_OP_MANAGE_PAGES:
 272         case MLX5_CMD_OP_DESTROY_MKEY:
 273         case MLX5_CMD_OP_DESTROY_EQ:
 274         case MLX5_CMD_OP_DESTROY_CQ:
 275         case MLX5_CMD_OP_DESTROY_QP:
 276         case MLX5_CMD_OP_DESTROY_PSV:
 277         case MLX5_CMD_OP_DESTROY_SRQ:
 278         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 279         case MLX5_CMD_OP_DESTROY_DCT:
 280         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 281         case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
 282         case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
 283         case MLX5_CMD_OP_DEALLOC_PD:
 284         case MLX5_CMD_OP_DEALLOC_UAR:
 285         case MLX5_CMD_OP_DETACH_FROM_MCG:
 286         case MLX5_CMD_OP_DEALLOC_XRCD:
 287         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 288         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 289         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 290         case MLX5_CMD_OP_DESTROY_LAG:
 291         case MLX5_CMD_OP_DESTROY_VPORT_LAG:
 292         case MLX5_CMD_OP_DESTROY_TIR:
 293         case MLX5_CMD_OP_DESTROY_SQ:
 294         case MLX5_CMD_OP_DESTROY_RQ:
 295         case MLX5_CMD_OP_DESTROY_RMP:
 296         case MLX5_CMD_OP_DESTROY_TIS:
 297         case MLX5_CMD_OP_DESTROY_RQT:
 298         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 299         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 300         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 301         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
 302         case MLX5_CMD_OP_2ERR_QP:
 303         case MLX5_CMD_OP_2RST_QP:
 304         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 305         case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
 306         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 307         case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
 308         case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
 309         case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
 310         case MLX5_CMD_OP_FPGA_DESTROY_QP:
 311                 return MLX5_CMD_STAT_OK;
 312
 313         case MLX5_CMD_OP_QUERY_HCA_CAP:
 314         case MLX5_CMD_OP_QUERY_ADAPTER:
 315         case MLX5_CMD_OP_INIT_HCA:
 316         case MLX5_CMD_OP_ENABLE_HCA:
 317         case MLX5_CMD_OP_QUERY_PAGES:
 318         case MLX5_CMD_OP_SET_HCA_CAP:
 319         case MLX5_CMD_OP_QUERY_ISSI:
 320         case MLX5_CMD_OP_SET_ISSI:
 321         case MLX5_CMD_OP_CREATE_MKEY:
 322         case MLX5_CMD_OP_QUERY_MKEY:
 323         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 324         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 325         case MLX5_CMD_OP_CREATE_EQ:
 326         case MLX5_CMD_OP_QUERY_EQ:
 327         case MLX5_CMD_OP_GEN_EQE:
 328         case MLX5_CMD_OP_CREATE_CQ:
 329         case MLX5_CMD_OP_QUERY_CQ:
 330         case MLX5_CMD_OP_MODIFY_CQ:
 331         case MLX5_CMD_OP_CREATE_QP:
 332         case MLX5_CMD_OP_RST2INIT_QP:
 333         case MLX5_CMD_OP_INIT2RTR_QP:
 334         case MLX5_CMD_OP_RTR2RTS_QP:
 335         case MLX5_CMD_OP_RTS2RTS_QP:
 336         case MLX5_CMD_OP_SQERR2RTS_QP:
 337         case MLX5_CMD_OP_QUERY_QP:
 338         case MLX5_CMD_OP_SQD_RTS_QP:
 339         case MLX5_CMD_OP_INIT2INIT_QP:
 340         case MLX5_CMD_OP_CREATE_PSV:
 341         case MLX5_CMD_OP_CREATE_SRQ:
 342         case MLX5_CMD_OP_QUERY_SRQ:
 343         case MLX5_CMD_OP_ARM_RQ:
 344         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 345         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 346         case MLX5_CMD_OP_ARM_XRC_SRQ:
 347         case MLX5_CMD_OP_CREATE_DCT:
 348         case MLX5_CMD_OP_DRAIN_DCT:
 349         case MLX5_CMD_OP_QUERY_DCT:
 350         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 351         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 352         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 353         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 354         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 355         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 356         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 357         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 358         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 359         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 360         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 361         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 362         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 363         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 364         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 365         case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
 366         case MLX5_CMD_OP_QUERY_RATE_LIMIT:
 367         case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
 368         case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
 369         case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
 370         case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
 371         case MLX5_CMD_OP_ALLOC_PD:
 372         case MLX5_CMD_OP_ALLOC_UAR:
 373         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 374         case MLX5_CMD_OP_ACCESS_REG:
 375         case MLX5_CMD_OP_ATTACH_TO_MCG:
 376         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 377         case MLX5_CMD_OP_MAD_IFC:
 378         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 379         case MLX5_CMD_OP_SET_MAD_DEMUX:
 380         case MLX5_CMD_OP_NOP:
 381         case MLX5_CMD_OP_ALLOC_XRCD:
 382         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 383         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 384         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 385         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 386         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 387         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 388         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 389         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 390         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 391         case MLX5_CMD_OP_CREATE_LAG:
 392         case MLX5_CMD_OP_MODIFY_LAG:
 393         case MLX5_CMD_OP_QUERY_LAG:
 394         case MLX5_CMD_OP_CREATE_VPORT_LAG:
 395         case MLX5_CMD_OP_CREATE_TIR:
 396         case MLX5_CMD_OP_MODIFY_TIR:
 397         case MLX5_CMD_OP_QUERY_TIR:
 398         case MLX5_CMD_OP_CREATE_SQ:
 399         case MLX5_CMD_OP_MODIFY_SQ:
 400         case MLX5_CMD_OP_QUERY_SQ:
 401         case MLX5_CMD_OP_CREATE_RQ:
 402         case MLX5_CMD_OP_MODIFY_RQ:
 403         case MLX5_CMD_OP_QUERY_RQ:
 404         case MLX5_CMD_OP_CREATE_RMP:
 405         case MLX5_CMD_OP_MODIFY_RMP:
 406         case MLX5_CMD_OP_QUERY_RMP:
 407         case MLX5_CMD_OP_CREATE_TIS:
 408         case MLX5_CMD_OP_MODIFY_TIS:
 409         case MLX5_CMD_OP_QUERY_TIS:
 410         case MLX5_CMD_OP_CREATE_RQT:
 411         case MLX5_CMD_OP_MODIFY_RQT:
 412         case MLX5_CMD_OP_QUERY_RQT:
 413
 414         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 415         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 416         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 417         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 418         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 419         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
 420         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
 421         case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
 422         case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
 423         case MLX5_CMD_OP_FPGA_CREATE_QP:
 424         case MLX5_CMD_OP_FPGA_MODIFY_QP:
 425         case MLX5_CMD_OP_FPGA_QUERY_QP:
 426         case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
 427                 *status = MLX5_DRIVER_STATUS_ABORTED;
 428                 *synd = MLX5_DRIVER_SYND;
 429                 return -EIO;
 430         default:
 431                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
 432                 return -EINVAL;
 433         }
 434 }
 435
 436 const char *mlx5_command_str(int command)
 437 {
 438 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
 439
 440         switch (command) {
 441         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
 442         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
 443         MLX5_COMMAND_STR_CASE(INIT_HCA);
 444         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
 445         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
 446         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
 447         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
 448         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
 449         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
 450         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
 451         MLX5_COMMAND_STR_CASE(SET_ISSI);
 452         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
 453         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
 454         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
 455         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
 456         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
 457         MLX5_COMMAND_STR_CASE(CREATE_EQ);
 458         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
 459         MLX5_COMMAND_STR_CASE(QUERY_EQ);
 460         MLX5_COMMAND_STR_CASE(GEN_EQE);
 461         MLX5_COMMAND_STR_CASE(CREATE_CQ);
 462         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
 463         MLX5_COMMAND_STR_CASE(QUERY_CQ);
 464         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
 465         MLX5_COMMAND_STR_CASE(CREATE_QP);
 466         MLX5_COMMAND_STR_CASE(DESTROY_QP);
 467         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
 468         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
 469         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
 470         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
 471         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
 472         MLX5_COMMAND_STR_CASE(2ERR_QP);
 473         MLX5_COMMAND_STR_CASE(2RST_QP);
 474         MLX5_COMMAND_STR_CASE(QUERY_QP);
 475         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
 476         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
 477         MLX5_COMMAND_STR_CASE(CREATE_PSV);
 478         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
 479         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
 480         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
 481         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
 482         MLX5_COMMAND_STR_CASE(ARM_RQ);
 483         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
 484         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
 485         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
 486         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
 487         MLX5_COMMAND_STR_CASE(CREATE_DCT);
 488         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
 489         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
 490         MLX5_COMMAND_STR_CASE(QUERY_DCT);
 491         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
 492         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
 493         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
 494         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
 495         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
 496         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
 497         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
 498         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
 499         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
 500         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
 501         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
 502         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
 503         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
 504         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
 505         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
 506         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
 507         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
 508         MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
 509         MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
 510         MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
 511         MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
 512         MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
 513         MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
 514         MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
 515         MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
 516         MLX5_COMMAND_STR_CASE(ALLOC_PD);
 517         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
 518         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
 519         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
 520         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
 521         MLX5_COMMAND_STR_CASE(ACCESS_REG);
 522         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
 523         MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
 524         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
 525         MLX5_COMMAND_STR_CASE(MAD_IFC);
 526         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
 527         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
 528         MLX5_COMMAND_STR_CASE(NOP);
 529         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
 530         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
 531         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
 532         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
 533         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
 534         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
 535         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
 536         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
 537         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
 538         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
 539         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
 540         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
 541         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
 542         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
 543         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
 544         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
 545         MLX5_COMMAND_STR_CASE(CREATE_LAG);
 546         MLX5_COMMAND_STR_CASE(MODIFY_LAG);
 547         MLX5_COMMAND_STR_CASE(QUERY_LAG);
 548         MLX5_COMMAND_STR_CASE(DESTROY_LAG);
 549         MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
 550         MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
 551         MLX5_COMMAND_STR_CASE(CREATE_TIR);
 552         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
 553         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
 554         MLX5_COMMAND_STR_CASE(QUERY_TIR);
 555         MLX5_COMMAND_STR_CASE(CREATE_SQ);
 556         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
 557         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
 558         MLX5_COMMAND_STR_CASE(QUERY_SQ);
 559         MLX5_COMMAND_STR_CASE(CREATE_RQ);
 560         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
 561         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
 562         MLX5_COMMAND_STR_CASE(QUERY_RQ);
 563         MLX5_COMMAND_STR_CASE(CREATE_RMP);
 564         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
 565         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
 566         MLX5_COMMAND_STR_CASE(QUERY_RMP);
 567         MLX5_COMMAND_STR_CASE(CREATE_TIS);
 568         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
 569         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
 570         MLX5_COMMAND_STR_CASE(QUERY_TIS);
 571         MLX5_COMMAND_STR_CASE(CREATE_RQT);
 572         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
 573         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
 574         MLX5_COMMAND_STR_CASE(QUERY_RQT);
 575         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
 576         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
 577         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
 578         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
 579         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
 580         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
 581         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
 582         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
 583         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
 584         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
 585         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
 586         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
 587         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
 588         MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
 589         MLX5_COMMAND_STR_CASE(ALLOC_ENCAP_HEADER);
 590         MLX5_COMMAND_STR_CASE(DEALLOC_ENCAP_HEADER);
 591         MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
 592         MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
 593         MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
 594         MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
 595         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
 596         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
 597         MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
 598         default: return "unknown command opcode";
 599         }
 600 }
 601
 602 static const char *cmd_status_str(u8 status)
 603 {
 604         switch (status) {
 605         case MLX5_CMD_STAT_OK:
 606                 return "OK";
 607         case MLX5_CMD_STAT_INT_ERR:
 608                 return "internal error";
 609         case MLX5_CMD_STAT_BAD_OP_ERR:
 610                 return "bad operation";
 611         case MLX5_CMD_STAT_BAD_PARAM_ERR:
 612                 return "bad parameter";
 613         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
 614                 return "bad system state";
 615         case MLX5_CMD_STAT_BAD_RES_ERR:
 616                 return "bad resource";
 617         case MLX5_CMD_STAT_RES_BUSY:
 618                 return "resource busy";
 619         case MLX5_CMD_STAT_LIM_ERR:
 620                 return "limits exceeded";
 621         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
 622                 return "bad resource state";
 623         case MLX5_CMD_STAT_IX_ERR:
 624                 return "bad index";
 625         case MLX5_CMD_STAT_NO_RES_ERR:
 626                 return "no resources";
 627         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
 628                 return "bad input length";
 629         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
 630                 return "bad output length";
 631         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
 632                 return "bad QP state";
 633         case MLX5_CMD_STAT_BAD_PKT_ERR:
 634                 return "bad packet (discarded)";
 635         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
 636                 return "bad size too many outstanding CQEs";
 637         default:
 638                 return "unknown status";
 639         }
 640 }
 641
 642 static int cmd_status_to_err(u8 status)
 643 {
 644         switch (status) {
 645         case MLX5_CMD_STAT_OK:                          return 0;
 646         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
 647         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
 648         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
 649         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
 650         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
 651         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
 652         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
 653         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
 654         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
 655         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
 656         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
 657         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
 658         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
 659         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
 660         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
 661         default:                                        return -EIO;
 662         }
 663 }
 664
 665 struct mlx5_ifc_mbox_out_bits {
 666         u8         status[0x8];
 667         u8         reserved_at_8[0x18];
 668
 669         u8         syndrome[0x20];
 670
 671         u8         reserved_at_40[0x40];
 672 };
 673
 674 struct mlx5_ifc_mbox_in_bits {
 675         u8         opcode[0x10];
 676         u8         reserved_at_10[0x10];
 677
 678         u8         reserved_at_20[0x10];
 679         u8         op_mod[0x10];
 680
 681         u8         reserved_at_40[0x40];
 682 };
 683
 684 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
 685 {
 686         *status = MLX5_GET(mbox_out, out, status);
 687         *syndrome = MLX5_GET(mbox_out, out, syndrome);
 688 }
 689
 690 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
 691 {
 692         u32 syndrome;
 693         u8  status;
 694         u16 opcode;
 695         u16 op_mod;
 696
 697         mlx5_cmd_mbox_status(out, &status, &syndrome);
 698         if (!status)
 699                 return 0;
 700
 701         opcode = MLX5_GET(mbox_in, in, opcode);
 702         op_mod = MLX5_GET(mbox_in, in, op_mod);
 703
 704         mlx5_core_err(dev,
 705                       "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
 706                       mlx5_command_str(opcode),
 707                       opcode, op_mod,
 708                       cmd_status_str(status),
 709                       status,
 710                       syndrome);
 711
 712         return cmd_status_to_err(status);
 713 }
 714
 715 static void dump_command(struct mlx5_core_dev *dev,
 716                          struct mlx5_cmd_work_ent *ent, int input)
 717 {
 718         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 719         u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
 720         struct mlx5_cmd_mailbox *next = msg->next;
 721         int data_only;
 722         u32 offset = 0;
 723         int dump_len;
 724
 725         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 726
 727         if (data_only)
 728                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 729                                    "dump command data %s(0x%x) %s\n",
 730                                    mlx5_command_str(op), op,
 731                                    input ? "INPUT" : "OUTPUT");
 732         else
 733                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 734                               mlx5_command_str(op), op,
 735                               input ? "INPUT" : "OUTPUT");
 736
 737         if (data_only) {
 738                 if (input) {
 739                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 740                         offset += sizeof(ent->lay->in);
 741                 } else {
 742                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 743                         offset += sizeof(ent->lay->out);
 744                 }
 745         } else {
 746                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 747                 offset += sizeof(*ent->lay);
 748         }
 749
 750         while (next && offset < msg->len) {
 751                 if (data_only) {
 752                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 753                         dump_buf(next->buf, dump_len, 1, offset);
 754                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 755                 } else {
 756                         mlx5_core_dbg(dev, "command block:\n");
 757                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 758                         offset += sizeof(struct mlx5_cmd_prot_block);
 759                 }
 760                 next = next->next;
 761         }
 762
 763         if (data_only)
 764                 pr_debug("\n");
 765 }
 766
 767 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 768 {
 769         return MLX5_GET(mbox_in, in->first.data, opcode);
 770 }
 771
 772 static void cb_timeout_handler(struct work_struct *work)
 773 {
 774         struct delayed_work *dwork = container_of(work, struct delayed_work,
 775                                                   work);
 776         struct mlx5_cmd_work_ent *ent = container_of(dwork,
 777                                                      struct mlx5_cmd_work_ent,
 778                                                      cb_timeout_work);
 779         struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
 780                                                  cmd);
 781
 782         ent->ret = -ETIMEDOUT;
 783         mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 784                        mlx5_command_str(msg_to_opcode(ent->in)),
 785                        msg_to_opcode(ent->in));
 786         mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 787 }
 788
 789 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
 790 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
 791                               struct mlx5_cmd_msg *msg);
 792
 793 static void cmd_work_handler(struct work_struct *work)
 794 {
 795         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 796         struct mlx5_cmd *cmd = ent->cmd;
 797         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 798         unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 799         struct mlx5_cmd_layout *lay;
 800         struct semaphore *sem;
 801         unsigned long flags;
 802         bool poll_cmd = ent->polling;
 803         int alloc_ret;
 804
 805         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 806         down(sem);
 807         if (!ent->page_queue) {
 808                 alloc_ret = alloc_ent(cmd);
 809                 if (alloc_ret < 0) {
 810                         mlx5_core_err(dev, "failed to allocate command entry\n");
 811                         if (ent->callback) {
 812                                 ent->callback(-EAGAIN, ent->context);
 813                                 mlx5_free_cmd_msg(dev, ent->out);
 814                                 free_msg(dev, ent->in);
 815                                 free_cmd(ent);
 816                         } else {
 817                                 ent->ret = -EAGAIN;
 818                                 complete(&ent->done);
 819                         }
 820                         up(sem);
 821                         return;
 822                 }
 823                 ent->idx = alloc_ret;
 824         } else {
 825                 ent->idx = cmd->max_reg_cmds;
 826                 spin_lock_irqsave(&cmd->alloc_lock, flags);
 827                 clear_bit(ent->idx, &cmd->bitmask);
 828                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 829         }
 830
 831         cmd->ent_arr[ent->idx] = ent;
 832         set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
 833         lay = get_inst(cmd, ent->idx);
 834         ent->lay = lay;
 835         memset(lay, 0, sizeof(*lay));
 836         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 837         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 838         if (ent->in->next)
 839                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 840         lay->inlen = cpu_to_be32(ent->in->len);
 841         if (ent->out->next)
 842                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 843         lay->outlen = cpu_to_be32(ent->out->len);
 844         lay->type = MLX5_PCI_CMD_XPORT;
 845         lay->token = ent->token;
 846         lay->status_own = CMD_OWNER_HW;
 847         set_signature(ent, !cmd->checksum_disabled);
 848         dump_command(dev, ent, 1);
 849         ent->ts1 = ktime_get_ns();
 850
 851         if (ent->callback)
 852                 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
 853
 854         /* Skip sending command to fw if internal error */
 855         if (pci_channel_offline(dev->pdev) ||
 856             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
 857                 u8 status = 0;
 858                 u32 drv_synd;
 859
 860                 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
 861                 MLX5_SET(mbox_out, ent->out, status, status);
 862                 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
 863
 864                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 865                 return;
 866         }
 867
 868         /* ring doorbell after the descriptor is valid */
 869         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
 870         wmb();
 871         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 872         mmiowb();
 873         /* if not in polling don't use ent after this point */
 874         if (cmd->mode == CMD_MODE_POLLING || poll_cmd) {
 875                 poll_timeout(ent);
 876                 /* make sure we read the descriptor after ownership is SW */
 877                 rmb();
 878                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
 879         }
 880 }
 881
 882 static const char *deliv_status_to_str(u8 status)
 883 {
 884         switch (status) {
 885         case MLX5_CMD_DELIVERY_STAT_OK:
 886                 return "no errors";
 887         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 888                 return "signature error";
 889         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 890                 return "token error";
 891         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 892                 return "bad block number";
 893         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 894                 return "output pointer not aligned to block size";
 895         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 896                 return "input pointer not aligned to block size";
 897         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 898                 return "firmware internal error";
 899         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 900                 return "command input length error";
 901         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 902                 return "command output length error";
 903         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 904                 return "reserved fields not cleared";
 905         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 906                 return "bad command descriptor type";
 907         default:
 908                 return "unknown status code";
 909         }
 910 }
 911
 912 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 913 {
 914         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 915         struct mlx5_cmd *cmd = &dev->cmd;
 916         int err;
 917
 918         if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
 919                 wait_for_completion(&ent->done);
 920         } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
 921                 ent->ret = -ETIMEDOUT;
 922                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 923         }
 924
 925         err = ent->ret;
 926
 927         if (err == -ETIMEDOUT) {
 928                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 929                                mlx5_command_str(msg_to_opcode(ent->in)),
 930                                msg_to_opcode(ent->in));
 931         }
 932         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
 933                       err, deliv_status_to_str(ent->status), ent->status);
 934
 935         return err;
 936 }
 937
 938 /*  Notes:
 939  *    1. Callback functions may not sleep
 940  *    2. page queue commands do not support asynchrous completion
 941  */
 942 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 943                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
 944                            mlx5_cmd_cbk_t callback,
 945                            void *context, int page_queue, u8 *status,
 946                            u8 token, bool force_polling)
 947 {
 948         struct mlx5_cmd *cmd = &dev->cmd;
 949         struct mlx5_cmd_work_ent *ent;
 950         struct mlx5_cmd_stats *stats;
 951         int err = 0;
 952         s64 ds;
 953         u16 op;
 954
 955         if (callback && page_queue)
 956                 return -EINVAL;
 957
 958         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
 959                         page_queue);
 960         if (IS_ERR(ent))
 961                 return PTR_ERR(ent);
 962
 963         ent->token = token;
 964         ent->polling = force_polling;
 965
 966         if (!callback)
 967                 init_completion(&ent->done);
 968
 969         INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
 970         INIT_WORK(&ent->work, cmd_work_handler);
 971         if (page_queue) {
 972                 cmd_work_handler(&ent->work);
 973         } else if (!queue_work(cmd->wq, &ent->work)) {
 974                 mlx5_core_warn(dev, "failed to queue work\n");
 975                 err = -ENOMEM;
 976                 goto out_free;
 977         }
 978
 979         if (callback)
 980                 goto out;
 981
 982         err = wait_func(dev, ent);
 983         if (err == -ETIMEDOUT)
 984                 goto out;
 985
 986         ds = ent->ts2 - ent->ts1;
 987         op = MLX5_GET(mbox_in, in->first.data, opcode);
 988         if (op < ARRAY_SIZE(cmd->stats)) {
 989                 stats = &cmd->stats[op];
 990                 spin_lock_irq(&stats->lock);
 991                 stats->sum += ds;
 992                 ++stats->n;
 993                 spin_unlock_irq(&stats->lock);
 994         }
 995         mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
 996                            "fw exec time for %s is %lld nsec\n",
 997                            mlx5_command_str(op), ds);
 998         *status = ent->status;
 999
1000 out_free:
1001         free_cmd(ent);
1002 out:
1003         return err;
1004 }
1005
1006 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1007                          size_t count, loff_t *pos)
1008 {
1009         struct mlx5_core_dev *dev = filp->private_data;
1010         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1011         char lbuf[3];
1012         int err;
1013
1014         if (!dbg->in_msg || !dbg->out_msg)
1015                 return -ENOMEM;
1016
1017         if (copy_from_user(lbuf, buf, sizeof(lbuf)))
1018                 return -EFAULT;
1019
1020         lbuf[sizeof(lbuf) - 1] = 0;
1021
1022         if (strcmp(lbuf, "go"))
1023                 return -EINVAL;
1024
1025         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1026
1027         return err ? err : count;
1028 }
1029
1030 static const struct file_operations fops = {
1031         .owner  = THIS_MODULE,
1032         .open   = simple_open,
1033         .write  = dbg_write,
1034 };
1035
1036 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1037                             u8 token)
1038 {
1039         struct mlx5_cmd_prot_block *block;
1040         struct mlx5_cmd_mailbox *next;
1041         int copy;
1042
1043         if (!to || !from)
1044                 return -ENOMEM;
1045
1046         copy = min_t(int, size, sizeof(to->first.data));
1047         memcpy(to->first.data, from, copy);
1048         size -= copy;
1049         from += copy;
1050
1051         next = to->next;
1052         while (size) {
1053                 if (!next) {
1054                         /* this is a BUG */
1055                         return -ENOMEM;
1056                 }
1057
1058                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1059                 block = next->buf;
1060                 memcpy(block->data, from, copy);
1061                 from += copy;
1062                 size -= copy;
1063                 block->token = token;
1064                 next = next->next;
1065         }
1066
1067         return 0;
1068 }
1069
1070 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1071 {
1072         struct mlx5_cmd_prot_block *block;
1073         struct mlx5_cmd_mailbox *next;
1074         int copy;
1075
1076         if (!to || !from)
1077                 return -ENOMEM;
1078
1079         copy = min_t(int, size, sizeof(from->first.data));
1080         memcpy(to, from->first.data, copy);
1081         size -= copy;
1082         to += copy;
1083
1084         next = from->next;
1085         while (size) {
1086                 if (!next) {
1087                         /* this is a BUG */
1088                         return -ENOMEM;
1089                 }
1090
1091                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1092                 block = next->buf;
1093
1094                 memcpy(to, block->data, copy);
1095                 to += copy;
1096                 size -= copy;
1097                 next = next->next;
1098         }
1099
1100         return 0;
1101 }
1102
1103 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1104                                               gfp_t flags)
1105 {
1106         struct mlx5_cmd_mailbox *mailbox;
1107
1108         mailbox = kmalloc(sizeof(*mailbox), flags);
1109         if (!mailbox)
1110                 return ERR_PTR(-ENOMEM);
1111
1112         mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1113                                        &mailbox->dma);
1114         if (!mailbox->buf) {
1115                 mlx5_core_dbg(dev, "failed allocation\n");
1116                 kfree(mailbox);
1117                 return ERR_PTR(-ENOMEM);
1118         }
1119         mailbox->next = NULL;
1120
1121         return mailbox;
1122 }
1123
1124 static void free_cmd_box(struct mlx5_core_dev *dev,
1125                          struct mlx5_cmd_mailbox *mailbox)
1126 {
1127         dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1128         kfree(mailbox);
1129 }
1130
1131 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1132                                                gfp_t flags, int size,
1133                                                u8 token)
1134 {
1135         struct mlx5_cmd_mailbox *tmp, *head = NULL;
1136         struct mlx5_cmd_prot_block *block;
1137         struct mlx5_cmd_msg *msg;
1138         int blen;
1139         int err;
1140         int n;
1141         int i;
1142
1143         msg = kzalloc(sizeof(*msg), flags);
1144         if (!msg)
1145                 return ERR_PTR(-ENOMEM);
1146
1147         blen = size - min_t(int, sizeof(msg->first.data), size);
1148         n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
1149
1150         for (i = 0; i < n; i++) {
1151                 tmp = alloc_cmd_box(dev, flags);
1152                 if (IS_ERR(tmp)) {
1153                         mlx5_core_warn(dev, "failed allocating block\n");
1154                         err = PTR_ERR(tmp);
1155                         goto err_alloc;
1156                 }
1157
1158                 block = tmp->buf;
1159                 tmp->next = head;
1160                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1161                 block->block_num = cpu_to_be32(n - i - 1);
1162                 block->token = token;
1163                 head = tmp;
1164         }
1165         msg->next = head;
1166         msg->len = size;
1167         return msg;
1168
1169 err_alloc:
1170         while (head) {
1171                 tmp = head->next;
1172                 free_cmd_box(dev, head);
1173                 head = tmp;
1174         }
1175         kfree(msg);
1176
1177         return ERR_PTR(err);
1178 }
1179
1180 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1181                               struct mlx5_cmd_msg *msg)
1182 {
1183         struct mlx5_cmd_mailbox *head = msg->next;
1184         struct mlx5_cmd_mailbox *next;
1185
1186         while (head) {
1187                 next = head->next;
1188                 free_cmd_box(dev, head);
1189                 head = next;
1190         }
1191         kfree(msg);
1192 }
1193
1194 static ssize_t data_write(struct file *filp, const char __user *buf,
1195                           size_t count, loff_t *pos)
1196 {
1197         struct mlx5_core_dev *dev = filp->private_data;
1198         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1199         void *ptr;
1200
1201         if (*pos != 0)
1202                 return -EINVAL;
1203
1204         kfree(dbg->in_msg);
1205         dbg->in_msg = NULL;
1206         dbg->inlen = 0;
1207         ptr = memdup_user(buf, count);
1208         if (IS_ERR(ptr))
1209                 return PTR_ERR(ptr);
1210         dbg->in_msg = ptr;
1211         dbg->inlen = count;
1212
1213         *pos = count;
1214
1215         return count;
1216 }
1217
1218 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1219                          loff_t *pos)
1220 {
1221         struct mlx5_core_dev *dev = filp->private_data;
1222         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1223         int copy;
1224
1225         if (*pos)
1226                 return 0;
1227
1228         if (!dbg->out_msg)
1229                 return -ENOMEM;
1230
1231         copy = min_t(int, count, dbg->outlen);
1232         if (copy_to_user(buf, dbg->out_msg, copy))
1233                 return -EFAULT;
1234
1235         *pos += copy;
1236
1237         return copy;
1238 }
1239
1240 static const struct file_operations dfops = {
1241         .owner  = THIS_MODULE,
1242         .open   = simple_open,
1243         .write  = data_write,
1244         .read   = data_read,
1245 };
1246
1247 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1248                            loff_t *pos)
1249 {
1250         struct mlx5_core_dev *dev = filp->private_data;
1251         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1252         char outlen[8];
1253         int err;
1254
1255         if (*pos)
1256                 return 0;
1257
1258         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1259         if (err < 0)
1260                 return err;
1261
1262         if (copy_to_user(buf, &outlen, err))
1263                 return -EFAULT;
1264
1265         *pos += err;
1266
1267         return err;
1268 }
1269
1270 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1271                             size_t count, loff_t *pos)
1272 {
1273         struct mlx5_core_dev *dev = filp->private_data;
1274         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1275         char outlen_str[8];
1276         int outlen;
1277         void *ptr;
1278         int err;
1279
1280         if (*pos != 0 || count > 6)
1281                 return -EINVAL;
1282
1283         kfree(dbg->out_msg);
1284         dbg->out_msg = NULL;
1285         dbg->outlen = 0;
1286
1287         if (copy_from_user(outlen_str, buf, count))
1288                 return -EFAULT;
1289
1290         outlen_str[7] = 0;
1291
1292         err = sscanf(outlen_str, "%d", &outlen);
1293         if (err < 0)
1294                 return err;
1295
1296         ptr = kzalloc(outlen, GFP_KERNEL);
1297         if (!ptr)
1298                 return -ENOMEM;
1299
1300         dbg->out_msg = ptr;
1301         dbg->outlen = outlen;
1302
1303         *pos = count;
1304
1305         return count;
1306 }
1307
1308 static const struct file_operations olfops = {
1309         .owner  = THIS_MODULE,
1310         .open   = simple_open,
1311         .write  = outlen_write,
1312         .read   = outlen_read,
1313 };
1314
1315 static void set_wqname(struct mlx5_core_dev *dev)
1316 {
1317         struct mlx5_cmd *cmd = &dev->cmd;
1318
1319         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1320                  dev_name(&dev->pdev->dev));
1321 }
1322
1323 static void clean_debug_files(struct mlx5_core_dev *dev)
1324 {
1325         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1326
1327         if (!mlx5_debugfs_root)
1328                 return;
1329
1330         mlx5_cmdif_debugfs_cleanup(dev);
1331         debugfs_remove_recursive(dbg->dbg_root);
1332 }
1333
1334 static int create_debugfs_files(struct mlx5_core_dev *dev)
1335 {
1336         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1337         int err = -ENOMEM;
1338
1339         if (!mlx5_debugfs_root)
1340                 return 0;
1341
1342         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1343         if (!dbg->dbg_root)
1344                 return err;
1345
1346         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1347                                           dev, &dfops);
1348         if (!dbg->dbg_in)
1349                 goto err_dbg;
1350
1351         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1352                                            dev, &dfops);
1353         if (!dbg->dbg_out)
1354                 goto err_dbg;
1355
1356         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1357                                               dev, &olfops);
1358         if (!dbg->dbg_outlen)
1359                 goto err_dbg;
1360
1361         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1362                                             &dbg->status);
1363         if (!dbg->dbg_status)
1364                 goto err_dbg;
1365
1366         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1367         if (!dbg->dbg_run)
1368                 goto err_dbg;
1369
1370         mlx5_cmdif_debugfs_init(dev);
1371
1372         return 0;
1373
1374 err_dbg:
1375         clean_debug_files(dev);
1376         return err;
1377 }
1378
1379 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1380 {
1381         struct mlx5_cmd *cmd = &dev->cmd;
1382         int i;
1383
1384         for (i = 0; i < cmd->max_reg_cmds; i++)
1385                 down(&cmd->sem);
1386         down(&cmd->pages_sem);
1387
1388         cmd->mode = mode;
1389
1390         up(&cmd->pages_sem);
1391         for (i = 0; i < cmd->max_reg_cmds; i++)
1392                 up(&cmd->sem);
1393 }
1394
1395 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1396 {
1397         mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1398 }
1399
1400 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1401 {
1402         mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1403 }
1404
1405 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1406 {
1407         unsigned long flags;
1408
1409         if (msg->parent) {
1410                 spin_lock_irqsave(&msg->parent->lock, flags);
1411                 list_add_tail(&msg->list, &msg->parent->head);
1412                 spin_unlock_irqrestore(&msg->parent->lock, flags);
1413         } else {
1414                 mlx5_free_cmd_msg(dev, msg);
1415         }
1416 }
1417
1418 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1419 {
1420         struct mlx5_cmd *cmd = &dev->cmd;
1421         struct mlx5_cmd_work_ent *ent;
1422         mlx5_cmd_cbk_t callback;
1423         void *context;
1424         int err;
1425         int i;
1426         s64 ds;
1427         struct mlx5_cmd_stats *stats;
1428         unsigned long flags;
1429         unsigned long vector;
1430
1431         /* there can be at most 32 command queues */
1432         vector = vec & 0xffffffff;
1433         for (i = 0; i < (1 << cmd->log_sz); i++) {
1434                 if (test_bit(i, &vector)) {
1435                         struct semaphore *sem;
1436
1437                         ent = cmd->ent_arr[i];
1438
1439                         /* if we already completed the command, ignore it */
1440                         if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1441                                                 &ent->state)) {
1442                                 /* only real completion can free the cmd slot */
1443                                 if (!forced) {
1444                                         mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1445                                                       ent->idx);
1446                                         free_ent(cmd, ent->idx);
1447                                         free_cmd(ent);
1448                                 }
1449                                 continue;
1450                         }
1451
1452                         if (ent->callback)
1453                                 cancel_delayed_work(&ent->cb_timeout_work);
1454                         if (ent->page_queue)
1455                                 sem = &cmd->pages_sem;
1456                         else
1457                                 sem = &cmd->sem;
1458                         ent->ts2 = ktime_get_ns();
1459                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1460                         dump_command(dev, ent, 0);
1461                         if (!ent->ret) {
1462                                 if (!cmd->checksum_disabled)
1463                                         ent->ret = verify_signature(ent);
1464                                 else
1465                                         ent->ret = 0;
1466                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1467                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1468                                 else
1469                                         ent->status = ent->lay->status_own >> 1;
1470
1471                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1472                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1473                         }
1474
1475                         /* only real completion will free the entry slot */
1476                         if (!forced)
1477                                 free_ent(cmd, ent->idx);
1478
1479                         if (ent->callback) {
1480                                 ds = ent->ts2 - ent->ts1;
1481                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1482                                         stats = &cmd->stats[ent->op];
1483                                         spin_lock_irqsave(&stats->lock, flags);
1484                                         stats->sum += ds;
1485                                         ++stats->n;
1486                                         spin_unlock_irqrestore(&stats->lock, flags);
1487                                 }
1488
1489                                 callback = ent->callback;
1490                                 context = ent->context;
1491                                 err = ent->ret;
1492                                 if (!err) {
1493                                         err = mlx5_copy_from_msg(ent->uout,
1494                                                                  ent->out,
1495                                                                  ent->uout_size);
1496
1497                                         err = err ? err : mlx5_cmd_check(dev,
1498                                                                         ent->in->first.data,
1499                                                                         ent->uout);
1500                                 }
1501
1502                                 mlx5_free_cmd_msg(dev, ent->out);
1503                                 free_msg(dev, ent->in);
1504
1505                                 err = err ? err : ent->status;
1506                                 if (!forced)
1507                                         free_cmd(ent);
1508                                 callback(err, context);
1509                         } else {
1510                                 complete(&ent->done);
1511                         }
1512                         up(sem);
1513                 }
1514         }
1515 }
1516 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1517
1518 static int status_to_err(u8 status)
1519 {
1520         return status ? -1 : 0; /* TBD more meaningful codes */
1521 }
1522
1523 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1524                                       gfp_t gfp)
1525 {
1526         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1527         struct cmd_msg_cache *ch = NULL;
1528         struct mlx5_cmd *cmd = &dev->cmd;
1529         int i;
1530
1531         if (in_size <= 16)
1532                 goto cache_miss;
1533
1534         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1535                 ch = &cmd->cache[i];
1536                 if (in_size > ch->max_inbox_size)
1537                         continue;
1538                 spin_lock_irq(&ch->lock);
1539                 if (list_empty(&ch->head)) {
1540                         spin_unlock_irq(&ch->lock);
1541                         continue;
1542                 }
1543                 msg = list_entry(ch->head.next, typeof(*msg), list);
1544                 /* For cached lists, we must explicitly state what is
1545                  * the real size
1546                  */
1547                 msg->len = in_size;
1548                 list_del(&msg->list);
1549                 spin_unlock_irq(&ch->lock);
1550                 break;
1551         }
1552
1553         if (!IS_ERR(msg))
1554                 return msg;
1555
1556 cache_miss:
1557         msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1558         return msg;
1559 }
1560
1561 static int is_manage_pages(void *in)
1562 {
1563         return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1564 }
1565
1566 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1567                     int out_size, mlx5_cmd_cbk_t callback, void *context,
1568                     bool force_polling)
1569 {
1570         struct mlx5_cmd_msg *inb;
1571         struct mlx5_cmd_msg *outb;
1572         int pages_queue;
1573         gfp_t gfp;
1574         int err;
1575         u8 status = 0;
1576         u32 drv_synd;
1577         u8 token;
1578
1579         if (pci_channel_offline(dev->pdev) ||
1580             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1581                 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1582
1583                 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1584                 MLX5_SET(mbox_out, out, status, status);
1585                 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1586                 return err;
1587         }
1588
1589         pages_queue = is_manage_pages(in);
1590         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1591
1592         inb = alloc_msg(dev, in_size, gfp);
1593         if (IS_ERR(inb)) {
1594                 err = PTR_ERR(inb);
1595                 return err;
1596         }
1597
1598         token = alloc_token(&dev->cmd);
1599
1600         err = mlx5_copy_to_msg(inb, in, in_size, token);
1601         if (err) {
1602                 mlx5_core_warn(dev, "err %d\n", err);
1603                 goto out_in;
1604         }
1605
1606         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1607         if (IS_ERR(outb)) {
1608                 err = PTR_ERR(outb);
1609                 goto out_in;
1610         }
1611
1612         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1613                               pages_queue, &status, token, force_polling);
1614         if (err)
1615                 goto out_out;
1616
1617         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1618         if (status) {
1619                 err = status_to_err(status);
1620                 goto out_out;
1621         }
1622
1623         if (!callback)
1624                 err = mlx5_copy_from_msg(out, outb, out_size);
1625
1626 out_out:
1627         if (!callback)
1628                 mlx5_free_cmd_msg(dev, outb);
1629
1630 out_in:
1631         if (!callback)
1632                 free_msg(dev, inb);
1633         return err;
1634 }
1635
1636 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1637                   int out_size)
1638 {
1639         int err;
1640
1641         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1642         return err ? : mlx5_cmd_check(dev, in, out);
1643 }
1644 EXPORT_SYMBOL(mlx5_cmd_exec);
1645
1646 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1647                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1648                      void *context)
1649 {
1650         return cmd_exec(dev, in, in_size, out, out_size, callback, context,
1651                         false);
1652 }
1653 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1654
1655 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1656                           void *out, int out_size)
1657 {
1658         int err;
1659
1660         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1661
1662         return err ? : mlx5_cmd_check(dev, in, out);
1663 }
1664 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1665
1666 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1667 {
1668         struct cmd_msg_cache *ch;
1669         struct mlx5_cmd_msg *msg;
1670         struct mlx5_cmd_msg *n;
1671         int i;
1672
1673         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1674                 ch = &dev->cmd.cache[i];
1675                 list_for_each_entry_safe(msg, n, &ch->head, list) {
1676                         list_del(&msg->list);
1677                         mlx5_free_cmd_msg(dev, msg);
1678                 }
1679         }
1680 }
1681
1682 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1683         512, 32, 16, 8, 2
1684 };
1685
1686 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1687         16 + MLX5_CMD_DATA_BLOCK_SIZE,
1688         16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1689         16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1690         16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1691         16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1692 };
1693
1694 static void create_msg_cache(struct mlx5_core_dev *dev)
1695 {
1696         struct mlx5_cmd *cmd = &dev->cmd;
1697         struct cmd_msg_cache *ch;
1698         struct mlx5_cmd_msg *msg;
1699         int i;
1700         int k;
1701
1702         /* Initialize and fill the caches with initial entries */
1703         for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1704                 ch = &cmd->cache[k];
1705                 spin_lock_init(&ch->lock);
1706                 INIT_LIST_HEAD(&ch->head);
1707                 ch->num_ent = cmd_cache_num_ent[k];
1708                 ch->max_inbox_size = cmd_cache_ent_size[k];
1709                 for (i = 0; i < ch->num_ent; i++) {
1710                         msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1711                                                  ch->max_inbox_size, 0);
1712                         if (IS_ERR(msg))
1713                                 break;
1714                         msg->parent = ch;
1715                         list_add_tail(&msg->list, &ch->head);
1716                 }
1717         }
1718 }
1719
1720 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1721 {
1722         struct device *ddev = &dev->pdev->dev;
1723
1724         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1725                                                  &cmd->alloc_dma, GFP_KERNEL);
1726         if (!cmd->cmd_alloc_buf)
1727                 return -ENOMEM;
1728
1729         /* make sure it is aligned to 4K */
1730         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1731                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1732                 cmd->dma = cmd->alloc_dma;
1733                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1734                 return 0;
1735         }
1736
1737         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1738                           cmd->alloc_dma);
1739         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1740                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1741                                                  &cmd->alloc_dma, GFP_KERNEL);
1742         if (!cmd->cmd_alloc_buf)
1743                 return -ENOMEM;
1744
1745         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1746         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1747         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1748         return 0;
1749 }
1750
1751 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1752 {
1753         struct device *ddev = &dev->pdev->dev;
1754
1755         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1756                           cmd->alloc_dma);
1757 }
1758
1759 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1760 {
1761         int size = sizeof(struct mlx5_cmd_prot_block);
1762         int align = roundup_pow_of_two(size);
1763         struct mlx5_cmd *cmd = &dev->cmd;
1764         u32 cmd_h, cmd_l;
1765         u16 cmd_if_rev;
1766         int err;
1767         int i;
1768
1769         memset(cmd, 0, sizeof(*cmd));
1770         cmd_if_rev = cmdif_rev(dev);
1771         if (cmd_if_rev != CMD_IF_REV) {
1772                 dev_err(&dev->pdev->dev,
1773                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1774                         CMD_IF_REV, cmd_if_rev);
1775                 return -EINVAL;
1776         }
1777
1778         cmd->pool = dma_pool_create("mlx5_cmd", &dev->pdev->dev, size, align,
1779                                     0);
1780         if (!cmd->pool)
1781                 return -ENOMEM;
1782
1783         err = alloc_cmd_page(dev, cmd);
1784         if (err)
1785                 goto err_free_pool;
1786
1787         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1788         cmd->log_sz = cmd_l >> 4 & 0xf;
1789         cmd->log_stride = cmd_l & 0xf;
1790         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1791                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1792                         1 << cmd->log_sz);
1793                 err = -EINVAL;
1794                 goto err_free_page;
1795         }
1796
1797         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1798                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1799                 err = -EINVAL;
1800                 goto err_free_page;
1801         }
1802
1803         cmd->checksum_disabled = 1;
1804         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1805         cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1806
1807         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1808         if (cmd->cmdif_rev > CMD_IF_REV) {
1809                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1810                         CMD_IF_REV, cmd->cmdif_rev);
1811                 err = -EOPNOTSUPP;
1812                 goto err_free_page;
1813         }
1814
1815         spin_lock_init(&cmd->alloc_lock);
1816         spin_lock_init(&cmd->token_lock);
1817         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1818                 spin_lock_init(&cmd->stats[i].lock);
1819
1820         sema_init(&cmd->sem, cmd->max_reg_cmds);
1821         sema_init(&cmd->pages_sem, 1);
1822
1823         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1824         cmd_l = (u32)(cmd->dma);
1825         if (cmd_l & 0xfff) {
1826                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1827                 err = -ENOMEM;
1828                 goto err_free_page;
1829         }
1830
1831         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1832         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1833
1834         /* Make sure firmware sees the complete address before we proceed */
1835         wmb();
1836
1837         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1838
1839         cmd->mode = CMD_MODE_POLLING;
1840
1841         create_msg_cache(dev);
1842
1843         set_wqname(dev);
1844         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1845         if (!cmd->wq) {
1846                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1847                 err = -ENOMEM;
1848                 goto err_cache;
1849         }
1850
1851         err = create_debugfs_files(dev);
1852         if (err) {
1853                 err = -ENOMEM;
1854                 goto err_wq;
1855         }
1856
1857         return 0;
1858
1859 err_wq:
1860         destroy_workqueue(cmd->wq);
1861
1862 err_cache:
1863         destroy_msg_cache(dev);
1864
1865 err_free_page:
1866         free_cmd_page(dev, cmd);
1867
1868 err_free_pool:
1869         dma_pool_destroy(cmd->pool);
1870
1871         return err;
1872 }
1873 EXPORT_SYMBOL(mlx5_cmd_init);
1874
1875 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1876 {
1877         struct mlx5_cmd *cmd = &dev->cmd;
1878
1879         clean_debug_files(dev);
1880         destroy_workqueue(cmd->wq);
1881         destroy_msg_cache(dev);
1882         free_cmd_page(dev, cmd);
1883         dma_pool_destroy(cmd->pool);
1884 }
1885 EXPORT_SYMBOL(mlx5_cmd_cleanup);