a94955302482d4349ff27ad00993a2b66af4e09d
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / cmd.c
1 /*
2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/debugfs.h>
44
45 #include "mlx5_core.h"
46
47 enum {
48         CMD_IF_REV = 5,
49 };
50
51 enum {
52         CMD_MODE_POLLING,
53         CMD_MODE_EVENTS
54 };
55
56 enum {
57         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
58         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
59         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
60         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
61         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
62         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
63         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
64         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
65         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
66         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
67         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
68 };
69
70 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
71                                            struct mlx5_cmd_msg *in,
72                                            struct mlx5_cmd_msg *out,
73                                            void *uout, int uout_size,
74                                            mlx5_cmd_cbk_t cbk,
75                                            void *context, int page_queue)
76 {
77         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
78         struct mlx5_cmd_work_ent *ent;
79
80         ent = kzalloc(sizeof(*ent), alloc_flags);
81         if (!ent)
82                 return ERR_PTR(-ENOMEM);
83
84         ent->in         = in;
85         ent->out        = out;
86         ent->uout       = uout;
87         ent->uout_size  = uout_size;
88         ent->callback   = cbk;
89         ent->context    = context;
90         ent->cmd        = cmd;
91         ent->page_queue = page_queue;
92
93         return ent;
94 }
95
96 static u8 alloc_token(struct mlx5_cmd *cmd)
97 {
98         u8 token;
99
100         spin_lock(&cmd->token_lock);
101         cmd->token++;
102         if (cmd->token == 0)
103                 cmd->token++;
104         token = cmd->token;
105         spin_unlock(&cmd->token_lock);
106
107         return token;
108 }
109
110 static int alloc_ent(struct mlx5_cmd *cmd)
111 {
112         unsigned long flags;
113         int ret;
114
115         spin_lock_irqsave(&cmd->alloc_lock, flags);
116         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
117         if (ret < cmd->max_reg_cmds)
118                 clear_bit(ret, &cmd->bitmask);
119         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
120
121         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
122 }
123
124 static void free_ent(struct mlx5_cmd *cmd, int idx)
125 {
126         unsigned long flags;
127
128         spin_lock_irqsave(&cmd->alloc_lock, flags);
129         set_bit(idx, &cmd->bitmask);
130         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
131 }
132
133 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
134 {
135         return cmd->cmd_buf + (idx << cmd->log_stride);
136 }
137
138 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
139 {
140         int size = msg->len;
141         int blen = size - min_t(int, sizeof(msg->first.data), size);
142
143         return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
144 }
145
146 static u8 xor8_buf(void *buf, size_t offset, int len)
147 {
148         u8 *ptr = buf;
149         u8 sum = 0;
150         int i;
151         int end = len + offset;
152
153         for (i = offset; i < end; i++)
154                 sum ^= ptr[i];
155
156         return sum;
157 }
158
159 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
160 {
161         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
162         int xor_len = sizeof(*block) - sizeof(block->data) - 1;
163
164         if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
165                 return -EINVAL;
166
167         if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
168                 return -EINVAL;
169
170         return 0;
171 }
172
173 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
174 {
175         int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
176         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
177
178         block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
179         block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
180 }
181
182 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
183 {
184         struct mlx5_cmd_mailbox *next = msg->next;
185         int n = mlx5_calc_cmd_blocks(msg);
186         int i = 0;
187
188         for (i = 0; i < n && next; i++)  {
189                 calc_block_sig(next->buf);
190                 next = next->next;
191         }
192 }
193
194 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
195 {
196         ent->lay->sig = ~xor8_buf(ent->lay, 0,  sizeof(*ent->lay));
197         if (csum) {
198                 calc_chain_sig(ent->in);
199                 calc_chain_sig(ent->out);
200         }
201 }
202
203 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
204 {
205         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
206         u8 own;
207
208         do {
209                 own = ent->lay->status_own;
210                 if (!(own & CMD_OWNER_HW)) {
211                         ent->ret = 0;
212                         return;
213                 }
214                 usleep_range(5000, 10000);
215         } while (time_before(jiffies, poll_end));
216
217         ent->ret = -ETIMEDOUT;
218 }
219
220 static void free_cmd(struct mlx5_cmd_work_ent *ent)
221 {
222         kfree(ent);
223 }
224
225 static int verify_signature(struct mlx5_cmd_work_ent *ent)
226 {
227         struct mlx5_cmd_mailbox *next = ent->out->next;
228         int n = mlx5_calc_cmd_blocks(ent->out);
229         int err;
230         u8 sig;
231         int i = 0;
232
233         sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
234         if (sig != 0xff)
235                 return -EINVAL;
236
237         for (i = 0; i < n && next; i++) {
238                 err = verify_block_sig(next->buf);
239                 if (err)
240                         return err;
241
242                 next = next->next;
243         }
244
245         return 0;
246 }
247
248 static void dump_buf(void *buf, int size, int data_only, int offset)
249 {
250         __be32 *p = buf;
251         int i;
252
253         for (i = 0; i < size; i += 16) {
254                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
255                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
256                          be32_to_cpu(p[3]));
257                 p += 4;
258                 offset += 16;
259         }
260         if (!data_only)
261                 pr_debug("\n");
262 }
263
264 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
265                                        u32 *synd, u8 *status)
266 {
267         *synd = 0;
268         *status = 0;
269
270         switch (op) {
271         case MLX5_CMD_OP_TEARDOWN_HCA:
272         case MLX5_CMD_OP_DISABLE_HCA:
273         case MLX5_CMD_OP_MANAGE_PAGES:
274         case MLX5_CMD_OP_DESTROY_MKEY:
275         case MLX5_CMD_OP_DESTROY_EQ:
276         case MLX5_CMD_OP_DESTROY_CQ:
277         case MLX5_CMD_OP_DESTROY_QP:
278         case MLX5_CMD_OP_DESTROY_PSV:
279         case MLX5_CMD_OP_DESTROY_SRQ:
280         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
281         case MLX5_CMD_OP_DESTROY_DCT:
282         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
283         case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
284         case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
285         case MLX5_CMD_OP_DEALLOC_PD:
286         case MLX5_CMD_OP_DEALLOC_UAR:
287         case MLX5_CMD_OP_DETACH_FROM_MCG:
288         case MLX5_CMD_OP_DEALLOC_XRCD:
289         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
290         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
291         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
292         case MLX5_CMD_OP_DESTROY_LAG:
293         case MLX5_CMD_OP_DESTROY_VPORT_LAG:
294         case MLX5_CMD_OP_DESTROY_TIR:
295         case MLX5_CMD_OP_DESTROY_SQ:
296         case MLX5_CMD_OP_DESTROY_RQ:
297         case MLX5_CMD_OP_DESTROY_RMP:
298         case MLX5_CMD_OP_DESTROY_TIS:
299         case MLX5_CMD_OP_DESTROY_RQT:
300         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
301         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
302         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
303         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
304         case MLX5_CMD_OP_2ERR_QP:
305         case MLX5_CMD_OP_2RST_QP:
306         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
307         case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
308         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
309         case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
310         case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
311         case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
312         case MLX5_CMD_OP_FPGA_DESTROY_QP:
313         case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
314                 return MLX5_CMD_STAT_OK;
315
316         case MLX5_CMD_OP_QUERY_HCA_CAP:
317         case MLX5_CMD_OP_QUERY_ADAPTER:
318         case MLX5_CMD_OP_INIT_HCA:
319         case MLX5_CMD_OP_ENABLE_HCA:
320         case MLX5_CMD_OP_QUERY_PAGES:
321         case MLX5_CMD_OP_SET_HCA_CAP:
322         case MLX5_CMD_OP_QUERY_ISSI:
323         case MLX5_CMD_OP_SET_ISSI:
324         case MLX5_CMD_OP_CREATE_MKEY:
325         case MLX5_CMD_OP_QUERY_MKEY:
326         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
327         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
328         case MLX5_CMD_OP_CREATE_EQ:
329         case MLX5_CMD_OP_QUERY_EQ:
330         case MLX5_CMD_OP_GEN_EQE:
331         case MLX5_CMD_OP_CREATE_CQ:
332         case MLX5_CMD_OP_QUERY_CQ:
333         case MLX5_CMD_OP_MODIFY_CQ:
334         case MLX5_CMD_OP_CREATE_QP:
335         case MLX5_CMD_OP_RST2INIT_QP:
336         case MLX5_CMD_OP_INIT2RTR_QP:
337         case MLX5_CMD_OP_RTR2RTS_QP:
338         case MLX5_CMD_OP_RTS2RTS_QP:
339         case MLX5_CMD_OP_SQERR2RTS_QP:
340         case MLX5_CMD_OP_QUERY_QP:
341         case MLX5_CMD_OP_SQD_RTS_QP:
342         case MLX5_CMD_OP_INIT2INIT_QP:
343         case MLX5_CMD_OP_CREATE_PSV:
344         case MLX5_CMD_OP_CREATE_SRQ:
345         case MLX5_CMD_OP_QUERY_SRQ:
346         case MLX5_CMD_OP_ARM_RQ:
347         case MLX5_CMD_OP_CREATE_XRC_SRQ:
348         case MLX5_CMD_OP_QUERY_XRC_SRQ:
349         case MLX5_CMD_OP_ARM_XRC_SRQ:
350         case MLX5_CMD_OP_CREATE_DCT:
351         case MLX5_CMD_OP_DRAIN_DCT:
352         case MLX5_CMD_OP_QUERY_DCT:
353         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
354         case MLX5_CMD_OP_QUERY_VPORT_STATE:
355         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
356         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
357         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
358         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
359         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
360         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
361         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
362         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
363         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
364         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
365         case MLX5_CMD_OP_QUERY_VNIC_ENV:
366         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
367         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
368         case MLX5_CMD_OP_QUERY_Q_COUNTER:
369         case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
370         case MLX5_CMD_OP_QUERY_RATE_LIMIT:
371         case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
372         case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
373         case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
374         case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
375         case MLX5_CMD_OP_ALLOC_PD:
376         case MLX5_CMD_OP_ALLOC_UAR:
377         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
378         case MLX5_CMD_OP_ACCESS_REG:
379         case MLX5_CMD_OP_ATTACH_TO_MCG:
380         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
381         case MLX5_CMD_OP_MAD_IFC:
382         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
383         case MLX5_CMD_OP_SET_MAD_DEMUX:
384         case MLX5_CMD_OP_NOP:
385         case MLX5_CMD_OP_ALLOC_XRCD:
386         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
387         case MLX5_CMD_OP_QUERY_CONG_STATUS:
388         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
389         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
390         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
391         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
392         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
393         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
394         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
395         case MLX5_CMD_OP_CREATE_LAG:
396         case MLX5_CMD_OP_MODIFY_LAG:
397         case MLX5_CMD_OP_QUERY_LAG:
398         case MLX5_CMD_OP_CREATE_VPORT_LAG:
399         case MLX5_CMD_OP_CREATE_TIR:
400         case MLX5_CMD_OP_MODIFY_TIR:
401         case MLX5_CMD_OP_QUERY_TIR:
402         case MLX5_CMD_OP_CREATE_SQ:
403         case MLX5_CMD_OP_MODIFY_SQ:
404         case MLX5_CMD_OP_QUERY_SQ:
405         case MLX5_CMD_OP_CREATE_RQ:
406         case MLX5_CMD_OP_MODIFY_RQ:
407         case MLX5_CMD_OP_QUERY_RQ:
408         case MLX5_CMD_OP_CREATE_RMP:
409         case MLX5_CMD_OP_MODIFY_RMP:
410         case MLX5_CMD_OP_QUERY_RMP:
411         case MLX5_CMD_OP_CREATE_TIS:
412         case MLX5_CMD_OP_MODIFY_TIS:
413         case MLX5_CMD_OP_QUERY_TIS:
414         case MLX5_CMD_OP_CREATE_RQT:
415         case MLX5_CMD_OP_MODIFY_RQT:
416         case MLX5_CMD_OP_QUERY_RQT:
417
418         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
419         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
420         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
421         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
422         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
423         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
424         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
425         case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
426         case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
427         case MLX5_CMD_OP_FPGA_CREATE_QP:
428         case MLX5_CMD_OP_FPGA_MODIFY_QP:
429         case MLX5_CMD_OP_FPGA_QUERY_QP:
430         case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
431         case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
432                 *status = MLX5_DRIVER_STATUS_ABORTED;
433                 *synd = MLX5_DRIVER_SYND;
434                 return -EIO;
435         default:
436                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
437                 return -EINVAL;
438         }
439 }
440
441 const char *mlx5_command_str(int command)
442 {
443 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
444
445         switch (command) {
446         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
447         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
448         MLX5_COMMAND_STR_CASE(INIT_HCA);
449         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
450         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
451         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
452         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
453         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
454         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
455         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
456         MLX5_COMMAND_STR_CASE(SET_ISSI);
457         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
458         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
459         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
460         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
461         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
462         MLX5_COMMAND_STR_CASE(CREATE_EQ);
463         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
464         MLX5_COMMAND_STR_CASE(QUERY_EQ);
465         MLX5_COMMAND_STR_CASE(GEN_EQE);
466         MLX5_COMMAND_STR_CASE(CREATE_CQ);
467         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
468         MLX5_COMMAND_STR_CASE(QUERY_CQ);
469         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
470         MLX5_COMMAND_STR_CASE(CREATE_QP);
471         MLX5_COMMAND_STR_CASE(DESTROY_QP);
472         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
473         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
474         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
475         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
476         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
477         MLX5_COMMAND_STR_CASE(2ERR_QP);
478         MLX5_COMMAND_STR_CASE(2RST_QP);
479         MLX5_COMMAND_STR_CASE(QUERY_QP);
480         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
481         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
482         MLX5_COMMAND_STR_CASE(CREATE_PSV);
483         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
484         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
485         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
486         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
487         MLX5_COMMAND_STR_CASE(ARM_RQ);
488         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
489         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
490         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
491         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
492         MLX5_COMMAND_STR_CASE(CREATE_DCT);
493         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
494         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
495         MLX5_COMMAND_STR_CASE(QUERY_DCT);
496         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
497         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
498         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
499         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
500         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
501         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
502         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
503         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
504         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
505         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
506         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
507         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
508         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
509         MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
510         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
511         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
512         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
513         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
514         MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
515         MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
516         MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
517         MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
518         MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
519         MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
520         MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
521         MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
522         MLX5_COMMAND_STR_CASE(ALLOC_PD);
523         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
524         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
525         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
526         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
527         MLX5_COMMAND_STR_CASE(ACCESS_REG);
528         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
529         MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
530         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
531         MLX5_COMMAND_STR_CASE(MAD_IFC);
532         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
533         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
534         MLX5_COMMAND_STR_CASE(NOP);
535         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
536         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
537         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
538         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
539         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
540         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
541         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
542         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
543         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
544         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
545         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
546         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
547         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
548         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
549         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
550         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
551         MLX5_COMMAND_STR_CASE(CREATE_LAG);
552         MLX5_COMMAND_STR_CASE(MODIFY_LAG);
553         MLX5_COMMAND_STR_CASE(QUERY_LAG);
554         MLX5_COMMAND_STR_CASE(DESTROY_LAG);
555         MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
556         MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
557         MLX5_COMMAND_STR_CASE(CREATE_TIR);
558         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
559         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
560         MLX5_COMMAND_STR_CASE(QUERY_TIR);
561         MLX5_COMMAND_STR_CASE(CREATE_SQ);
562         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
563         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
564         MLX5_COMMAND_STR_CASE(QUERY_SQ);
565         MLX5_COMMAND_STR_CASE(CREATE_RQ);
566         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
567         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
568         MLX5_COMMAND_STR_CASE(QUERY_RQ);
569         MLX5_COMMAND_STR_CASE(CREATE_RMP);
570         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
571         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
572         MLX5_COMMAND_STR_CASE(QUERY_RMP);
573         MLX5_COMMAND_STR_CASE(CREATE_TIS);
574         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
575         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
576         MLX5_COMMAND_STR_CASE(QUERY_TIS);
577         MLX5_COMMAND_STR_CASE(CREATE_RQT);
578         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
579         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
580         MLX5_COMMAND_STR_CASE(QUERY_RQT);
581         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
582         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
583         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
584         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
585         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
586         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
587         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
588         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
589         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
590         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
591         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
592         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
593         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
594         MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
595         MLX5_COMMAND_STR_CASE(ALLOC_ENCAP_HEADER);
596         MLX5_COMMAND_STR_CASE(DEALLOC_ENCAP_HEADER);
597         MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
598         MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
599         MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
600         MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
601         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
602         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
603         MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
604         MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
605         MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
606         default: return "unknown command opcode";
607         }
608 }
609
610 static const char *cmd_status_str(u8 status)
611 {
612         switch (status) {
613         case MLX5_CMD_STAT_OK:
614                 return "OK";
615         case MLX5_CMD_STAT_INT_ERR:
616                 return "internal error";
617         case MLX5_CMD_STAT_BAD_OP_ERR:
618                 return "bad operation";
619         case MLX5_CMD_STAT_BAD_PARAM_ERR:
620                 return "bad parameter";
621         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
622                 return "bad system state";
623         case MLX5_CMD_STAT_BAD_RES_ERR:
624                 return "bad resource";
625         case MLX5_CMD_STAT_RES_BUSY:
626                 return "resource busy";
627         case MLX5_CMD_STAT_LIM_ERR:
628                 return "limits exceeded";
629         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
630                 return "bad resource state";
631         case MLX5_CMD_STAT_IX_ERR:
632                 return "bad index";
633         case MLX5_CMD_STAT_NO_RES_ERR:
634                 return "no resources";
635         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
636                 return "bad input length";
637         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
638                 return "bad output length";
639         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
640                 return "bad QP state";
641         case MLX5_CMD_STAT_BAD_PKT_ERR:
642                 return "bad packet (discarded)";
643         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
644                 return "bad size too many outstanding CQEs";
645         default:
646                 return "unknown status";
647         }
648 }
649
650 static int cmd_status_to_err(u8 status)
651 {
652         switch (status) {
653         case MLX5_CMD_STAT_OK:                          return 0;
654         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
655         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
656         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
657         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
658         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
659         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
660         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
661         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
662         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
663         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
664         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
665         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
666         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
667         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
668         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
669         default:                                        return -EIO;
670         }
671 }
672
673 struct mlx5_ifc_mbox_out_bits {
674         u8         status[0x8];
675         u8         reserved_at_8[0x18];
676
677         u8         syndrome[0x20];
678
679         u8         reserved_at_40[0x40];
680 };
681
682 struct mlx5_ifc_mbox_in_bits {
683         u8         opcode[0x10];
684         u8         uid[0x10];
685
686         u8         reserved_at_20[0x10];
687         u8         op_mod[0x10];
688
689         u8         reserved_at_40[0x40];
690 };
691
692 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
693 {
694         *status = MLX5_GET(mbox_out, out, status);
695         *syndrome = MLX5_GET(mbox_out, out, syndrome);
696 }
697
698 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
699 {
700         u32 syndrome;
701         u8  status;
702         u16 opcode;
703         u16 op_mod;
704         u16 uid;
705
706         mlx5_cmd_mbox_status(out, &status, &syndrome);
707         if (!status)
708                 return 0;
709
710         opcode = MLX5_GET(mbox_in, in, opcode);
711         op_mod = MLX5_GET(mbox_in, in, op_mod);
712         uid    = MLX5_GET(mbox_in, in, uid);
713
714         if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
715                 mlx5_core_err_rl(dev,
716                         "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
717                         mlx5_command_str(opcode), opcode, op_mod,
718                         cmd_status_str(status), status, syndrome);
719         else
720                 mlx5_core_dbg(dev,
721                       "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
722                       mlx5_command_str(opcode),
723                       opcode, op_mod,
724                       cmd_status_str(status),
725                       status,
726                       syndrome);
727
728         return cmd_status_to_err(status);
729 }
730
731 static void dump_command(struct mlx5_core_dev *dev,
732                          struct mlx5_cmd_work_ent *ent, int input)
733 {
734         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
735         u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
736         struct mlx5_cmd_mailbox *next = msg->next;
737         int n = mlx5_calc_cmd_blocks(msg);
738         int data_only;
739         u32 offset = 0;
740         int dump_len;
741         int i;
742
743         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
744
745         if (data_only)
746                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
747                                    "dump command data %s(0x%x) %s\n",
748                                    mlx5_command_str(op), op,
749                                    input ? "INPUT" : "OUTPUT");
750         else
751                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
752                               mlx5_command_str(op), op,
753                               input ? "INPUT" : "OUTPUT");
754
755         if (data_only) {
756                 if (input) {
757                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
758                         offset += sizeof(ent->lay->in);
759                 } else {
760                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
761                         offset += sizeof(ent->lay->out);
762                 }
763         } else {
764                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
765                 offset += sizeof(*ent->lay);
766         }
767
768         for (i = 0; i < n && next; i++)  {
769                 if (data_only) {
770                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
771                         dump_buf(next->buf, dump_len, 1, offset);
772                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
773                 } else {
774                         mlx5_core_dbg(dev, "command block:\n");
775                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
776                         offset += sizeof(struct mlx5_cmd_prot_block);
777                 }
778                 next = next->next;
779         }
780
781         if (data_only)
782                 pr_debug("\n");
783 }
784
785 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
786 {
787         return MLX5_GET(mbox_in, in->first.data, opcode);
788 }
789
790 static void cb_timeout_handler(struct work_struct *work)
791 {
792         struct delayed_work *dwork = container_of(work, struct delayed_work,
793                                                   work);
794         struct mlx5_cmd_work_ent *ent = container_of(dwork,
795                                                      struct mlx5_cmd_work_ent,
796                                                      cb_timeout_work);
797         struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
798                                                  cmd);
799
800         ent->ret = -ETIMEDOUT;
801         mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
802                        mlx5_command_str(msg_to_opcode(ent->in)),
803                        msg_to_opcode(ent->in));
804         mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
805 }
806
807 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
808 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
809                               struct mlx5_cmd_msg *msg);
810
811 static void cmd_work_handler(struct work_struct *work)
812 {
813         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
814         struct mlx5_cmd *cmd = ent->cmd;
815         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
816         unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
817         struct mlx5_cmd_layout *lay;
818         struct semaphore *sem;
819         unsigned long flags;
820         bool poll_cmd = ent->polling;
821         int alloc_ret;
822
823         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
824         down(sem);
825         if (!ent->page_queue) {
826                 alloc_ret = alloc_ent(cmd);
827                 if (alloc_ret < 0) {
828                         mlx5_core_err(dev, "failed to allocate command entry\n");
829                         if (ent->callback) {
830                                 ent->callback(-EAGAIN, ent->context);
831                                 mlx5_free_cmd_msg(dev, ent->out);
832                                 free_msg(dev, ent->in);
833                                 free_cmd(ent);
834                         } else {
835                                 ent->ret = -EAGAIN;
836                                 complete(&ent->done);
837                         }
838                         up(sem);
839                         return;
840                 }
841                 ent->idx = alloc_ret;
842         } else {
843                 ent->idx = cmd->max_reg_cmds;
844                 spin_lock_irqsave(&cmd->alloc_lock, flags);
845                 clear_bit(ent->idx, &cmd->bitmask);
846                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
847         }
848
849         cmd->ent_arr[ent->idx] = ent;
850         set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
851         lay = get_inst(cmd, ent->idx);
852         ent->lay = lay;
853         memset(lay, 0, sizeof(*lay));
854         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
855         ent->op = be32_to_cpu(lay->in[0]) >> 16;
856         if (ent->in->next)
857                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
858         lay->inlen = cpu_to_be32(ent->in->len);
859         if (ent->out->next)
860                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
861         lay->outlen = cpu_to_be32(ent->out->len);
862         lay->type = MLX5_PCI_CMD_XPORT;
863         lay->token = ent->token;
864         lay->status_own = CMD_OWNER_HW;
865         set_signature(ent, !cmd->checksum_disabled);
866         dump_command(dev, ent, 1);
867         ent->ts1 = ktime_get_ns();
868
869         if (ent->callback)
870                 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
871
872         /* Skip sending command to fw if internal error */
873         if (pci_channel_offline(dev->pdev) ||
874             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
875                 u8 status = 0;
876                 u32 drv_synd;
877
878                 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
879                 MLX5_SET(mbox_out, ent->out, status, status);
880                 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
881
882                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
883                 return;
884         }
885
886         /* ring doorbell after the descriptor is valid */
887         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
888         wmb();
889         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
890         mmiowb();
891         /* if not in polling don't use ent after this point */
892         if (cmd->mode == CMD_MODE_POLLING || poll_cmd) {
893                 poll_timeout(ent);
894                 /* make sure we read the descriptor after ownership is SW */
895                 rmb();
896                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
897         }
898 }
899
900 static const char *deliv_status_to_str(u8 status)
901 {
902         switch (status) {
903         case MLX5_CMD_DELIVERY_STAT_OK:
904                 return "no errors";
905         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
906                 return "signature error";
907         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
908                 return "token error";
909         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
910                 return "bad block number";
911         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
912                 return "output pointer not aligned to block size";
913         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
914                 return "input pointer not aligned to block size";
915         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
916                 return "firmware internal error";
917         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
918                 return "command input length error";
919         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
920                 return "command output length error";
921         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
922                 return "reserved fields not cleared";
923         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
924                 return "bad command descriptor type";
925         default:
926                 return "unknown status code";
927         }
928 }
929
930 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
931 {
932         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
933         struct mlx5_cmd *cmd = &dev->cmd;
934         int err;
935
936         if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
937                 wait_for_completion(&ent->done);
938         } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
939                 ent->ret = -ETIMEDOUT;
940                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
941         }
942
943         err = ent->ret;
944
945         if (err == -ETIMEDOUT) {
946                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
947                                mlx5_command_str(msg_to_opcode(ent->in)),
948                                msg_to_opcode(ent->in));
949         }
950         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
951                       err, deliv_status_to_str(ent->status), ent->status);
952
953         return err;
954 }
955
956 /*  Notes:
957  *    1. Callback functions may not sleep
958  *    2. page queue commands do not support asynchrous completion
959  */
960 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
961                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
962                            mlx5_cmd_cbk_t callback,
963                            void *context, int page_queue, u8 *status,
964                            u8 token, bool force_polling)
965 {
966         struct mlx5_cmd *cmd = &dev->cmd;
967         struct mlx5_cmd_work_ent *ent;
968         struct mlx5_cmd_stats *stats;
969         int err = 0;
970         s64 ds;
971         u16 op;
972
973         if (callback && page_queue)
974                 return -EINVAL;
975
976         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
977                         page_queue);
978         if (IS_ERR(ent))
979                 return PTR_ERR(ent);
980
981         ent->token = token;
982         ent->polling = force_polling;
983
984         if (!callback)
985                 init_completion(&ent->done);
986
987         INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
988         INIT_WORK(&ent->work, cmd_work_handler);
989         if (page_queue) {
990                 cmd_work_handler(&ent->work);
991         } else if (!queue_work(cmd->wq, &ent->work)) {
992                 mlx5_core_warn(dev, "failed to queue work\n");
993                 err = -ENOMEM;
994                 goto out_free;
995         }
996
997         if (callback)
998                 goto out;
999
1000         err = wait_func(dev, ent);
1001         if (err == -ETIMEDOUT)
1002                 goto out;
1003
1004         ds = ent->ts2 - ent->ts1;
1005         op = MLX5_GET(mbox_in, in->first.data, opcode);
1006         if (op < ARRAY_SIZE(cmd->stats)) {
1007                 stats = &cmd->stats[op];
1008                 spin_lock_irq(&stats->lock);
1009                 stats->sum += ds;
1010                 ++stats->n;
1011                 spin_unlock_irq(&stats->lock);
1012         }
1013         mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1014                            "fw exec time for %s is %lld nsec\n",
1015                            mlx5_command_str(op), ds);
1016         *status = ent->status;
1017
1018 out_free:
1019         free_cmd(ent);
1020 out:
1021         return err;
1022 }
1023
1024 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1025                          size_t count, loff_t *pos)
1026 {
1027         struct mlx5_core_dev *dev = filp->private_data;
1028         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1029         char lbuf[3];
1030         int err;
1031
1032         if (!dbg->in_msg || !dbg->out_msg)
1033                 return -ENOMEM;
1034
1035         if (count < sizeof(lbuf) - 1)
1036                 return -EINVAL;
1037
1038         if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1039                 return -EFAULT;
1040
1041         lbuf[sizeof(lbuf) - 1] = 0;
1042
1043         if (strcmp(lbuf, "go"))
1044                 return -EINVAL;
1045
1046         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1047
1048         return err ? err : count;
1049 }
1050
1051 static const struct file_operations fops = {
1052         .owner  = THIS_MODULE,
1053         .open   = simple_open,
1054         .write  = dbg_write,
1055 };
1056
1057 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1058                             u8 token)
1059 {
1060         struct mlx5_cmd_prot_block *block;
1061         struct mlx5_cmd_mailbox *next;
1062         int copy;
1063
1064         if (!to || !from)
1065                 return -ENOMEM;
1066
1067         copy = min_t(int, size, sizeof(to->first.data));
1068         memcpy(to->first.data, from, copy);
1069         size -= copy;
1070         from += copy;
1071
1072         next = to->next;
1073         while (size) {
1074                 if (!next) {
1075                         /* this is a BUG */
1076                         return -ENOMEM;
1077                 }
1078
1079                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1080                 block = next->buf;
1081                 memcpy(block->data, from, copy);
1082                 from += copy;
1083                 size -= copy;
1084                 block->token = token;
1085                 next = next->next;
1086         }
1087
1088         return 0;
1089 }
1090
1091 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1092 {
1093         struct mlx5_cmd_prot_block *block;
1094         struct mlx5_cmd_mailbox *next;
1095         int copy;
1096
1097         if (!to || !from)
1098                 return -ENOMEM;
1099
1100         copy = min_t(int, size, sizeof(from->first.data));
1101         memcpy(to, from->first.data, copy);
1102         size -= copy;
1103         to += copy;
1104
1105         next = from->next;
1106         while (size) {
1107                 if (!next) {
1108                         /* this is a BUG */
1109                         return -ENOMEM;
1110                 }
1111
1112                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1113                 block = next->buf;
1114
1115                 memcpy(to, block->data, copy);
1116                 to += copy;
1117                 size -= copy;
1118                 next = next->next;
1119         }
1120
1121         return 0;
1122 }
1123
1124 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1125                                               gfp_t flags)
1126 {
1127         struct mlx5_cmd_mailbox *mailbox;
1128
1129         mailbox = kmalloc(sizeof(*mailbox), flags);
1130         if (!mailbox)
1131                 return ERR_PTR(-ENOMEM);
1132
1133         mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1134                                        &mailbox->dma);
1135         if (!mailbox->buf) {
1136                 mlx5_core_dbg(dev, "failed allocation\n");
1137                 kfree(mailbox);
1138                 return ERR_PTR(-ENOMEM);
1139         }
1140         mailbox->next = NULL;
1141
1142         return mailbox;
1143 }
1144
1145 static void free_cmd_box(struct mlx5_core_dev *dev,
1146                          struct mlx5_cmd_mailbox *mailbox)
1147 {
1148         dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1149         kfree(mailbox);
1150 }
1151
1152 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1153                                                gfp_t flags, int size,
1154                                                u8 token)
1155 {
1156         struct mlx5_cmd_mailbox *tmp, *head = NULL;
1157         struct mlx5_cmd_prot_block *block;
1158         struct mlx5_cmd_msg *msg;
1159         int err;
1160         int n;
1161         int i;
1162
1163         msg = kzalloc(sizeof(*msg), flags);
1164         if (!msg)
1165                 return ERR_PTR(-ENOMEM);
1166
1167         msg->len = size;
1168         n = mlx5_calc_cmd_blocks(msg);
1169
1170         for (i = 0; i < n; i++) {
1171                 tmp = alloc_cmd_box(dev, flags);
1172                 if (IS_ERR(tmp)) {
1173                         mlx5_core_warn(dev, "failed allocating block\n");
1174                         err = PTR_ERR(tmp);
1175                         goto err_alloc;
1176                 }
1177
1178                 block = tmp->buf;
1179                 tmp->next = head;
1180                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1181                 block->block_num = cpu_to_be32(n - i - 1);
1182                 block->token = token;
1183                 head = tmp;
1184         }
1185         msg->next = head;
1186         return msg;
1187
1188 err_alloc:
1189         while (head) {
1190                 tmp = head->next;
1191                 free_cmd_box(dev, head);
1192                 head = tmp;
1193         }
1194         kfree(msg);
1195
1196         return ERR_PTR(err);
1197 }
1198
1199 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1200                               struct mlx5_cmd_msg *msg)
1201 {
1202         struct mlx5_cmd_mailbox *head = msg->next;
1203         struct mlx5_cmd_mailbox *next;
1204
1205         while (head) {
1206                 next = head->next;
1207                 free_cmd_box(dev, head);
1208                 head = next;
1209         }
1210         kfree(msg);
1211 }
1212
1213 static ssize_t data_write(struct file *filp, const char __user *buf,
1214                           size_t count, loff_t *pos)
1215 {
1216         struct mlx5_core_dev *dev = filp->private_data;
1217         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1218         void *ptr;
1219
1220         if (*pos != 0)
1221                 return -EINVAL;
1222
1223         kfree(dbg->in_msg);
1224         dbg->in_msg = NULL;
1225         dbg->inlen = 0;
1226         ptr = memdup_user(buf, count);
1227         if (IS_ERR(ptr))
1228                 return PTR_ERR(ptr);
1229         dbg->in_msg = ptr;
1230         dbg->inlen = count;
1231
1232         *pos = count;
1233
1234         return count;
1235 }
1236
1237 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1238                          loff_t *pos)
1239 {
1240         struct mlx5_core_dev *dev = filp->private_data;
1241         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1242
1243         if (!dbg->out_msg)
1244                 return -ENOMEM;
1245
1246         return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1247                                        dbg->outlen);
1248 }
1249
1250 static const struct file_operations dfops = {
1251         .owner  = THIS_MODULE,
1252         .open   = simple_open,
1253         .write  = data_write,
1254         .read   = data_read,
1255 };
1256
1257 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1258                            loff_t *pos)
1259 {
1260         struct mlx5_core_dev *dev = filp->private_data;
1261         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1262         char outlen[8];
1263         int err;
1264
1265         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1266         if (err < 0)
1267                 return err;
1268
1269         return simple_read_from_buffer(buf, count, pos, outlen, err);
1270 }
1271
1272 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1273                             size_t count, loff_t *pos)
1274 {
1275         struct mlx5_core_dev *dev = filp->private_data;
1276         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1277         char outlen_str[8];
1278         int outlen;
1279         void *ptr;
1280         int err;
1281
1282         if (*pos != 0 || count > 6)
1283                 return -EINVAL;
1284
1285         kfree(dbg->out_msg);
1286         dbg->out_msg = NULL;
1287         dbg->outlen = 0;
1288
1289         if (copy_from_user(outlen_str, buf, count))
1290                 return -EFAULT;
1291
1292         outlen_str[7] = 0;
1293
1294         err = sscanf(outlen_str, "%d", &outlen);
1295         if (err < 0)
1296                 return err;
1297
1298         ptr = kzalloc(outlen, GFP_KERNEL);
1299         if (!ptr)
1300                 return -ENOMEM;
1301
1302         dbg->out_msg = ptr;
1303         dbg->outlen = outlen;
1304
1305         *pos = count;
1306
1307         return count;
1308 }
1309
1310 static const struct file_operations olfops = {
1311         .owner  = THIS_MODULE,
1312         .open   = simple_open,
1313         .write  = outlen_write,
1314         .read   = outlen_read,
1315 };
1316
1317 static void set_wqname(struct mlx5_core_dev *dev)
1318 {
1319         struct mlx5_cmd *cmd = &dev->cmd;
1320
1321         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1322                  dev_name(&dev->pdev->dev));
1323 }
1324
1325 static void clean_debug_files(struct mlx5_core_dev *dev)
1326 {
1327         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1328
1329         if (!mlx5_debugfs_root)
1330                 return;
1331
1332         mlx5_cmdif_debugfs_cleanup(dev);
1333         debugfs_remove_recursive(dbg->dbg_root);
1334 }
1335
1336 static int create_debugfs_files(struct mlx5_core_dev *dev)
1337 {
1338         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1339         int err = -ENOMEM;
1340
1341         if (!mlx5_debugfs_root)
1342                 return 0;
1343
1344         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1345         if (!dbg->dbg_root)
1346                 return err;
1347
1348         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1349                                           dev, &dfops);
1350         if (!dbg->dbg_in)
1351                 goto err_dbg;
1352
1353         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1354                                            dev, &dfops);
1355         if (!dbg->dbg_out)
1356                 goto err_dbg;
1357
1358         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1359                                               dev, &olfops);
1360         if (!dbg->dbg_outlen)
1361                 goto err_dbg;
1362
1363         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1364                                             &dbg->status);
1365         if (!dbg->dbg_status)
1366                 goto err_dbg;
1367
1368         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1369         if (!dbg->dbg_run)
1370                 goto err_dbg;
1371
1372         mlx5_cmdif_debugfs_init(dev);
1373
1374         return 0;
1375
1376 err_dbg:
1377         clean_debug_files(dev);
1378         return err;
1379 }
1380
1381 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1382 {
1383         struct mlx5_cmd *cmd = &dev->cmd;
1384         int i;
1385
1386         for (i = 0; i < cmd->max_reg_cmds; i++)
1387                 down(&cmd->sem);
1388         down(&cmd->pages_sem);
1389
1390         cmd->mode = mode;
1391
1392         up(&cmd->pages_sem);
1393         for (i = 0; i < cmd->max_reg_cmds; i++)
1394                 up(&cmd->sem);
1395 }
1396
1397 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1398 {
1399         mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1400 }
1401
1402 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1403 {
1404         mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1405 }
1406
1407 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1408 {
1409         unsigned long flags;
1410
1411         if (msg->parent) {
1412                 spin_lock_irqsave(&msg->parent->lock, flags);
1413                 list_add_tail(&msg->list, &msg->parent->head);
1414                 spin_unlock_irqrestore(&msg->parent->lock, flags);
1415         } else {
1416                 mlx5_free_cmd_msg(dev, msg);
1417         }
1418 }
1419
1420 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1421 {
1422         struct mlx5_cmd *cmd = &dev->cmd;
1423         struct mlx5_cmd_work_ent *ent;
1424         mlx5_cmd_cbk_t callback;
1425         void *context;
1426         int err;
1427         int i;
1428         s64 ds;
1429         struct mlx5_cmd_stats *stats;
1430         unsigned long flags;
1431         unsigned long vector;
1432
1433         /* there can be at most 32 command queues */
1434         vector = vec & 0xffffffff;
1435         for (i = 0; i < (1 << cmd->log_sz); i++) {
1436                 if (test_bit(i, &vector)) {
1437                         struct semaphore *sem;
1438
1439                         ent = cmd->ent_arr[i];
1440
1441                         /* if we already completed the command, ignore it */
1442                         if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1443                                                 &ent->state)) {
1444                                 /* only real completion can free the cmd slot */
1445                                 if (!forced) {
1446                                         mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1447                                                       ent->idx);
1448                                         free_ent(cmd, ent->idx);
1449                                         free_cmd(ent);
1450                                 }
1451                                 continue;
1452                         }
1453
1454                         if (ent->callback)
1455                                 cancel_delayed_work(&ent->cb_timeout_work);
1456                         if (ent->page_queue)
1457                                 sem = &cmd->pages_sem;
1458                         else
1459                                 sem = &cmd->sem;
1460                         ent->ts2 = ktime_get_ns();
1461                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1462                         dump_command(dev, ent, 0);
1463                         if (!ent->ret) {
1464                                 if (!cmd->checksum_disabled)
1465                                         ent->ret = verify_signature(ent);
1466                                 else
1467                                         ent->ret = 0;
1468                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1469                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1470                                 else
1471                                         ent->status = ent->lay->status_own >> 1;
1472
1473                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1474                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1475                         }
1476
1477                         /* only real completion will free the entry slot */
1478                         if (!forced)
1479                                 free_ent(cmd, ent->idx);
1480
1481                         if (ent->callback) {
1482                                 ds = ent->ts2 - ent->ts1;
1483                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1484                                         stats = &cmd->stats[ent->op];
1485                                         spin_lock_irqsave(&stats->lock, flags);
1486                                         stats->sum += ds;
1487                                         ++stats->n;
1488                                         spin_unlock_irqrestore(&stats->lock, flags);
1489                                 }
1490
1491                                 callback = ent->callback;
1492                                 context = ent->context;
1493                                 err = ent->ret;
1494                                 if (!err) {
1495                                         err = mlx5_copy_from_msg(ent->uout,
1496                                                                  ent->out,
1497                                                                  ent->uout_size);
1498
1499                                         err = err ? err : mlx5_cmd_check(dev,
1500                                                                         ent->in->first.data,
1501                                                                         ent->uout);
1502                                 }
1503
1504                                 mlx5_free_cmd_msg(dev, ent->out);
1505                                 free_msg(dev, ent->in);
1506
1507                                 err = err ? err : ent->status;
1508                                 if (!forced)
1509                                         free_cmd(ent);
1510                                 callback(err, context);
1511                         } else {
1512                                 complete(&ent->done);
1513                         }
1514                         up(sem);
1515                 }
1516         }
1517 }
1518 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1519
1520 static int status_to_err(u8 status)
1521 {
1522         return status ? -1 : 0; /* TBD more meaningful codes */
1523 }
1524
1525 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1526                                       gfp_t gfp)
1527 {
1528         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1529         struct cmd_msg_cache *ch = NULL;
1530         struct mlx5_cmd *cmd = &dev->cmd;
1531         int i;
1532
1533         if (in_size <= 16)
1534                 goto cache_miss;
1535
1536         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1537                 ch = &cmd->cache[i];
1538                 if (in_size > ch->max_inbox_size)
1539                         continue;
1540                 spin_lock_irq(&ch->lock);
1541                 if (list_empty(&ch->head)) {
1542                         spin_unlock_irq(&ch->lock);
1543                         continue;
1544                 }
1545                 msg = list_entry(ch->head.next, typeof(*msg), list);
1546                 /* For cached lists, we must explicitly state what is
1547                  * the real size
1548                  */
1549                 msg->len = in_size;
1550                 list_del(&msg->list);
1551                 spin_unlock_irq(&ch->lock);
1552                 break;
1553         }
1554
1555         if (!IS_ERR(msg))
1556                 return msg;
1557
1558 cache_miss:
1559         msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1560         return msg;
1561 }
1562
1563 static int is_manage_pages(void *in)
1564 {
1565         return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1566 }
1567
1568 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1569                     int out_size, mlx5_cmd_cbk_t callback, void *context,
1570                     bool force_polling)
1571 {
1572         struct mlx5_cmd_msg *inb;
1573         struct mlx5_cmd_msg *outb;
1574         int pages_queue;
1575         gfp_t gfp;
1576         int err;
1577         u8 status = 0;
1578         u32 drv_synd;
1579         u8 token;
1580
1581         if (pci_channel_offline(dev->pdev) ||
1582             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1583                 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1584
1585                 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1586                 MLX5_SET(mbox_out, out, status, status);
1587                 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1588                 return err;
1589         }
1590
1591         pages_queue = is_manage_pages(in);
1592         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1593
1594         inb = alloc_msg(dev, in_size, gfp);
1595         if (IS_ERR(inb)) {
1596                 err = PTR_ERR(inb);
1597                 return err;
1598         }
1599
1600         token = alloc_token(&dev->cmd);
1601
1602         err = mlx5_copy_to_msg(inb, in, in_size, token);
1603         if (err) {
1604                 mlx5_core_warn(dev, "err %d\n", err);
1605                 goto out_in;
1606         }
1607
1608         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1609         if (IS_ERR(outb)) {
1610                 err = PTR_ERR(outb);
1611                 goto out_in;
1612         }
1613
1614         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1615                               pages_queue, &status, token, force_polling);
1616         if (err)
1617                 goto out_out;
1618
1619         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1620         if (status) {
1621                 err = status_to_err(status);
1622                 goto out_out;
1623         }
1624
1625         if (!callback)
1626                 err = mlx5_copy_from_msg(out, outb, out_size);
1627
1628 out_out:
1629         if (!callback)
1630                 mlx5_free_cmd_msg(dev, outb);
1631
1632 out_in:
1633         if (!callback)
1634                 free_msg(dev, inb);
1635         return err;
1636 }
1637
1638 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1639                   int out_size)
1640 {
1641         int err;
1642
1643         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1644         return err ? : mlx5_cmd_check(dev, in, out);
1645 }
1646 EXPORT_SYMBOL(mlx5_cmd_exec);
1647
1648 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1649                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1650                      void *context)
1651 {
1652         return cmd_exec(dev, in, in_size, out, out_size, callback, context,
1653                         false);
1654 }
1655 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1656
1657 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1658                           void *out, int out_size)
1659 {
1660         int err;
1661
1662         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1663
1664         return err ? : mlx5_cmd_check(dev, in, out);
1665 }
1666 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1667
1668 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1669 {
1670         struct cmd_msg_cache *ch;
1671         struct mlx5_cmd_msg *msg;
1672         struct mlx5_cmd_msg *n;
1673         int i;
1674
1675         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1676                 ch = &dev->cmd.cache[i];
1677                 list_for_each_entry_safe(msg, n, &ch->head, list) {
1678                         list_del(&msg->list);
1679                         mlx5_free_cmd_msg(dev, msg);
1680                 }
1681         }
1682 }
1683
1684 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1685         512, 32, 16, 8, 2
1686 };
1687
1688 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1689         16 + MLX5_CMD_DATA_BLOCK_SIZE,
1690         16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1691         16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1692         16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1693         16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1694 };
1695
1696 static void create_msg_cache(struct mlx5_core_dev *dev)
1697 {
1698         struct mlx5_cmd *cmd = &dev->cmd;
1699         struct cmd_msg_cache *ch;
1700         struct mlx5_cmd_msg *msg;
1701         int i;
1702         int k;
1703
1704         /* Initialize and fill the caches with initial entries */
1705         for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1706                 ch = &cmd->cache[k];
1707                 spin_lock_init(&ch->lock);
1708                 INIT_LIST_HEAD(&ch->head);
1709                 ch->num_ent = cmd_cache_num_ent[k];
1710                 ch->max_inbox_size = cmd_cache_ent_size[k];
1711                 for (i = 0; i < ch->num_ent; i++) {
1712                         msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1713                                                  ch->max_inbox_size, 0);
1714                         if (IS_ERR(msg))
1715                                 break;
1716                         msg->parent = ch;
1717                         list_add_tail(&msg->list, &ch->head);
1718                 }
1719         }
1720 }
1721
1722 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1723 {
1724         struct device *ddev = &dev->pdev->dev;
1725
1726         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1727                                                  &cmd->alloc_dma, GFP_KERNEL);
1728         if (!cmd->cmd_alloc_buf)
1729                 return -ENOMEM;
1730
1731         /* make sure it is aligned to 4K */
1732         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1733                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1734                 cmd->dma = cmd->alloc_dma;
1735                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1736                 return 0;
1737         }
1738
1739         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1740                           cmd->alloc_dma);
1741         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1742                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1743                                                  &cmd->alloc_dma, GFP_KERNEL);
1744         if (!cmd->cmd_alloc_buf)
1745                 return -ENOMEM;
1746
1747         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1748         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1749         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1750         return 0;
1751 }
1752
1753 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1754 {
1755         struct device *ddev = &dev->pdev->dev;
1756
1757         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1758                           cmd->alloc_dma);
1759 }
1760
1761 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1762 {
1763         int size = sizeof(struct mlx5_cmd_prot_block);
1764         int align = roundup_pow_of_two(size);
1765         struct mlx5_cmd *cmd = &dev->cmd;
1766         u32 cmd_h, cmd_l;
1767         u16 cmd_if_rev;
1768         int err;
1769         int i;
1770
1771         memset(cmd, 0, sizeof(*cmd));
1772         cmd_if_rev = cmdif_rev(dev);
1773         if (cmd_if_rev != CMD_IF_REV) {
1774                 dev_err(&dev->pdev->dev,
1775                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1776                         CMD_IF_REV, cmd_if_rev);
1777                 return -EINVAL;
1778         }
1779
1780         cmd->pool = dma_pool_create("mlx5_cmd", &dev->pdev->dev, size, align,
1781                                     0);
1782         if (!cmd->pool)
1783                 return -ENOMEM;
1784
1785         err = alloc_cmd_page(dev, cmd);
1786         if (err)
1787                 goto err_free_pool;
1788
1789         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1790         cmd->log_sz = cmd_l >> 4 & 0xf;
1791         cmd->log_stride = cmd_l & 0xf;
1792         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1793                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1794                         1 << cmd->log_sz);
1795                 err = -EINVAL;
1796                 goto err_free_page;
1797         }
1798
1799         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1800                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1801                 err = -EINVAL;
1802                 goto err_free_page;
1803         }
1804
1805         cmd->checksum_disabled = 1;
1806         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1807         cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
1808
1809         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1810         if (cmd->cmdif_rev > CMD_IF_REV) {
1811                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1812                         CMD_IF_REV, cmd->cmdif_rev);
1813                 err = -EOPNOTSUPP;
1814                 goto err_free_page;
1815         }
1816
1817         spin_lock_init(&cmd->alloc_lock);
1818         spin_lock_init(&cmd->token_lock);
1819         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1820                 spin_lock_init(&cmd->stats[i].lock);
1821
1822         sema_init(&cmd->sem, cmd->max_reg_cmds);
1823         sema_init(&cmd->pages_sem, 1);
1824
1825         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1826         cmd_l = (u32)(cmd->dma);
1827         if (cmd_l & 0xfff) {
1828                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1829                 err = -ENOMEM;
1830                 goto err_free_page;
1831         }
1832
1833         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1834         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1835
1836         /* Make sure firmware sees the complete address before we proceed */
1837         wmb();
1838
1839         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1840
1841         cmd->mode = CMD_MODE_POLLING;
1842
1843         create_msg_cache(dev);
1844
1845         set_wqname(dev);
1846         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1847         if (!cmd->wq) {
1848                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1849                 err = -ENOMEM;
1850                 goto err_cache;
1851         }
1852
1853         err = create_debugfs_files(dev);
1854         if (err) {
1855                 err = -ENOMEM;
1856                 goto err_wq;
1857         }
1858
1859         return 0;
1860
1861 err_wq:
1862         destroy_workqueue(cmd->wq);
1863
1864 err_cache:
1865         destroy_msg_cache(dev);
1866
1867 err_free_page:
1868         free_cmd_page(dev, cmd);
1869
1870 err_free_pool:
1871         dma_pool_destroy(cmd->pool);
1872
1873         return err;
1874 }
1875 EXPORT_SYMBOL(mlx5_cmd_init);
1876
1877 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1878 {
1879         struct mlx5_cmd *cmd = &dev->cmd;
1880
1881         clean_debug_files(dev);
1882         destroy_workqueue(cmd->wq);
1883         destroy_msg_cache(dev);
1884         free_cmd_page(dev, cmd);
1885         dma_pool_destroy(cmd->pool);
1886 }
1887 EXPORT_SYMBOL(mlx5_cmd_cleanup);