Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox...
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / cmd.c
1 /*
2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/debugfs.h>
44
45 #include "mlx5_core.h"
46
47 enum {
48         CMD_IF_REV = 5,
49 };
50
51 enum {
52         CMD_MODE_POLLING,
53         CMD_MODE_EVENTS
54 };
55
56 enum {
57         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
58         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
59         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
60         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
61         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
62         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
63         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
64         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
65         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
66         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
67         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
68 };
69
70 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
71                                            struct mlx5_cmd_msg *in,
72                                            struct mlx5_cmd_msg *out,
73                                            void *uout, int uout_size,
74                                            mlx5_cmd_cbk_t cbk,
75                                            void *context, int page_queue)
76 {
77         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
78         struct mlx5_cmd_work_ent *ent;
79
80         ent = kzalloc(sizeof(*ent), alloc_flags);
81         if (!ent)
82                 return ERR_PTR(-ENOMEM);
83
84         ent->in         = in;
85         ent->out        = out;
86         ent->uout       = uout;
87         ent->uout_size  = uout_size;
88         ent->callback   = cbk;
89         ent->context    = context;
90         ent->cmd        = cmd;
91         ent->page_queue = page_queue;
92
93         return ent;
94 }
95
96 static u8 alloc_token(struct mlx5_cmd *cmd)
97 {
98         u8 token;
99
100         spin_lock(&cmd->token_lock);
101         cmd->token++;
102         if (cmd->token == 0)
103                 cmd->token++;
104         token = cmd->token;
105         spin_unlock(&cmd->token_lock);
106
107         return token;
108 }
109
110 static int alloc_ent(struct mlx5_cmd *cmd)
111 {
112         unsigned long flags;
113         int ret;
114
115         spin_lock_irqsave(&cmd->alloc_lock, flags);
116         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
117         if (ret < cmd->max_reg_cmds)
118                 clear_bit(ret, &cmd->bitmask);
119         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
120
121         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
122 }
123
124 static void free_ent(struct mlx5_cmd *cmd, int idx)
125 {
126         unsigned long flags;
127
128         spin_lock_irqsave(&cmd->alloc_lock, flags);
129         set_bit(idx, &cmd->bitmask);
130         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
131 }
132
133 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
134 {
135         return cmd->cmd_buf + (idx << cmd->log_stride);
136 }
137
138 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
139 {
140         int size = msg->len;
141         int blen = size - min_t(int, sizeof(msg->first.data), size);
142
143         return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
144 }
145
146 static u8 xor8_buf(void *buf, size_t offset, int len)
147 {
148         u8 *ptr = buf;
149         u8 sum = 0;
150         int i;
151         int end = len + offset;
152
153         for (i = offset; i < end; i++)
154                 sum ^= ptr[i];
155
156         return sum;
157 }
158
159 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
160 {
161         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
162         int xor_len = sizeof(*block) - sizeof(block->data) - 1;
163
164         if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
165                 return -EINVAL;
166
167         if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
168                 return -EINVAL;
169
170         return 0;
171 }
172
173 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
174 {
175         int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
176         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
177
178         block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
179         block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
180 }
181
182 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
183 {
184         struct mlx5_cmd_mailbox *next = msg->next;
185         int n = mlx5_calc_cmd_blocks(msg);
186         int i = 0;
187
188         for (i = 0; i < n && next; i++)  {
189                 calc_block_sig(next->buf);
190                 next = next->next;
191         }
192 }
193
194 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
195 {
196         ent->lay->sig = ~xor8_buf(ent->lay, 0,  sizeof(*ent->lay));
197         if (csum) {
198                 calc_chain_sig(ent->in);
199                 calc_chain_sig(ent->out);
200         }
201 }
202
203 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
204 {
205         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
206         u8 own;
207
208         do {
209                 own = READ_ONCE(ent->lay->status_own);
210                 if (!(own & CMD_OWNER_HW)) {
211                         ent->ret = 0;
212                         return;
213                 }
214                 cond_resched();
215         } while (time_before(jiffies, poll_end));
216
217         ent->ret = -ETIMEDOUT;
218 }
219
220 static void free_cmd(struct mlx5_cmd_work_ent *ent)
221 {
222         kfree(ent);
223 }
224
225 static int verify_signature(struct mlx5_cmd_work_ent *ent)
226 {
227         struct mlx5_cmd_mailbox *next = ent->out->next;
228         int n = mlx5_calc_cmd_blocks(ent->out);
229         int err;
230         u8 sig;
231         int i = 0;
232
233         sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
234         if (sig != 0xff)
235                 return -EINVAL;
236
237         for (i = 0; i < n && next; i++) {
238                 err = verify_block_sig(next->buf);
239                 if (err)
240                         return err;
241
242                 next = next->next;
243         }
244
245         return 0;
246 }
247
248 static void dump_buf(void *buf, int size, int data_only, int offset)
249 {
250         __be32 *p = buf;
251         int i;
252
253         for (i = 0; i < size; i += 16) {
254                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
255                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
256                          be32_to_cpu(p[3]));
257                 p += 4;
258                 offset += 16;
259         }
260         if (!data_only)
261                 pr_debug("\n");
262 }
263
264 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
265                                        u32 *synd, u8 *status)
266 {
267         *synd = 0;
268         *status = 0;
269
270         switch (op) {
271         case MLX5_CMD_OP_TEARDOWN_HCA:
272         case MLX5_CMD_OP_DISABLE_HCA:
273         case MLX5_CMD_OP_MANAGE_PAGES:
274         case MLX5_CMD_OP_DESTROY_MKEY:
275         case MLX5_CMD_OP_DESTROY_EQ:
276         case MLX5_CMD_OP_DESTROY_CQ:
277         case MLX5_CMD_OP_DESTROY_QP:
278         case MLX5_CMD_OP_DESTROY_PSV:
279         case MLX5_CMD_OP_DESTROY_SRQ:
280         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
281         case MLX5_CMD_OP_DESTROY_XRQ:
282         case MLX5_CMD_OP_DESTROY_DCT:
283         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
284         case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
285         case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
286         case MLX5_CMD_OP_DEALLOC_PD:
287         case MLX5_CMD_OP_DEALLOC_UAR:
288         case MLX5_CMD_OP_DETACH_FROM_MCG:
289         case MLX5_CMD_OP_DEALLOC_XRCD:
290         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
291         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
292         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
293         case MLX5_CMD_OP_DESTROY_LAG:
294         case MLX5_CMD_OP_DESTROY_VPORT_LAG:
295         case MLX5_CMD_OP_DESTROY_TIR:
296         case MLX5_CMD_OP_DESTROY_SQ:
297         case MLX5_CMD_OP_DESTROY_RQ:
298         case MLX5_CMD_OP_DESTROY_RMP:
299         case MLX5_CMD_OP_DESTROY_TIS:
300         case MLX5_CMD_OP_DESTROY_RQT:
301         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
302         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
303         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
304         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
305         case MLX5_CMD_OP_2ERR_QP:
306         case MLX5_CMD_OP_2RST_QP:
307         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
308         case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
309         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
310         case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
311         case MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT:
312         case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
313         case MLX5_CMD_OP_FPGA_DESTROY_QP:
314         case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
315         case MLX5_CMD_OP_DEALLOC_MEMIC:
316                 return MLX5_CMD_STAT_OK;
317
318         case MLX5_CMD_OP_QUERY_HCA_CAP:
319         case MLX5_CMD_OP_QUERY_ADAPTER:
320         case MLX5_CMD_OP_INIT_HCA:
321         case MLX5_CMD_OP_ENABLE_HCA:
322         case MLX5_CMD_OP_QUERY_PAGES:
323         case MLX5_CMD_OP_SET_HCA_CAP:
324         case MLX5_CMD_OP_QUERY_ISSI:
325         case MLX5_CMD_OP_SET_ISSI:
326         case MLX5_CMD_OP_CREATE_MKEY:
327         case MLX5_CMD_OP_QUERY_MKEY:
328         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
329         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
330         case MLX5_CMD_OP_CREATE_EQ:
331         case MLX5_CMD_OP_QUERY_EQ:
332         case MLX5_CMD_OP_GEN_EQE:
333         case MLX5_CMD_OP_CREATE_CQ:
334         case MLX5_CMD_OP_QUERY_CQ:
335         case MLX5_CMD_OP_MODIFY_CQ:
336         case MLX5_CMD_OP_CREATE_QP:
337         case MLX5_CMD_OP_RST2INIT_QP:
338         case MLX5_CMD_OP_INIT2RTR_QP:
339         case MLX5_CMD_OP_RTR2RTS_QP:
340         case MLX5_CMD_OP_RTS2RTS_QP:
341         case MLX5_CMD_OP_SQERR2RTS_QP:
342         case MLX5_CMD_OP_QUERY_QP:
343         case MLX5_CMD_OP_SQD_RTS_QP:
344         case MLX5_CMD_OP_INIT2INIT_QP:
345         case MLX5_CMD_OP_CREATE_PSV:
346         case MLX5_CMD_OP_CREATE_SRQ:
347         case MLX5_CMD_OP_QUERY_SRQ:
348         case MLX5_CMD_OP_ARM_RQ:
349         case MLX5_CMD_OP_CREATE_XRC_SRQ:
350         case MLX5_CMD_OP_QUERY_XRC_SRQ:
351         case MLX5_CMD_OP_ARM_XRC_SRQ:
352         case MLX5_CMD_OP_CREATE_XRQ:
353         case MLX5_CMD_OP_QUERY_XRQ:
354         case MLX5_CMD_OP_ARM_XRQ:
355         case MLX5_CMD_OP_CREATE_DCT:
356         case MLX5_CMD_OP_DRAIN_DCT:
357         case MLX5_CMD_OP_QUERY_DCT:
358         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
359         case MLX5_CMD_OP_QUERY_VPORT_STATE:
360         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
361         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
362         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
363         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
364         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
365         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
366         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
367         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
368         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
369         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
370         case MLX5_CMD_OP_QUERY_VNIC_ENV:
371         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
372         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
373         case MLX5_CMD_OP_QUERY_Q_COUNTER:
374         case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
375         case MLX5_CMD_OP_QUERY_RATE_LIMIT:
376         case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
377         case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
378         case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
379         case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
380         case MLX5_CMD_OP_ALLOC_PD:
381         case MLX5_CMD_OP_ALLOC_UAR:
382         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
383         case MLX5_CMD_OP_ACCESS_REG:
384         case MLX5_CMD_OP_ATTACH_TO_MCG:
385         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
386         case MLX5_CMD_OP_MAD_IFC:
387         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
388         case MLX5_CMD_OP_SET_MAD_DEMUX:
389         case MLX5_CMD_OP_NOP:
390         case MLX5_CMD_OP_ALLOC_XRCD:
391         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
392         case MLX5_CMD_OP_QUERY_CONG_STATUS:
393         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
394         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
395         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
396         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
397         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
398         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
399         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
400         case MLX5_CMD_OP_CREATE_LAG:
401         case MLX5_CMD_OP_MODIFY_LAG:
402         case MLX5_CMD_OP_QUERY_LAG:
403         case MLX5_CMD_OP_CREATE_VPORT_LAG:
404         case MLX5_CMD_OP_CREATE_TIR:
405         case MLX5_CMD_OP_MODIFY_TIR:
406         case MLX5_CMD_OP_QUERY_TIR:
407         case MLX5_CMD_OP_CREATE_SQ:
408         case MLX5_CMD_OP_MODIFY_SQ:
409         case MLX5_CMD_OP_QUERY_SQ:
410         case MLX5_CMD_OP_CREATE_RQ:
411         case MLX5_CMD_OP_MODIFY_RQ:
412         case MLX5_CMD_OP_QUERY_RQ:
413         case MLX5_CMD_OP_CREATE_RMP:
414         case MLX5_CMD_OP_MODIFY_RMP:
415         case MLX5_CMD_OP_QUERY_RMP:
416         case MLX5_CMD_OP_CREATE_TIS:
417         case MLX5_CMD_OP_MODIFY_TIS:
418         case MLX5_CMD_OP_QUERY_TIS:
419         case MLX5_CMD_OP_CREATE_RQT:
420         case MLX5_CMD_OP_MODIFY_RQT:
421         case MLX5_CMD_OP_QUERY_RQT:
422
423         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
424         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
425         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
426         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
427         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
428         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
429         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
430         case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
431         case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
432         case MLX5_CMD_OP_FPGA_CREATE_QP:
433         case MLX5_CMD_OP_FPGA_MODIFY_QP:
434         case MLX5_CMD_OP_FPGA_QUERY_QP:
435         case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
436         case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
437         case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
438         case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
439         case MLX5_CMD_OP_ALLOC_MEMIC:
440                 *status = MLX5_DRIVER_STATUS_ABORTED;
441                 *synd = MLX5_DRIVER_SYND;
442                 return -EIO;
443         default:
444                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
445                 return -EINVAL;
446         }
447 }
448
449 const char *mlx5_command_str(int command)
450 {
451 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
452
453         switch (command) {
454         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
455         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
456         MLX5_COMMAND_STR_CASE(INIT_HCA);
457         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
458         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
459         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
460         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
461         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
462         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
463         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
464         MLX5_COMMAND_STR_CASE(SET_ISSI);
465         MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
466         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
467         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
468         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
469         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
470         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
471         MLX5_COMMAND_STR_CASE(CREATE_EQ);
472         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
473         MLX5_COMMAND_STR_CASE(QUERY_EQ);
474         MLX5_COMMAND_STR_CASE(GEN_EQE);
475         MLX5_COMMAND_STR_CASE(CREATE_CQ);
476         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
477         MLX5_COMMAND_STR_CASE(QUERY_CQ);
478         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
479         MLX5_COMMAND_STR_CASE(CREATE_QP);
480         MLX5_COMMAND_STR_CASE(DESTROY_QP);
481         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
482         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
483         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
484         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
485         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
486         MLX5_COMMAND_STR_CASE(2ERR_QP);
487         MLX5_COMMAND_STR_CASE(2RST_QP);
488         MLX5_COMMAND_STR_CASE(QUERY_QP);
489         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
490         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
491         MLX5_COMMAND_STR_CASE(CREATE_PSV);
492         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
493         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
494         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
495         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
496         MLX5_COMMAND_STR_CASE(ARM_RQ);
497         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
498         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
499         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
500         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
501         MLX5_COMMAND_STR_CASE(CREATE_DCT);
502         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
503         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
504         MLX5_COMMAND_STR_CASE(QUERY_DCT);
505         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
506         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
507         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
508         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
509         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
510         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
511         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
512         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
513         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
514         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
515         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
516         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
517         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
518         MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
519         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
520         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
521         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
522         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
523         MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
524         MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
525         MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
526         MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
527         MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
528         MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
529         MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
530         MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
531         MLX5_COMMAND_STR_CASE(ALLOC_PD);
532         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
533         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
534         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
535         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
536         MLX5_COMMAND_STR_CASE(ACCESS_REG);
537         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
538         MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
539         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
540         MLX5_COMMAND_STR_CASE(MAD_IFC);
541         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
542         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
543         MLX5_COMMAND_STR_CASE(NOP);
544         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
545         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
546         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
547         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
548         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
549         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
550         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
551         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
552         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
553         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
554         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
555         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
556         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
557         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
558         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
559         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
560         MLX5_COMMAND_STR_CASE(CREATE_LAG);
561         MLX5_COMMAND_STR_CASE(MODIFY_LAG);
562         MLX5_COMMAND_STR_CASE(QUERY_LAG);
563         MLX5_COMMAND_STR_CASE(DESTROY_LAG);
564         MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
565         MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
566         MLX5_COMMAND_STR_CASE(CREATE_TIR);
567         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
568         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
569         MLX5_COMMAND_STR_CASE(QUERY_TIR);
570         MLX5_COMMAND_STR_CASE(CREATE_SQ);
571         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
572         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
573         MLX5_COMMAND_STR_CASE(QUERY_SQ);
574         MLX5_COMMAND_STR_CASE(CREATE_RQ);
575         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
576         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
577         MLX5_COMMAND_STR_CASE(QUERY_RQ);
578         MLX5_COMMAND_STR_CASE(CREATE_RMP);
579         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
580         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
581         MLX5_COMMAND_STR_CASE(QUERY_RMP);
582         MLX5_COMMAND_STR_CASE(CREATE_TIS);
583         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
584         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
585         MLX5_COMMAND_STR_CASE(QUERY_TIS);
586         MLX5_COMMAND_STR_CASE(CREATE_RQT);
587         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
588         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
589         MLX5_COMMAND_STR_CASE(QUERY_RQT);
590         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
591         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
592         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
593         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
594         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
595         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
596         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
597         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
598         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
599         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
600         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
601         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
602         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
603         MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
604         MLX5_COMMAND_STR_CASE(ALLOC_PACKET_REFORMAT_CONTEXT);
605         MLX5_COMMAND_STR_CASE(DEALLOC_PACKET_REFORMAT_CONTEXT);
606         MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
607         MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
608         MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
609         MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
610         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
611         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
612         MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
613         MLX5_COMMAND_STR_CASE(CREATE_XRQ);
614         MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
615         MLX5_COMMAND_STR_CASE(QUERY_XRQ);
616         MLX5_COMMAND_STR_CASE(ARM_XRQ);
617         MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
618         MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
619         MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
620         MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT);
621         MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
622         MLX5_COMMAND_STR_CASE(ALLOC_MEMIC);
623         MLX5_COMMAND_STR_CASE(DEALLOC_MEMIC);
624         default: return "unknown command opcode";
625         }
626 }
627
628 static const char *cmd_status_str(u8 status)
629 {
630         switch (status) {
631         case MLX5_CMD_STAT_OK:
632                 return "OK";
633         case MLX5_CMD_STAT_INT_ERR:
634                 return "internal error";
635         case MLX5_CMD_STAT_BAD_OP_ERR:
636                 return "bad operation";
637         case MLX5_CMD_STAT_BAD_PARAM_ERR:
638                 return "bad parameter";
639         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
640                 return "bad system state";
641         case MLX5_CMD_STAT_BAD_RES_ERR:
642                 return "bad resource";
643         case MLX5_CMD_STAT_RES_BUSY:
644                 return "resource busy";
645         case MLX5_CMD_STAT_LIM_ERR:
646                 return "limits exceeded";
647         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
648                 return "bad resource state";
649         case MLX5_CMD_STAT_IX_ERR:
650                 return "bad index";
651         case MLX5_CMD_STAT_NO_RES_ERR:
652                 return "no resources";
653         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
654                 return "bad input length";
655         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
656                 return "bad output length";
657         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
658                 return "bad QP state";
659         case MLX5_CMD_STAT_BAD_PKT_ERR:
660                 return "bad packet (discarded)";
661         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
662                 return "bad size too many outstanding CQEs";
663         default:
664                 return "unknown status";
665         }
666 }
667
668 static int cmd_status_to_err(u8 status)
669 {
670         switch (status) {
671         case MLX5_CMD_STAT_OK:                          return 0;
672         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
673         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
674         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
675         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
676         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
677         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
678         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
679         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
680         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
681         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
682         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
683         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
684         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
685         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
686         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
687         default:                                        return -EIO;
688         }
689 }
690
691 struct mlx5_ifc_mbox_out_bits {
692         u8         status[0x8];
693         u8         reserved_at_8[0x18];
694
695         u8         syndrome[0x20];
696
697         u8         reserved_at_40[0x40];
698 };
699
700 struct mlx5_ifc_mbox_in_bits {
701         u8         opcode[0x10];
702         u8         uid[0x10];
703
704         u8         reserved_at_20[0x10];
705         u8         op_mod[0x10];
706
707         u8         reserved_at_40[0x40];
708 };
709
710 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
711 {
712         *status = MLX5_GET(mbox_out, out, status);
713         *syndrome = MLX5_GET(mbox_out, out, syndrome);
714 }
715
716 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
717 {
718         u32 syndrome;
719         u8  status;
720         u16 opcode;
721         u16 op_mod;
722         u16 uid;
723
724         mlx5_cmd_mbox_status(out, &status, &syndrome);
725         if (!status)
726                 return 0;
727
728         opcode = MLX5_GET(mbox_in, in, opcode);
729         op_mod = MLX5_GET(mbox_in, in, op_mod);
730         uid    = MLX5_GET(mbox_in, in, uid);
731
732         if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
733                 mlx5_core_err_rl(dev,
734                         "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
735                         mlx5_command_str(opcode), opcode, op_mod,
736                         cmd_status_str(status), status, syndrome);
737         else
738                 mlx5_core_dbg(dev,
739                       "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
740                       mlx5_command_str(opcode),
741                       opcode, op_mod,
742                       cmd_status_str(status),
743                       status,
744                       syndrome);
745
746         return cmd_status_to_err(status);
747 }
748
749 static void dump_command(struct mlx5_core_dev *dev,
750                          struct mlx5_cmd_work_ent *ent, int input)
751 {
752         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
753         u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
754         struct mlx5_cmd_mailbox *next = msg->next;
755         int n = mlx5_calc_cmd_blocks(msg);
756         int data_only;
757         u32 offset = 0;
758         int dump_len;
759         int i;
760
761         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
762
763         if (data_only)
764                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
765                                    "dump command data %s(0x%x) %s\n",
766                                    mlx5_command_str(op), op,
767                                    input ? "INPUT" : "OUTPUT");
768         else
769                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
770                               mlx5_command_str(op), op,
771                               input ? "INPUT" : "OUTPUT");
772
773         if (data_only) {
774                 if (input) {
775                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
776                         offset += sizeof(ent->lay->in);
777                 } else {
778                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
779                         offset += sizeof(ent->lay->out);
780                 }
781         } else {
782                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
783                 offset += sizeof(*ent->lay);
784         }
785
786         for (i = 0; i < n && next; i++)  {
787                 if (data_only) {
788                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
789                         dump_buf(next->buf, dump_len, 1, offset);
790                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
791                 } else {
792                         mlx5_core_dbg(dev, "command block:\n");
793                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
794                         offset += sizeof(struct mlx5_cmd_prot_block);
795                 }
796                 next = next->next;
797         }
798
799         if (data_only)
800                 pr_debug("\n");
801 }
802
803 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
804 {
805         return MLX5_GET(mbox_in, in->first.data, opcode);
806 }
807
808 static void cb_timeout_handler(struct work_struct *work)
809 {
810         struct delayed_work *dwork = container_of(work, struct delayed_work,
811                                                   work);
812         struct mlx5_cmd_work_ent *ent = container_of(dwork,
813                                                      struct mlx5_cmd_work_ent,
814                                                      cb_timeout_work);
815         struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
816                                                  cmd);
817
818         ent->ret = -ETIMEDOUT;
819         mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
820                        mlx5_command_str(msg_to_opcode(ent->in)),
821                        msg_to_opcode(ent->in));
822         mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
823 }
824
825 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
826 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
827                               struct mlx5_cmd_msg *msg);
828
829 static void cmd_work_handler(struct work_struct *work)
830 {
831         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
832         struct mlx5_cmd *cmd = ent->cmd;
833         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
834         unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
835         struct mlx5_cmd_layout *lay;
836         struct semaphore *sem;
837         unsigned long flags;
838         bool poll_cmd = ent->polling;
839         int alloc_ret;
840         int cmd_mode;
841
842         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
843         down(sem);
844         if (!ent->page_queue) {
845                 alloc_ret = alloc_ent(cmd);
846                 if (alloc_ret < 0) {
847                         mlx5_core_err(dev, "failed to allocate command entry\n");
848                         if (ent->callback) {
849                                 ent->callback(-EAGAIN, ent->context);
850                                 mlx5_free_cmd_msg(dev, ent->out);
851                                 free_msg(dev, ent->in);
852                                 free_cmd(ent);
853                         } else {
854                                 ent->ret = -EAGAIN;
855                                 complete(&ent->done);
856                         }
857                         up(sem);
858                         return;
859                 }
860                 ent->idx = alloc_ret;
861         } else {
862                 ent->idx = cmd->max_reg_cmds;
863                 spin_lock_irqsave(&cmd->alloc_lock, flags);
864                 clear_bit(ent->idx, &cmd->bitmask);
865                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
866         }
867
868         cmd->ent_arr[ent->idx] = ent;
869         set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
870         lay = get_inst(cmd, ent->idx);
871         ent->lay = lay;
872         memset(lay, 0, sizeof(*lay));
873         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
874         ent->op = be32_to_cpu(lay->in[0]) >> 16;
875         if (ent->in->next)
876                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
877         lay->inlen = cpu_to_be32(ent->in->len);
878         if (ent->out->next)
879                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
880         lay->outlen = cpu_to_be32(ent->out->len);
881         lay->type = MLX5_PCI_CMD_XPORT;
882         lay->token = ent->token;
883         lay->status_own = CMD_OWNER_HW;
884         set_signature(ent, !cmd->checksum_disabled);
885         dump_command(dev, ent, 1);
886         ent->ts1 = ktime_get_ns();
887         cmd_mode = cmd->mode;
888
889         if (ent->callback)
890                 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
891
892         /* Skip sending command to fw if internal error */
893         if (pci_channel_offline(dev->pdev) ||
894             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
895                 u8 status = 0;
896                 u32 drv_synd;
897
898                 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
899                 MLX5_SET(mbox_out, ent->out, status, status);
900                 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
901
902                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
903                 return;
904         }
905
906         /* ring doorbell after the descriptor is valid */
907         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
908         wmb();
909         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
910         mmiowb();
911         /* if not in polling don't use ent after this point */
912         if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
913                 poll_timeout(ent);
914                 /* make sure we read the descriptor after ownership is SW */
915                 rmb();
916                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
917         }
918 }
919
920 static const char *deliv_status_to_str(u8 status)
921 {
922         switch (status) {
923         case MLX5_CMD_DELIVERY_STAT_OK:
924                 return "no errors";
925         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
926                 return "signature error";
927         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
928                 return "token error";
929         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
930                 return "bad block number";
931         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
932                 return "output pointer not aligned to block size";
933         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
934                 return "input pointer not aligned to block size";
935         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
936                 return "firmware internal error";
937         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
938                 return "command input length error";
939         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
940                 return "command output length error";
941         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
942                 return "reserved fields not cleared";
943         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
944                 return "bad command descriptor type";
945         default:
946                 return "unknown status code";
947         }
948 }
949
950 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
951 {
952         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
953         struct mlx5_cmd *cmd = &dev->cmd;
954         int err;
955
956         if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
957                 wait_for_completion(&ent->done);
958         } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
959                 ent->ret = -ETIMEDOUT;
960                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
961         }
962
963         err = ent->ret;
964
965         if (err == -ETIMEDOUT) {
966                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
967                                mlx5_command_str(msg_to_opcode(ent->in)),
968                                msg_to_opcode(ent->in));
969         }
970         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
971                       err, deliv_status_to_str(ent->status), ent->status);
972
973         return err;
974 }
975
976 /*  Notes:
977  *    1. Callback functions may not sleep
978  *    2. page queue commands do not support asynchrous completion
979  */
980 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
981                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
982                            mlx5_cmd_cbk_t callback,
983                            void *context, int page_queue, u8 *status,
984                            u8 token, bool force_polling)
985 {
986         struct mlx5_cmd *cmd = &dev->cmd;
987         struct mlx5_cmd_work_ent *ent;
988         struct mlx5_cmd_stats *stats;
989         int err = 0;
990         s64 ds;
991         u16 op;
992
993         if (callback && page_queue)
994                 return -EINVAL;
995
996         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
997                         page_queue);
998         if (IS_ERR(ent))
999                 return PTR_ERR(ent);
1000
1001         ent->token = token;
1002         ent->polling = force_polling;
1003
1004         if (!callback)
1005                 init_completion(&ent->done);
1006
1007         INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
1008         INIT_WORK(&ent->work, cmd_work_handler);
1009         if (page_queue) {
1010                 cmd_work_handler(&ent->work);
1011         } else if (!queue_work(cmd->wq, &ent->work)) {
1012                 mlx5_core_warn(dev, "failed to queue work\n");
1013                 err = -ENOMEM;
1014                 goto out_free;
1015         }
1016
1017         if (callback)
1018                 goto out;
1019
1020         err = wait_func(dev, ent);
1021         if (err == -ETIMEDOUT)
1022                 goto out;
1023
1024         ds = ent->ts2 - ent->ts1;
1025         op = MLX5_GET(mbox_in, in->first.data, opcode);
1026         if (op < ARRAY_SIZE(cmd->stats)) {
1027                 stats = &cmd->stats[op];
1028                 spin_lock_irq(&stats->lock);
1029                 stats->sum += ds;
1030                 ++stats->n;
1031                 spin_unlock_irq(&stats->lock);
1032         }
1033         mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1034                            "fw exec time for %s is %lld nsec\n",
1035                            mlx5_command_str(op), ds);
1036         *status = ent->status;
1037
1038 out_free:
1039         free_cmd(ent);
1040 out:
1041         return err;
1042 }
1043
1044 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1045                          size_t count, loff_t *pos)
1046 {
1047         struct mlx5_core_dev *dev = filp->private_data;
1048         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1049         char lbuf[3];
1050         int err;
1051
1052         if (!dbg->in_msg || !dbg->out_msg)
1053                 return -ENOMEM;
1054
1055         if (count < sizeof(lbuf) - 1)
1056                 return -EINVAL;
1057
1058         if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1059                 return -EFAULT;
1060
1061         lbuf[sizeof(lbuf) - 1] = 0;
1062
1063         if (strcmp(lbuf, "go"))
1064                 return -EINVAL;
1065
1066         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1067
1068         return err ? err : count;
1069 }
1070
1071 static const struct file_operations fops = {
1072         .owner  = THIS_MODULE,
1073         .open   = simple_open,
1074         .write  = dbg_write,
1075 };
1076
1077 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1078                             u8 token)
1079 {
1080         struct mlx5_cmd_prot_block *block;
1081         struct mlx5_cmd_mailbox *next;
1082         int copy;
1083
1084         if (!to || !from)
1085                 return -ENOMEM;
1086
1087         copy = min_t(int, size, sizeof(to->first.data));
1088         memcpy(to->first.data, from, copy);
1089         size -= copy;
1090         from += copy;
1091
1092         next = to->next;
1093         while (size) {
1094                 if (!next) {
1095                         /* this is a BUG */
1096                         return -ENOMEM;
1097                 }
1098
1099                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1100                 block = next->buf;
1101                 memcpy(block->data, from, copy);
1102                 from += copy;
1103                 size -= copy;
1104                 block->token = token;
1105                 next = next->next;
1106         }
1107
1108         return 0;
1109 }
1110
1111 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1112 {
1113         struct mlx5_cmd_prot_block *block;
1114         struct mlx5_cmd_mailbox *next;
1115         int copy;
1116
1117         if (!to || !from)
1118                 return -ENOMEM;
1119
1120         copy = min_t(int, size, sizeof(from->first.data));
1121         memcpy(to, from->first.data, copy);
1122         size -= copy;
1123         to += copy;
1124
1125         next = from->next;
1126         while (size) {
1127                 if (!next) {
1128                         /* this is a BUG */
1129                         return -ENOMEM;
1130                 }
1131
1132                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1133                 block = next->buf;
1134
1135                 memcpy(to, block->data, copy);
1136                 to += copy;
1137                 size -= copy;
1138                 next = next->next;
1139         }
1140
1141         return 0;
1142 }
1143
1144 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1145                                               gfp_t flags)
1146 {
1147         struct mlx5_cmd_mailbox *mailbox;
1148
1149         mailbox = kmalloc(sizeof(*mailbox), flags);
1150         if (!mailbox)
1151                 return ERR_PTR(-ENOMEM);
1152
1153         mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1154                                        &mailbox->dma);
1155         if (!mailbox->buf) {
1156                 mlx5_core_dbg(dev, "failed allocation\n");
1157                 kfree(mailbox);
1158                 return ERR_PTR(-ENOMEM);
1159         }
1160         mailbox->next = NULL;
1161
1162         return mailbox;
1163 }
1164
1165 static void free_cmd_box(struct mlx5_core_dev *dev,
1166                          struct mlx5_cmd_mailbox *mailbox)
1167 {
1168         dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1169         kfree(mailbox);
1170 }
1171
1172 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1173                                                gfp_t flags, int size,
1174                                                u8 token)
1175 {
1176         struct mlx5_cmd_mailbox *tmp, *head = NULL;
1177         struct mlx5_cmd_prot_block *block;
1178         struct mlx5_cmd_msg *msg;
1179         int err;
1180         int n;
1181         int i;
1182
1183         msg = kzalloc(sizeof(*msg), flags);
1184         if (!msg)
1185                 return ERR_PTR(-ENOMEM);
1186
1187         msg->len = size;
1188         n = mlx5_calc_cmd_blocks(msg);
1189
1190         for (i = 0; i < n; i++) {
1191                 tmp = alloc_cmd_box(dev, flags);
1192                 if (IS_ERR(tmp)) {
1193                         mlx5_core_warn(dev, "failed allocating block\n");
1194                         err = PTR_ERR(tmp);
1195                         goto err_alloc;
1196                 }
1197
1198                 block = tmp->buf;
1199                 tmp->next = head;
1200                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1201                 block->block_num = cpu_to_be32(n - i - 1);
1202                 block->token = token;
1203                 head = tmp;
1204         }
1205         msg->next = head;
1206         return msg;
1207
1208 err_alloc:
1209         while (head) {
1210                 tmp = head->next;
1211                 free_cmd_box(dev, head);
1212                 head = tmp;
1213         }
1214         kfree(msg);
1215
1216         return ERR_PTR(err);
1217 }
1218
1219 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1220                               struct mlx5_cmd_msg *msg)
1221 {
1222         struct mlx5_cmd_mailbox *head = msg->next;
1223         struct mlx5_cmd_mailbox *next;
1224
1225         while (head) {
1226                 next = head->next;
1227                 free_cmd_box(dev, head);
1228                 head = next;
1229         }
1230         kfree(msg);
1231 }
1232
1233 static ssize_t data_write(struct file *filp, const char __user *buf,
1234                           size_t count, loff_t *pos)
1235 {
1236         struct mlx5_core_dev *dev = filp->private_data;
1237         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1238         void *ptr;
1239
1240         if (*pos != 0)
1241                 return -EINVAL;
1242
1243         kfree(dbg->in_msg);
1244         dbg->in_msg = NULL;
1245         dbg->inlen = 0;
1246         ptr = memdup_user(buf, count);
1247         if (IS_ERR(ptr))
1248                 return PTR_ERR(ptr);
1249         dbg->in_msg = ptr;
1250         dbg->inlen = count;
1251
1252         *pos = count;
1253
1254         return count;
1255 }
1256
1257 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1258                          loff_t *pos)
1259 {
1260         struct mlx5_core_dev *dev = filp->private_data;
1261         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1262
1263         if (!dbg->out_msg)
1264                 return -ENOMEM;
1265
1266         return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1267                                        dbg->outlen);
1268 }
1269
1270 static const struct file_operations dfops = {
1271         .owner  = THIS_MODULE,
1272         .open   = simple_open,
1273         .write  = data_write,
1274         .read   = data_read,
1275 };
1276
1277 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1278                            loff_t *pos)
1279 {
1280         struct mlx5_core_dev *dev = filp->private_data;
1281         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1282         char outlen[8];
1283         int err;
1284
1285         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1286         if (err < 0)
1287                 return err;
1288
1289         return simple_read_from_buffer(buf, count, pos, outlen, err);
1290 }
1291
1292 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1293                             size_t count, loff_t *pos)
1294 {
1295         struct mlx5_core_dev *dev = filp->private_data;
1296         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1297         char outlen_str[8] = {0};
1298         int outlen;
1299         void *ptr;
1300         int err;
1301
1302         if (*pos != 0 || count > 6)
1303                 return -EINVAL;
1304
1305         kfree(dbg->out_msg);
1306         dbg->out_msg = NULL;
1307         dbg->outlen = 0;
1308
1309         if (copy_from_user(outlen_str, buf, count))
1310                 return -EFAULT;
1311
1312         err = sscanf(outlen_str, "%d", &outlen);
1313         if (err < 0)
1314                 return err;
1315
1316         ptr = kzalloc(outlen, GFP_KERNEL);
1317         if (!ptr)
1318                 return -ENOMEM;
1319
1320         dbg->out_msg = ptr;
1321         dbg->outlen = outlen;
1322
1323         *pos = count;
1324
1325         return count;
1326 }
1327
1328 static const struct file_operations olfops = {
1329         .owner  = THIS_MODULE,
1330         .open   = simple_open,
1331         .write  = outlen_write,
1332         .read   = outlen_read,
1333 };
1334
1335 static void set_wqname(struct mlx5_core_dev *dev)
1336 {
1337         struct mlx5_cmd *cmd = &dev->cmd;
1338
1339         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1340                  dev_name(&dev->pdev->dev));
1341 }
1342
1343 static void clean_debug_files(struct mlx5_core_dev *dev)
1344 {
1345         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1346
1347         if (!mlx5_debugfs_root)
1348                 return;
1349
1350         mlx5_cmdif_debugfs_cleanup(dev);
1351         debugfs_remove_recursive(dbg->dbg_root);
1352 }
1353
1354 static int create_debugfs_files(struct mlx5_core_dev *dev)
1355 {
1356         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1357         int err = -ENOMEM;
1358
1359         if (!mlx5_debugfs_root)
1360                 return 0;
1361
1362         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1363         if (!dbg->dbg_root)
1364                 return err;
1365
1366         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1367                                           dev, &dfops);
1368         if (!dbg->dbg_in)
1369                 goto err_dbg;
1370
1371         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1372                                            dev, &dfops);
1373         if (!dbg->dbg_out)
1374                 goto err_dbg;
1375
1376         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1377                                               dev, &olfops);
1378         if (!dbg->dbg_outlen)
1379                 goto err_dbg;
1380
1381         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1382                                             &dbg->status);
1383         if (!dbg->dbg_status)
1384                 goto err_dbg;
1385
1386         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1387         if (!dbg->dbg_run)
1388                 goto err_dbg;
1389
1390         mlx5_cmdif_debugfs_init(dev);
1391
1392         return 0;
1393
1394 err_dbg:
1395         clean_debug_files(dev);
1396         return err;
1397 }
1398
1399 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1400 {
1401         struct mlx5_cmd *cmd = &dev->cmd;
1402         int i;
1403
1404         for (i = 0; i < cmd->max_reg_cmds; i++)
1405                 down(&cmd->sem);
1406         down(&cmd->pages_sem);
1407
1408         cmd->mode = mode;
1409
1410         up(&cmd->pages_sem);
1411         for (i = 0; i < cmd->max_reg_cmds; i++)
1412                 up(&cmd->sem);
1413 }
1414
1415 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1416 {
1417         mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1418 }
1419
1420 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1421 {
1422         mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1423 }
1424
1425 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1426 {
1427         unsigned long flags;
1428
1429         if (msg->parent) {
1430                 spin_lock_irqsave(&msg->parent->lock, flags);
1431                 list_add_tail(&msg->list, &msg->parent->head);
1432                 spin_unlock_irqrestore(&msg->parent->lock, flags);
1433         } else {
1434                 mlx5_free_cmd_msg(dev, msg);
1435         }
1436 }
1437
1438 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1439 {
1440         struct mlx5_cmd *cmd = &dev->cmd;
1441         struct mlx5_cmd_work_ent *ent;
1442         mlx5_cmd_cbk_t callback;
1443         void *context;
1444         int err;
1445         int i;
1446         s64 ds;
1447         struct mlx5_cmd_stats *stats;
1448         unsigned long flags;
1449         unsigned long vector;
1450
1451         /* there can be at most 32 command queues */
1452         vector = vec & 0xffffffff;
1453         for (i = 0; i < (1 << cmd->log_sz); i++) {
1454                 if (test_bit(i, &vector)) {
1455                         struct semaphore *sem;
1456
1457                         ent = cmd->ent_arr[i];
1458
1459                         /* if we already completed the command, ignore it */
1460                         if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1461                                                 &ent->state)) {
1462                                 /* only real completion can free the cmd slot */
1463                                 if (!forced) {
1464                                         mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1465                                                       ent->idx);
1466                                         free_ent(cmd, ent->idx);
1467                                         free_cmd(ent);
1468                                 }
1469                                 continue;
1470                         }
1471
1472                         if (ent->callback)
1473                                 cancel_delayed_work(&ent->cb_timeout_work);
1474                         if (ent->page_queue)
1475                                 sem = &cmd->pages_sem;
1476                         else
1477                                 sem = &cmd->sem;
1478                         ent->ts2 = ktime_get_ns();
1479                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1480                         dump_command(dev, ent, 0);
1481                         if (!ent->ret) {
1482                                 if (!cmd->checksum_disabled)
1483                                         ent->ret = verify_signature(ent);
1484                                 else
1485                                         ent->ret = 0;
1486                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1487                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1488                                 else
1489                                         ent->status = ent->lay->status_own >> 1;
1490
1491                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1492                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1493                         }
1494
1495                         /* only real completion will free the entry slot */
1496                         if (!forced)
1497                                 free_ent(cmd, ent->idx);
1498
1499                         if (ent->callback) {
1500                                 ds = ent->ts2 - ent->ts1;
1501                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1502                                         stats = &cmd->stats[ent->op];
1503                                         spin_lock_irqsave(&stats->lock, flags);
1504                                         stats->sum += ds;
1505                                         ++stats->n;
1506                                         spin_unlock_irqrestore(&stats->lock, flags);
1507                                 }
1508
1509                                 callback = ent->callback;
1510                                 context = ent->context;
1511                                 err = ent->ret;
1512                                 if (!err) {
1513                                         err = mlx5_copy_from_msg(ent->uout,
1514                                                                  ent->out,
1515                                                                  ent->uout_size);
1516
1517                                         err = err ? err : mlx5_cmd_check(dev,
1518                                                                         ent->in->first.data,
1519                                                                         ent->uout);
1520                                 }
1521
1522                                 mlx5_free_cmd_msg(dev, ent->out);
1523                                 free_msg(dev, ent->in);
1524
1525                                 err = err ? err : ent->status;
1526                                 if (!forced)
1527                                         free_cmd(ent);
1528                                 callback(err, context);
1529                         } else {
1530                                 complete(&ent->done);
1531                         }
1532                         up(sem);
1533                 }
1534         }
1535 }
1536 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1537
1538 static int status_to_err(u8 status)
1539 {
1540         return status ? -1 : 0; /* TBD more meaningful codes */
1541 }
1542
1543 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1544                                       gfp_t gfp)
1545 {
1546         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1547         struct cmd_msg_cache *ch = NULL;
1548         struct mlx5_cmd *cmd = &dev->cmd;
1549         int i;
1550
1551         if (in_size <= 16)
1552                 goto cache_miss;
1553
1554         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1555                 ch = &cmd->cache[i];
1556                 if (in_size > ch->max_inbox_size)
1557                         continue;
1558                 spin_lock_irq(&ch->lock);
1559                 if (list_empty(&ch->head)) {
1560                         spin_unlock_irq(&ch->lock);
1561                         continue;
1562                 }
1563                 msg = list_entry(ch->head.next, typeof(*msg), list);
1564                 /* For cached lists, we must explicitly state what is
1565                  * the real size
1566                  */
1567                 msg->len = in_size;
1568                 list_del(&msg->list);
1569                 spin_unlock_irq(&ch->lock);
1570                 break;
1571         }
1572
1573         if (!IS_ERR(msg))
1574                 return msg;
1575
1576 cache_miss:
1577         msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1578         return msg;
1579 }
1580
1581 static int is_manage_pages(void *in)
1582 {
1583         return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1584 }
1585
1586 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1587                     int out_size, mlx5_cmd_cbk_t callback, void *context,
1588                     bool force_polling)
1589 {
1590         struct mlx5_cmd_msg *inb;
1591         struct mlx5_cmd_msg *outb;
1592         int pages_queue;
1593         gfp_t gfp;
1594         int err;
1595         u8 status = 0;
1596         u32 drv_synd;
1597         u8 token;
1598
1599         if (pci_channel_offline(dev->pdev) ||
1600             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1601                 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1602
1603                 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1604                 MLX5_SET(mbox_out, out, status, status);
1605                 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1606                 return err;
1607         }
1608
1609         pages_queue = is_manage_pages(in);
1610         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1611
1612         inb = alloc_msg(dev, in_size, gfp);
1613         if (IS_ERR(inb)) {
1614                 err = PTR_ERR(inb);
1615                 return err;
1616         }
1617
1618         token = alloc_token(&dev->cmd);
1619
1620         err = mlx5_copy_to_msg(inb, in, in_size, token);
1621         if (err) {
1622                 mlx5_core_warn(dev, "err %d\n", err);
1623                 goto out_in;
1624         }
1625
1626         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1627         if (IS_ERR(outb)) {
1628                 err = PTR_ERR(outb);
1629                 goto out_in;
1630         }
1631
1632         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1633                               pages_queue, &status, token, force_polling);
1634         if (err)
1635                 goto out_out;
1636
1637         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1638         if (status) {
1639                 err = status_to_err(status);
1640                 goto out_out;
1641         }
1642
1643         if (!callback)
1644                 err = mlx5_copy_from_msg(out, outb, out_size);
1645
1646 out_out:
1647         if (!callback)
1648                 mlx5_free_cmd_msg(dev, outb);
1649
1650 out_in:
1651         if (!callback)
1652                 free_msg(dev, inb);
1653         return err;
1654 }
1655
1656 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1657                   int out_size)
1658 {
1659         int err;
1660
1661         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1662         return err ? : mlx5_cmd_check(dev, in, out);
1663 }
1664 EXPORT_SYMBOL(mlx5_cmd_exec);
1665
1666 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1667                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1668                      void *context)
1669 {
1670         return cmd_exec(dev, in, in_size, out, out_size, callback, context,
1671                         false);
1672 }
1673 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1674
1675 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1676                           void *out, int out_size)
1677 {
1678         int err;
1679
1680         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1681
1682         return err ? : mlx5_cmd_check(dev, in, out);
1683 }
1684 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1685
1686 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1687 {
1688         struct cmd_msg_cache *ch;
1689         struct mlx5_cmd_msg *msg;
1690         struct mlx5_cmd_msg *n;
1691         int i;
1692
1693         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1694                 ch = &dev->cmd.cache[i];
1695                 list_for_each_entry_safe(msg, n, &ch->head, list) {
1696                         list_del(&msg->list);
1697                         mlx5_free_cmd_msg(dev, msg);
1698                 }
1699         }
1700 }
1701
1702 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1703         512, 32, 16, 8, 2
1704 };
1705
1706 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1707         16 + MLX5_CMD_DATA_BLOCK_SIZE,
1708         16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1709         16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1710         16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1711         16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1712 };
1713
1714 static void create_msg_cache(struct mlx5_core_dev *dev)
1715 {
1716         struct mlx5_cmd *cmd = &dev->cmd;
1717         struct cmd_msg_cache *ch;
1718         struct mlx5_cmd_msg *msg;
1719         int i;
1720         int k;
1721
1722         /* Initialize and fill the caches with initial entries */
1723         for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1724                 ch = &cmd->cache[k];
1725                 spin_lock_init(&ch->lock);
1726                 INIT_LIST_HEAD(&ch->head);
1727                 ch->num_ent = cmd_cache_num_ent[k];
1728                 ch->max_inbox_size = cmd_cache_ent_size[k];
1729                 for (i = 0; i < ch->num_ent; i++) {
1730                         msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1731                                                  ch->max_inbox_size, 0);
1732                         if (IS_ERR(msg))
1733                                 break;
1734                         msg->parent = ch;
1735                         list_add_tail(&msg->list, &ch->head);
1736                 }
1737         }
1738 }
1739
1740 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1741 {
1742         struct device *ddev = &dev->pdev->dev;
1743
1744         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1745                                                  &cmd->alloc_dma, GFP_KERNEL);
1746         if (!cmd->cmd_alloc_buf)
1747                 return -ENOMEM;
1748
1749         /* make sure it is aligned to 4K */
1750         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1751                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1752                 cmd->dma = cmd->alloc_dma;
1753                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1754                 return 0;
1755         }
1756
1757         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1758                           cmd->alloc_dma);
1759         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1760                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1761                                                  &cmd->alloc_dma, GFP_KERNEL);
1762         if (!cmd->cmd_alloc_buf)
1763                 return -ENOMEM;
1764
1765         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1766         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1767         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1768         return 0;
1769 }
1770
1771 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1772 {
1773         struct device *ddev = &dev->pdev->dev;
1774
1775         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1776                           cmd->alloc_dma);
1777 }
1778
1779 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1780 {
1781         int size = sizeof(struct mlx5_cmd_prot_block);
1782         int align = roundup_pow_of_two(size);
1783         struct mlx5_cmd *cmd = &dev->cmd;
1784         u32 cmd_h, cmd_l;
1785         u16 cmd_if_rev;
1786         int err;
1787         int i;
1788
1789         memset(cmd, 0, sizeof(*cmd));
1790         cmd_if_rev = cmdif_rev(dev);
1791         if (cmd_if_rev != CMD_IF_REV) {
1792                 dev_err(&dev->pdev->dev,
1793                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1794                         CMD_IF_REV, cmd_if_rev);
1795                 return -EINVAL;
1796         }
1797
1798         cmd->pool = dma_pool_create("mlx5_cmd", &dev->pdev->dev, size, align,
1799                                     0);
1800         if (!cmd->pool)
1801                 return -ENOMEM;
1802
1803         err = alloc_cmd_page(dev, cmd);
1804         if (err)
1805                 goto err_free_pool;
1806
1807         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1808         cmd->log_sz = cmd_l >> 4 & 0xf;
1809         cmd->log_stride = cmd_l & 0xf;
1810         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1811                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1812                         1 << cmd->log_sz);
1813                 err = -EINVAL;
1814                 goto err_free_page;
1815         }
1816
1817         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1818                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1819                 err = -EINVAL;
1820                 goto err_free_page;
1821         }
1822
1823         cmd->checksum_disabled = 1;
1824         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1825         cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
1826
1827         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1828         if (cmd->cmdif_rev > CMD_IF_REV) {
1829                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1830                         CMD_IF_REV, cmd->cmdif_rev);
1831                 err = -EOPNOTSUPP;
1832                 goto err_free_page;
1833         }
1834
1835         spin_lock_init(&cmd->alloc_lock);
1836         spin_lock_init(&cmd->token_lock);
1837         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1838                 spin_lock_init(&cmd->stats[i].lock);
1839
1840         sema_init(&cmd->sem, cmd->max_reg_cmds);
1841         sema_init(&cmd->pages_sem, 1);
1842
1843         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1844         cmd_l = (u32)(cmd->dma);
1845         if (cmd_l & 0xfff) {
1846                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1847                 err = -ENOMEM;
1848                 goto err_free_page;
1849         }
1850
1851         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1852         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1853
1854         /* Make sure firmware sees the complete address before we proceed */
1855         wmb();
1856
1857         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1858
1859         cmd->mode = CMD_MODE_POLLING;
1860
1861         create_msg_cache(dev);
1862
1863         set_wqname(dev);
1864         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1865         if (!cmd->wq) {
1866                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1867                 err = -ENOMEM;
1868                 goto err_cache;
1869         }
1870
1871         err = create_debugfs_files(dev);
1872         if (err) {
1873                 err = -ENOMEM;
1874                 goto err_wq;
1875         }
1876
1877         return 0;
1878
1879 err_wq:
1880         destroy_workqueue(cmd->wq);
1881
1882 err_cache:
1883         destroy_msg_cache(dev);
1884
1885 err_free_page:
1886         free_cmd_page(dev, cmd);
1887
1888 err_free_pool:
1889         dma_pool_destroy(cmd->pool);
1890
1891         return err;
1892 }
1893 EXPORT_SYMBOL(mlx5_cmd_init);
1894
1895 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1896 {
1897         struct mlx5_cmd *cmd = &dev->cmd;
1898
1899         clean_debug_files(dev);
1900         destroy_workqueue(cmd->wq);
1901         destroy_msg_cache(dev);
1902         free_cmd_page(dev, cmd);
1903         dma_pool_destroy(cmd->pool);
1904 }
1905 EXPORT_SYMBOL(mlx5_cmd_cleanup);