10517b2a0643f183c0026296da1cf49bc9e002a6
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / cmd.c
1 /*
2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/debugfs.h>
44
45 #include "mlx5_core.h"
46
47 enum {
48         CMD_IF_REV = 5,
49 };
50
51 enum {
52         CMD_MODE_POLLING,
53         CMD_MODE_EVENTS
54 };
55
56 enum {
57         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
58         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
59         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
60         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
61         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
62         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
63         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
64         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
65         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
66         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
67         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
68 };
69
70 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
71                                            struct mlx5_cmd_msg *in,
72                                            struct mlx5_cmd_msg *out,
73                                            void *uout, int uout_size,
74                                            mlx5_cmd_cbk_t cbk,
75                                            void *context, int page_queue)
76 {
77         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
78         struct mlx5_cmd_work_ent *ent;
79
80         ent = kzalloc(sizeof(*ent), alloc_flags);
81         if (!ent)
82                 return ERR_PTR(-ENOMEM);
83
84         ent->in         = in;
85         ent->out        = out;
86         ent->uout       = uout;
87         ent->uout_size  = uout_size;
88         ent->callback   = cbk;
89         ent->context    = context;
90         ent->cmd        = cmd;
91         ent->page_queue = page_queue;
92
93         return ent;
94 }
95
96 static u8 alloc_token(struct mlx5_cmd *cmd)
97 {
98         u8 token;
99
100         spin_lock(&cmd->token_lock);
101         cmd->token++;
102         if (cmd->token == 0)
103                 cmd->token++;
104         token = cmd->token;
105         spin_unlock(&cmd->token_lock);
106
107         return token;
108 }
109
110 static int alloc_ent(struct mlx5_cmd *cmd)
111 {
112         unsigned long flags;
113         int ret;
114
115         spin_lock_irqsave(&cmd->alloc_lock, flags);
116         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
117         if (ret < cmd->max_reg_cmds)
118                 clear_bit(ret, &cmd->bitmask);
119         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
120
121         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
122 }
123
124 static void free_ent(struct mlx5_cmd *cmd, int idx)
125 {
126         unsigned long flags;
127
128         spin_lock_irqsave(&cmd->alloc_lock, flags);
129         set_bit(idx, &cmd->bitmask);
130         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
131 }
132
133 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
134 {
135         return cmd->cmd_buf + (idx << cmd->log_stride);
136 }
137
138 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
139 {
140         int size = msg->len;
141         int blen = size - min_t(int, sizeof(msg->first.data), size);
142
143         return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
144 }
145
146 static u8 xor8_buf(void *buf, size_t offset, int len)
147 {
148         u8 *ptr = buf;
149         u8 sum = 0;
150         int i;
151         int end = len + offset;
152
153         for (i = offset; i < end; i++)
154                 sum ^= ptr[i];
155
156         return sum;
157 }
158
159 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
160 {
161         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
162         int xor_len = sizeof(*block) - sizeof(block->data) - 1;
163
164         if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
165                 return -EINVAL;
166
167         if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
168                 return -EINVAL;
169
170         return 0;
171 }
172
173 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
174 {
175         int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
176         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
177
178         block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
179         block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
180 }
181
182 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
183 {
184         struct mlx5_cmd_mailbox *next = msg->next;
185         int n = mlx5_calc_cmd_blocks(msg);
186         int i = 0;
187
188         for (i = 0; i < n && next; i++)  {
189                 calc_block_sig(next->buf);
190                 next = next->next;
191         }
192 }
193
194 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
195 {
196         ent->lay->sig = ~xor8_buf(ent->lay, 0,  sizeof(*ent->lay));
197         if (csum) {
198                 calc_chain_sig(ent->in);
199                 calc_chain_sig(ent->out);
200         }
201 }
202
203 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
204 {
205         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
206         u8 own;
207
208         do {
209                 own = ent->lay->status_own;
210                 if (!(own & CMD_OWNER_HW)) {
211                         ent->ret = 0;
212                         return;
213                 }
214                 usleep_range(5000, 10000);
215         } while (time_before(jiffies, poll_end));
216
217         ent->ret = -ETIMEDOUT;
218 }
219
220 static void free_cmd(struct mlx5_cmd_work_ent *ent)
221 {
222         kfree(ent);
223 }
224
225 static int verify_signature(struct mlx5_cmd_work_ent *ent)
226 {
227         struct mlx5_cmd_mailbox *next = ent->out->next;
228         int n = mlx5_calc_cmd_blocks(ent->out);
229         int err;
230         u8 sig;
231         int i = 0;
232
233         sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
234         if (sig != 0xff)
235                 return -EINVAL;
236
237         for (i = 0; i < n && next; i++) {
238                 err = verify_block_sig(next->buf);
239                 if (err)
240                         return err;
241
242                 next = next->next;
243         }
244
245         return 0;
246 }
247
248 static void dump_buf(void *buf, int size, int data_only, int offset)
249 {
250         __be32 *p = buf;
251         int i;
252
253         for (i = 0; i < size; i += 16) {
254                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
255                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
256                          be32_to_cpu(p[3]));
257                 p += 4;
258                 offset += 16;
259         }
260         if (!data_only)
261                 pr_debug("\n");
262 }
263
264 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
265                                        u32 *synd, u8 *status)
266 {
267         *synd = 0;
268         *status = 0;
269
270         switch (op) {
271         case MLX5_CMD_OP_TEARDOWN_HCA:
272         case MLX5_CMD_OP_DISABLE_HCA:
273         case MLX5_CMD_OP_MANAGE_PAGES:
274         case MLX5_CMD_OP_DESTROY_MKEY:
275         case MLX5_CMD_OP_DESTROY_EQ:
276         case MLX5_CMD_OP_DESTROY_CQ:
277         case MLX5_CMD_OP_DESTROY_QP:
278         case MLX5_CMD_OP_DESTROY_PSV:
279         case MLX5_CMD_OP_DESTROY_SRQ:
280         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
281         case MLX5_CMD_OP_DESTROY_XRQ:
282         case MLX5_CMD_OP_DESTROY_DCT:
283         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
284         case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
285         case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
286         case MLX5_CMD_OP_DEALLOC_PD:
287         case MLX5_CMD_OP_DEALLOC_UAR:
288         case MLX5_CMD_OP_DETACH_FROM_MCG:
289         case MLX5_CMD_OP_DEALLOC_XRCD:
290         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
291         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
292         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
293         case MLX5_CMD_OP_DESTROY_LAG:
294         case MLX5_CMD_OP_DESTROY_VPORT_LAG:
295         case MLX5_CMD_OP_DESTROY_TIR:
296         case MLX5_CMD_OP_DESTROY_SQ:
297         case MLX5_CMD_OP_DESTROY_RQ:
298         case MLX5_CMD_OP_DESTROY_RMP:
299         case MLX5_CMD_OP_DESTROY_TIS:
300         case MLX5_CMD_OP_DESTROY_RQT:
301         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
302         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
303         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
304         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
305         case MLX5_CMD_OP_2ERR_QP:
306         case MLX5_CMD_OP_2RST_QP:
307         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
308         case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
309         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
310         case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
311         case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
312         case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
313         case MLX5_CMD_OP_FPGA_DESTROY_QP:
314         case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
315                 return MLX5_CMD_STAT_OK;
316
317         case MLX5_CMD_OP_QUERY_HCA_CAP:
318         case MLX5_CMD_OP_QUERY_ADAPTER:
319         case MLX5_CMD_OP_INIT_HCA:
320         case MLX5_CMD_OP_ENABLE_HCA:
321         case MLX5_CMD_OP_QUERY_PAGES:
322         case MLX5_CMD_OP_SET_HCA_CAP:
323         case MLX5_CMD_OP_QUERY_ISSI:
324         case MLX5_CMD_OP_SET_ISSI:
325         case MLX5_CMD_OP_CREATE_MKEY:
326         case MLX5_CMD_OP_QUERY_MKEY:
327         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
328         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
329         case MLX5_CMD_OP_CREATE_EQ:
330         case MLX5_CMD_OP_QUERY_EQ:
331         case MLX5_CMD_OP_GEN_EQE:
332         case MLX5_CMD_OP_CREATE_CQ:
333         case MLX5_CMD_OP_QUERY_CQ:
334         case MLX5_CMD_OP_MODIFY_CQ:
335         case MLX5_CMD_OP_CREATE_QP:
336         case MLX5_CMD_OP_RST2INIT_QP:
337         case MLX5_CMD_OP_INIT2RTR_QP:
338         case MLX5_CMD_OP_RTR2RTS_QP:
339         case MLX5_CMD_OP_RTS2RTS_QP:
340         case MLX5_CMD_OP_SQERR2RTS_QP:
341         case MLX5_CMD_OP_QUERY_QP:
342         case MLX5_CMD_OP_SQD_RTS_QP:
343         case MLX5_CMD_OP_INIT2INIT_QP:
344         case MLX5_CMD_OP_CREATE_PSV:
345         case MLX5_CMD_OP_CREATE_SRQ:
346         case MLX5_CMD_OP_QUERY_SRQ:
347         case MLX5_CMD_OP_ARM_RQ:
348         case MLX5_CMD_OP_CREATE_XRC_SRQ:
349         case MLX5_CMD_OP_QUERY_XRC_SRQ:
350         case MLX5_CMD_OP_ARM_XRC_SRQ:
351         case MLX5_CMD_OP_CREATE_XRQ:
352         case MLX5_CMD_OP_QUERY_XRQ:
353         case MLX5_CMD_OP_ARM_XRQ:
354         case MLX5_CMD_OP_CREATE_DCT:
355         case MLX5_CMD_OP_DRAIN_DCT:
356         case MLX5_CMD_OP_QUERY_DCT:
357         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
358         case MLX5_CMD_OP_QUERY_VPORT_STATE:
359         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
360         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
361         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
362         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
363         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
364         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
365         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
366         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
367         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
368         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
369         case MLX5_CMD_OP_QUERY_VNIC_ENV:
370         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
371         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
372         case MLX5_CMD_OP_QUERY_Q_COUNTER:
373         case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
374         case MLX5_CMD_OP_QUERY_RATE_LIMIT:
375         case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
376         case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
377         case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
378         case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
379         case MLX5_CMD_OP_ALLOC_PD:
380         case MLX5_CMD_OP_ALLOC_UAR:
381         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
382         case MLX5_CMD_OP_ACCESS_REG:
383         case MLX5_CMD_OP_ATTACH_TO_MCG:
384         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
385         case MLX5_CMD_OP_MAD_IFC:
386         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
387         case MLX5_CMD_OP_SET_MAD_DEMUX:
388         case MLX5_CMD_OP_NOP:
389         case MLX5_CMD_OP_ALLOC_XRCD:
390         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
391         case MLX5_CMD_OP_QUERY_CONG_STATUS:
392         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
393         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
394         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
395         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
396         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
397         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
398         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
399         case MLX5_CMD_OP_CREATE_LAG:
400         case MLX5_CMD_OP_MODIFY_LAG:
401         case MLX5_CMD_OP_QUERY_LAG:
402         case MLX5_CMD_OP_CREATE_VPORT_LAG:
403         case MLX5_CMD_OP_CREATE_TIR:
404         case MLX5_CMD_OP_MODIFY_TIR:
405         case MLX5_CMD_OP_QUERY_TIR:
406         case MLX5_CMD_OP_CREATE_SQ:
407         case MLX5_CMD_OP_MODIFY_SQ:
408         case MLX5_CMD_OP_QUERY_SQ:
409         case MLX5_CMD_OP_CREATE_RQ:
410         case MLX5_CMD_OP_MODIFY_RQ:
411         case MLX5_CMD_OP_QUERY_RQ:
412         case MLX5_CMD_OP_CREATE_RMP:
413         case MLX5_CMD_OP_MODIFY_RMP:
414         case MLX5_CMD_OP_QUERY_RMP:
415         case MLX5_CMD_OP_CREATE_TIS:
416         case MLX5_CMD_OP_MODIFY_TIS:
417         case MLX5_CMD_OP_QUERY_TIS:
418         case MLX5_CMD_OP_CREATE_RQT:
419         case MLX5_CMD_OP_MODIFY_RQT:
420         case MLX5_CMD_OP_QUERY_RQT:
421
422         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
423         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
424         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
425         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
426         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
427         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
428         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
429         case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
430         case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
431         case MLX5_CMD_OP_FPGA_CREATE_QP:
432         case MLX5_CMD_OP_FPGA_MODIFY_QP:
433         case MLX5_CMD_OP_FPGA_QUERY_QP:
434         case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
435         case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
436                 *status = MLX5_DRIVER_STATUS_ABORTED;
437                 *synd = MLX5_DRIVER_SYND;
438                 return -EIO;
439         default:
440                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
441                 return -EINVAL;
442         }
443 }
444
445 const char *mlx5_command_str(int command)
446 {
447 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
448
449         switch (command) {
450         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
451         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
452         MLX5_COMMAND_STR_CASE(INIT_HCA);
453         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
454         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
455         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
456         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
457         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
458         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
459         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
460         MLX5_COMMAND_STR_CASE(SET_ISSI);
461         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
462         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
463         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
464         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
465         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
466         MLX5_COMMAND_STR_CASE(CREATE_EQ);
467         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
468         MLX5_COMMAND_STR_CASE(QUERY_EQ);
469         MLX5_COMMAND_STR_CASE(GEN_EQE);
470         MLX5_COMMAND_STR_CASE(CREATE_CQ);
471         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
472         MLX5_COMMAND_STR_CASE(QUERY_CQ);
473         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
474         MLX5_COMMAND_STR_CASE(CREATE_QP);
475         MLX5_COMMAND_STR_CASE(DESTROY_QP);
476         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
477         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
478         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
479         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
480         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
481         MLX5_COMMAND_STR_CASE(2ERR_QP);
482         MLX5_COMMAND_STR_CASE(2RST_QP);
483         MLX5_COMMAND_STR_CASE(QUERY_QP);
484         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
485         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
486         MLX5_COMMAND_STR_CASE(CREATE_PSV);
487         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
488         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
489         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
490         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
491         MLX5_COMMAND_STR_CASE(ARM_RQ);
492         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
493         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
494         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
495         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
496         MLX5_COMMAND_STR_CASE(CREATE_DCT);
497         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
498         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
499         MLX5_COMMAND_STR_CASE(QUERY_DCT);
500         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
501         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
502         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
503         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
504         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
505         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
506         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
507         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
508         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
509         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
510         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
511         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
512         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
513         MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
514         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
515         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
516         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
517         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
518         MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
519         MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
520         MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
521         MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
522         MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
523         MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
524         MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
525         MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
526         MLX5_COMMAND_STR_CASE(ALLOC_PD);
527         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
528         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
529         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
530         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
531         MLX5_COMMAND_STR_CASE(ACCESS_REG);
532         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
533         MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
534         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
535         MLX5_COMMAND_STR_CASE(MAD_IFC);
536         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
537         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
538         MLX5_COMMAND_STR_CASE(NOP);
539         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
540         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
541         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
542         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
543         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
544         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
545         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
546         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
547         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
548         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
549         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
550         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
551         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
552         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
553         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
554         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
555         MLX5_COMMAND_STR_CASE(CREATE_LAG);
556         MLX5_COMMAND_STR_CASE(MODIFY_LAG);
557         MLX5_COMMAND_STR_CASE(QUERY_LAG);
558         MLX5_COMMAND_STR_CASE(DESTROY_LAG);
559         MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
560         MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
561         MLX5_COMMAND_STR_CASE(CREATE_TIR);
562         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
563         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
564         MLX5_COMMAND_STR_CASE(QUERY_TIR);
565         MLX5_COMMAND_STR_CASE(CREATE_SQ);
566         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
567         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
568         MLX5_COMMAND_STR_CASE(QUERY_SQ);
569         MLX5_COMMAND_STR_CASE(CREATE_RQ);
570         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
571         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
572         MLX5_COMMAND_STR_CASE(QUERY_RQ);
573         MLX5_COMMAND_STR_CASE(CREATE_RMP);
574         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
575         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
576         MLX5_COMMAND_STR_CASE(QUERY_RMP);
577         MLX5_COMMAND_STR_CASE(CREATE_TIS);
578         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
579         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
580         MLX5_COMMAND_STR_CASE(QUERY_TIS);
581         MLX5_COMMAND_STR_CASE(CREATE_RQT);
582         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
583         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
584         MLX5_COMMAND_STR_CASE(QUERY_RQT);
585         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
586         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
587         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
588         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
589         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
590         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
591         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
592         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
593         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
594         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
595         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
596         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
597         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
598         MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
599         MLX5_COMMAND_STR_CASE(ALLOC_ENCAP_HEADER);
600         MLX5_COMMAND_STR_CASE(DEALLOC_ENCAP_HEADER);
601         MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
602         MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
603         MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
604         MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
605         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
606         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
607         MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
608         MLX5_COMMAND_STR_CASE(CREATE_XRQ);
609         MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
610         MLX5_COMMAND_STR_CASE(QUERY_XRQ);
611         MLX5_COMMAND_STR_CASE(ARM_XRQ);
612         MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
613         MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
614         default: return "unknown command opcode";
615         }
616 }
617
618 static const char *cmd_status_str(u8 status)
619 {
620         switch (status) {
621         case MLX5_CMD_STAT_OK:
622                 return "OK";
623         case MLX5_CMD_STAT_INT_ERR:
624                 return "internal error";
625         case MLX5_CMD_STAT_BAD_OP_ERR:
626                 return "bad operation";
627         case MLX5_CMD_STAT_BAD_PARAM_ERR:
628                 return "bad parameter";
629         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
630                 return "bad system state";
631         case MLX5_CMD_STAT_BAD_RES_ERR:
632                 return "bad resource";
633         case MLX5_CMD_STAT_RES_BUSY:
634                 return "resource busy";
635         case MLX5_CMD_STAT_LIM_ERR:
636                 return "limits exceeded";
637         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
638                 return "bad resource state";
639         case MLX5_CMD_STAT_IX_ERR:
640                 return "bad index";
641         case MLX5_CMD_STAT_NO_RES_ERR:
642                 return "no resources";
643         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
644                 return "bad input length";
645         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
646                 return "bad output length";
647         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
648                 return "bad QP state";
649         case MLX5_CMD_STAT_BAD_PKT_ERR:
650                 return "bad packet (discarded)";
651         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
652                 return "bad size too many outstanding CQEs";
653         default:
654                 return "unknown status";
655         }
656 }
657
658 static int cmd_status_to_err(u8 status)
659 {
660         switch (status) {
661         case MLX5_CMD_STAT_OK:                          return 0;
662         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
663         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
664         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
665         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
666         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
667         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
668         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
669         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
670         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
671         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
672         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
673         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
674         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
675         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
676         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
677         default:                                        return -EIO;
678         }
679 }
680
681 struct mlx5_ifc_mbox_out_bits {
682         u8         status[0x8];
683         u8         reserved_at_8[0x18];
684
685         u8         syndrome[0x20];
686
687         u8         reserved_at_40[0x40];
688 };
689
690 struct mlx5_ifc_mbox_in_bits {
691         u8         opcode[0x10];
692         u8         uid[0x10];
693
694         u8         reserved_at_20[0x10];
695         u8         op_mod[0x10];
696
697         u8         reserved_at_40[0x40];
698 };
699
700 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
701 {
702         *status = MLX5_GET(mbox_out, out, status);
703         *syndrome = MLX5_GET(mbox_out, out, syndrome);
704 }
705
706 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
707 {
708         u32 syndrome;
709         u8  status;
710         u16 opcode;
711         u16 op_mod;
712         u16 uid;
713
714         mlx5_cmd_mbox_status(out, &status, &syndrome);
715         if (!status)
716                 return 0;
717
718         opcode = MLX5_GET(mbox_in, in, opcode);
719         op_mod = MLX5_GET(mbox_in, in, op_mod);
720         uid    = MLX5_GET(mbox_in, in, uid);
721
722         if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
723                 mlx5_core_err_rl(dev,
724                         "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
725                         mlx5_command_str(opcode), opcode, op_mod,
726                         cmd_status_str(status), status, syndrome);
727         else
728                 mlx5_core_dbg(dev,
729                       "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
730                       mlx5_command_str(opcode),
731                       opcode, op_mod,
732                       cmd_status_str(status),
733                       status,
734                       syndrome);
735
736         return cmd_status_to_err(status);
737 }
738
739 static void dump_command(struct mlx5_core_dev *dev,
740                          struct mlx5_cmd_work_ent *ent, int input)
741 {
742         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
743         u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
744         struct mlx5_cmd_mailbox *next = msg->next;
745         int n = mlx5_calc_cmd_blocks(msg);
746         int data_only;
747         u32 offset = 0;
748         int dump_len;
749         int i;
750
751         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
752
753         if (data_only)
754                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
755                                    "dump command data %s(0x%x) %s\n",
756                                    mlx5_command_str(op), op,
757                                    input ? "INPUT" : "OUTPUT");
758         else
759                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
760                               mlx5_command_str(op), op,
761                               input ? "INPUT" : "OUTPUT");
762
763         if (data_only) {
764                 if (input) {
765                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
766                         offset += sizeof(ent->lay->in);
767                 } else {
768                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
769                         offset += sizeof(ent->lay->out);
770                 }
771         } else {
772                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
773                 offset += sizeof(*ent->lay);
774         }
775
776         for (i = 0; i < n && next; i++)  {
777                 if (data_only) {
778                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
779                         dump_buf(next->buf, dump_len, 1, offset);
780                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
781                 } else {
782                         mlx5_core_dbg(dev, "command block:\n");
783                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
784                         offset += sizeof(struct mlx5_cmd_prot_block);
785                 }
786                 next = next->next;
787         }
788
789         if (data_only)
790                 pr_debug("\n");
791 }
792
793 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
794 {
795         return MLX5_GET(mbox_in, in->first.data, opcode);
796 }
797
798 static void cb_timeout_handler(struct work_struct *work)
799 {
800         struct delayed_work *dwork = container_of(work, struct delayed_work,
801                                                   work);
802         struct mlx5_cmd_work_ent *ent = container_of(dwork,
803                                                      struct mlx5_cmd_work_ent,
804                                                      cb_timeout_work);
805         struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
806                                                  cmd);
807
808         ent->ret = -ETIMEDOUT;
809         mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
810                        mlx5_command_str(msg_to_opcode(ent->in)),
811                        msg_to_opcode(ent->in));
812         mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
813 }
814
815 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
816 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
817                               struct mlx5_cmd_msg *msg);
818
819 static void cmd_work_handler(struct work_struct *work)
820 {
821         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
822         struct mlx5_cmd *cmd = ent->cmd;
823         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
824         unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
825         struct mlx5_cmd_layout *lay;
826         struct semaphore *sem;
827         unsigned long flags;
828         bool poll_cmd = ent->polling;
829         int alloc_ret;
830
831         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
832         down(sem);
833         if (!ent->page_queue) {
834                 alloc_ret = alloc_ent(cmd);
835                 if (alloc_ret < 0) {
836                         mlx5_core_err(dev, "failed to allocate command entry\n");
837                         if (ent->callback) {
838                                 ent->callback(-EAGAIN, ent->context);
839                                 mlx5_free_cmd_msg(dev, ent->out);
840                                 free_msg(dev, ent->in);
841                                 free_cmd(ent);
842                         } else {
843                                 ent->ret = -EAGAIN;
844                                 complete(&ent->done);
845                         }
846                         up(sem);
847                         return;
848                 }
849                 ent->idx = alloc_ret;
850         } else {
851                 ent->idx = cmd->max_reg_cmds;
852                 spin_lock_irqsave(&cmd->alloc_lock, flags);
853                 clear_bit(ent->idx, &cmd->bitmask);
854                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
855         }
856
857         cmd->ent_arr[ent->idx] = ent;
858         set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
859         lay = get_inst(cmd, ent->idx);
860         ent->lay = lay;
861         memset(lay, 0, sizeof(*lay));
862         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
863         ent->op = be32_to_cpu(lay->in[0]) >> 16;
864         if (ent->in->next)
865                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
866         lay->inlen = cpu_to_be32(ent->in->len);
867         if (ent->out->next)
868                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
869         lay->outlen = cpu_to_be32(ent->out->len);
870         lay->type = MLX5_PCI_CMD_XPORT;
871         lay->token = ent->token;
872         lay->status_own = CMD_OWNER_HW;
873         set_signature(ent, !cmd->checksum_disabled);
874         dump_command(dev, ent, 1);
875         ent->ts1 = ktime_get_ns();
876
877         if (ent->callback)
878                 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
879
880         /* Skip sending command to fw if internal error */
881         if (pci_channel_offline(dev->pdev) ||
882             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
883                 u8 status = 0;
884                 u32 drv_synd;
885
886                 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
887                 MLX5_SET(mbox_out, ent->out, status, status);
888                 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
889
890                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
891                 return;
892         }
893
894         /* ring doorbell after the descriptor is valid */
895         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
896         wmb();
897         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
898         mmiowb();
899         /* if not in polling don't use ent after this point */
900         if (cmd->mode == CMD_MODE_POLLING || poll_cmd) {
901                 poll_timeout(ent);
902                 /* make sure we read the descriptor after ownership is SW */
903                 rmb();
904                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
905         }
906 }
907
908 static const char *deliv_status_to_str(u8 status)
909 {
910         switch (status) {
911         case MLX5_CMD_DELIVERY_STAT_OK:
912                 return "no errors";
913         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
914                 return "signature error";
915         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
916                 return "token error";
917         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
918                 return "bad block number";
919         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
920                 return "output pointer not aligned to block size";
921         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
922                 return "input pointer not aligned to block size";
923         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
924                 return "firmware internal error";
925         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
926                 return "command input length error";
927         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
928                 return "command output length error";
929         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
930                 return "reserved fields not cleared";
931         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
932                 return "bad command descriptor type";
933         default:
934                 return "unknown status code";
935         }
936 }
937
938 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
939 {
940         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
941         struct mlx5_cmd *cmd = &dev->cmd;
942         int err;
943
944         if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
945                 wait_for_completion(&ent->done);
946         } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
947                 ent->ret = -ETIMEDOUT;
948                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
949         }
950
951         err = ent->ret;
952
953         if (err == -ETIMEDOUT) {
954                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
955                                mlx5_command_str(msg_to_opcode(ent->in)),
956                                msg_to_opcode(ent->in));
957         }
958         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
959                       err, deliv_status_to_str(ent->status), ent->status);
960
961         return err;
962 }
963
964 /*  Notes:
965  *    1. Callback functions may not sleep
966  *    2. page queue commands do not support asynchrous completion
967  */
968 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
969                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
970                            mlx5_cmd_cbk_t callback,
971                            void *context, int page_queue, u8 *status,
972                            u8 token, bool force_polling)
973 {
974         struct mlx5_cmd *cmd = &dev->cmd;
975         struct mlx5_cmd_work_ent *ent;
976         struct mlx5_cmd_stats *stats;
977         int err = 0;
978         s64 ds;
979         u16 op;
980
981         if (callback && page_queue)
982                 return -EINVAL;
983
984         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
985                         page_queue);
986         if (IS_ERR(ent))
987                 return PTR_ERR(ent);
988
989         ent->token = token;
990         ent->polling = force_polling;
991
992         if (!callback)
993                 init_completion(&ent->done);
994
995         INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
996         INIT_WORK(&ent->work, cmd_work_handler);
997         if (page_queue) {
998                 cmd_work_handler(&ent->work);
999         } else if (!queue_work(cmd->wq, &ent->work)) {
1000                 mlx5_core_warn(dev, "failed to queue work\n");
1001                 err = -ENOMEM;
1002                 goto out_free;
1003         }
1004
1005         if (callback)
1006                 goto out;
1007
1008         err = wait_func(dev, ent);
1009         if (err == -ETIMEDOUT)
1010                 goto out;
1011
1012         ds = ent->ts2 - ent->ts1;
1013         op = MLX5_GET(mbox_in, in->first.data, opcode);
1014         if (op < ARRAY_SIZE(cmd->stats)) {
1015                 stats = &cmd->stats[op];
1016                 spin_lock_irq(&stats->lock);
1017                 stats->sum += ds;
1018                 ++stats->n;
1019                 spin_unlock_irq(&stats->lock);
1020         }
1021         mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1022                            "fw exec time for %s is %lld nsec\n",
1023                            mlx5_command_str(op), ds);
1024         *status = ent->status;
1025
1026 out_free:
1027         free_cmd(ent);
1028 out:
1029         return err;
1030 }
1031
1032 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1033                          size_t count, loff_t *pos)
1034 {
1035         struct mlx5_core_dev *dev = filp->private_data;
1036         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1037         char lbuf[3];
1038         int err;
1039
1040         if (!dbg->in_msg || !dbg->out_msg)
1041                 return -ENOMEM;
1042
1043         if (count < sizeof(lbuf) - 1)
1044                 return -EINVAL;
1045
1046         if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1047                 return -EFAULT;
1048
1049         lbuf[sizeof(lbuf) - 1] = 0;
1050
1051         if (strcmp(lbuf, "go"))
1052                 return -EINVAL;
1053
1054         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1055
1056         return err ? err : count;
1057 }
1058
1059 static const struct file_operations fops = {
1060         .owner  = THIS_MODULE,
1061         .open   = simple_open,
1062         .write  = dbg_write,
1063 };
1064
1065 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1066                             u8 token)
1067 {
1068         struct mlx5_cmd_prot_block *block;
1069         struct mlx5_cmd_mailbox *next;
1070         int copy;
1071
1072         if (!to || !from)
1073                 return -ENOMEM;
1074
1075         copy = min_t(int, size, sizeof(to->first.data));
1076         memcpy(to->first.data, from, copy);
1077         size -= copy;
1078         from += copy;
1079
1080         next = to->next;
1081         while (size) {
1082                 if (!next) {
1083                         /* this is a BUG */
1084                         return -ENOMEM;
1085                 }
1086
1087                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1088                 block = next->buf;
1089                 memcpy(block->data, from, copy);
1090                 from += copy;
1091                 size -= copy;
1092                 block->token = token;
1093                 next = next->next;
1094         }
1095
1096         return 0;
1097 }
1098
1099 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1100 {
1101         struct mlx5_cmd_prot_block *block;
1102         struct mlx5_cmd_mailbox *next;
1103         int copy;
1104
1105         if (!to || !from)
1106                 return -ENOMEM;
1107
1108         copy = min_t(int, size, sizeof(from->first.data));
1109         memcpy(to, from->first.data, copy);
1110         size -= copy;
1111         to += copy;
1112
1113         next = from->next;
1114         while (size) {
1115                 if (!next) {
1116                         /* this is a BUG */
1117                         return -ENOMEM;
1118                 }
1119
1120                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1121                 block = next->buf;
1122
1123                 memcpy(to, block->data, copy);
1124                 to += copy;
1125                 size -= copy;
1126                 next = next->next;
1127         }
1128
1129         return 0;
1130 }
1131
1132 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1133                                               gfp_t flags)
1134 {
1135         struct mlx5_cmd_mailbox *mailbox;
1136
1137         mailbox = kmalloc(sizeof(*mailbox), flags);
1138         if (!mailbox)
1139                 return ERR_PTR(-ENOMEM);
1140
1141         mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1142                                        &mailbox->dma);
1143         if (!mailbox->buf) {
1144                 mlx5_core_dbg(dev, "failed allocation\n");
1145                 kfree(mailbox);
1146                 return ERR_PTR(-ENOMEM);
1147         }
1148         mailbox->next = NULL;
1149
1150         return mailbox;
1151 }
1152
1153 static void free_cmd_box(struct mlx5_core_dev *dev,
1154                          struct mlx5_cmd_mailbox *mailbox)
1155 {
1156         dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1157         kfree(mailbox);
1158 }
1159
1160 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1161                                                gfp_t flags, int size,
1162                                                u8 token)
1163 {
1164         struct mlx5_cmd_mailbox *tmp, *head = NULL;
1165         struct mlx5_cmd_prot_block *block;
1166         struct mlx5_cmd_msg *msg;
1167         int err;
1168         int n;
1169         int i;
1170
1171         msg = kzalloc(sizeof(*msg), flags);
1172         if (!msg)
1173                 return ERR_PTR(-ENOMEM);
1174
1175         msg->len = size;
1176         n = mlx5_calc_cmd_blocks(msg);
1177
1178         for (i = 0; i < n; i++) {
1179                 tmp = alloc_cmd_box(dev, flags);
1180                 if (IS_ERR(tmp)) {
1181                         mlx5_core_warn(dev, "failed allocating block\n");
1182                         err = PTR_ERR(tmp);
1183                         goto err_alloc;
1184                 }
1185
1186                 block = tmp->buf;
1187                 tmp->next = head;
1188                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1189                 block->block_num = cpu_to_be32(n - i - 1);
1190                 block->token = token;
1191                 head = tmp;
1192         }
1193         msg->next = head;
1194         return msg;
1195
1196 err_alloc:
1197         while (head) {
1198                 tmp = head->next;
1199                 free_cmd_box(dev, head);
1200                 head = tmp;
1201         }
1202         kfree(msg);
1203
1204         return ERR_PTR(err);
1205 }
1206
1207 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1208                               struct mlx5_cmd_msg *msg)
1209 {
1210         struct mlx5_cmd_mailbox *head = msg->next;
1211         struct mlx5_cmd_mailbox *next;
1212
1213         while (head) {
1214                 next = head->next;
1215                 free_cmd_box(dev, head);
1216                 head = next;
1217         }
1218         kfree(msg);
1219 }
1220
1221 static ssize_t data_write(struct file *filp, const char __user *buf,
1222                           size_t count, loff_t *pos)
1223 {
1224         struct mlx5_core_dev *dev = filp->private_data;
1225         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1226         void *ptr;
1227
1228         if (*pos != 0)
1229                 return -EINVAL;
1230
1231         kfree(dbg->in_msg);
1232         dbg->in_msg = NULL;
1233         dbg->inlen = 0;
1234         ptr = memdup_user(buf, count);
1235         if (IS_ERR(ptr))
1236                 return PTR_ERR(ptr);
1237         dbg->in_msg = ptr;
1238         dbg->inlen = count;
1239
1240         *pos = count;
1241
1242         return count;
1243 }
1244
1245 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1246                          loff_t *pos)
1247 {
1248         struct mlx5_core_dev *dev = filp->private_data;
1249         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1250
1251         if (!dbg->out_msg)
1252                 return -ENOMEM;
1253
1254         return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1255                                        dbg->outlen);
1256 }
1257
1258 static const struct file_operations dfops = {
1259         .owner  = THIS_MODULE,
1260         .open   = simple_open,
1261         .write  = data_write,
1262         .read   = data_read,
1263 };
1264
1265 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1266                            loff_t *pos)
1267 {
1268         struct mlx5_core_dev *dev = filp->private_data;
1269         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1270         char outlen[8];
1271         int err;
1272
1273         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1274         if (err < 0)
1275                 return err;
1276
1277         return simple_read_from_buffer(buf, count, pos, outlen, err);
1278 }
1279
1280 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1281                             size_t count, loff_t *pos)
1282 {
1283         struct mlx5_core_dev *dev = filp->private_data;
1284         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1285         char outlen_str[8];
1286         int outlen;
1287         void *ptr;
1288         int err;
1289
1290         if (*pos != 0 || count > 6)
1291                 return -EINVAL;
1292
1293         kfree(dbg->out_msg);
1294         dbg->out_msg = NULL;
1295         dbg->outlen = 0;
1296
1297         if (copy_from_user(outlen_str, buf, count))
1298                 return -EFAULT;
1299
1300         outlen_str[7] = 0;
1301
1302         err = sscanf(outlen_str, "%d", &outlen);
1303         if (err < 0)
1304                 return err;
1305
1306         ptr = kzalloc(outlen, GFP_KERNEL);
1307         if (!ptr)
1308                 return -ENOMEM;
1309
1310         dbg->out_msg = ptr;
1311         dbg->outlen = outlen;
1312
1313         *pos = count;
1314
1315         return count;
1316 }
1317
1318 static const struct file_operations olfops = {
1319         .owner  = THIS_MODULE,
1320         .open   = simple_open,
1321         .write  = outlen_write,
1322         .read   = outlen_read,
1323 };
1324
1325 static void set_wqname(struct mlx5_core_dev *dev)
1326 {
1327         struct mlx5_cmd *cmd = &dev->cmd;
1328
1329         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1330                  dev_name(&dev->pdev->dev));
1331 }
1332
1333 static void clean_debug_files(struct mlx5_core_dev *dev)
1334 {
1335         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1336
1337         if (!mlx5_debugfs_root)
1338                 return;
1339
1340         mlx5_cmdif_debugfs_cleanup(dev);
1341         debugfs_remove_recursive(dbg->dbg_root);
1342 }
1343
1344 static int create_debugfs_files(struct mlx5_core_dev *dev)
1345 {
1346         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1347         int err = -ENOMEM;
1348
1349         if (!mlx5_debugfs_root)
1350                 return 0;
1351
1352         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1353         if (!dbg->dbg_root)
1354                 return err;
1355
1356         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1357                                           dev, &dfops);
1358         if (!dbg->dbg_in)
1359                 goto err_dbg;
1360
1361         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1362                                            dev, &dfops);
1363         if (!dbg->dbg_out)
1364                 goto err_dbg;
1365
1366         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1367                                               dev, &olfops);
1368         if (!dbg->dbg_outlen)
1369                 goto err_dbg;
1370
1371         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1372                                             &dbg->status);
1373         if (!dbg->dbg_status)
1374                 goto err_dbg;
1375
1376         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1377         if (!dbg->dbg_run)
1378                 goto err_dbg;
1379
1380         mlx5_cmdif_debugfs_init(dev);
1381
1382         return 0;
1383
1384 err_dbg:
1385         clean_debug_files(dev);
1386         return err;
1387 }
1388
1389 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1390 {
1391         struct mlx5_cmd *cmd = &dev->cmd;
1392         int i;
1393
1394         for (i = 0; i < cmd->max_reg_cmds; i++)
1395                 down(&cmd->sem);
1396         down(&cmd->pages_sem);
1397
1398         cmd->mode = mode;
1399
1400         up(&cmd->pages_sem);
1401         for (i = 0; i < cmd->max_reg_cmds; i++)
1402                 up(&cmd->sem);
1403 }
1404
1405 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1406 {
1407         mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1408 }
1409
1410 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1411 {
1412         mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1413 }
1414
1415 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1416 {
1417         unsigned long flags;
1418
1419         if (msg->parent) {
1420                 spin_lock_irqsave(&msg->parent->lock, flags);
1421                 list_add_tail(&msg->list, &msg->parent->head);
1422                 spin_unlock_irqrestore(&msg->parent->lock, flags);
1423         } else {
1424                 mlx5_free_cmd_msg(dev, msg);
1425         }
1426 }
1427
1428 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1429 {
1430         struct mlx5_cmd *cmd = &dev->cmd;
1431         struct mlx5_cmd_work_ent *ent;
1432         mlx5_cmd_cbk_t callback;
1433         void *context;
1434         int err;
1435         int i;
1436         s64 ds;
1437         struct mlx5_cmd_stats *stats;
1438         unsigned long flags;
1439         unsigned long vector;
1440
1441         /* there can be at most 32 command queues */
1442         vector = vec & 0xffffffff;
1443         for (i = 0; i < (1 << cmd->log_sz); i++) {
1444                 if (test_bit(i, &vector)) {
1445                         struct semaphore *sem;
1446
1447                         ent = cmd->ent_arr[i];
1448
1449                         /* if we already completed the command, ignore it */
1450                         if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1451                                                 &ent->state)) {
1452                                 /* only real completion can free the cmd slot */
1453                                 if (!forced) {
1454                                         mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1455                                                       ent->idx);
1456                                         free_ent(cmd, ent->idx);
1457                                         free_cmd(ent);
1458                                 }
1459                                 continue;
1460                         }
1461
1462                         if (ent->callback)
1463                                 cancel_delayed_work(&ent->cb_timeout_work);
1464                         if (ent->page_queue)
1465                                 sem = &cmd->pages_sem;
1466                         else
1467                                 sem = &cmd->sem;
1468                         ent->ts2 = ktime_get_ns();
1469                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1470                         dump_command(dev, ent, 0);
1471                         if (!ent->ret) {
1472                                 if (!cmd->checksum_disabled)
1473                                         ent->ret = verify_signature(ent);
1474                                 else
1475                                         ent->ret = 0;
1476                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1477                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1478                                 else
1479                                         ent->status = ent->lay->status_own >> 1;
1480
1481                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1482                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1483                         }
1484
1485                         /* only real completion will free the entry slot */
1486                         if (!forced)
1487                                 free_ent(cmd, ent->idx);
1488
1489                         if (ent->callback) {
1490                                 ds = ent->ts2 - ent->ts1;
1491                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1492                                         stats = &cmd->stats[ent->op];
1493                                         spin_lock_irqsave(&stats->lock, flags);
1494                                         stats->sum += ds;
1495                                         ++stats->n;
1496                                         spin_unlock_irqrestore(&stats->lock, flags);
1497                                 }
1498
1499                                 callback = ent->callback;
1500                                 context = ent->context;
1501                                 err = ent->ret;
1502                                 if (!err) {
1503                                         err = mlx5_copy_from_msg(ent->uout,
1504                                                                  ent->out,
1505                                                                  ent->uout_size);
1506
1507                                         err = err ? err : mlx5_cmd_check(dev,
1508                                                                         ent->in->first.data,
1509                                                                         ent->uout);
1510                                 }
1511
1512                                 mlx5_free_cmd_msg(dev, ent->out);
1513                                 free_msg(dev, ent->in);
1514
1515                                 err = err ? err : ent->status;
1516                                 if (!forced)
1517                                         free_cmd(ent);
1518                                 callback(err, context);
1519                         } else {
1520                                 complete(&ent->done);
1521                         }
1522                         up(sem);
1523                 }
1524         }
1525 }
1526 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1527
1528 static int status_to_err(u8 status)
1529 {
1530         return status ? -1 : 0; /* TBD more meaningful codes */
1531 }
1532
1533 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1534                                       gfp_t gfp)
1535 {
1536         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1537         struct cmd_msg_cache *ch = NULL;
1538         struct mlx5_cmd *cmd = &dev->cmd;
1539         int i;
1540
1541         if (in_size <= 16)
1542                 goto cache_miss;
1543
1544         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1545                 ch = &cmd->cache[i];
1546                 if (in_size > ch->max_inbox_size)
1547                         continue;
1548                 spin_lock_irq(&ch->lock);
1549                 if (list_empty(&ch->head)) {
1550                         spin_unlock_irq(&ch->lock);
1551                         continue;
1552                 }
1553                 msg = list_entry(ch->head.next, typeof(*msg), list);
1554                 /* For cached lists, we must explicitly state what is
1555                  * the real size
1556                  */
1557                 msg->len = in_size;
1558                 list_del(&msg->list);
1559                 spin_unlock_irq(&ch->lock);
1560                 break;
1561         }
1562
1563         if (!IS_ERR(msg))
1564                 return msg;
1565
1566 cache_miss:
1567         msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1568         return msg;
1569 }
1570
1571 static int is_manage_pages(void *in)
1572 {
1573         return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1574 }
1575
1576 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1577                     int out_size, mlx5_cmd_cbk_t callback, void *context,
1578                     bool force_polling)
1579 {
1580         struct mlx5_cmd_msg *inb;
1581         struct mlx5_cmd_msg *outb;
1582         int pages_queue;
1583         gfp_t gfp;
1584         int err;
1585         u8 status = 0;
1586         u32 drv_synd;
1587         u8 token;
1588
1589         if (pci_channel_offline(dev->pdev) ||
1590             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1591                 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1592
1593                 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1594                 MLX5_SET(mbox_out, out, status, status);
1595                 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1596                 return err;
1597         }
1598
1599         pages_queue = is_manage_pages(in);
1600         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1601
1602         inb = alloc_msg(dev, in_size, gfp);
1603         if (IS_ERR(inb)) {
1604                 err = PTR_ERR(inb);
1605                 return err;
1606         }
1607
1608         token = alloc_token(&dev->cmd);
1609
1610         err = mlx5_copy_to_msg(inb, in, in_size, token);
1611         if (err) {
1612                 mlx5_core_warn(dev, "err %d\n", err);
1613                 goto out_in;
1614         }
1615
1616         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1617         if (IS_ERR(outb)) {
1618                 err = PTR_ERR(outb);
1619                 goto out_in;
1620         }
1621
1622         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1623                               pages_queue, &status, token, force_polling);
1624         if (err)
1625                 goto out_out;
1626
1627         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1628         if (status) {
1629                 err = status_to_err(status);
1630                 goto out_out;
1631         }
1632
1633         if (!callback)
1634                 err = mlx5_copy_from_msg(out, outb, out_size);
1635
1636 out_out:
1637         if (!callback)
1638                 mlx5_free_cmd_msg(dev, outb);
1639
1640 out_in:
1641         if (!callback)
1642                 free_msg(dev, inb);
1643         return err;
1644 }
1645
1646 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1647                   int out_size)
1648 {
1649         int err;
1650
1651         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1652         return err ? : mlx5_cmd_check(dev, in, out);
1653 }
1654 EXPORT_SYMBOL(mlx5_cmd_exec);
1655
1656 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1657                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1658                      void *context)
1659 {
1660         return cmd_exec(dev, in, in_size, out, out_size, callback, context,
1661                         false);
1662 }
1663 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1664
1665 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1666                           void *out, int out_size)
1667 {
1668         int err;
1669
1670         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1671
1672         return err ? : mlx5_cmd_check(dev, in, out);
1673 }
1674 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1675
1676 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1677 {
1678         struct cmd_msg_cache *ch;
1679         struct mlx5_cmd_msg *msg;
1680         struct mlx5_cmd_msg *n;
1681         int i;
1682
1683         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1684                 ch = &dev->cmd.cache[i];
1685                 list_for_each_entry_safe(msg, n, &ch->head, list) {
1686                         list_del(&msg->list);
1687                         mlx5_free_cmd_msg(dev, msg);
1688                 }
1689         }
1690 }
1691
1692 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1693         512, 32, 16, 8, 2
1694 };
1695
1696 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1697         16 + MLX5_CMD_DATA_BLOCK_SIZE,
1698         16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1699         16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1700         16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1701         16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1702 };
1703
1704 static void create_msg_cache(struct mlx5_core_dev *dev)
1705 {
1706         struct mlx5_cmd *cmd = &dev->cmd;
1707         struct cmd_msg_cache *ch;
1708         struct mlx5_cmd_msg *msg;
1709         int i;
1710         int k;
1711
1712         /* Initialize and fill the caches with initial entries */
1713         for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1714                 ch = &cmd->cache[k];
1715                 spin_lock_init(&ch->lock);
1716                 INIT_LIST_HEAD(&ch->head);
1717                 ch->num_ent = cmd_cache_num_ent[k];
1718                 ch->max_inbox_size = cmd_cache_ent_size[k];
1719                 for (i = 0; i < ch->num_ent; i++) {
1720                         msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1721                                                  ch->max_inbox_size, 0);
1722                         if (IS_ERR(msg))
1723                                 break;
1724                         msg->parent = ch;
1725                         list_add_tail(&msg->list, &ch->head);
1726                 }
1727         }
1728 }
1729
1730 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1731 {
1732         struct device *ddev = &dev->pdev->dev;
1733
1734         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1735                                                  &cmd->alloc_dma, GFP_KERNEL);
1736         if (!cmd->cmd_alloc_buf)
1737                 return -ENOMEM;
1738
1739         /* make sure it is aligned to 4K */
1740         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1741                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1742                 cmd->dma = cmd->alloc_dma;
1743                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1744                 return 0;
1745         }
1746
1747         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1748                           cmd->alloc_dma);
1749         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1750                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1751                                                  &cmd->alloc_dma, GFP_KERNEL);
1752         if (!cmd->cmd_alloc_buf)
1753                 return -ENOMEM;
1754
1755         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1756         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1757         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1758         return 0;
1759 }
1760
1761 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1762 {
1763         struct device *ddev = &dev->pdev->dev;
1764
1765         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1766                           cmd->alloc_dma);
1767 }
1768
1769 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1770 {
1771         int size = sizeof(struct mlx5_cmd_prot_block);
1772         int align = roundup_pow_of_two(size);
1773         struct mlx5_cmd *cmd = &dev->cmd;
1774         u32 cmd_h, cmd_l;
1775         u16 cmd_if_rev;
1776         int err;
1777         int i;
1778
1779         memset(cmd, 0, sizeof(*cmd));
1780         cmd_if_rev = cmdif_rev(dev);
1781         if (cmd_if_rev != CMD_IF_REV) {
1782                 dev_err(&dev->pdev->dev,
1783                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1784                         CMD_IF_REV, cmd_if_rev);
1785                 return -EINVAL;
1786         }
1787
1788         cmd->pool = dma_pool_create("mlx5_cmd", &dev->pdev->dev, size, align,
1789                                     0);
1790         if (!cmd->pool)
1791                 return -ENOMEM;
1792
1793         err = alloc_cmd_page(dev, cmd);
1794         if (err)
1795                 goto err_free_pool;
1796
1797         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1798         cmd->log_sz = cmd_l >> 4 & 0xf;
1799         cmd->log_stride = cmd_l & 0xf;
1800         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1801                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1802                         1 << cmd->log_sz);
1803                 err = -EINVAL;
1804                 goto err_free_page;
1805         }
1806
1807         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1808                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1809                 err = -EINVAL;
1810                 goto err_free_page;
1811         }
1812
1813         cmd->checksum_disabled = 1;
1814         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1815         cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
1816
1817         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1818         if (cmd->cmdif_rev > CMD_IF_REV) {
1819                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1820                         CMD_IF_REV, cmd->cmdif_rev);
1821                 err = -EOPNOTSUPP;
1822                 goto err_free_page;
1823         }
1824
1825         spin_lock_init(&cmd->alloc_lock);
1826         spin_lock_init(&cmd->token_lock);
1827         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1828                 spin_lock_init(&cmd->stats[i].lock);
1829
1830         sema_init(&cmd->sem, cmd->max_reg_cmds);
1831         sema_init(&cmd->pages_sem, 1);
1832
1833         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1834         cmd_l = (u32)(cmd->dma);
1835         if (cmd_l & 0xfff) {
1836                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1837                 err = -ENOMEM;
1838                 goto err_free_page;
1839         }
1840
1841         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1842         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1843
1844         /* Make sure firmware sees the complete address before we proceed */
1845         wmb();
1846
1847         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1848
1849         cmd->mode = CMD_MODE_POLLING;
1850
1851         create_msg_cache(dev);
1852
1853         set_wqname(dev);
1854         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1855         if (!cmd->wq) {
1856                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1857                 err = -ENOMEM;
1858                 goto err_cache;
1859         }
1860
1861         err = create_debugfs_files(dev);
1862         if (err) {
1863                 err = -ENOMEM;
1864                 goto err_wq;
1865         }
1866
1867         return 0;
1868
1869 err_wq:
1870         destroy_workqueue(cmd->wq);
1871
1872 err_cache:
1873         destroy_msg_cache(dev);
1874
1875 err_free_page:
1876         free_cmd_page(dev, cmd);
1877
1878 err_free_pool:
1879         dma_pool_destroy(cmd->pool);
1880
1881         return err;
1882 }
1883 EXPORT_SYMBOL(mlx5_cmd_init);
1884
1885 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1886 {
1887         struct mlx5_cmd *cmd = &dev->cmd;
1888
1889         clean_debug_files(dev);
1890         destroy_workqueue(cmd->wq);
1891         destroy_msg_cache(dev);
1892         free_cmd_page(dev, cmd);
1893         dma_pool_destroy(cmd->pool);
1894 }
1895 EXPORT_SYMBOL(mlx5_cmd_cleanup);