drivers/net/ethernet/mellanox/mlx4/en_tx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <asm/page.h>
  35 #include <linux/mlx4/cq.h>
  36 #include <linux/slab.h>
  37 #include <linux/mlx4/qp.h>
  38 #include <linux/skbuff.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/prefetch.h>
  41 #include <linux/vmalloc.h>
  42 #include <linux/tcp.h>
  43 #include <linux/ip.h>
  44 #include <linux/ipv6.h>
  45 #include <linux/moduleparam.h>
  46
  47 #include "mlx4_en.h"
  48
  49 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
  50                            struct mlx4_en_tx_ring **pring, u32 size,
  51                            u16 stride, int node, int queue_index)
  52 {
  53         struct mlx4_en_dev *mdev = priv->mdev;
  54         struct mlx4_en_tx_ring *ring;
  55         int tmp;
  56         int err;
  57
  58         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
  59         if (!ring) {
  60                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  61                 if (!ring) {
  62                         en_err(priv, "Failed allocating TX ring\n");
  63                         return -ENOMEM;
  64                 }
  65         }
  66
  67         ring->size = size;
  68         ring->size_mask = size - 1;
  69         ring->sp_stride = stride;
  70         ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS;
  71
  72         tmp = size * sizeof(struct mlx4_en_tx_info);
  73         ring->tx_info = kvmalloc_node(tmp, GFP_KERNEL, node);
  74         if (!ring->tx_info) {
  75                 err = -ENOMEM;
  76                 goto err_ring;
  77         }
  78
  79         en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
  80                  ring->tx_info, tmp);
  81
  82         ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node);
  83         if (!ring->bounce_buf) {
  84                 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
  85                 if (!ring->bounce_buf) {
  86                         err = -ENOMEM;
  87                         goto err_info;
  88                 }
  89         }
  90         ring->buf_size = ALIGN(size * ring->sp_stride, MLX4_EN_PAGE_SIZE);
  91
  92         /* Allocate HW buffers on provided NUMA node */
  93         set_dev_node(&mdev->dev->persist->pdev->dev, node);
  94         err = mlx4_alloc_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
  95         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
  96         if (err) {
  97                 en_err(priv, "Failed allocating hwq resources\n");
  98                 goto err_bounce;
  99         }
 100
 101         ring->buf = ring->sp_wqres.buf.direct.buf;
 102
 103         en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n",
 104                ring, ring->buf, ring->size, ring->buf_size,
 105                (unsigned long long) ring->sp_wqres.buf.direct.map);
 106
 107         err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn,
 108                                     MLX4_RESERVE_ETH_BF_QP,
 109                                     MLX4_RES_USAGE_DRIVER);
 110         if (err) {
 111                 en_err(priv, "failed reserving qp for TX ring\n");
 112                 goto err_hwq_res;
 113         }
 114
 115         err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->sp_qp);
 116         if (err) {
 117                 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
 118                 goto err_reserve;
 119         }
 120         ring->sp_qp.event = mlx4_en_sqp_event;
 121
 122         err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
 123         if (err) {
 124                 en_dbg(DRV, priv, "working without blueflame (%d)\n", err);
 125                 ring->bf.uar = &mdev->priv_uar;
 126                 ring->bf.uar->map = mdev->uar_map;
 127                 ring->bf_enabled = false;
 128                 ring->bf_alloced = false;
 129                 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
 130         } else {
 131                 ring->bf_alloced = true;
 132                 ring->bf_enabled = !!(priv->pflags &
 133                                       MLX4_EN_PRIV_FLAGS_BLUEFLAME);
 134         }
 135
 136         ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type;
 137         ring->queue_index = queue_index;
 138
 139         if (queue_index < priv->num_tx_rings_p_up)
 140                 cpumask_set_cpu(cpumask_local_spread(queue_index,
 141                                                      priv->mdev->dev->numa_node),
 142                                 &ring->sp_affinity_mask);
 143
 144         *pring = ring;
 145         return 0;
 146
 147 err_reserve:
 148         mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
 149 err_hwq_res:
 150         mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
 151 err_bounce:
 152         kfree(ring->bounce_buf);
 153         ring->bounce_buf = NULL;
 154 err_info:
 155         kvfree(ring->tx_info);
 156         ring->tx_info = NULL;
 157 err_ring:
 158         kfree(ring);
 159         *pring = NULL;
 160         return err;
 161 }
 162
 163 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
 164                              struct mlx4_en_tx_ring **pring)
 165 {
 166         struct mlx4_en_dev *mdev = priv->mdev;
 167         struct mlx4_en_tx_ring *ring = *pring;
 168         en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
 169
 170         if (ring->bf_alloced)
 171                 mlx4_bf_free(mdev->dev, &ring->bf);
 172         mlx4_qp_remove(mdev->dev, &ring->sp_qp);
 173         mlx4_qp_free(mdev->dev, &ring->sp_qp);
 174         mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1);
 175         mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
 176         kfree(ring->bounce_buf);
 177         ring->bounce_buf = NULL;
 178         kvfree(ring->tx_info);
 179         ring->tx_info = NULL;
 180         kfree(ring);
 181         *pring = NULL;
 182 }
 183
 184 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 185                              struct mlx4_en_tx_ring *ring,
 186                              int cq, int user_prio)
 187 {
 188         struct mlx4_en_dev *mdev = priv->mdev;
 189         int err;
 190
 191         ring->sp_cqn = cq;
 192         ring->prod = 0;
 193         ring->cons = 0xffffffff;
 194         ring->last_nr_txbb = 1;
 195         memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
 196         memset(ring->buf, 0, ring->buf_size);
 197         ring->free_tx_desc = mlx4_en_free_tx_desc;
 198
 199         ring->sp_qp_state = MLX4_QP_STATE_RST;
 200         ring->doorbell_qpn = cpu_to_be32(ring->sp_qp.qpn << 8);
 201         ring->mr_key = cpu_to_be32(mdev->mr.key);
 202
 203         mlx4_en_fill_qp_context(priv, ring->size, ring->sp_stride, 1, 0, ring->qpn,
 204                                 ring->sp_cqn, user_prio, &ring->sp_context);
 205         if (ring->bf_alloced)
 206                 ring->sp_context.usr_page =
 207                         cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev,
 208                                                          ring->bf.uar->index));
 209
 210         err = mlx4_qp_to_ready(mdev->dev, &ring->sp_wqres.mtt, &ring->sp_context,
 211                                &ring->sp_qp, &ring->sp_qp_state);
 212         if (!cpumask_empty(&ring->sp_affinity_mask))
 213                 netif_set_xps_queue(priv->dev, &ring->sp_affinity_mask,
 214                                     ring->queue_index);
 215
 216         return err;
 217 }
 218
 219 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 220                                 struct mlx4_en_tx_ring *ring)
 221 {
 222         struct mlx4_en_dev *mdev = priv->mdev;
 223
 224         mlx4_qp_modify(mdev->dev, NULL, ring->sp_qp_state,
 225                        MLX4_QP_STATE_RST, NULL, 0, 0, &ring->sp_qp);
 226 }
 227
 228 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring)
 229 {
 230         return ring->prod - ring->cons > ring->full_size;
 231 }
 232
 233 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
 234                               struct mlx4_en_tx_ring *ring, int index,
 235                               u8 owner)
 236 {
 237         __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
 238         struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
 239         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 240         void *end = ring->buf + ring->buf_size;
 241         __be32 *ptr = (__be32 *)tx_desc;
 242         int i;
 243
 244         /* Optimize the common case when there are no wraparounds */
 245         if (likely((void *)tx_desc +
 246                    (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) {
 247                 /* Stamp the freed descriptor */
 248                 for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE;
 249                      i += STAMP_STRIDE) {
 250                         *ptr = stamp;
 251                         ptr += STAMP_DWORDS;
 252                 }
 253         } else {
 254                 /* Stamp the freed descriptor */
 255                 for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE;
 256                      i += STAMP_STRIDE) {
 257                         *ptr = stamp;
 258                         ptr += STAMP_DWORDS;
 259                         if ((void *)ptr >= end) {
 260                                 ptr = ring->buf;
 261                                 stamp ^= cpu_to_be32(0x80000000);
 262                         }
 263                 }
 264         }
 265 }
 266
 267
 268 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
 269                          struct mlx4_en_tx_ring *ring,
 270                          int index, u64 timestamp,
 271                          int napi_mode)
 272 {
 273         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 274         struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
 275         struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
 276         void *end = ring->buf + ring->buf_size;
 277         struct sk_buff *skb = tx_info->skb;
 278         int nr_maps = tx_info->nr_maps;
 279         int i;
 280
 281         /* We do not touch skb here, so prefetch skb->users location
 282          * to speedup consume_skb()
 283          */
 284         prefetchw(&skb->users);
 285
 286         if (unlikely(timestamp)) {
 287                 struct skb_shared_hwtstamps hwts;
 288
 289                 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp);
 290                 skb_tstamp_tx(skb, &hwts);
 291         }
 292
 293         if (!tx_info->inl) {
 294                 if (tx_info->linear)
 295                         dma_unmap_single(priv->ddev,
 296                                          tx_info->map0_dma,
 297                                          tx_info->map0_byte_count,
 298                                          PCI_DMA_TODEVICE);
 299                 else
 300                         dma_unmap_page(priv->ddev,
 301                                        tx_info->map0_dma,
 302                                        tx_info->map0_byte_count,
 303                                        PCI_DMA_TODEVICE);
 304                 /* Optimize the common case when there are no wraparounds */
 305                 if (likely((void *)tx_desc +
 306                            (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) {
 307                         for (i = 1; i < nr_maps; i++) {
 308                                 data++;
 309                                 dma_unmap_page(priv->ddev,
 310                                         (dma_addr_t)be64_to_cpu(data->addr),
 311                                         be32_to_cpu(data->byte_count),
 312                                         PCI_DMA_TODEVICE);
 313                         }
 314                 } else {
 315                         if ((void *)data >= end)
 316                                 data = ring->buf + ((void *)data - end);
 317
 318                         for (i = 1; i < nr_maps; i++) {
 319                                 data++;
 320                                 /* Check for wraparound before unmapping */
 321                                 if ((void *) data >= end)
 322                                         data = ring->buf;
 323                                 dma_unmap_page(priv->ddev,
 324                                         (dma_addr_t)be64_to_cpu(data->addr),
 325                                         be32_to_cpu(data->byte_count),
 326                                         PCI_DMA_TODEVICE);
 327                         }
 328                 }
 329         }
 330         napi_consume_skb(skb, napi_mode);
 331
 332         return tx_info->nr_txbb;
 333 }
 334
 335 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
 336                             struct mlx4_en_tx_ring *ring,
 337                             int index, u64 timestamp,
 338                             int napi_mode)
 339 {
 340         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 341         struct mlx4_en_rx_alloc frame = {
 342                 .page = tx_info->page,
 343                 .dma = tx_info->map0_dma,
 344         };
 345
 346         if (!mlx4_en_rx_recycle(ring->recycle_ring, &frame)) {
 347                 dma_unmap_page(priv->ddev, tx_info->map0_dma,
 348                                PAGE_SIZE, priv->dma_dir);
 349                 put_page(tx_info->page);
 350         }
 351
 352         return tx_info->nr_txbb;
 353 }
 354
 355 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
 356 {
 357         struct mlx4_en_priv *priv = netdev_priv(dev);
 358         int cnt = 0;
 359
 360         /* Skip last polled descriptor */
 361         ring->cons += ring->last_nr_txbb;
 362         en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
 363                  ring->cons, ring->prod);
 364
 365         if ((u32) (ring->prod - ring->cons) > ring->size) {
 366                 if (netif_msg_tx_err(priv))
 367                         en_warn(priv, "Tx consumer passed producer!\n");
 368                 return 0;
 369         }
 370
 371         while (ring->cons != ring->prod) {
 372                 ring->last_nr_txbb = ring->free_tx_desc(priv, ring,
 373                                                 ring->cons & ring->size_mask,
 374                                                 0, 0 /* Non-NAPI caller */);
 375                 ring->cons += ring->last_nr_txbb;
 376                 cnt++;
 377         }
 378
 379         if (ring->tx_queue)
 380                 netdev_tx_reset_queue(ring->tx_queue);
 381
 382         if (cnt)
 383                 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
 384
 385         return cnt;
 386 }
 387
 388 bool mlx4_en_process_tx_cq(struct net_device *dev,
 389                            struct mlx4_en_cq *cq, int napi_budget)
 390 {
 391         struct mlx4_en_priv *priv = netdev_priv(dev);
 392         struct mlx4_cq *mcq = &cq->mcq;
 393         struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->type][cq->ring];
 394         struct mlx4_cqe *cqe;
 395         u16 index, ring_index, stamp_index;
 396         u32 txbbs_skipped = 0;
 397         u32 txbbs_stamp = 0;
 398         u32 cons_index = mcq->cons_index;
 399         int size = cq->size;
 400         u32 size_mask = ring->size_mask;
 401         struct mlx4_cqe *buf = cq->buf;
 402         u32 packets = 0;
 403         u32 bytes = 0;
 404         int factor = priv->cqe_factor;
 405         int done = 0;
 406         int budget = priv->tx_work_limit;
 407         u32 last_nr_txbb;
 408         u32 ring_cons;
 409
 410         if (unlikely(!priv->port_up))
 411                 return true;
 412
 413         netdev_txq_bql_complete_prefetchw(ring->tx_queue);
 414
 415         index = cons_index & size_mask;
 416         cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
 417         last_nr_txbb = READ_ONCE(ring->last_nr_txbb);
 418         ring_cons = READ_ONCE(ring->cons);
 419         ring_index = ring_cons & size_mask;
 420         stamp_index = ring_index;
 421
 422         /* Process all completed CQEs */
 423         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 424                         cons_index & size) && (done < budget)) {
 425                 u16 new_index;
 426
 427                 /*
 428                  * make sure we read the CQE after we read the
 429                  * ownership bit
 430                  */
 431                 dma_rmb();
 432
 433                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 434                              MLX4_CQE_OPCODE_ERROR)) {
 435                         struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe;
 436
 437                         en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n",
 438                                cqe_err->vendor_err_syndrome,
 439                                cqe_err->syndrome);
 440                 }
 441
 442                 /* Skip over last polled CQE */
 443                 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
 444
 445                 do {
 446                         u64 timestamp = 0;
 447
 448                         txbbs_skipped += last_nr_txbb;
 449                         ring_index = (ring_index + last_nr_txbb) & size_mask;
 450
 451                         if (unlikely(ring->tx_info[ring_index].ts_requested))
 452                                 timestamp = mlx4_en_get_cqe_ts(cqe);
 453
 454                         /* free next descriptor */
 455                         last_nr_txbb = ring->free_tx_desc(
 456                                         priv, ring, ring_index,
 457                                         timestamp, napi_budget);
 458
 459                         mlx4_en_stamp_wqe(priv, ring, stamp_index,
 460                                           !!((ring_cons + txbbs_stamp) &
 461                                                 ring->size));
 462                         stamp_index = ring_index;
 463                         txbbs_stamp = txbbs_skipped;
 464                         packets++;
 465                         bytes += ring->tx_info[ring_index].nr_bytes;
 466                 } while ((++done < budget) && (ring_index != new_index));
 467
 468                 ++cons_index;
 469                 index = cons_index & size_mask;
 470                 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
 471         }
 472
 473         /*
 474          * To prevent CQ overflow we first update CQ consumer and only then
 475          * the ring consumer.
 476          */
 477         mcq->cons_index = cons_index;
 478         mlx4_cq_set_ci(mcq);
 479         wmb();
 480
 481         /* we want to dirty this cache line once */
 482         WRITE_ONCE(ring->last_nr_txbb, last_nr_txbb);
 483         WRITE_ONCE(ring->cons, ring_cons + txbbs_skipped);
 484
 485         if (cq->type == TX_XDP)
 486                 return done < budget;
 487
 488         netdev_tx_completed_queue(ring->tx_queue, packets, bytes);
 489
 490         /* Wakeup Tx queue if this stopped, and ring is not full.
 491          */
 492         if (netif_tx_queue_stopped(ring->tx_queue) &&
 493             !mlx4_en_is_tx_ring_full(ring)) {
 494                 netif_tx_wake_queue(ring->tx_queue);
 495                 ring->wake_queue++;
 496         }
 497
 498         return done < budget;
 499 }
 500
 501 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
 502 {
 503         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
 504         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
 505
 506         if (likely(priv->port_up))
 507                 napi_schedule_irqoff(&cq->napi);
 508         else
 509                 mlx4_en_arm_cq(priv, cq);
 510 }
 511
 512 /* TX CQ polling - called by NAPI */
 513 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget)
 514 {
 515         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
 516         struct net_device *dev = cq->dev;
 517         struct mlx4_en_priv *priv = netdev_priv(dev);
 518         bool clean_complete;
 519
 520         clean_complete = mlx4_en_process_tx_cq(dev, cq, budget);
 521         if (!clean_complete)
 522                 return budget;
 523
 524         napi_complete(napi);
 525         mlx4_en_arm_cq(priv, cq);
 526
 527         return 0;
 528 }
 529
 530 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
 531                                                       struct mlx4_en_tx_ring *ring,
 532                                                       u32 index,
 533                                                       unsigned int desc_size)
 534 {
 535         u32 copy = (ring->size - index) << LOG_TXBB_SIZE;
 536         int i;
 537
 538         for (i = desc_size - copy - 4; i >= 0; i -= 4) {
 539                 if ((i & (TXBB_SIZE - 1)) == 0)
 540                         wmb();
 541
 542                 *((u32 *) (ring->buf + i)) =
 543                         *((u32 *) (ring->bounce_buf + copy + i));
 544         }
 545
 546         for (i = copy - 4; i >= 4 ; i -= 4) {
 547                 if ((i & (TXBB_SIZE - 1)) == 0)
 548                         wmb();
 549
 550                 *((u32 *)(ring->buf + (index << LOG_TXBB_SIZE) + i)) =
 551                         *((u32 *) (ring->bounce_buf + i));
 552         }
 553
 554         /* Return real descriptor location */
 555         return ring->buf + (index << LOG_TXBB_SIZE);
 556 }
 557
 558 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping
 559  *
 560  * It seems strange we do not simply use skb_copy_bits().
 561  * This would allow to inline all skbs iff skb->len <= inline_thold
 562  *
 563  * Note that caller already checked skb was not a gso packet
 564  */
 565 static bool is_inline(int inline_thold, const struct sk_buff *skb,
 566                       const struct skb_shared_info *shinfo,
 567                       void **pfrag)
 568 {
 569         void *ptr;
 570
 571         if (skb->len > inline_thold || !inline_thold)
 572                 return false;
 573
 574         if (shinfo->nr_frags == 1) {
 575                 ptr = skb_frag_address_safe(&shinfo->frags[0]);
 576                 if (unlikely(!ptr))
 577                         return false;
 578                 *pfrag = ptr;
 579                 return true;
 580         }
 581         if (shinfo->nr_frags)
 582                 return false;
 583         return true;
 584 }
 585
 586 static int inline_size(const struct sk_buff *skb)
 587 {
 588         if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
 589             <= MLX4_INLINE_ALIGN)
 590                 return ALIGN(skb->len + CTRL_SIZE +
 591                              sizeof(struct mlx4_wqe_inline_seg), 16);
 592         else
 593                 return ALIGN(skb->len + CTRL_SIZE + 2 *
 594                              sizeof(struct mlx4_wqe_inline_seg), 16);
 595 }
 596
 597 static int get_real_size(const struct sk_buff *skb,
 598                          const struct skb_shared_info *shinfo,
 599                          struct net_device *dev,
 600                          int *lso_header_size,
 601                          bool *inline_ok,
 602                          void **pfrag)
 603 {
 604         struct mlx4_en_priv *priv = netdev_priv(dev);
 605         int real_size;
 606
 607         if (shinfo->gso_size) {
 608                 *inline_ok = false;
 609                 if (skb->encapsulation)
 610                         *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb);
 611                 else
 612                         *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
 613                 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE +
 614                         ALIGN(*lso_header_size + 4, DS_SIZE);
 615                 if (unlikely(*lso_header_size != skb_headlen(skb))) {
 616                         /* We add a segment for the skb linear buffer only if
 617                          * it contains data */
 618                         if (*lso_header_size < skb_headlen(skb))
 619                                 real_size += DS_SIZE;
 620                         else {
 621                                 if (netif_msg_tx_err(priv))
 622                                         en_warn(priv, "Non-linear headers\n");
 623                                 return 0;
 624                         }
 625                 }
 626         } else {
 627                 *lso_header_size = 0;
 628                 *inline_ok = is_inline(priv->prof->inline_thold, skb,
 629                                        shinfo, pfrag);
 630
 631                 if (*inline_ok)
 632                         real_size = inline_size(skb);
 633                 else
 634                         real_size = CTRL_SIZE +
 635                                     (shinfo->nr_frags + 1) * DS_SIZE;
 636         }
 637
 638         return real_size;
 639 }
 640
 641 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc,
 642                              const struct sk_buff *skb,
 643                              const struct skb_shared_info *shinfo,
 644                              void *fragptr)
 645 {
 646         struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
 647         int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof(*inl);
 648         unsigned int hlen = skb_headlen(skb);
 649
 650         if (skb->len <= spc) {
 651                 if (likely(skb->len >= MIN_PKT_LEN)) {
 652                         inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
 653                 } else {
 654                         inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN);
 655                         memset(((void *)(inl + 1)) + skb->len, 0,
 656                                MIN_PKT_LEN - skb->len);
 657                 }
 658                 skb_copy_from_linear_data(skb, inl + 1, hlen);
 659                 if (shinfo->nr_frags)
 660                         memcpy(((void *)(inl + 1)) + hlen, fragptr,
 661                                skb_frag_size(&shinfo->frags[0]));
 662
 663         } else {
 664                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
 665                 if (hlen <= spc) {
 666                         skb_copy_from_linear_data(skb, inl + 1, hlen);
 667                         if (hlen < spc) {
 668                                 memcpy(((void *)(inl + 1)) + hlen,
 669                                        fragptr, spc - hlen);
 670                                 fragptr +=  spc - hlen;
 671                         }
 672                         inl = (void *) (inl + 1) + spc;
 673                         memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
 674                 } else {
 675                         skb_copy_from_linear_data(skb, inl + 1, spc);
 676                         inl = (void *) (inl + 1) + spc;
 677                         skb_copy_from_linear_data_offset(skb, spc, inl + 1,
 678                                                          hlen - spc);
 679                         if (shinfo->nr_frags)
 680                                 memcpy(((void *)(inl + 1)) + hlen - spc,
 681                                        fragptr,
 682                                        skb_frag_size(&shinfo->frags[0]));
 683                 }
 684
 685                 dma_wmb();
 686                 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
 687         }
 688 }
 689
 690 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
 691                          struct net_device *sb_dev,
 692                          select_queue_fallback_t fallback)
 693 {
 694         struct mlx4_en_priv *priv = netdev_priv(dev);
 695         u16 rings_p_up = priv->num_tx_rings_p_up;
 696
 697         if (netdev_get_num_tc(dev))
 698                 return fallback(dev, skb, NULL);
 699
 700         return fallback(dev, skb, NULL) % rings_p_up;
 701 }
 702
 703 static void mlx4_bf_copy(void __iomem *dst, const void *src,
 704                          unsigned int bytecnt)
 705 {
 706         __iowrite64_copy(dst, src, bytecnt / 8);
 707 }
 708
 709 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring)
 710 {
 711         wmb();
 712         /* Since there is no iowrite*_native() that writes the
 713          * value as is, without byteswapping - using the one
 714          * the doesn't do byteswapping in the relevant arch
 715          * endianness.
 716          */
 717 #if defined(__LITTLE_ENDIAN)
 718         iowrite32(
 719 #else
 720         iowrite32be(
 721 #endif
 722                   (__force u32)ring->doorbell_qpn,
 723                   ring->bf.uar->map + MLX4_SEND_DOORBELL);
 724 }
 725
 726 static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring,
 727                                   struct mlx4_en_tx_desc *tx_desc,
 728                                   union mlx4_wqe_qpn_vlan qpn_vlan,
 729                                   int desc_size, int bf_index,
 730                                   __be32 op_own, bool bf_ok,
 731                                   bool send_doorbell)
 732 {
 733         tx_desc->ctrl.qpn_vlan = qpn_vlan;
 734
 735         if (bf_ok) {
 736                 op_own |= htonl((bf_index & 0xffff) << 8);
 737                 /* Ensure new descriptor hits memory
 738                  * before setting ownership of this descriptor to HW
 739                  */
 740                 dma_wmb();
 741                 tx_desc->ctrl.owner_opcode = op_own;
 742
 743                 wmb();
 744
 745                 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl,
 746                              desc_size);
 747
 748                 wmb();
 749
 750                 ring->bf.offset ^= ring->bf.buf_size;
 751         } else {
 752                 /* Ensure new descriptor hits memory
 753                  * before setting ownership of this descriptor to HW
 754                  */
 755                 dma_wmb();
 756                 tx_desc->ctrl.owner_opcode = op_own;
 757                 if (send_doorbell)
 758                         mlx4_en_xmit_doorbell(ring);
 759                 else
 760                         ring->xmit_more++;
 761         }
 762 }
 763
 764 static bool mlx4_en_build_dma_wqe(struct mlx4_en_priv *priv,
 765                                   struct skb_shared_info *shinfo,
 766                                   struct mlx4_wqe_data_seg *data,
 767                                   struct sk_buff *skb,
 768                                   int lso_header_size,
 769                                   __be32 mr_key,
 770                                   struct mlx4_en_tx_info *tx_info)
 771 {
 772         struct device *ddev = priv->ddev;
 773         dma_addr_t dma = 0;
 774         u32 byte_count = 0;
 775         int i_frag;
 776
 777         /* Map fragments if any */
 778         for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) {
 779                 const struct skb_frag_struct *frag;
 780
 781                 frag = &shinfo->frags[i_frag];
 782                 byte_count = skb_frag_size(frag);
 783                 dma = skb_frag_dma_map(ddev, frag,
 784                                        0, byte_count,
 785                                        DMA_TO_DEVICE);
 786                 if (dma_mapping_error(ddev, dma))
 787                         goto tx_drop_unmap;
 788
 789                 data->addr = cpu_to_be64(dma);
 790                 data->lkey = mr_key;
 791                 dma_wmb();
 792                 data->byte_count = cpu_to_be32(byte_count);
 793                 --data;
 794         }
 795
 796         /* Map linear part if needed */
 797         if (tx_info->linear) {
 798                 byte_count = skb_headlen(skb) - lso_header_size;
 799
 800                 dma = dma_map_single(ddev, skb->data +
 801                                      lso_header_size, byte_count,
 802                                      PCI_DMA_TODEVICE);
 803                 if (dma_mapping_error(ddev, dma))
 804                         goto tx_drop_unmap;
 805
 806                 data->addr = cpu_to_be64(dma);
 807                 data->lkey = mr_key;
 808                 dma_wmb();
 809                 data->byte_count = cpu_to_be32(byte_count);
 810         }
 811         /* tx completion can avoid cache line miss for common cases */
 812         tx_info->map0_dma = dma;
 813         tx_info->map0_byte_count = byte_count;
 814
 815         return true;
 816
 817 tx_drop_unmap:
 818         en_err(priv, "DMA mapping error\n");
 819
 820         while (++i_frag < shinfo->nr_frags) {
 821                 ++data;
 822                 dma_unmap_page(ddev, (dma_addr_t)be64_to_cpu(data->addr),
 823                                be32_to_cpu(data->byte_count),
 824                                PCI_DMA_TODEVICE);
 825         }
 826
 827         return false;
 828 }
 829
 830 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
 831 {
 832         struct skb_shared_info *shinfo = skb_shinfo(skb);
 833         struct mlx4_en_priv *priv = netdev_priv(dev);
 834         union mlx4_wqe_qpn_vlan qpn_vlan = {};
 835         struct mlx4_en_tx_ring *ring;
 836         struct mlx4_en_tx_desc *tx_desc;
 837         struct mlx4_wqe_data_seg *data;
 838         struct mlx4_en_tx_info *tx_info;
 839         int tx_ind;
 840         int nr_txbb;
 841         int desc_size;
 842         int real_size;
 843         u32 index, bf_index;
 844         __be32 op_own;
 845         int lso_header_size;
 846         void *fragptr = NULL;
 847         bool bounce = false;
 848         bool send_doorbell;
 849         bool stop_queue;
 850         bool inline_ok;
 851         u8 data_offset;
 852         u32 ring_cons;
 853         bool bf_ok;
 854
 855         tx_ind = skb_get_queue_mapping(skb);
 856         ring = priv->tx_ring[TX][tx_ind];
 857
 858         if (unlikely(!priv->port_up))
 859                 goto tx_drop;
 860
 861         /* fetch ring->cons far ahead before needing it to avoid stall */
 862         ring_cons = READ_ONCE(ring->cons);
 863
 864         real_size = get_real_size(skb, shinfo, dev, &lso_header_size,
 865                                   &inline_ok, &fragptr);
 866         if (unlikely(!real_size))
 867                 goto tx_drop_count;
 868
 869         /* Align descriptor to TXBB size */
 870         desc_size = ALIGN(real_size, TXBB_SIZE);
 871         nr_txbb = desc_size >> LOG_TXBB_SIZE;
 872         if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
 873                 if (netif_msg_tx_err(priv))
 874                         en_warn(priv, "Oversized header or SG list\n");
 875                 goto tx_drop_count;
 876         }
 877
 878         bf_ok = ring->bf_enabled;
 879         if (skb_vlan_tag_present(skb)) {
 880                 u16 vlan_proto;
 881
 882                 qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb));
 883                 vlan_proto = be16_to_cpu(skb->vlan_proto);
 884                 if (vlan_proto == ETH_P_8021AD)
 885                         qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN;
 886                 else if (vlan_proto == ETH_P_8021Q)
 887                         qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN;
 888                 else
 889                         qpn_vlan.ins_vlan = 0;
 890                 bf_ok = false;
 891         }
 892
 893         netdev_txq_bql_enqueue_prefetchw(ring->tx_queue);
 894
 895         /* Track current inflight packets for performance analysis */
 896         AVG_PERF_COUNTER(priv->pstats.inflight_avg,
 897                          (u32)(ring->prod - ring_cons - 1));
 898
 899         /* Packet is good - grab an index and transmit it */
 900         index = ring->prod & ring->size_mask;
 901         bf_index = ring->prod;
 902
 903         /* See if we have enough space for whole descriptor TXBB for setting
 904          * SW ownership on next descriptor; if not, use a bounce buffer. */
 905         if (likely(index + nr_txbb <= ring->size))
 906                 tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
 907         else {
 908                 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
 909                 bounce = true;
 910                 bf_ok = false;
 911         }
 912
 913         /* Save skb in tx_info ring */
 914         tx_info = &ring->tx_info[index];
 915         tx_info->skb = skb;
 916         tx_info->nr_txbb = nr_txbb;
 917
 918         if (!lso_header_size) {
 919                 data = &tx_desc->data;
 920                 data_offset = offsetof(struct mlx4_en_tx_desc, data);
 921         } else {
 922                 int lso_align = ALIGN(lso_header_size + 4, DS_SIZE);
 923
 924                 data = (void *)&tx_desc->lso + lso_align;
 925                 data_offset = offsetof(struct mlx4_en_tx_desc, lso) + lso_align;
 926         }
 927
 928         /* valid only for none inline segments */
 929         tx_info->data_offset = data_offset;
 930
 931         tx_info->inl = inline_ok;
 932
 933         tx_info->linear = lso_header_size < skb_headlen(skb) && !inline_ok;
 934
 935         tx_info->nr_maps = shinfo->nr_frags + tx_info->linear;
 936         data += tx_info->nr_maps - 1;
 937
 938         if (!tx_info->inl)
 939                 if (!mlx4_en_build_dma_wqe(priv, shinfo, data, skb,
 940                                            lso_header_size, ring->mr_key,
 941                                            tx_info))
 942                         goto tx_drop_count;
 943
 944         /*
 945          * For timestamping add flag to skb_shinfo and
 946          * set flag for further reference
 947          */
 948         tx_info->ts_requested = 0;
 949         if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON &&
 950                      shinfo->tx_flags & SKBTX_HW_TSTAMP)) {
 951                 shinfo->tx_flags |= SKBTX_IN_PROGRESS;
 952                 tx_info->ts_requested = 1;
 953         }
 954
 955         /* Prepare ctrl segement apart opcode+ownership, which depends on
 956          * whether LSO is used */
 957         tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
 958         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
 959                 if (!skb->encapsulation)
 960                         tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
 961                                                                  MLX4_WQE_CTRL_TCP_UDP_CSUM);
 962                 else
 963                         tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
 964                 ring->tx_csum++;
 965         }
 966
 967         if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) {
 968                 struct ethhdr *ethh;
 969
 970                 /* Copy dst mac address to wqe. This allows loopback in eSwitch,
 971                  * so that VFs and PF can communicate with each other
 972                  */
 973                 ethh = (struct ethhdr *)skb->data;
 974                 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
 975                 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
 976         }
 977
 978         /* Handle LSO (TSO) packets */
 979         if (lso_header_size) {
 980                 int i;
 981
 982                 /* Mark opcode as LSO */
 983                 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
 984                         ((ring->prod & ring->size) ?
 985                                 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
 986
 987                 /* Fill in the LSO prefix */
 988                 tx_desc->lso.mss_hdr_size = cpu_to_be32(
 989                         shinfo->gso_size << 16 | lso_header_size);
 990
 991                 /* Copy headers;
 992                  * note that we already verified that it is linear */
 993                 memcpy(tx_desc->lso.header, skb->data, lso_header_size);
 994
 995                 ring->tso_packets++;
 996
 997                 i = shinfo->gso_segs;
 998                 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size;
 999                 ring->packets += i;
1000         } else {
1001                 /* Normal (Non LSO) packet */
1002                 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
1003                         ((ring->prod & ring->size) ?
1004                          cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1005                 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
1006                 ring->packets++;
1007         }
1008         ring->bytes += tx_info->nr_bytes;
1009         AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
1010
1011         if (tx_info->inl)
1012                 build_inline_wqe(tx_desc, skb, shinfo, fragptr);
1013
1014         if (skb->encapsulation) {
1015                 union {
1016                         struct iphdr *v4;
1017                         struct ipv6hdr *v6;
1018                         unsigned char *hdr;
1019                 } ip;
1020                 u8 proto;
1021
1022                 ip.hdr = skb_inner_network_header(skb);
1023                 proto = (ip.v4->version == 4) ? ip.v4->protocol :
1024                                                 ip.v6->nexthdr;
1025
1026                 if (proto == IPPROTO_TCP || proto == IPPROTO_UDP)
1027                         op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP);
1028                 else
1029                         op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP);
1030         }
1031
1032         ring->prod += nr_txbb;
1033
1034         /* If we used a bounce buffer then copy descriptor back into place */
1035         if (unlikely(bounce))
1036                 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
1037
1038         skb_tx_timestamp(skb);
1039
1040         /* Check available TXBBs And 2K spare for prefetch */
1041         stop_queue = mlx4_en_is_tx_ring_full(ring);
1042         if (unlikely(stop_queue)) {
1043                 netif_tx_stop_queue(ring->tx_queue);
1044                 ring->queue_stopped++;
1045         }
1046
1047         send_doorbell = __netdev_tx_sent_queue(ring->tx_queue,
1048                                                tx_info->nr_bytes,
1049                                                skb->xmit_more);
1050
1051         real_size = (real_size / 16) & 0x3f;
1052
1053         bf_ok &= desc_size <= MAX_BF && send_doorbell;
1054
1055         if (bf_ok)
1056                 qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size);
1057         else
1058                 qpn_vlan.fence_size = real_size;
1059
1060         mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index,
1061                               op_own, bf_ok, send_doorbell);
1062
1063         if (unlikely(stop_queue)) {
1064                 /* If queue was emptied after the if (stop_queue) , and before
1065                  * the netif_tx_stop_queue() - need to wake the queue,
1066                  * or else it will remain stopped forever.
1067                  * Need a memory barrier to make sure ring->cons was not
1068                  * updated before queue was stopped.
1069                  */
1070                 smp_rmb();
1071
1072                 ring_cons = READ_ONCE(ring->cons);
1073                 if (unlikely(!mlx4_en_is_tx_ring_full(ring))) {
1074                         netif_tx_wake_queue(ring->tx_queue);
1075                         ring->wake_queue++;
1076                 }
1077         }
1078         return NETDEV_TX_OK;
1079
1080 tx_drop_count:
1081         ring->tx_dropped++;
1082 tx_drop:
1083         dev_kfree_skb_any(skb);
1084         return NETDEV_TX_OK;
1085 }
1086
1087 #define MLX4_EN_XDP_TX_NRTXBB  1
1088 #define MLX4_EN_XDP_TX_REAL_SZ (((CTRL_SIZE + MLX4_EN_XDP_TX_NRTXBB * DS_SIZE) \
1089                                  / 16) & 0x3f)
1090
1091 void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv,
1092                                     struct mlx4_en_tx_ring *ring)
1093 {
1094         int i;
1095
1096         for (i = 0; i < ring->size; i++) {
1097                 struct mlx4_en_tx_info *tx_info = &ring->tx_info[i];
1098                 struct mlx4_en_tx_desc *tx_desc = ring->buf +
1099                         (i << LOG_TXBB_SIZE);
1100
1101                 tx_info->map0_byte_count = PAGE_SIZE;
1102                 tx_info->nr_txbb = MLX4_EN_XDP_TX_NRTXBB;
1103                 tx_info->data_offset = offsetof(struct mlx4_en_tx_desc, data);
1104                 tx_info->ts_requested = 0;
1105                 tx_info->nr_maps = 1;
1106                 tx_info->linear = 1;
1107                 tx_info->inl = 0;
1108
1109                 tx_desc->data.lkey = ring->mr_key;
1110                 tx_desc->ctrl.qpn_vlan.fence_size = MLX4_EN_XDP_TX_REAL_SZ;
1111                 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
1112         }
1113 }
1114
1115 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
1116                                struct mlx4_en_rx_alloc *frame,
1117                                struct mlx4_en_priv *priv, unsigned int length,
1118                                int tx_ind, bool *doorbell_pending)
1119 {
1120         struct mlx4_en_tx_desc *tx_desc;
1121         struct mlx4_en_tx_info *tx_info;
1122         struct mlx4_wqe_data_seg *data;
1123         struct mlx4_en_tx_ring *ring;
1124         dma_addr_t dma;
1125         __be32 op_own;
1126         int index;
1127
1128         if (unlikely(!priv->port_up))
1129                 goto tx_drop;
1130
1131         ring = priv->tx_ring[TX_XDP][tx_ind];
1132
1133         if (unlikely(mlx4_en_is_tx_ring_full(ring)))
1134                 goto tx_drop_count;
1135
1136         index = ring->prod & ring->size_mask;
1137         tx_info = &ring->tx_info[index];
1138
1139         /* Track current inflight packets for performance analysis */
1140         AVG_PERF_COUNTER(priv->pstats.inflight_avg,
1141                          (u32)(ring->prod - READ_ONCE(ring->cons) - 1));
1142
1143         tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
1144         data = &tx_desc->data;
1145
1146         dma = frame->dma;
1147
1148         tx_info->page = frame->page;
1149         frame->page = NULL;
1150         tx_info->map0_dma = dma;
1151         tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN);
1152
1153         dma_sync_single_range_for_device(priv->ddev, dma, frame->page_offset,
1154                                          length, PCI_DMA_TODEVICE);
1155
1156         data->addr = cpu_to_be64(dma + frame->page_offset);
1157         dma_wmb();
1158         data->byte_count = cpu_to_be32(length);
1159
1160         /* tx completion can avoid cache line miss for common cases */
1161
1162         op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
1163                 ((ring->prod & ring->size) ?
1164                  cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1165
1166         rx_ring->xdp_tx++;
1167         AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, length);
1168
1169         ring->prod += MLX4_EN_XDP_TX_NRTXBB;
1170
1171         /* Ensure new descriptor hits memory
1172          * before setting ownership of this descriptor to HW
1173          */
1174         dma_wmb();
1175         tx_desc->ctrl.owner_opcode = op_own;
1176         ring->xmit_more++;
1177
1178         *doorbell_pending = true;
1179
1180         return NETDEV_TX_OK;
1181
1182 tx_drop_count:
1183         rx_ring->xdp_tx_full++;
1184         *doorbell_pending = true;
1185 tx_drop:
1186         return NETDEV_TX_BUSY;
1187 }