drivers/net/ethernet/mellanox/mlx4/cmd.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/export.h>
  38 #include <linux/pci.h>
  39 #include <linux/errno.h>
  40
  41 #include <linux/mlx4/cmd.h>
  42 #include <linux/mlx4/device.h>
  43 #include <linux/semaphore.h>
  44 #include <rdma/ib_smi.h>
  45 #include <linux/delay.h>
  46 #include <linux/etherdevice.h>
  47
  48 #include <asm/io.h>
  49
  50 #include "mlx4.h"
  51 #include "fw.h"
  52 #include "fw_qos.h"
  53 #include "mlx4_stats.h"
  54
  55 #define CMD_POLL_TOKEN 0xffff
  56 #define INBOX_MASK      0xffffffffffffff00ULL
  57
  58 #define CMD_CHAN_VER 1
  59 #define CMD_CHAN_IF_REV 1
  60
  61 enum {
  62         /* command completed successfully: */
  63         CMD_STAT_OK             = 0x00,
  64         /* Internal error (such as a bus error) occurred while processing command: */
  65         CMD_STAT_INTERNAL_ERR   = 0x01,
  66         /* Operation/command not supported or opcode modifier not supported: */
  67         CMD_STAT_BAD_OP         = 0x02,
  68         /* Parameter not supported or parameter out of range: */
  69         CMD_STAT_BAD_PARAM      = 0x03,
  70         /* System not enabled or bad system state: */
  71         CMD_STAT_BAD_SYS_STATE  = 0x04,
  72         /* Attempt to access reserved or unallocaterd resource: */
  73         CMD_STAT_BAD_RESOURCE   = 0x05,
  74         /* Requested resource is currently executing a command, or is otherwise busy: */
  75         CMD_STAT_RESOURCE_BUSY  = 0x06,
  76         /* Required capability exceeds device limits: */
  77         CMD_STAT_EXCEED_LIM     = 0x08,
  78         /* Resource is not in the appropriate state or ownership: */
  79         CMD_STAT_BAD_RES_STATE  = 0x09,
  80         /* Index out of range: */
  81         CMD_STAT_BAD_INDEX      = 0x0a,
  82         /* FW image corrupted: */
  83         CMD_STAT_BAD_NVMEM      = 0x0b,
  84         /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
  85         CMD_STAT_ICM_ERROR      = 0x0c,
  86         /* Attempt to modify a QP/EE which is not in the presumed state: */
  87         CMD_STAT_BAD_QP_STATE   = 0x10,
  88         /* Bad segment parameters (Address/Size): */
  89         CMD_STAT_BAD_SEG_PARAM  = 0x20,
  90         /* Memory Region has Memory Windows bound to: */
  91         CMD_STAT_REG_BOUND      = 0x21,
  92         /* HCA local attached memory not present: */
  93         CMD_STAT_LAM_NOT_PRE    = 0x22,
  94         /* Bad management packet (silently discarded): */
  95         CMD_STAT_BAD_PKT        = 0x30,
  96         /* More outstanding CQEs in CQ than new CQ size: */
  97         CMD_STAT_BAD_SIZE       = 0x40,
  98         /* Multi Function device support required: */
  99         CMD_STAT_MULTI_FUNC_REQ = 0x50,
 100 };
 101
 102 enum {
 103         HCR_IN_PARAM_OFFSET     = 0x00,
 104         HCR_IN_MODIFIER_OFFSET  = 0x08,
 105         HCR_OUT_PARAM_OFFSET    = 0x0c,
 106         HCR_TOKEN_OFFSET        = 0x14,
 107         HCR_STATUS_OFFSET       = 0x18,
 108
 109         HCR_OPMOD_SHIFT         = 12,
 110         HCR_T_BIT               = 21,
 111         HCR_E_BIT               = 22,
 112         HCR_GO_BIT              = 23
 113 };
 114
 115 enum {
 116         GO_BIT_TIMEOUT_MSECS    = 10000
 117 };
 118
 119 enum mlx4_vlan_transition {
 120         MLX4_VLAN_TRANSITION_VST_VST = 0,
 121         MLX4_VLAN_TRANSITION_VST_VGT = 1,
 122         MLX4_VLAN_TRANSITION_VGT_VST = 2,
 123         MLX4_VLAN_TRANSITION_VGT_VGT = 3,
 124 };
 125
 126
 127 struct mlx4_cmd_context {
 128         struct completion       done;
 129         int                     result;
 130         int                     next;
 131         u64                     out_param;
 132         u16                     token;
 133         u8                      fw_status;
 134 };
 135
 136 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
 137                                     struct mlx4_vhcr_cmd *in_vhcr);
 138
 139 static int mlx4_status_to_errno(u8 status)
 140 {
 141         static const int trans_table[] = {
 142                 [CMD_STAT_INTERNAL_ERR]   = -EIO,
 143                 [CMD_STAT_BAD_OP]         = -EPERM,
 144                 [CMD_STAT_BAD_PARAM]      = -EINVAL,
 145                 [CMD_STAT_BAD_SYS_STATE]  = -ENXIO,
 146                 [CMD_STAT_BAD_RESOURCE]   = -EBADF,
 147                 [CMD_STAT_RESOURCE_BUSY]  = -EBUSY,
 148                 [CMD_STAT_EXCEED_LIM]     = -ENOMEM,
 149                 [CMD_STAT_BAD_RES_STATE]  = -EBADF,
 150                 [CMD_STAT_BAD_INDEX]      = -EBADF,
 151                 [CMD_STAT_BAD_NVMEM]      = -EFAULT,
 152                 [CMD_STAT_ICM_ERROR]      = -ENFILE,
 153                 [CMD_STAT_BAD_QP_STATE]   = -EINVAL,
 154                 [CMD_STAT_BAD_SEG_PARAM]  = -EFAULT,
 155                 [CMD_STAT_REG_BOUND]      = -EBUSY,
 156                 [CMD_STAT_LAM_NOT_PRE]    = -EAGAIN,
 157                 [CMD_STAT_BAD_PKT]        = -EINVAL,
 158                 [CMD_STAT_BAD_SIZE]       = -ENOMEM,
 159                 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
 160         };
 161
 162         if (status >= ARRAY_SIZE(trans_table) ||
 163             (status != CMD_STAT_OK && trans_table[status] == 0))
 164                 return -EIO;
 165
 166         return trans_table[status];
 167 }
 168
 169 static u8 mlx4_errno_to_status(int errno)
 170 {
 171         switch (errno) {
 172         case -EPERM:
 173                 return CMD_STAT_BAD_OP;
 174         case -EINVAL:
 175                 return CMD_STAT_BAD_PARAM;
 176         case -ENXIO:
 177                 return CMD_STAT_BAD_SYS_STATE;
 178         case -EBUSY:
 179                 return CMD_STAT_RESOURCE_BUSY;
 180         case -ENOMEM:
 181                 return CMD_STAT_EXCEED_LIM;
 182         case -ENFILE:
 183                 return CMD_STAT_ICM_ERROR;
 184         default:
 185                 return CMD_STAT_INTERNAL_ERR;
 186         }
 187 }
 188
 189 static int mlx4_internal_err_ret_value(struct mlx4_dev *dev, u16 op,
 190                                        u8 op_modifier)
 191 {
 192         switch (op) {
 193         case MLX4_CMD_UNMAP_ICM:
 194         case MLX4_CMD_UNMAP_ICM_AUX:
 195         case MLX4_CMD_UNMAP_FA:
 196         case MLX4_CMD_2RST_QP:
 197         case MLX4_CMD_HW2SW_EQ:
 198         case MLX4_CMD_HW2SW_CQ:
 199         case MLX4_CMD_HW2SW_SRQ:
 200         case MLX4_CMD_HW2SW_MPT:
 201         case MLX4_CMD_CLOSE_HCA:
 202         case MLX4_QP_FLOW_STEERING_DETACH:
 203         case MLX4_CMD_FREE_RES:
 204         case MLX4_CMD_CLOSE_PORT:
 205                 return CMD_STAT_OK;
 206
 207         case MLX4_CMD_QP_ATTACH:
 208                 /* On Detach case return success */
 209                 if (op_modifier == 0)
 210                         return CMD_STAT_OK;
 211                 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 212
 213         default:
 214                 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 215         }
 216 }
 217
 218 static int mlx4_closing_cmd_fatal_error(u16 op, u8 fw_status)
 219 {
 220         /* Any error during the closing commands below is considered fatal */
 221         if (op == MLX4_CMD_CLOSE_HCA ||
 222             op == MLX4_CMD_HW2SW_EQ ||
 223             op == MLX4_CMD_HW2SW_CQ ||
 224             op == MLX4_CMD_2RST_QP ||
 225             op == MLX4_CMD_HW2SW_SRQ ||
 226             op == MLX4_CMD_SYNC_TPT ||
 227             op == MLX4_CMD_UNMAP_ICM ||
 228             op == MLX4_CMD_UNMAP_ICM_AUX ||
 229             op == MLX4_CMD_UNMAP_FA)
 230                 return 1;
 231         /* Error on MLX4_CMD_HW2SW_MPT is fatal except when fw status equals
 232           * CMD_STAT_REG_BOUND.
 233           * This status indicates that memory region has memory windows bound to it
 234           * which may result from invalid user space usage and is not fatal.
 235           */
 236         if (op == MLX4_CMD_HW2SW_MPT && fw_status != CMD_STAT_REG_BOUND)
 237                 return 1;
 238         return 0;
 239 }
 240
 241 static int mlx4_cmd_reset_flow(struct mlx4_dev *dev, u16 op, u8 op_modifier,
 242                                int err)
 243 {
 244         /* Only if reset flow is really active return code is based on
 245           * command, otherwise current error code is returned.
 246           */
 247         if (mlx4_internal_err_reset) {
 248                 mlx4_enter_error_state(dev->persist);
 249                 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
 250         }
 251
 252         return err;
 253 }
 254
 255 static int comm_pending(struct mlx4_dev *dev)
 256 {
 257         struct mlx4_priv *priv = mlx4_priv(dev);
 258         u32 status = readl(&priv->mfunc.comm->slave_read);
 259
 260         return (swab32(status) >> 31) != priv->cmd.comm_toggle;
 261 }
 262
 263 static int mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
 264 {
 265         struct mlx4_priv *priv = mlx4_priv(dev);
 266         u32 val;
 267
 268         /* To avoid writing to unknown addresses after the device state was
 269          * changed to internal error and the function was rest,
 270          * check the INTERNAL_ERROR flag which is updated under
 271          * device_state_mutex lock.
 272          */
 273         mutex_lock(&dev->persist->device_state_mutex);
 274
 275         if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
 276                 mutex_unlock(&dev->persist->device_state_mutex);
 277                 return -EIO;
 278         }
 279
 280         priv->cmd.comm_toggle ^= 1;
 281         val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
 282         __raw_writel((__force u32) cpu_to_be32(val),
 283                      &priv->mfunc.comm->slave_write);
 284         mmiowb();
 285         mutex_unlock(&dev->persist->device_state_mutex);
 286         return 0;
 287 }
 288
 289 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
 290                        unsigned long timeout)
 291 {
 292         struct mlx4_priv *priv = mlx4_priv(dev);
 293         unsigned long end;
 294         int err = 0;
 295         int ret_from_pending = 0;
 296
 297         /* First, verify that the master reports correct status */
 298         if (comm_pending(dev)) {
 299                 mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
 300                           priv->cmd.comm_toggle, cmd);
 301                 return -EAGAIN;
 302         }
 303
 304         /* Write command */
 305         down(&priv->cmd.poll_sem);
 306         if (mlx4_comm_cmd_post(dev, cmd, param)) {
 307                 /* Only in case the device state is INTERNAL_ERROR,
 308                  * mlx4_comm_cmd_post returns with an error
 309                  */
 310                 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 311                 goto out;
 312         }
 313
 314         end = msecs_to_jiffies(timeout) + jiffies;
 315         while (comm_pending(dev) && time_before(jiffies, end))
 316                 cond_resched();
 317         ret_from_pending = comm_pending(dev);
 318         if (ret_from_pending) {
 319                 /* check if the slave is trying to boot in the middle of
 320                  * FLR process. The only non-zero result in the RESET command
 321                  * is MLX4_DELAY_RESET_SLAVE*/
 322                 if ((MLX4_COMM_CMD_RESET == cmd)) {
 323                         err = MLX4_DELAY_RESET_SLAVE;
 324                         goto out;
 325                 } else {
 326                         mlx4_warn(dev, "Communication channel command 0x%x timed out\n",
 327                                   cmd);
 328                         err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 329                 }
 330         }
 331
 332         if (err)
 333                 mlx4_enter_error_state(dev->persist);
 334 out:
 335         up(&priv->cmd.poll_sem);
 336         return err;
 337 }
 338
 339 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 vhcr_cmd,
 340                               u16 param, u16 op, unsigned long timeout)
 341 {
 342         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 343         struct mlx4_cmd_context *context;
 344         unsigned long end;
 345         int err = 0;
 346
 347         down(&cmd->event_sem);
 348
 349         spin_lock(&cmd->context_lock);
 350         BUG_ON(cmd->free_head < 0);
 351         context = &cmd->context[cmd->free_head];
 352         context->token += cmd->token_mask + 1;
 353         cmd->free_head = context->next;
 354         spin_unlock(&cmd->context_lock);
 355
 356         reinit_completion(&context->done);
 357
 358         if (mlx4_comm_cmd_post(dev, vhcr_cmd, param)) {
 359                 /* Only in case the device state is INTERNAL_ERROR,
 360                  * mlx4_comm_cmd_post returns with an error
 361                  */
 362                 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 363                 goto out;
 364         }
 365
 366         if (!wait_for_completion_timeout(&context->done,
 367                                          msecs_to_jiffies(timeout))) {
 368                 mlx4_warn(dev, "communication channel command 0x%x (op=0x%x) timed out\n",
 369                           vhcr_cmd, op);
 370                 goto out_reset;
 371         }
 372
 373         err = context->result;
 374         if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
 375                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 376                          vhcr_cmd, context->fw_status);
 377                 if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
 378                         goto out_reset;
 379         }
 380
 381         /* wait for comm channel ready
 382          * this is necessary for prevention the race
 383          * when switching between event to polling mode
 384          * Skipping this section in case the device is in FATAL_ERROR state,
 385          * In this state, no commands are sent via the comm channel until
 386          * the device has returned from reset.
 387          */
 388         if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
 389                 end = msecs_to_jiffies(timeout) + jiffies;
 390                 while (comm_pending(dev) && time_before(jiffies, end))
 391                         cond_resched();
 392         }
 393         goto out;
 394
 395 out_reset:
 396         err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 397         mlx4_enter_error_state(dev->persist);
 398 out:
 399         spin_lock(&cmd->context_lock);
 400         context->next = cmd->free_head;
 401         cmd->free_head = context - cmd->context;
 402         spin_unlock(&cmd->context_lock);
 403
 404         up(&cmd->event_sem);
 405         return err;
 406 }
 407
 408 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
 409                   u16 op, unsigned long timeout)
 410 {
 411         if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
 412                 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 413
 414         if (mlx4_priv(dev)->cmd.use_events)
 415                 return mlx4_comm_cmd_wait(dev, cmd, param, op, timeout);
 416         return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
 417 }
 418
 419 static int cmd_pending(struct mlx4_dev *dev)
 420 {
 421         u32 status;
 422
 423         if (pci_channel_offline(dev->persist->pdev))
 424                 return -EIO;
 425
 426         status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
 427
 428         return (status & swab32(1 << HCR_GO_BIT)) ||
 429                 (mlx4_priv(dev)->cmd.toggle ==
 430                  !!(status & swab32(1 << HCR_T_BIT)));
 431 }
 432
 433 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
 434                          u32 in_modifier, u8 op_modifier, u16 op, u16 token,
 435                          int event)
 436 {
 437         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 438         u32 __iomem *hcr = cmd->hcr;
 439         int ret = -EIO;
 440         unsigned long end;
 441
 442         mutex_lock(&dev->persist->device_state_mutex);
 443         /* To avoid writing to unknown addresses after the device state was
 444           * changed to internal error and the chip was reset,
 445           * check the INTERNAL_ERROR flag which is updated under
 446           * device_state_mutex lock.
 447           */
 448         if (pci_channel_offline(dev->persist->pdev) ||
 449             (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
 450                 /*
 451                  * Device is going through error recovery
 452                  * and cannot accept commands.
 453                  */
 454                 goto out;
 455         }
 456
 457         end = jiffies;
 458         if (event)
 459                 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
 460
 461         while (cmd_pending(dev)) {
 462                 if (pci_channel_offline(dev->persist->pdev)) {
 463                         /*
 464                          * Device is going through error recovery
 465                          * and cannot accept commands.
 466                          */
 467                         goto out;
 468                 }
 469
 470                 if (time_after_eq(jiffies, end)) {
 471                         mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
 472                         goto out;
 473                 }
 474                 cond_resched();
 475         }
 476
 477         /*
 478          * We use writel (instead of something like memcpy_toio)
 479          * because writes of less than 32 bits to the HCR don't work
 480          * (and some architectures such as ia64 implement memcpy_toio
 481          * in terms of writeb).
 482          */
 483         __raw_writel((__force u32) cpu_to_be32(in_param >> 32),           hcr + 0);
 484         __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  hcr + 1);
 485         __raw_writel((__force u32) cpu_to_be32(in_modifier),              hcr + 2);
 486         __raw_writel((__force u32) cpu_to_be32(out_param >> 32),          hcr + 3);
 487         __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
 488         __raw_writel((__force u32) cpu_to_be32(token << 16),              hcr + 5);
 489
 490         /* __raw_writel may not order writes. */
 491         wmb();
 492
 493         __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)                |
 494                                                (cmd->toggle << HCR_T_BIT)       |
 495                                                (event ? (1 << HCR_E_BIT) : 0)   |
 496                                                (op_modifier << HCR_OPMOD_SHIFT) |
 497                                                op), hcr + 6);
 498
 499         /*
 500          * Make sure that our HCR writes don't get mixed in with
 501          * writes from another CPU starting a FW command.
 502          */
 503         mmiowb();
 504
 505         cmd->toggle = cmd->toggle ^ 1;
 506
 507         ret = 0;
 508
 509 out:
 510         if (ret)
 511                 mlx4_warn(dev, "Could not post command 0x%x: ret=%d, in_param=0x%llx, in_mod=0x%x, op_mod=0x%x\n",
 512                           op, ret, in_param, in_modifier, op_modifier);
 513         mutex_unlock(&dev->persist->device_state_mutex);
 514
 515         return ret;
 516 }
 517
 518 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 519                           int out_is_imm, u32 in_modifier, u8 op_modifier,
 520                           u16 op, unsigned long timeout)
 521 {
 522         struct mlx4_priv *priv = mlx4_priv(dev);
 523         struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
 524         int ret;
 525
 526         mutex_lock(&priv->cmd.slave_cmd_mutex);
 527
 528         vhcr->in_param = cpu_to_be64(in_param);
 529         vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
 530         vhcr->in_modifier = cpu_to_be32(in_modifier);
 531         vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
 532         vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
 533         vhcr->status = 0;
 534         vhcr->flags = !!(priv->cmd.use_events) << 6;
 535
 536         if (mlx4_is_master(dev)) {
 537                 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
 538                 if (!ret) {
 539                         if (out_is_imm) {
 540                                 if (out_param)
 541                                         *out_param =
 542                                                 be64_to_cpu(vhcr->out_param);
 543                                 else {
 544                                         mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
 545                                                  op);
 546                                         vhcr->status = CMD_STAT_BAD_PARAM;
 547                                 }
 548                         }
 549                         ret = mlx4_status_to_errno(vhcr->status);
 550                 }
 551                 if (ret &&
 552                     dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
 553                         ret = mlx4_internal_err_ret_value(dev, op, op_modifier);
 554         } else {
 555                 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0, op,
 556                                     MLX4_COMM_TIME + timeout);
 557                 if (!ret) {
 558                         if (out_is_imm) {
 559                                 if (out_param)
 560                                         *out_param =
 561                                                 be64_to_cpu(vhcr->out_param);
 562                                 else {
 563                                         mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
 564                                                  op);
 565                                         vhcr->status = CMD_STAT_BAD_PARAM;
 566                                 }
 567                         }
 568                         ret = mlx4_status_to_errno(vhcr->status);
 569                 } else {
 570                         if (dev->persist->state &
 571                             MLX4_DEVICE_STATE_INTERNAL_ERROR)
 572                                 ret = mlx4_internal_err_ret_value(dev, op,
 573                                                                   op_modifier);
 574                         else
 575                                 mlx4_err(dev, "failed execution of VHCR_POST command opcode 0x%x\n", op);
 576                 }
 577         }
 578
 579         mutex_unlock(&priv->cmd.slave_cmd_mutex);
 580         return ret;
 581 }
 582
 583 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 584                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 585                          u16 op, unsigned long timeout)
 586 {
 587         struct mlx4_priv *priv = mlx4_priv(dev);
 588         void __iomem *hcr = priv->cmd.hcr;
 589         int err = 0;
 590         unsigned long end;
 591         u32 stat;
 592
 593         down(&priv->cmd.poll_sem);
 594
 595         if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
 596                 /*
 597                  * Device is going through error recovery
 598                  * and cannot accept commands.
 599                  */
 600                 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
 601                 goto out;
 602         }
 603
 604         if (out_is_imm && !out_param) {
 605                 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
 606                          op);
 607                 err = -EINVAL;
 608                 goto out;
 609         }
 610
 611         err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 612                             in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
 613         if (err)
 614                 goto out_reset;
 615
 616         end = msecs_to_jiffies(timeout) + jiffies;
 617         while (cmd_pending(dev) && time_before(jiffies, end)) {
 618                 if (pci_channel_offline(dev->persist->pdev)) {
 619                         /*
 620                          * Device is going through error recovery
 621                          * and cannot accept commands.
 622                          */
 623                         err = -EIO;
 624                         goto out_reset;
 625                 }
 626
 627                 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
 628                         err = mlx4_internal_err_ret_value(dev, op, op_modifier);
 629                         goto out;
 630                 }
 631
 632                 cond_resched();
 633         }
 634
 635         if (cmd_pending(dev)) {
 636                 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
 637                           op);
 638                 err = -EIO;
 639                 goto out_reset;
 640         }
 641
 642         if (out_is_imm)
 643                 *out_param =
 644                         (u64) be32_to_cpu((__force __be32)
 645                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
 646                         (u64) be32_to_cpu((__force __be32)
 647                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
 648         stat = be32_to_cpu((__force __be32)
 649                            __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
 650         err = mlx4_status_to_errno(stat);
 651         if (err) {
 652                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 653                          op, stat);
 654                 if (mlx4_closing_cmd_fatal_error(op, stat))
 655                         goto out_reset;
 656                 goto out;
 657         }
 658
 659 out_reset:
 660         if (err)
 661                 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
 662 out:
 663         up(&priv->cmd.poll_sem);
 664         return err;
 665 }
 666
 667 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
 668 {
 669         struct mlx4_priv *priv = mlx4_priv(dev);
 670         struct mlx4_cmd_context *context =
 671                 &priv->cmd.context[token & priv->cmd.token_mask];
 672
 673         /* previously timed out command completing at long last */
 674         if (token != context->token)
 675                 return;
 676
 677         context->fw_status = status;
 678         context->result    = mlx4_status_to_errno(status);
 679         context->out_param = out_param;
 680
 681         complete(&context->done);
 682 }
 683
 684 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 685                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 686                          u16 op, unsigned long timeout)
 687 {
 688         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 689         struct mlx4_cmd_context *context;
 690         long ret_wait;
 691         int err = 0;
 692
 693         down(&cmd->event_sem);
 694
 695         spin_lock(&cmd->context_lock);
 696         BUG_ON(cmd->free_head < 0);
 697         context = &cmd->context[cmd->free_head];
 698         context->token += cmd->token_mask + 1;
 699         cmd->free_head = context->next;
 700         spin_unlock(&cmd->context_lock);
 701
 702         if (out_is_imm && !out_param) {
 703                 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
 704                          op);
 705                 err = -EINVAL;
 706                 goto out;
 707         }
 708
 709         reinit_completion(&context->done);
 710
 711         err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 712                             in_modifier, op_modifier, op, context->token, 1);
 713         if (err)
 714                 goto out_reset;
 715
 716         if (op == MLX4_CMD_SENSE_PORT) {
 717                 ret_wait =
 718                         wait_for_completion_interruptible_timeout(&context->done,
 719                                                                   msecs_to_jiffies(timeout));
 720                 if (ret_wait < 0) {
 721                         context->fw_status = 0;
 722                         context->out_param = 0;
 723                         context->result = 0;
 724                 }
 725         } else {
 726                 ret_wait = (long)wait_for_completion_timeout(&context->done,
 727                                                              msecs_to_jiffies(timeout));
 728         }
 729         if (!ret_wait) {
 730                 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
 731                           op);
 732                 if (op == MLX4_CMD_NOP) {
 733                         err = -EBUSY;
 734                         goto out;
 735                 } else {
 736                         err = -EIO;
 737                         goto out_reset;
 738                 }
 739         }
 740
 741         err = context->result;
 742         if (err) {
 743                 /* Since we do not want to have this error message always
 744                  * displayed at driver start when there are ConnectX2 HCAs
 745                  * on the host, we deprecate the error message for this
 746                  * specific command/input_mod/opcode_mod/fw-status to be debug.
 747                  */
 748                 if (op == MLX4_CMD_SET_PORT &&
 749                     (in_modifier == 1 || in_modifier == 2) &&
 750                     op_modifier == MLX4_SET_PORT_IB_OPCODE &&
 751                     context->fw_status == CMD_STAT_BAD_SIZE)
 752                         mlx4_dbg(dev, "command 0x%x failed: fw status = 0x%x\n",
 753                                  op, context->fw_status);
 754                 else
 755                         mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 756                                  op, context->fw_status);
 757                 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
 758                         err = mlx4_internal_err_ret_value(dev, op, op_modifier);
 759                 else if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
 760                         goto out_reset;
 761
 762                 goto out;
 763         }
 764
 765         if (out_is_imm)
 766                 *out_param = context->out_param;
 767
 768 out_reset:
 769         if (err)
 770                 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
 771 out:
 772         spin_lock(&cmd->context_lock);
 773         context->next = cmd->free_head;
 774         cmd->free_head = context - cmd->context;
 775         spin_unlock(&cmd->context_lock);
 776
 777         up(&cmd->event_sem);
 778         return err;
 779 }
 780
 781 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 782                int out_is_imm, u32 in_modifier, u8 op_modifier,
 783                u16 op, unsigned long timeout, int native)
 784 {
 785         if (pci_channel_offline(dev->persist->pdev))
 786                 return mlx4_cmd_reset_flow(dev, op, op_modifier, -EIO);
 787
 788         if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
 789                 int ret;
 790
 791                 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
 792                         return mlx4_internal_err_ret_value(dev, op,
 793                                                           op_modifier);
 794                 down_read(&mlx4_priv(dev)->cmd.switch_sem);
 795                 if (mlx4_priv(dev)->cmd.use_events)
 796                         ret = mlx4_cmd_wait(dev, in_param, out_param,
 797                                             out_is_imm, in_modifier,
 798                                             op_modifier, op, timeout);
 799                 else
 800                         ret = mlx4_cmd_poll(dev, in_param, out_param,
 801                                             out_is_imm, in_modifier,
 802                                             op_modifier, op, timeout);
 803
 804                 up_read(&mlx4_priv(dev)->cmd.switch_sem);
 805                 return ret;
 806         }
 807         return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
 808                               in_modifier, op_modifier, op, timeout);
 809 }
 810 EXPORT_SYMBOL_GPL(__mlx4_cmd);
 811
 812
 813 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
 814 {
 815         return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
 816                         MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
 817 }
 818
 819 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
 820                            int slave, u64 slave_addr,
 821                            int size, int is_read)
 822 {
 823         u64 in_param;
 824         u64 out_param;
 825
 826         if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
 827             (slave & ~0x7f) | (size & 0xff)) {
 828                 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
 829                          slave_addr, master_addr, slave, size);
 830                 return -EINVAL;
 831         }
 832
 833         if (is_read) {
 834                 in_param = (u64) slave | slave_addr;
 835                 out_param = (u64) dev->caps.function | master_addr;
 836         } else {
 837                 in_param = (u64) dev->caps.function | master_addr;
 838                 out_param = (u64) slave | slave_addr;
 839         }
 840
 841         return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
 842                             MLX4_CMD_ACCESS_MEM,
 843                             MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 844 }
 845
 846 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
 847                                struct mlx4_cmd_mailbox *inbox,
 848                                struct mlx4_cmd_mailbox *outbox)
 849 {
 850         struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
 851         struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
 852         int err;
 853         int i;
 854
 855         if (index & 0x1f)
 856                 return -EINVAL;
 857
 858         in_mad->attr_mod = cpu_to_be32(index / 32);
 859
 860         err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
 861                            MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
 862                            MLX4_CMD_NATIVE);
 863         if (err)
 864                 return err;
 865
 866         for (i = 0; i < 32; ++i)
 867                 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
 868
 869         return err;
 870 }
 871
 872 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
 873                                struct mlx4_cmd_mailbox *inbox,
 874                                struct mlx4_cmd_mailbox *outbox)
 875 {
 876         int i;
 877         int err;
 878
 879         for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
 880                 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
 881                 if (err)
 882                         return err;
 883         }
 884
 885         return 0;
 886 }
 887 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
 888 #define PORT_STATE_OFFSET 32
 889
 890 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
 891 {
 892         if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
 893                 return IB_PORT_ACTIVE;
 894         else
 895                 return IB_PORT_DOWN;
 896 }
 897
 898 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
 899                                 struct mlx4_vhcr *vhcr,
 900                                 struct mlx4_cmd_mailbox *inbox,
 901                                 struct mlx4_cmd_mailbox *outbox,
 902                                 struct mlx4_cmd_info *cmd)
 903 {
 904         struct ib_smp *smp = inbox->buf;
 905         u32 index;
 906         u8 port, slave_port;
 907         u8 opcode_modifier;
 908         u16 *table;
 909         int err;
 910         int vidx, pidx;
 911         int network_view;
 912         struct mlx4_priv *priv = mlx4_priv(dev);
 913         struct ib_smp *outsmp = outbox->buf;
 914         __be16 *outtab = (__be16 *)(outsmp->data);
 915         __be32 slave_cap_mask;
 916         __be64 slave_node_guid;
 917
 918         slave_port = vhcr->in_modifier;
 919         port = mlx4_slave_convert_port(dev, slave, slave_port);
 920
 921         /* network-view bit is for driver use only, and should not be passed to FW */
 922         opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */
 923         network_view = !!(vhcr->op_modifier & 0x8);
 924
 925         if (smp->base_version == 1 &&
 926             smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
 927             smp->class_version == 1) {
 928                 /* host view is paravirtualized */
 929                 if (!network_view && smp->method == IB_MGMT_METHOD_GET) {
 930                         if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
 931                                 index = be32_to_cpu(smp->attr_mod);
 932                                 if (port < 1 || port > dev->caps.num_ports)
 933                                         return -EINVAL;
 934                                 table = kcalloc((dev->caps.pkey_table_len[port] / 32) + 1,
 935                                                 sizeof(*table) * 32, GFP_KERNEL);
 936
 937                                 if (!table)
 938                                         return -ENOMEM;
 939                                 /* need to get the full pkey table because the paravirtualized
 940                                  * pkeys may be scattered among several pkey blocks.
 941                                  */
 942                                 err = get_full_pkey_table(dev, port, table, inbox, outbox);
 943                                 if (!err) {
 944                                         for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
 945                                                 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
 946                                                 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
 947                                         }
 948                                 }
 949                                 kfree(table);
 950                                 return err;
 951                         }
 952                         if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
 953                                 /*get the slave specific caps:*/
 954                                 /*do the command */
 955                                 smp->attr_mod = cpu_to_be32(port);
 956                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 957                                             port, opcode_modifier,
 958                                             vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 959                                 /* modify the response for slaves */
 960                                 if (!err && slave != mlx4_master_func_num(dev)) {
 961                                         u8 *state = outsmp->data + PORT_STATE_OFFSET;
 962
 963                                         *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
 964                                         slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
 965                                         memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
 966                                 }
 967                                 return err;
 968                         }
 969                         if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
 970                                 __be64 guid = mlx4_get_admin_guid(dev, slave,
 971                                                                   port);
 972
 973                                 /* set the PF admin guid to the FW/HW burned
 974                                  * GUID, if it wasn't yet set
 975                                  */
 976                                 if (slave == 0 && guid == 0) {
 977                                         smp->attr_mod = 0;
 978                                         err = mlx4_cmd_box(dev,
 979                                                            inbox->dma,
 980                                                            outbox->dma,
 981                                                            vhcr->in_modifier,
 982                                                            opcode_modifier,
 983                                                            vhcr->op,
 984                                                            MLX4_CMD_TIME_CLASS_C,
 985                                                            MLX4_CMD_NATIVE);
 986                                         if (err)
 987                                                 return err;
 988                                         mlx4_set_admin_guid(dev,
 989                                                             *(__be64 *)outsmp->
 990                                                             data, slave, port);
 991                                 } else {
 992                                         memcpy(outsmp->data, &guid, 8);
 993                                 }
 994
 995                                 /* clean all other gids */
 996                                 memset(outsmp->data + 8, 0, 56);
 997                                 return 0;
 998                         }
 999                         if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
1000                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
1001                                              port, opcode_modifier,
1002                                              vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
1003                                 if (!err) {
1004                                         slave_node_guid =  mlx4_get_slave_node_guid(dev, slave);
1005                                         memcpy(outsmp->data + 12, &slave_node_guid, 8);
1006                                 }
1007                                 return err;
1008                         }
1009                 }
1010         }
1011
1012         /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
1013          * These are the MADs used by ib verbs (such as ib_query_gids).
1014          */
1015         if (slave != mlx4_master_func_num(dev) &&
1016             !mlx4_vf_smi_enabled(dev, slave, port)) {
1017                 if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
1018                       smp->method == IB_MGMT_METHOD_GET) || network_view) {
1019                         mlx4_err(dev, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
1020                                  slave, smp->mgmt_class, smp->method,
1021                                  network_view ? "Network" : "Host",
1022                                  be16_to_cpu(smp->attr_id));
1023                         return -EPERM;
1024                 }
1025         }
1026
1027         return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
1028                                     vhcr->in_modifier, opcode_modifier,
1029                                     vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
1030 }
1031
1032 static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
1033                      struct mlx4_vhcr *vhcr,
1034                      struct mlx4_cmd_mailbox *inbox,
1035                      struct mlx4_cmd_mailbox *outbox,
1036                      struct mlx4_cmd_info *cmd)
1037 {
1038         return -EPERM;
1039 }
1040
1041 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
1042                      struct mlx4_vhcr *vhcr,
1043                      struct mlx4_cmd_mailbox *inbox,
1044                      struct mlx4_cmd_mailbox *outbox,
1045                      struct mlx4_cmd_info *cmd)
1046 {
1047         u64 in_param;
1048         u64 out_param;
1049         int err;
1050
1051         in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
1052         out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
1053         if (cmd->encode_slave_id) {
1054                 in_param &= 0xffffffffffffff00ll;
1055                 in_param |= slave;
1056         }
1057
1058         err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
1059                          vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
1060                          MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1061
1062         if (cmd->out_is_imm)
1063                 vhcr->out_param = out_param;
1064
1065         return err;
1066 }
1067
1068 static struct mlx4_cmd_info cmd_info[] = {
1069         {
1070                 .opcode = MLX4_CMD_QUERY_FW,
1071                 .has_inbox = false,
1072                 .has_outbox = true,
1073                 .out_is_imm = false,
1074                 .encode_slave_id = false,
1075                 .verify = NULL,
1076                 .wrapper = mlx4_QUERY_FW_wrapper
1077         },
1078         {
1079                 .opcode = MLX4_CMD_QUERY_HCA,
1080                 .has_inbox = false,
1081                 .has_outbox = true,
1082                 .out_is_imm = false,
1083                 .encode_slave_id = false,
1084                 .verify = NULL,
1085                 .wrapper = NULL
1086         },
1087         {
1088                 .opcode = MLX4_CMD_QUERY_DEV_CAP,
1089                 .has_inbox = false,
1090                 .has_outbox = true,
1091                 .out_is_imm = false,
1092                 .encode_slave_id = false,
1093                 .verify = NULL,
1094                 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
1095         },
1096         {
1097                 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
1098                 .has_inbox = false,
1099                 .has_outbox = true,
1100                 .out_is_imm = false,
1101                 .encode_slave_id = false,
1102                 .verify = NULL,
1103                 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
1104         },
1105         {
1106                 .opcode = MLX4_CMD_QUERY_ADAPTER,
1107                 .has_inbox = false,
1108                 .has_outbox = true,
1109                 .out_is_imm = false,
1110                 .encode_slave_id = false,
1111                 .verify = NULL,
1112                 .wrapper = NULL
1113         },
1114         {
1115                 .opcode = MLX4_CMD_INIT_PORT,
1116                 .has_inbox = false,
1117                 .has_outbox = false,
1118                 .out_is_imm = false,
1119                 .encode_slave_id = false,
1120                 .verify = NULL,
1121                 .wrapper = mlx4_INIT_PORT_wrapper
1122         },
1123         {
1124                 .opcode = MLX4_CMD_CLOSE_PORT,
1125                 .has_inbox = false,
1126                 .has_outbox = false,
1127                 .out_is_imm  = false,
1128                 .encode_slave_id = false,
1129                 .verify = NULL,
1130                 .wrapper = mlx4_CLOSE_PORT_wrapper
1131         },
1132         {
1133                 .opcode = MLX4_CMD_QUERY_PORT,
1134                 .has_inbox = false,
1135                 .has_outbox = true,
1136                 .out_is_imm = false,
1137                 .encode_slave_id = false,
1138                 .verify = NULL,
1139                 .wrapper = mlx4_QUERY_PORT_wrapper
1140         },
1141         {
1142                 .opcode = MLX4_CMD_SET_PORT,
1143                 .has_inbox = true,
1144                 .has_outbox = false,
1145                 .out_is_imm = false,
1146                 .encode_slave_id = false,
1147                 .verify = NULL,
1148                 .wrapper = mlx4_SET_PORT_wrapper
1149         },
1150         {
1151                 .opcode = MLX4_CMD_MAP_EQ,
1152                 .has_inbox = false,
1153                 .has_outbox = false,
1154                 .out_is_imm = false,
1155                 .encode_slave_id = false,
1156                 .verify = NULL,
1157                 .wrapper = mlx4_MAP_EQ_wrapper
1158         },
1159         {
1160                 .opcode = MLX4_CMD_SW2HW_EQ,
1161                 .has_inbox = true,
1162                 .has_outbox = false,
1163                 .out_is_imm = false,
1164                 .encode_slave_id = true,
1165                 .verify = NULL,
1166                 .wrapper = mlx4_SW2HW_EQ_wrapper
1167         },
1168         {
1169                 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
1170                 .has_inbox = false,
1171                 .has_outbox = false,
1172                 .out_is_imm = false,
1173                 .encode_slave_id = false,
1174                 .verify = NULL,
1175                 .wrapper = NULL
1176         },
1177         {
1178                 .opcode = MLX4_CMD_NOP,
1179                 .has_inbox = false,
1180                 .has_outbox = false,
1181                 .out_is_imm = false,
1182                 .encode_slave_id = false,
1183                 .verify = NULL,
1184                 .wrapper = NULL
1185         },
1186         {
1187                 .opcode = MLX4_CMD_CONFIG_DEV,
1188                 .has_inbox = false,
1189                 .has_outbox = true,
1190                 .out_is_imm = false,
1191                 .encode_slave_id = false,
1192                 .verify = NULL,
1193                 .wrapper = mlx4_CONFIG_DEV_wrapper
1194         },
1195         {
1196                 .opcode = MLX4_CMD_ALLOC_RES,
1197                 .has_inbox = false,
1198                 .has_outbox = false,
1199                 .out_is_imm = true,
1200                 .encode_slave_id = false,
1201                 .verify = NULL,
1202                 .wrapper = mlx4_ALLOC_RES_wrapper
1203         },
1204         {
1205                 .opcode = MLX4_CMD_FREE_RES,
1206                 .has_inbox = false,
1207                 .has_outbox = false,
1208                 .out_is_imm = false,
1209                 .encode_slave_id = false,
1210                 .verify = NULL,
1211                 .wrapper = mlx4_FREE_RES_wrapper
1212         },
1213         {
1214                 .opcode = MLX4_CMD_SW2HW_MPT,
1215                 .has_inbox = true,
1216                 .has_outbox = false,
1217                 .out_is_imm = false,
1218                 .encode_slave_id = true,
1219                 .verify = NULL,
1220                 .wrapper = mlx4_SW2HW_MPT_wrapper
1221         },
1222         {
1223                 .opcode = MLX4_CMD_QUERY_MPT,
1224                 .has_inbox = false,
1225                 .has_outbox = true,
1226                 .out_is_imm = false,
1227                 .encode_slave_id = false,
1228                 .verify = NULL,
1229                 .wrapper = mlx4_QUERY_MPT_wrapper
1230         },
1231         {
1232                 .opcode = MLX4_CMD_HW2SW_MPT,
1233                 .has_inbox = false,
1234                 .has_outbox = false,
1235                 .out_is_imm = false,
1236                 .encode_slave_id = false,
1237                 .verify = NULL,
1238                 .wrapper = mlx4_HW2SW_MPT_wrapper
1239         },
1240         {
1241                 .opcode = MLX4_CMD_READ_MTT,
1242                 .has_inbox = false,
1243                 .has_outbox = true,
1244                 .out_is_imm = false,
1245                 .encode_slave_id = false,
1246                 .verify = NULL,
1247                 .wrapper = NULL
1248         },
1249         {
1250                 .opcode = MLX4_CMD_WRITE_MTT,
1251                 .has_inbox = true,
1252                 .has_outbox = false,
1253                 .out_is_imm = false,
1254                 .encode_slave_id = false,
1255                 .verify = NULL,
1256                 .wrapper = mlx4_WRITE_MTT_wrapper
1257         },
1258         {
1259                 .opcode = MLX4_CMD_SYNC_TPT,
1260                 .has_inbox = true,
1261                 .has_outbox = false,
1262                 .out_is_imm = false,
1263                 .encode_slave_id = false,
1264                 .verify = NULL,
1265                 .wrapper = NULL
1266         },
1267         {
1268                 .opcode = MLX4_CMD_HW2SW_EQ,
1269                 .has_inbox = false,
1270                 .has_outbox = false,
1271                 .out_is_imm = false,
1272                 .encode_slave_id = true,
1273                 .verify = NULL,
1274                 .wrapper = mlx4_HW2SW_EQ_wrapper
1275         },
1276         {
1277                 .opcode = MLX4_CMD_QUERY_EQ,
1278                 .has_inbox = false,
1279                 .has_outbox = true,
1280                 .out_is_imm = false,
1281                 .encode_slave_id = true,
1282                 .verify = NULL,
1283                 .wrapper = mlx4_QUERY_EQ_wrapper
1284         },
1285         {
1286                 .opcode = MLX4_CMD_SW2HW_CQ,
1287                 .has_inbox = true,
1288                 .has_outbox = false,
1289                 .out_is_imm = false,
1290                 .encode_slave_id = true,
1291                 .verify = NULL,
1292                 .wrapper = mlx4_SW2HW_CQ_wrapper
1293         },
1294         {
1295                 .opcode = MLX4_CMD_HW2SW_CQ,
1296                 .has_inbox = false,
1297                 .has_outbox = false,
1298                 .out_is_imm = false,
1299                 .encode_slave_id = false,
1300                 .verify = NULL,
1301                 .wrapper = mlx4_HW2SW_CQ_wrapper
1302         },
1303         {
1304                 .opcode = MLX4_CMD_QUERY_CQ,
1305                 .has_inbox = false,
1306                 .has_outbox = true,
1307                 .out_is_imm = false,
1308                 .encode_slave_id = false,
1309                 .verify = NULL,
1310                 .wrapper = mlx4_QUERY_CQ_wrapper
1311         },
1312         {
1313                 .opcode = MLX4_CMD_MODIFY_CQ,
1314                 .has_inbox = true,
1315                 .has_outbox = false,
1316                 .out_is_imm = true,
1317                 .encode_slave_id = false,
1318                 .verify = NULL,
1319                 .wrapper = mlx4_MODIFY_CQ_wrapper
1320         },
1321         {
1322                 .opcode = MLX4_CMD_SW2HW_SRQ,
1323                 .has_inbox = true,
1324                 .has_outbox = false,
1325                 .out_is_imm = false,
1326                 .encode_slave_id = true,
1327                 .verify = NULL,
1328                 .wrapper = mlx4_SW2HW_SRQ_wrapper
1329         },
1330         {
1331                 .opcode = MLX4_CMD_HW2SW_SRQ,
1332                 .has_inbox = false,
1333                 .has_outbox = false,
1334                 .out_is_imm = false,
1335                 .encode_slave_id = false,
1336                 .verify = NULL,
1337                 .wrapper = mlx4_HW2SW_SRQ_wrapper
1338         },
1339         {
1340                 .opcode = MLX4_CMD_QUERY_SRQ,
1341                 .has_inbox = false,
1342                 .has_outbox = true,
1343                 .out_is_imm = false,
1344                 .encode_slave_id = false,
1345                 .verify = NULL,
1346                 .wrapper = mlx4_QUERY_SRQ_wrapper
1347         },
1348         {
1349                 .opcode = MLX4_CMD_ARM_SRQ,
1350                 .has_inbox = false,
1351                 .has_outbox = false,
1352                 .out_is_imm = false,
1353                 .encode_slave_id = false,
1354                 .verify = NULL,
1355                 .wrapper = mlx4_ARM_SRQ_wrapper
1356         },
1357         {
1358                 .opcode = MLX4_CMD_RST2INIT_QP,
1359                 .has_inbox = true,
1360                 .has_outbox = false,
1361                 .out_is_imm = false,
1362                 .encode_slave_id = true,
1363                 .verify = NULL,
1364                 .wrapper = mlx4_RST2INIT_QP_wrapper
1365         },
1366         {
1367                 .opcode = MLX4_CMD_INIT2INIT_QP,
1368                 .has_inbox = true,
1369                 .has_outbox = false,
1370                 .out_is_imm = false,
1371                 .encode_slave_id = false,
1372                 .verify = NULL,
1373                 .wrapper = mlx4_INIT2INIT_QP_wrapper
1374         },
1375         {
1376                 .opcode = MLX4_CMD_INIT2RTR_QP,
1377                 .has_inbox = true,
1378                 .has_outbox = false,
1379                 .out_is_imm = false,
1380                 .encode_slave_id = false,
1381                 .verify = NULL,
1382                 .wrapper = mlx4_INIT2RTR_QP_wrapper
1383         },
1384         {
1385                 .opcode = MLX4_CMD_RTR2RTS_QP,
1386                 .has_inbox = true,
1387                 .has_outbox = false,
1388                 .out_is_imm = false,
1389                 .encode_slave_id = false,
1390                 .verify = NULL,
1391                 .wrapper = mlx4_RTR2RTS_QP_wrapper
1392         },
1393         {
1394                 .opcode = MLX4_CMD_RTS2RTS_QP,
1395                 .has_inbox = true,
1396                 .has_outbox = false,
1397                 .out_is_imm = false,
1398                 .encode_slave_id = false,
1399                 .verify = NULL,
1400                 .wrapper = mlx4_RTS2RTS_QP_wrapper
1401         },
1402         {
1403                 .opcode = MLX4_CMD_SQERR2RTS_QP,
1404                 .has_inbox = true,
1405                 .has_outbox = false,
1406                 .out_is_imm = false,
1407                 .encode_slave_id = false,
1408                 .verify = NULL,
1409                 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1410         },
1411         {
1412                 .opcode = MLX4_CMD_2ERR_QP,
1413                 .has_inbox = false,
1414                 .has_outbox = false,
1415                 .out_is_imm = false,
1416                 .encode_slave_id = false,
1417                 .verify = NULL,
1418                 .wrapper = mlx4_GEN_QP_wrapper
1419         },
1420         {
1421                 .opcode = MLX4_CMD_RTS2SQD_QP,
1422                 .has_inbox = false,
1423                 .has_outbox = false,
1424                 .out_is_imm = false,
1425                 .encode_slave_id = false,
1426                 .verify = NULL,
1427                 .wrapper = mlx4_GEN_QP_wrapper
1428         },
1429         {
1430                 .opcode = MLX4_CMD_SQD2SQD_QP,
1431                 .has_inbox = true,
1432                 .has_outbox = false,
1433                 .out_is_imm = false,
1434                 .encode_slave_id = false,
1435                 .verify = NULL,
1436                 .wrapper = mlx4_SQD2SQD_QP_wrapper
1437         },
1438         {
1439                 .opcode = MLX4_CMD_SQD2RTS_QP,
1440                 .has_inbox = true,
1441                 .has_outbox = false,
1442                 .out_is_imm = false,
1443                 .encode_slave_id = false,
1444                 .verify = NULL,
1445                 .wrapper = mlx4_SQD2RTS_QP_wrapper
1446         },
1447         {
1448                 .opcode = MLX4_CMD_2RST_QP,
1449                 .has_inbox = false,
1450                 .has_outbox = false,
1451                 .out_is_imm = false,
1452                 .encode_slave_id = false,
1453                 .verify = NULL,
1454                 .wrapper = mlx4_2RST_QP_wrapper
1455         },
1456         {
1457                 .opcode = MLX4_CMD_QUERY_QP,
1458                 .has_inbox = false,
1459                 .has_outbox = true,
1460                 .out_is_imm = false,
1461                 .encode_slave_id = false,
1462                 .verify = NULL,
1463                 .wrapper = mlx4_GEN_QP_wrapper
1464         },
1465         {
1466                 .opcode = MLX4_CMD_SUSPEND_QP,
1467                 .has_inbox = false,
1468                 .has_outbox = false,
1469                 .out_is_imm = false,
1470                 .encode_slave_id = false,
1471                 .verify = NULL,
1472                 .wrapper = mlx4_GEN_QP_wrapper
1473         },
1474         {
1475                 .opcode = MLX4_CMD_UNSUSPEND_QP,
1476                 .has_inbox = false,
1477                 .has_outbox = false,
1478                 .out_is_imm = false,
1479                 .encode_slave_id = false,
1480                 .verify = NULL,
1481                 .wrapper = mlx4_GEN_QP_wrapper
1482         },
1483         {
1484                 .opcode = MLX4_CMD_UPDATE_QP,
1485                 .has_inbox = true,
1486                 .has_outbox = false,
1487                 .out_is_imm = false,
1488                 .encode_slave_id = false,
1489                 .verify = NULL,
1490                 .wrapper = mlx4_UPDATE_QP_wrapper
1491         },
1492         {
1493                 .opcode = MLX4_CMD_GET_OP_REQ,
1494                 .has_inbox = false,
1495                 .has_outbox = false,
1496                 .out_is_imm = false,
1497                 .encode_slave_id = false,
1498                 .verify = NULL,
1499                 .wrapper = mlx4_CMD_EPERM_wrapper,
1500         },
1501         {
1502                 .opcode = MLX4_CMD_ALLOCATE_VPP,
1503                 .has_inbox = false,
1504                 .has_outbox = true,
1505                 .out_is_imm = false,
1506                 .encode_slave_id = false,
1507                 .verify = NULL,
1508                 .wrapper = mlx4_CMD_EPERM_wrapper,
1509         },
1510         {
1511                 .opcode = MLX4_CMD_SET_VPORT_QOS,
1512                 .has_inbox = false,
1513                 .has_outbox = true,
1514                 .out_is_imm = false,
1515                 .encode_slave_id = false,
1516                 .verify = NULL,
1517                 .wrapper = mlx4_CMD_EPERM_wrapper,
1518         },
1519         {
1520                 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1521                 .has_inbox = false,
1522                 .has_outbox = false,
1523                 .out_is_imm = false,
1524                 .encode_slave_id = false,
1525                 .verify = NULL, /* XXX verify: only demux can do this */
1526                 .wrapper = NULL
1527         },
1528         {
1529                 .opcode = MLX4_CMD_MAD_IFC,
1530                 .has_inbox = true,
1531                 .has_outbox = true,
1532                 .out_is_imm = false,
1533                 .encode_slave_id = false,
1534                 .verify = NULL,
1535                 .wrapper = mlx4_MAD_IFC_wrapper
1536         },
1537         {
1538                 .opcode = MLX4_CMD_MAD_DEMUX,
1539                 .has_inbox = false,
1540                 .has_outbox = false,
1541                 .out_is_imm = false,
1542                 .encode_slave_id = false,
1543                 .verify = NULL,
1544                 .wrapper = mlx4_CMD_EPERM_wrapper
1545         },
1546         {
1547                 .opcode = MLX4_CMD_QUERY_IF_STAT,
1548                 .has_inbox = false,
1549                 .has_outbox = true,
1550                 .out_is_imm = false,
1551                 .encode_slave_id = false,
1552                 .verify = NULL,
1553                 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1554         },
1555         {
1556                 .opcode = MLX4_CMD_ACCESS_REG,
1557                 .has_inbox = true,
1558                 .has_outbox = true,
1559                 .out_is_imm = false,
1560                 .encode_slave_id = false,
1561                 .verify = NULL,
1562                 .wrapper = mlx4_ACCESS_REG_wrapper,
1563         },
1564         {
1565                 .opcode = MLX4_CMD_CONGESTION_CTRL_OPCODE,
1566                 .has_inbox = false,
1567                 .has_outbox = false,
1568                 .out_is_imm = false,
1569                 .encode_slave_id = false,
1570                 .verify = NULL,
1571                 .wrapper = mlx4_CMD_EPERM_wrapper,
1572         },
1573         /* Native multicast commands are not available for guests */
1574         {
1575                 .opcode = MLX4_CMD_QP_ATTACH,
1576                 .has_inbox = true,
1577                 .has_outbox = false,
1578                 .out_is_imm = false,
1579                 .encode_slave_id = false,
1580                 .verify = NULL,
1581                 .wrapper = mlx4_QP_ATTACH_wrapper
1582         },
1583         {
1584                 .opcode = MLX4_CMD_PROMISC,
1585                 .has_inbox = false,
1586                 .has_outbox = false,
1587                 .out_is_imm = false,
1588                 .encode_slave_id = false,
1589                 .verify = NULL,
1590                 .wrapper = mlx4_PROMISC_wrapper
1591         },
1592         /* Ethernet specific commands */
1593         {
1594                 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1595                 .has_inbox = true,
1596                 .has_outbox = false,
1597                 .out_is_imm = false,
1598                 .encode_slave_id = false,
1599                 .verify = NULL,
1600                 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1601         },
1602         {
1603                 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1604                 .has_inbox = false,
1605                 .has_outbox = false,
1606                 .out_is_imm = false,
1607                 .encode_slave_id = false,
1608                 .verify = NULL,
1609                 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1610         },
1611         {
1612                 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1613                 .has_inbox = false,
1614                 .has_outbox = true,
1615                 .out_is_imm = false,
1616                 .encode_slave_id = false,
1617                 .verify = NULL,
1618                 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1619         },
1620         {
1621                 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1622                 .has_inbox = false,
1623                 .has_outbox = false,
1624                 .out_is_imm = false,
1625                 .encode_slave_id = false,
1626                 .verify = NULL,
1627                 .wrapper = NULL
1628         },
1629         /* flow steering commands */
1630         {
1631                 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1632                 .has_inbox = true,
1633                 .has_outbox = false,
1634                 .out_is_imm = true,
1635                 .encode_slave_id = false,
1636                 .verify = NULL,
1637                 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1638         },
1639         {
1640                 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1641                 .has_inbox = false,
1642                 .has_outbox = false,
1643                 .out_is_imm = false,
1644                 .encode_slave_id = false,
1645                 .verify = NULL,
1646                 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1647         },
1648         {
1649                 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1650                 .has_inbox = false,
1651                 .has_outbox = false,
1652                 .out_is_imm = false,
1653                 .encode_slave_id = false,
1654                 .verify = NULL,
1655                 .wrapper = mlx4_CMD_EPERM_wrapper
1656         },
1657         {
1658                 .opcode = MLX4_CMD_VIRT_PORT_MAP,
1659                 .has_inbox = false,
1660                 .has_outbox = false,
1661                 .out_is_imm = false,
1662                 .encode_slave_id = false,
1663                 .verify = NULL,
1664                 .wrapper = mlx4_CMD_EPERM_wrapper
1665         },
1666 };
1667
1668 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1669                                     struct mlx4_vhcr_cmd *in_vhcr)
1670 {
1671         struct mlx4_priv *priv = mlx4_priv(dev);
1672         struct mlx4_cmd_info *cmd = NULL;
1673         struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1674         struct mlx4_vhcr *vhcr;
1675         struct mlx4_cmd_mailbox *inbox = NULL;
1676         struct mlx4_cmd_mailbox *outbox = NULL;
1677         u64 in_param;
1678         u64 out_param;
1679         int ret = 0;
1680         int i;
1681         int err = 0;
1682
1683         /* Create sw representation of Virtual HCR */
1684         vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1685         if (!vhcr)
1686                 return -ENOMEM;
1687
1688         /* DMA in the vHCR */
1689         if (!in_vhcr) {
1690                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1691                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1692                                       ALIGN(sizeof(struct mlx4_vhcr_cmd),
1693                                             MLX4_ACCESS_MEM_ALIGN), 1);
1694                 if (ret) {
1695                         if (!(dev->persist->state &
1696                             MLX4_DEVICE_STATE_INTERNAL_ERROR))
1697                                 mlx4_err(dev, "%s: Failed reading vhcr ret: 0x%x\n",
1698                                          __func__, ret);
1699                         kfree(vhcr);
1700                         return ret;
1701                 }
1702         }
1703
1704         /* Fill SW VHCR fields */
1705         vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1706         vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1707         vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1708         vhcr->token = be16_to_cpu(vhcr_cmd->token);
1709         vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1710         vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1711         vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1712
1713         /* Lookup command */
1714         for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1715                 if (vhcr->op == cmd_info[i].opcode) {
1716                         cmd = &cmd_info[i];
1717                         break;
1718                 }
1719         }
1720         if (!cmd) {
1721                 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1722                          vhcr->op, slave);
1723                 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1724                 goto out_status;
1725         }
1726
1727         /* Read inbox */
1728         if (cmd->has_inbox) {
1729                 vhcr->in_param &= INBOX_MASK;
1730                 inbox = mlx4_alloc_cmd_mailbox(dev);
1731                 if (IS_ERR(inbox)) {
1732                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1733                         inbox = NULL;
1734                         goto out_status;
1735                 }
1736
1737                 ret = mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1738                                       vhcr->in_param,
1739                                       MLX4_MAILBOX_SIZE, 1);
1740                 if (ret) {
1741                         if (!(dev->persist->state &
1742                             MLX4_DEVICE_STATE_INTERNAL_ERROR))
1743                                 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1744                                          __func__, cmd->opcode);
1745                         vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1746                         goto out_status;
1747                 }
1748         }
1749
1750         /* Apply permission and bound checks if applicable */
1751         if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1752                 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1753                           vhcr->op, slave, vhcr->in_modifier);
1754                 vhcr_cmd->status = CMD_STAT_BAD_OP;
1755                 goto out_status;
1756         }
1757
1758         /* Allocate outbox */
1759         if (cmd->has_outbox) {
1760                 outbox = mlx4_alloc_cmd_mailbox(dev);
1761                 if (IS_ERR(outbox)) {
1762                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1763                         outbox = NULL;
1764                         goto out_status;
1765                 }
1766         }
1767
1768         /* Execute the command! */
1769         if (cmd->wrapper) {
1770                 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1771                                    cmd);
1772                 if (cmd->out_is_imm)
1773                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1774         } else {
1775                 in_param = cmd->has_inbox ? (u64) inbox->dma :
1776                         vhcr->in_param;
1777                 out_param = cmd->has_outbox ? (u64) outbox->dma :
1778                         vhcr->out_param;
1779                 err = __mlx4_cmd(dev, in_param, &out_param,
1780                                  cmd->out_is_imm, vhcr->in_modifier,
1781                                  vhcr->op_modifier, vhcr->op,
1782                                  MLX4_CMD_TIME_CLASS_A,
1783                                  MLX4_CMD_NATIVE);
1784
1785                 if (cmd->out_is_imm) {
1786                         vhcr->out_param = out_param;
1787                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1788                 }
1789         }
1790
1791         if (err) {
1792                 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR))
1793                         mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
1794                                   vhcr->op, slave, vhcr->errno, err);
1795                 vhcr_cmd->status = mlx4_errno_to_status(err);
1796                 goto out_status;
1797         }
1798
1799
1800         /* Write outbox if command completed successfully */
1801         if (cmd->has_outbox && !vhcr_cmd->status) {
1802                 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1803                                       vhcr->out_param,
1804                                       MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1805                 if (ret) {
1806                         /* If we failed to write back the outbox after the
1807                          *command was successfully executed, we must fail this
1808                          * slave, as it is now in undefined state */
1809                         if (!(dev->persist->state &
1810                             MLX4_DEVICE_STATE_INTERNAL_ERROR))
1811                                 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1812                         goto out;
1813                 }
1814         }
1815
1816 out_status:
1817         /* DMA back vhcr result */
1818         if (!in_vhcr) {
1819                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1820                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1821                                       ALIGN(sizeof(struct mlx4_vhcr),
1822                                             MLX4_ACCESS_MEM_ALIGN),
1823                                       MLX4_CMD_WRAPPED);
1824                 if (ret)
1825                         mlx4_err(dev, "%s:Failed writing vhcr result\n",
1826                                  __func__);
1827                 else if (vhcr->e_bit &&
1828                          mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1829                                 mlx4_warn(dev, "Failed to generate command completion eqe for slave %d\n",
1830                                           slave);
1831         }
1832
1833 out:
1834         kfree(vhcr);
1835         mlx4_free_cmd_mailbox(dev, inbox);
1836         mlx4_free_cmd_mailbox(dev, outbox);
1837         return ret;
1838 }
1839
1840 static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
1841                                             int slave, int port)
1842 {
1843         struct mlx4_vport_oper_state *vp_oper;
1844         struct mlx4_vport_state *vp_admin;
1845         struct mlx4_vf_immed_vlan_work *work;
1846         struct mlx4_dev *dev = &(priv->dev);
1847         int err;
1848         int admin_vlan_ix = NO_INDX;
1849
1850         vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1851         vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1852
1853         if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
1854             vp_oper->state.default_qos == vp_admin->default_qos &&
1855             vp_oper->state.vlan_proto == vp_admin->vlan_proto &&
1856             vp_oper->state.link_state == vp_admin->link_state &&
1857             vp_oper->state.qos_vport == vp_admin->qos_vport)
1858                 return 0;
1859
1860         if (!(priv->mfunc.master.slave_state[slave].active &&
1861               dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
1862                 /* even if the UPDATE_QP command isn't supported, we still want
1863                  * to set this VF link according to the admin directive
1864                  */
1865                 vp_oper->state.link_state = vp_admin->link_state;
1866                 return -1;
1867         }
1868
1869         mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1870                  slave, port);
1871         mlx4_dbg(dev, "vlan %d QoS %d link down %d\n",
1872                  vp_admin->default_vlan, vp_admin->default_qos,
1873                  vp_admin->link_state);
1874
1875         work = kzalloc(sizeof(*work), GFP_KERNEL);
1876         if (!work)
1877                 return -ENOMEM;
1878
1879         if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
1880                 if (MLX4_VGT != vp_admin->default_vlan) {
1881                         err = __mlx4_register_vlan(&priv->dev, port,
1882                                                    vp_admin->default_vlan,
1883                                                    &admin_vlan_ix);
1884                         if (err) {
1885                                 kfree(work);
1886                                 mlx4_warn(&priv->dev,
1887                                           "No vlan resources slave %d, port %d\n",
1888                                           slave, port);
1889                                 return err;
1890                         }
1891                 } else {
1892                         admin_vlan_ix = NO_INDX;
1893                 }
1894                 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1895                 mlx4_dbg(&priv->dev,
1896                          "alloc vlan %d idx  %d slave %d port %d\n",
1897                          (int)(vp_admin->default_vlan),
1898                          admin_vlan_ix, slave, port);
1899         }
1900
1901         /* save original vlan ix and vlan id */
1902         work->orig_vlan_id = vp_oper->state.default_vlan;
1903         work->orig_vlan_ix = vp_oper->vlan_idx;
1904
1905         /* handle new qos */
1906         if (vp_oper->state.default_qos != vp_admin->default_qos)
1907                 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1908
1909         if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1910                 vp_oper->vlan_idx = admin_vlan_ix;
1911
1912         vp_oper->state.default_vlan = vp_admin->default_vlan;
1913         vp_oper->state.default_qos = vp_admin->default_qos;
1914         vp_oper->state.vlan_proto = vp_admin->vlan_proto;
1915         vp_oper->state.link_state = vp_admin->link_state;
1916         vp_oper->state.qos_vport = vp_admin->qos_vport;
1917
1918         if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1919                 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
1920
1921         /* iterate over QPs owned by this slave, using UPDATE_QP */
1922         work->port = port;
1923         work->slave = slave;
1924         work->qos = vp_oper->state.default_qos;
1925         work->qos_vport = vp_oper->state.qos_vport;
1926         work->vlan_id = vp_oper->state.default_vlan;
1927         work->vlan_ix = vp_oper->vlan_idx;
1928         work->vlan_proto = vp_oper->state.vlan_proto;
1929         work->priv = priv;
1930         INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1931         queue_work(priv->mfunc.master.comm_wq, &work->work);
1932
1933         return 0;
1934 }
1935
1936 static void mlx4_set_default_port_qos(struct mlx4_dev *dev, int port)
1937 {
1938         struct mlx4_qos_manager *port_qos_ctl;
1939         struct mlx4_priv *priv = mlx4_priv(dev);
1940
1941         port_qos_ctl = &priv->mfunc.master.qos_ctl[port];
1942         bitmap_zero(port_qos_ctl->priority_bm, MLX4_NUM_UP);
1943
1944         /* Enable only default prio at PF init routine */
1945         set_bit(MLX4_DEFAULT_QOS_PRIO, port_qos_ctl->priority_bm);
1946 }
1947
1948 static void mlx4_allocate_port_vpps(struct mlx4_dev *dev, int port)
1949 {
1950         int i;
1951         int err;
1952         int num_vfs;
1953         u16 availible_vpp;
1954         u8 vpp_param[MLX4_NUM_UP];
1955         struct mlx4_qos_manager *port_qos;
1956         struct mlx4_priv *priv = mlx4_priv(dev);
1957
1958         err = mlx4_ALLOCATE_VPP_get(dev, port, &availible_vpp, vpp_param);
1959         if (err) {
1960                 mlx4_info(dev, "Failed query availible VPPs\n");
1961                 return;
1962         }
1963
1964         port_qos = &priv->mfunc.master.qos_ctl[port];
1965         num_vfs = (availible_vpp /
1966                    bitmap_weight(port_qos->priority_bm, MLX4_NUM_UP));
1967
1968         for (i = 0; i < MLX4_NUM_UP; i++) {
1969                 if (test_bit(i, port_qos->priority_bm))
1970                         vpp_param[i] = num_vfs;
1971         }
1972
1973         err = mlx4_ALLOCATE_VPP_set(dev, port, vpp_param);
1974         if (err) {
1975                 mlx4_info(dev, "Failed allocating VPPs\n");
1976                 return;
1977         }
1978
1979         /* Query actual allocated VPP, just to make sure */
1980         err = mlx4_ALLOCATE_VPP_get(dev, port, &availible_vpp, vpp_param);
1981         if (err) {
1982                 mlx4_info(dev, "Failed query availible VPPs\n");
1983                 return;
1984         }
1985
1986         port_qos->num_of_qos_vfs = num_vfs;
1987         mlx4_dbg(dev, "Port %d Availible VPPs %d\n", port, availible_vpp);
1988
1989         for (i = 0; i < MLX4_NUM_UP; i++)
1990                 mlx4_dbg(dev, "Port %d UP %d Allocated %d VPPs\n", port, i,
1991                          vpp_param[i]);
1992 }
1993
1994 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1995 {
1996         int port, err;
1997         struct mlx4_vport_state *vp_admin;
1998         struct mlx4_vport_oper_state *vp_oper;
1999         struct mlx4_slave_state *slave_state =
2000                 &priv->mfunc.master.slave_state[slave];
2001         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
2002                         &priv->dev, slave);
2003         int min_port = find_first_bit(actv_ports.ports,
2004                                       priv->dev.caps.num_ports) + 1;
2005         int max_port = min_port - 1 +
2006                 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
2007
2008         for (port = min_port; port <= max_port; port++) {
2009                 if (!test_bit(port - 1, actv_ports.ports))
2010                         continue;
2011                 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
2012                         priv->mfunc.master.vf_admin[slave].enable_smi[port];
2013                 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2014                 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2015                 if (vp_admin->vlan_proto != htons(ETH_P_8021AD) ||
2016                     slave_state->vst_qinq_supported) {
2017                         vp_oper->state.vlan_proto   = vp_admin->vlan_proto;
2018                         vp_oper->state.default_vlan = vp_admin->default_vlan;
2019                         vp_oper->state.default_qos  = vp_admin->default_qos;
2020                 }
2021                 vp_oper->state.link_state = vp_admin->link_state;
2022                 vp_oper->state.mac        = vp_admin->mac;
2023                 vp_oper->state.spoofchk   = vp_admin->spoofchk;
2024                 vp_oper->state.tx_rate    = vp_admin->tx_rate;
2025                 vp_oper->state.qos_vport  = vp_admin->qos_vport;
2026                 vp_oper->state.guid       = vp_admin->guid;
2027
2028                 if (MLX4_VGT != vp_admin->default_vlan) {
2029                         err = __mlx4_register_vlan(&priv->dev, port,
2030                                                    vp_admin->default_vlan, &(vp_oper->vlan_idx));
2031                         if (err) {
2032                                 vp_oper->vlan_idx = NO_INDX;
2033                                 vp_oper->state.default_vlan = MLX4_VGT;
2034                                 vp_oper->state.vlan_proto = htons(ETH_P_8021Q);
2035                                 mlx4_warn(&priv->dev,
2036                                           "No vlan resources slave %d, port %d\n",
2037                                           slave, port);
2038                                 return err;
2039                         }
2040                         mlx4_dbg(&priv->dev, "alloc vlan %d idx  %d slave %d port %d\n",
2041                                  (int)(vp_oper->state.default_vlan),
2042                                  vp_oper->vlan_idx, slave, port);
2043                 }
2044                 if (vp_admin->spoofchk) {
2045                         vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
2046                                                                port,
2047                                                                vp_admin->mac);
2048                         if (0 > vp_oper->mac_idx) {
2049                                 err = vp_oper->mac_idx;
2050                                 vp_oper->mac_idx = NO_INDX;
2051                                 mlx4_warn(&priv->dev,
2052                                           "No mac resources slave %d, port %d\n",
2053                                           slave, port);
2054                                 return err;
2055                         }
2056                         mlx4_dbg(&priv->dev, "alloc mac %llx idx  %d slave %d port %d\n",
2057                                  vp_oper->state.mac, vp_oper->mac_idx, slave, port);
2058                 }
2059         }
2060         return 0;
2061 }
2062
2063 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
2064 {
2065         int port;
2066         struct mlx4_vport_oper_state *vp_oper;
2067         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
2068                         &priv->dev, slave);
2069         int min_port = find_first_bit(actv_ports.ports,
2070                                       priv->dev.caps.num_ports) + 1;
2071         int max_port = min_port - 1 +
2072                 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
2073
2074
2075         for (port = min_port; port <= max_port; port++) {
2076                 if (!test_bit(port - 1, actv_ports.ports))
2077                         continue;
2078                 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
2079                         MLX4_VF_SMI_DISABLED;
2080                 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2081                 if (NO_INDX != vp_oper->vlan_idx) {
2082                         __mlx4_unregister_vlan(&priv->dev,
2083                                                port, vp_oper->state.default_vlan);
2084                         vp_oper->vlan_idx = NO_INDX;
2085                 }
2086                 if (NO_INDX != vp_oper->mac_idx) {
2087                         __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
2088                         vp_oper->mac_idx = NO_INDX;
2089                 }
2090         }
2091         return;
2092 }
2093
2094 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
2095                                u16 param, u8 toggle)
2096 {
2097         struct mlx4_priv *priv = mlx4_priv(dev);
2098         struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2099         u32 reply;
2100         u8 is_going_down = 0;
2101         int i;
2102         unsigned long flags;
2103
2104         slave_state[slave].comm_toggle ^= 1;
2105         reply = (u32) slave_state[slave].comm_toggle << 31;
2106         if (toggle != slave_state[slave].comm_toggle) {
2107                 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n",
2108                           toggle, slave);
2109                 goto reset_slave;
2110         }
2111         if (cmd == MLX4_COMM_CMD_RESET) {
2112                 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
2113                 slave_state[slave].active = false;
2114                 slave_state[slave].old_vlan_api = false;
2115                 slave_state[slave].vst_qinq_supported = false;
2116                 mlx4_master_deactivate_admin_state(priv, slave);
2117                 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
2118                                 slave_state[slave].event_eq[i].eqn = -1;
2119                                 slave_state[slave].event_eq[i].token = 0;
2120                 }
2121                 /*check if we are in the middle of FLR process,
2122                 if so return "retry" status to the slave*/
2123                 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
2124                         goto inform_slave_state;
2125
2126                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
2127
2128                 /* write the version in the event field */
2129                 reply |= mlx4_comm_get_version();
2130
2131                 goto reset_slave;
2132         }
2133         /*command from slave in the middle of FLR*/
2134         if (cmd != MLX4_COMM_CMD_RESET &&
2135             MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
2136                 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n",
2137                           slave, cmd);
2138                 return;
2139         }
2140
2141         switch (cmd) {
2142         case MLX4_COMM_CMD_VHCR0:
2143                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
2144                         goto reset_slave;
2145                 slave_state[slave].vhcr_dma = ((u64) param) << 48;
2146                 priv->mfunc.master.slave_state[slave].cookie = 0;
2147                 break;
2148         case MLX4_COMM_CMD_VHCR1:
2149                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
2150                         goto reset_slave;
2151                 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
2152                 break;
2153         case MLX4_COMM_CMD_VHCR2:
2154                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
2155                         goto reset_slave;
2156                 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
2157                 break;
2158         case MLX4_COMM_CMD_VHCR_EN:
2159                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
2160                         goto reset_slave;
2161                 slave_state[slave].vhcr_dma |= param;
2162                 if (mlx4_master_activate_admin_state(priv, slave))
2163                                 goto reset_slave;
2164                 slave_state[slave].active = true;
2165                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
2166                 break;
2167         case MLX4_COMM_CMD_VHCR_POST:
2168                 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
2169                     (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST)) {
2170                         mlx4_warn(dev, "slave:%d is out of sync, cmd=0x%x, last command=0x%x, reset is needed\n",
2171                                   slave, cmd, slave_state[slave].last_cmd);
2172                         goto reset_slave;
2173                 }
2174
2175                 mutex_lock(&priv->cmd.slave_cmd_mutex);
2176                 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
2177                         mlx4_err(dev, "Failed processing vhcr for slave:%d, resetting slave\n",
2178                                  slave);
2179                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
2180                         goto reset_slave;
2181                 }
2182                 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2183                 break;
2184         default:
2185                 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
2186                 goto reset_slave;
2187         }
2188         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
2189         if (!slave_state[slave].is_slave_going_down)
2190                 slave_state[slave].last_cmd = cmd;
2191         else
2192                 is_going_down = 1;
2193         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
2194         if (is_going_down) {
2195                 mlx4_warn(dev, "Slave is going down aborting command(%d) executing from slave:%d\n",
2196                           cmd, slave);
2197                 return;
2198         }
2199         __raw_writel((__force u32) cpu_to_be32(reply),
2200                      &priv->mfunc.comm[slave].slave_read);
2201         mmiowb();
2202
2203         return;
2204
2205 reset_slave:
2206         /* cleanup any slave resources */
2207         if (dev->persist->interface_state & MLX4_INTERFACE_STATE_UP)
2208                 mlx4_delete_all_resources_for_slave(dev, slave);
2209
2210         if (cmd != MLX4_COMM_CMD_RESET) {
2211                 mlx4_warn(dev, "Turn on internal error to force reset, slave=%d, cmd=0x%x\n",
2212                           slave, cmd);
2213                 /* Turn on internal error letting slave reset itself immeditaly,
2214                  * otherwise it might take till timeout on command is passed
2215                  */
2216                 reply |= ((u32)COMM_CHAN_EVENT_INTERNAL_ERR);
2217         }
2218
2219         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
2220         if (!slave_state[slave].is_slave_going_down)
2221                 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
2222         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
2223         /*with slave in the middle of flr, no need to clean resources again.*/
2224 inform_slave_state:
2225         memset(&slave_state[slave].event_eq, 0,
2226                sizeof(struct mlx4_slave_event_eq_info));
2227         __raw_writel((__force u32) cpu_to_be32(reply),
2228                      &priv->mfunc.comm[slave].slave_read);
2229         wmb();
2230 }
2231
2232 /* master command processing */
2233 void mlx4_master_comm_channel(struct work_struct *work)
2234 {
2235         struct mlx4_mfunc_master_ctx *master =
2236                 container_of(work,
2237                              struct mlx4_mfunc_master_ctx,
2238                              comm_work);
2239         struct mlx4_mfunc *mfunc =
2240                 container_of(master, struct mlx4_mfunc, master);
2241         struct mlx4_priv *priv =
2242                 container_of(mfunc, struct mlx4_priv, mfunc);
2243         struct mlx4_dev *dev = &priv->dev;
2244         __be32 *bit_vec;
2245         u32 comm_cmd;
2246         u32 vec;
2247         int i, j, slave;
2248         int toggle;
2249         int served = 0;
2250         int reported = 0;
2251         u32 slt;
2252
2253         bit_vec = master->comm_arm_bit_vector;
2254         for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
2255                 vec = be32_to_cpu(bit_vec[i]);
2256                 for (j = 0; j < 32; j++) {
2257                         if (!(vec & (1 << j)))
2258                                 continue;
2259                         ++reported;
2260                         slave = (i * 32) + j;
2261                         comm_cmd = swab32(readl(
2262                                           &mfunc->comm[slave].slave_write));
2263                         slt = swab32(readl(&mfunc->comm[slave].slave_read))
2264                                      >> 31;
2265                         toggle = comm_cmd >> 31;
2266                         if (toggle != slt) {
2267                                 if (master->slave_state[slave].comm_toggle
2268                                     != slt) {
2269                                         pr_info("slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n",
2270                                                 slave, slt,
2271                                                 master->slave_state[slave].comm_toggle);
2272                                         master->slave_state[slave].comm_toggle =
2273                                                 slt;
2274                                 }
2275                                 mlx4_master_do_cmd(dev, slave,
2276                                                    comm_cmd >> 16 & 0xff,
2277                                                    comm_cmd & 0xffff, toggle);
2278                                 ++served;
2279                         }
2280                 }
2281         }
2282
2283         if (reported && reported != served)
2284                 mlx4_warn(dev, "Got command event with bitmask from %d slaves but %d were served\n",
2285                           reported, served);
2286
2287         if (mlx4_ARM_COMM_CHANNEL(dev))
2288                 mlx4_warn(dev, "Failed to arm comm channel events\n");
2289 }
2290
2291 static int sync_toggles(struct mlx4_dev *dev)
2292 {
2293         struct mlx4_priv *priv = mlx4_priv(dev);
2294         u32 wr_toggle;
2295         u32 rd_toggle;
2296         unsigned long end;
2297
2298         wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write));
2299         if (wr_toggle == 0xffffffff)
2300                 end = jiffies + msecs_to_jiffies(30000);
2301         else
2302                 end = jiffies + msecs_to_jiffies(5000);
2303
2304         while (time_before(jiffies, end)) {
2305                 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read));
2306                 if (wr_toggle == 0xffffffff || rd_toggle == 0xffffffff) {
2307                         /* PCI might be offline */
2308
2309                         /* If device removal has been requested,
2310                          * do not continue retrying.
2311                          */
2312                         if (dev->persist->interface_state &
2313                             MLX4_INTERFACE_STATE_NOWAIT) {
2314                                 mlx4_warn(dev,
2315                                           "communication channel is offline\n");
2316                                 return -EIO;
2317                         }
2318
2319                         msleep(100);
2320                         wr_toggle = swab32(readl(&priv->mfunc.comm->
2321                                            slave_write));
2322                         continue;
2323                 }
2324
2325                 if (rd_toggle >> 31 == wr_toggle >> 31) {
2326                         priv->cmd.comm_toggle = rd_toggle >> 31;
2327                         return 0;
2328                 }
2329
2330                 cond_resched();
2331         }
2332
2333         /*
2334          * we could reach here if for example the previous VM using this
2335          * function misbehaved and left the channel with unsynced state. We
2336          * should fix this here and give this VM a chance to use a properly
2337          * synced channel
2338          */
2339         mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
2340         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
2341         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
2342         priv->cmd.comm_toggle = 0;
2343
2344         return 0;
2345 }
2346
2347 int mlx4_multi_func_init(struct mlx4_dev *dev)
2348 {
2349         struct mlx4_priv *priv = mlx4_priv(dev);
2350         struct mlx4_slave_state *s_state;
2351         int i, j, err, port;
2352
2353         if (mlx4_is_master(dev))
2354                 priv->mfunc.comm =
2355                 ioremap(pci_resource_start(dev->persist->pdev,
2356                                            priv->fw.comm_bar) +
2357                         priv->fw.comm_base, MLX4_COMM_PAGESIZE);
2358         else
2359                 priv->mfunc.comm =
2360                 ioremap(pci_resource_start(dev->persist->pdev, 2) +
2361                         MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
2362         if (!priv->mfunc.comm) {
2363                 mlx4_err(dev, "Couldn't map communication vector\n");
2364                 goto err_vhcr;
2365         }
2366
2367         if (mlx4_is_master(dev)) {
2368                 struct mlx4_vf_oper_state *vf_oper;
2369                 struct mlx4_vf_admin_state *vf_admin;
2370
2371                 priv->mfunc.master.slave_state =
2372                         kzalloc(dev->num_slaves *
2373                                 sizeof(struct mlx4_slave_state), GFP_KERNEL);
2374                 if (!priv->mfunc.master.slave_state)
2375                         goto err_comm;
2376
2377                 priv->mfunc.master.vf_admin =
2378                         kzalloc(dev->num_slaves *
2379                                 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
2380                 if (!priv->mfunc.master.vf_admin)
2381                         goto err_comm_admin;
2382
2383                 priv->mfunc.master.vf_oper =
2384                         kzalloc(dev->num_slaves *
2385                                 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
2386                 if (!priv->mfunc.master.vf_oper)
2387                         goto err_comm_oper;
2388
2389                 for (i = 0; i < dev->num_slaves; ++i) {
2390                         vf_admin = &priv->mfunc.master.vf_admin[i];
2391                         vf_oper = &priv->mfunc.master.vf_oper[i];
2392                         s_state = &priv->mfunc.master.slave_state[i];
2393                         s_state->last_cmd = MLX4_COMM_CMD_RESET;
2394                         s_state->vst_qinq_supported = false;
2395                         mutex_init(&priv->mfunc.master.gen_eqe_mutex[i]);
2396                         for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
2397                                 s_state->event_eq[j].eqn = -1;
2398                         __raw_writel((__force u32) 0,
2399                                      &priv->mfunc.comm[i].slave_write);
2400                         __raw_writel((__force u32) 0,
2401                                      &priv->mfunc.comm[i].slave_read);
2402                         mmiowb();
2403                         for (port = 1; port <= MLX4_MAX_PORTS; port++) {
2404                                 struct mlx4_vport_state *admin_vport;
2405                                 struct mlx4_vport_state *oper_vport;
2406
2407                                 s_state->vlan_filter[port] =
2408                                         kzalloc(sizeof(struct mlx4_vlan_fltr),
2409                                                 GFP_KERNEL);
2410                                 if (!s_state->vlan_filter[port]) {
2411                                         if (--port)
2412                                                 kfree(s_state->vlan_filter[port]);
2413                                         goto err_slaves;
2414                                 }
2415
2416                                 admin_vport = &vf_admin->vport[port];
2417                                 oper_vport = &vf_oper->vport[port].state;
2418                                 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
2419                                 admin_vport->default_vlan = MLX4_VGT;
2420                                 oper_vport->default_vlan = MLX4_VGT;
2421                                 admin_vport->qos_vport =
2422                                                 MLX4_VPP_DEFAULT_VPORT;
2423                                 oper_vport->qos_vport = MLX4_VPP_DEFAULT_VPORT;
2424                                 admin_vport->vlan_proto = htons(ETH_P_8021Q);
2425                                 oper_vport->vlan_proto = htons(ETH_P_8021Q);
2426                                 vf_oper->vport[port].vlan_idx = NO_INDX;
2427                                 vf_oper->vport[port].mac_idx = NO_INDX;
2428                                 mlx4_set_random_admin_guid(dev, i, port);
2429                         }
2430                         spin_lock_init(&s_state->lock);
2431                 }
2432
2433                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP) {
2434                         for (port = 1; port <= dev->caps.num_ports; port++) {
2435                                 if (mlx4_is_eth(dev, port)) {
2436                                         mlx4_set_default_port_qos(dev, port);
2437                                         mlx4_allocate_port_vpps(dev, port);
2438                                 }
2439                         }
2440                 }
2441
2442                 memset(&priv->mfunc.master.cmd_eqe, 0, sizeof(struct mlx4_eqe));
2443                 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2444                 INIT_WORK(&priv->mfunc.master.comm_work,
2445                           mlx4_master_comm_channel);
2446                 INIT_WORK(&priv->mfunc.master.slave_event_work,
2447                           mlx4_gen_slave_eqe);
2448                 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2449                           mlx4_master_handle_slave_flr);
2450                 spin_lock_init(&priv->mfunc.master.slave_state_lock);
2451                 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
2452                 priv->mfunc.master.comm_wq =
2453                         create_singlethread_workqueue("mlx4_comm");
2454                 if (!priv->mfunc.master.comm_wq)
2455                         goto err_slaves;
2456
2457                 if (mlx4_init_resource_tracker(dev))
2458                         goto err_thread;
2459
2460         } else {
2461                 err = sync_toggles(dev);
2462                 if (err) {
2463                         mlx4_err(dev, "Couldn't sync toggles\n");
2464                         goto err_comm;
2465                 }
2466         }
2467         return 0;
2468
2469 err_thread:
2470         flush_workqueue(priv->mfunc.master.comm_wq);
2471         destroy_workqueue(priv->mfunc.master.comm_wq);
2472 err_slaves:
2473         while (i--) {
2474                 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2475                         kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2476         }
2477         kfree(priv->mfunc.master.vf_oper);
2478 err_comm_oper:
2479         kfree(priv->mfunc.master.vf_admin);
2480 err_comm_admin:
2481         kfree(priv->mfunc.master.slave_state);
2482 err_comm:
2483         iounmap(priv->mfunc.comm);
2484         priv->mfunc.comm = NULL;
2485 err_vhcr:
2486         dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
2487                           priv->mfunc.vhcr,
2488                           priv->mfunc.vhcr_dma);
2489         priv->mfunc.vhcr = NULL;
2490         return -ENOMEM;
2491 }
2492
2493 int mlx4_cmd_init(struct mlx4_dev *dev)
2494 {
2495         struct mlx4_priv *priv = mlx4_priv(dev);
2496         int flags = 0;
2497
2498         if (!priv->cmd.initialized) {
2499                 init_rwsem(&priv->cmd.switch_sem);
2500                 mutex_init(&priv->cmd.slave_cmd_mutex);
2501                 sema_init(&priv->cmd.poll_sem, 1);
2502                 priv->cmd.use_events = 0;
2503                 priv->cmd.toggle     = 1;
2504                 priv->cmd.initialized = 1;
2505                 flags |= MLX4_CMD_CLEANUP_STRUCT;
2506         }
2507
2508         if (!mlx4_is_slave(dev) && !priv->cmd.hcr) {
2509                 priv->cmd.hcr = ioremap(pci_resource_start(dev->persist->pdev,
2510                                         0) + MLX4_HCR_BASE, MLX4_HCR_SIZE);
2511                 if (!priv->cmd.hcr) {
2512                         mlx4_err(dev, "Couldn't map command register\n");
2513                         goto err;
2514                 }
2515                 flags |= MLX4_CMD_CLEANUP_HCR;
2516         }
2517
2518         if (mlx4_is_mfunc(dev) && !priv->mfunc.vhcr) {
2519                 priv->mfunc.vhcr = dma_alloc_coherent(&dev->persist->pdev->dev,
2520                                                       PAGE_SIZE,
2521                                                       &priv->mfunc.vhcr_dma,
2522                                                       GFP_KERNEL);
2523                 if (!priv->mfunc.vhcr)
2524                         goto err;
2525
2526                 flags |= MLX4_CMD_CLEANUP_VHCR;
2527         }
2528
2529         if (!priv->cmd.pool) {
2530                 priv->cmd.pool = pci_pool_create("mlx4_cmd",
2531                                                  dev->persist->pdev,
2532                                                  MLX4_MAILBOX_SIZE,
2533                                                  MLX4_MAILBOX_SIZE, 0);
2534                 if (!priv->cmd.pool)
2535                         goto err;
2536
2537                 flags |= MLX4_CMD_CLEANUP_POOL;
2538         }
2539
2540         return 0;
2541
2542 err:
2543         mlx4_cmd_cleanup(dev, flags);
2544         return -ENOMEM;
2545 }
2546
2547 void mlx4_report_internal_err_comm_event(struct mlx4_dev *dev)
2548 {
2549         struct mlx4_priv *priv = mlx4_priv(dev);
2550         int slave;
2551         u32 slave_read;
2552
2553         /* If the comm channel has not yet been initialized,
2554          * skip reporting the internal error event to all
2555          * the communication channels.
2556          */
2557         if (!priv->mfunc.comm)
2558                 return;
2559
2560         /* Report an internal error event to all
2561          * communication channels.
2562          */
2563         for (slave = 0; slave < dev->num_slaves; slave++) {
2564                 slave_read = swab32(readl(&priv->mfunc.comm[slave].slave_read));
2565                 slave_read |= (u32)COMM_CHAN_EVENT_INTERNAL_ERR;
2566                 __raw_writel((__force u32)cpu_to_be32(slave_read),
2567                              &priv->mfunc.comm[slave].slave_read);
2568                 /* Make sure that our comm channel write doesn't
2569                  * get mixed in with writes from another CPU.
2570                  */
2571                 mmiowb();
2572         }
2573 }
2574
2575 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2576 {
2577         struct mlx4_priv *priv = mlx4_priv(dev);
2578         int i, port;
2579
2580         if (mlx4_is_master(dev)) {
2581                 flush_workqueue(priv->mfunc.master.comm_wq);
2582                 destroy_workqueue(priv->mfunc.master.comm_wq);
2583                 for (i = 0; i < dev->num_slaves; i++) {
2584                         for (port = 1; port <= MLX4_MAX_PORTS; port++)
2585                                 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2586                 }
2587                 kfree(priv->mfunc.master.slave_state);
2588                 kfree(priv->mfunc.master.vf_admin);
2589                 kfree(priv->mfunc.master.vf_oper);
2590                 dev->num_slaves = 0;
2591         }
2592
2593         iounmap(priv->mfunc.comm);
2594         priv->mfunc.comm = NULL;
2595 }
2596
2597 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask)
2598 {
2599         struct mlx4_priv *priv = mlx4_priv(dev);
2600
2601         if (priv->cmd.pool && (cleanup_mask & MLX4_CMD_CLEANUP_POOL)) {
2602                 pci_pool_destroy(priv->cmd.pool);
2603                 priv->cmd.pool = NULL;
2604         }
2605
2606         if (!mlx4_is_slave(dev) && priv->cmd.hcr &&
2607             (cleanup_mask & MLX4_CMD_CLEANUP_HCR)) {
2608                 iounmap(priv->cmd.hcr);
2609                 priv->cmd.hcr = NULL;
2610         }
2611         if (mlx4_is_mfunc(dev) && priv->mfunc.vhcr &&
2612             (cleanup_mask & MLX4_CMD_CLEANUP_VHCR)) {
2613                 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
2614                                   priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2615                 priv->mfunc.vhcr = NULL;
2616         }
2617         if (priv->cmd.initialized && (cleanup_mask & MLX4_CMD_CLEANUP_STRUCT))
2618                 priv->cmd.initialized = 0;
2619 }
2620
2621 /*
2622  * Switch to using events to issue FW commands (can only be called
2623  * after event queue for command events has been initialized).
2624  */
2625 int mlx4_cmd_use_events(struct mlx4_dev *dev)
2626 {
2627         struct mlx4_priv *priv = mlx4_priv(dev);
2628         int i;
2629         int err = 0;
2630
2631         priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2632                                    sizeof (struct mlx4_cmd_context),
2633                                    GFP_KERNEL);
2634         if (!priv->cmd.context)
2635                 return -ENOMEM;
2636
2637         down_write(&priv->cmd.switch_sem);
2638         for (i = 0; i < priv->cmd.max_cmds; ++i) {
2639                 priv->cmd.context[i].token = i;
2640                 priv->cmd.context[i].next  = i + 1;
2641                 /* To support fatal error flow, initialize all
2642                  * cmd contexts to allow simulating completions
2643                  * with complete() at any time.
2644                  */
2645                 init_completion(&priv->cmd.context[i].done);
2646         }
2647
2648         priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2649         priv->cmd.free_head = 0;
2650
2651         sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2652
2653         for (priv->cmd.token_mask = 1;
2654              priv->cmd.token_mask < priv->cmd.max_cmds;
2655              priv->cmd.token_mask <<= 1)
2656                 ; /* nothing */
2657         --priv->cmd.token_mask;
2658
2659         down(&priv->cmd.poll_sem);
2660         priv->cmd.use_events = 1;
2661         up_write(&priv->cmd.switch_sem);
2662
2663         return err;
2664 }
2665
2666 /*
2667  * Switch back to polling (used when shutting down the device)
2668  */
2669 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2670 {
2671         struct mlx4_priv *priv = mlx4_priv(dev);
2672         int i;
2673
2674         down_write(&priv->cmd.switch_sem);
2675         priv->cmd.use_events = 0;
2676
2677         for (i = 0; i < priv->cmd.max_cmds; ++i)
2678                 down(&priv->cmd.event_sem);
2679
2680         kfree(priv->cmd.context);
2681
2682         up(&priv->cmd.poll_sem);
2683         up_write(&priv->cmd.switch_sem);
2684 }
2685
2686 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2687 {
2688         struct mlx4_cmd_mailbox *mailbox;
2689
2690         mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2691         if (!mailbox)
2692                 return ERR_PTR(-ENOMEM);
2693
2694         mailbox->buf = pci_pool_zalloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2695                                        &mailbox->dma);
2696         if (!mailbox->buf) {
2697                 kfree(mailbox);
2698                 return ERR_PTR(-ENOMEM);
2699         }
2700
2701         return mailbox;
2702 }
2703 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2704
2705 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2706                            struct mlx4_cmd_mailbox *mailbox)
2707 {
2708         if (!mailbox)
2709                 return;
2710
2711         pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2712         kfree(mailbox);
2713 }
2714 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2715
2716 u32 mlx4_comm_get_version(void)
2717 {
2718          return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2719 }
2720
2721 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2722 {
2723         if ((vf < 0) || (vf >= dev->persist->num_vfs)) {
2724                 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n",
2725                          vf, dev->persist->num_vfs);
2726                 return -EINVAL;
2727         }
2728
2729         return vf+1;
2730 }
2731
2732 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2733 {
2734         if (slave < 1 || slave > dev->persist->num_vfs) {
2735                 mlx4_err(dev,
2736                          "Bad slave number:%d (number of activated slaves: %lu)\n",
2737                          slave, dev->num_slaves);
2738                 return -EINVAL;
2739         }
2740         return slave - 1;
2741 }
2742
2743 void mlx4_cmd_wake_completions(struct mlx4_dev *dev)
2744 {
2745         struct mlx4_priv *priv = mlx4_priv(dev);
2746         struct mlx4_cmd_context *context;
2747         int i;
2748
2749         spin_lock(&priv->cmd.context_lock);
2750         if (priv->cmd.context) {
2751                 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2752                         context = &priv->cmd.context[i];
2753                         context->fw_status = CMD_STAT_INTERNAL_ERR;
2754                         context->result    =
2755                                 mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
2756                         complete(&context->done);
2757                 }
2758         }
2759         spin_unlock(&priv->cmd.context_lock);
2760 }
2761
2762 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2763 {
2764         struct mlx4_active_ports actv_ports;
2765         int vf;
2766
2767         bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2768
2769         if (slave == 0) {
2770                 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2771                 return actv_ports;
2772         }
2773
2774         vf = mlx4_get_vf_indx(dev, slave);
2775         if (vf < 0)
2776                 return actv_ports;
2777
2778         bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2779                    min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2780                    dev->caps.num_ports));
2781
2782         return actv_ports;
2783 }
2784 EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2785
2786 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2787 {
2788         unsigned n;
2789         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2790         unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2791
2792         if (port <= 0 || port > m)
2793                 return -EINVAL;
2794
2795         n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2796         if (port <= n)
2797                 port = n + 1;
2798
2799         return port;
2800 }
2801 EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2802
2803 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2804 {
2805         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2806         if (test_bit(port - 1, actv_ports.ports))
2807                 return port -
2808                         find_first_bit(actv_ports.ports, dev->caps.num_ports);
2809
2810         return -1;
2811 }
2812 EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2813
2814 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2815                                                    int port)
2816 {
2817         unsigned i;
2818         struct mlx4_slaves_pport slaves_pport;
2819
2820         bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2821
2822         if (port <= 0 || port > dev->caps.num_ports)
2823                 return slaves_pport;
2824
2825         for (i = 0; i < dev->persist->num_vfs + 1; i++) {
2826                 struct mlx4_active_ports actv_ports =
2827                         mlx4_get_active_ports(dev, i);
2828                 if (test_bit(port - 1, actv_ports.ports))
2829                         set_bit(i, slaves_pport.slaves);
2830         }
2831
2832         return slaves_pport;
2833 }
2834 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2835
2836 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2837                 struct mlx4_dev *dev,
2838                 const struct mlx4_active_ports *crit_ports)
2839 {
2840         unsigned i;
2841         struct mlx4_slaves_pport slaves_pport;
2842
2843         bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2844
2845         for (i = 0; i < dev->persist->num_vfs + 1; i++) {
2846                 struct mlx4_active_ports actv_ports =
2847                         mlx4_get_active_ports(dev, i);
2848                 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2849                                  dev->caps.num_ports))
2850                         set_bit(i, slaves_pport.slaves);
2851         }
2852
2853         return slaves_pport;
2854 }
2855 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2856
2857 static int mlx4_slaves_closest_port(struct mlx4_dev *dev, int slave, int port)
2858 {
2859         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2860         int min_port = find_first_bit(actv_ports.ports, dev->caps.num_ports)
2861                         + 1;
2862         int max_port = min_port +
2863                 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2864
2865         if (port < min_port)
2866                 port = min_port;
2867         else if (port >= max_port)
2868                 port = max_port - 1;
2869
2870         return port;
2871 }
2872
2873 static int mlx4_set_vport_qos(struct mlx4_priv *priv, int slave, int port,
2874                               int max_tx_rate)
2875 {
2876         int i;
2877         int err;
2878         struct mlx4_qos_manager *port_qos;
2879         struct mlx4_dev *dev = &priv->dev;
2880         struct mlx4_vport_qos_param vpp_qos[MLX4_NUM_UP];
2881
2882         port_qos = &priv->mfunc.master.qos_ctl[port];
2883         memset(vpp_qos, 0, sizeof(struct mlx4_vport_qos_param) * MLX4_NUM_UP);
2884
2885         if (slave > port_qos->num_of_qos_vfs) {
2886                 mlx4_info(dev, "No availible VPP resources for this VF\n");
2887                 return -EINVAL;
2888         }
2889
2890         /* Query for default QoS values from Vport 0 is needed */
2891         err = mlx4_SET_VPORT_QOS_get(dev, port, 0, vpp_qos);
2892         if (err) {
2893                 mlx4_info(dev, "Failed to query Vport 0 QoS values\n");
2894                 return err;
2895         }
2896
2897         for (i = 0; i < MLX4_NUM_UP; i++) {
2898                 if (test_bit(i, port_qos->priority_bm) && max_tx_rate) {
2899                         vpp_qos[i].max_avg_bw = max_tx_rate;
2900                         vpp_qos[i].enable = 1;
2901                 } else {
2902                         /* if user supplied tx_rate == 0, meaning no rate limit
2903                          * configuration is required. so we are leaving the
2904                          * value of max_avg_bw as queried from Vport 0.
2905                          */
2906                         vpp_qos[i].enable = 0;
2907                 }
2908         }
2909
2910         err = mlx4_SET_VPORT_QOS_set(dev, port, slave, vpp_qos);
2911         if (err) {
2912                 mlx4_info(dev, "Failed to set Vport %d QoS values\n", slave);
2913                 return err;
2914         }
2915
2916         return 0;
2917 }
2918
2919 static bool mlx4_is_vf_vst_and_prio_qos(struct mlx4_dev *dev, int port,
2920                                         struct mlx4_vport_state *vf_admin)
2921 {
2922         struct mlx4_qos_manager *info;
2923         struct mlx4_priv *priv = mlx4_priv(dev);
2924
2925         if (!mlx4_is_master(dev) ||
2926             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP))
2927                 return false;
2928
2929         info = &priv->mfunc.master.qos_ctl[port];
2930
2931         if (vf_admin->default_vlan != MLX4_VGT &&
2932             test_bit(vf_admin->default_qos, info->priority_bm))
2933                 return true;
2934
2935         return false;
2936 }
2937
2938 static bool mlx4_valid_vf_state_change(struct mlx4_dev *dev, int port,
2939                                        struct mlx4_vport_state *vf_admin,
2940                                        int vlan, int qos)
2941 {
2942         struct mlx4_vport_state dummy_admin = {0};
2943
2944         if (!mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin) ||
2945             !vf_admin->tx_rate)
2946                 return true;
2947
2948         dummy_admin.default_qos = qos;
2949         dummy_admin.default_vlan = vlan;
2950
2951         /* VF wants to move to other VST state which is valid with current
2952          * rate limit. Either differnt default vlan in VST or other
2953          * supported QoS priority. Otherwise we don't allow this change when
2954          * the TX rate is still configured.
2955          */
2956         if (mlx4_is_vf_vst_and_prio_qos(dev, port, &dummy_admin))
2957                 return true;
2958
2959         mlx4_info(dev, "Cannot change VF state to %s while rate is set\n",
2960                   (vlan == MLX4_VGT) ? "VGT" : "VST");
2961
2962         if (vlan != MLX4_VGT)
2963                 mlx4_info(dev, "VST priority %d not supported for QoS\n", qos);
2964
2965         mlx4_info(dev, "Please set rate to 0 prior to this VF state change\n");
2966
2967         return false;
2968 }
2969
2970 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u8 *mac)
2971 {
2972         struct mlx4_priv *priv = mlx4_priv(dev);
2973         struct mlx4_vport_state *s_info;
2974         int slave;
2975
2976         if (!mlx4_is_master(dev))
2977                 return -EPROTONOSUPPORT;
2978
2979         if (is_multicast_ether_addr(mac))
2980                 return -EINVAL;
2981
2982         slave = mlx4_get_slave_indx(dev, vf);
2983         if (slave < 0)
2984                 return -EINVAL;
2985
2986         port = mlx4_slaves_closest_port(dev, slave, port);
2987         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2988
2989         if (s_info->spoofchk && is_zero_ether_addr(mac)) {
2990                 mlx4_info(dev, "MAC invalidation is not allowed when spoofchk is on\n");
2991                 return -EPERM;
2992         }
2993
2994         s_info->mac = mlx4_mac_to_u64(mac);
2995         mlx4_info(dev, "default mac on vf %d port %d to %llX will take effect only after vf restart\n",
2996                   vf, port, s_info->mac);
2997         return 0;
2998 }
2999 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
3000
3001
3002 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos,
3003                      __be16 proto)
3004 {
3005         struct mlx4_priv *priv = mlx4_priv(dev);
3006         struct mlx4_vport_state *vf_admin;
3007         struct mlx4_slave_state *slave_state;
3008         struct mlx4_vport_oper_state *vf_oper;
3009         int slave;
3010
3011         if ((!mlx4_is_master(dev)) ||
3012             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
3013                 return -EPROTONOSUPPORT;
3014
3015         if ((vlan > 4095) || (qos > 7))
3016                 return -EINVAL;
3017
3018         if (proto == htons(ETH_P_8021AD) &&
3019             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP))
3020                 return -EPROTONOSUPPORT;
3021
3022         if (proto != htons(ETH_P_8021Q) &&
3023             proto != htons(ETH_P_8021AD))
3024                 return -EINVAL;
3025
3026         if ((proto == htons(ETH_P_8021AD)) &&
3027             ((vlan == 0) || (vlan == MLX4_VGT)))
3028                 return -EINVAL;
3029
3030         slave = mlx4_get_slave_indx(dev, vf);
3031         if (slave < 0)
3032                 return -EINVAL;
3033
3034         slave_state = &priv->mfunc.master.slave_state[slave];
3035         if ((proto == htons(ETH_P_8021AD)) && (slave_state->active) &&
3036             (!slave_state->vst_qinq_supported)) {
3037                 mlx4_err(dev, "vf %d does not support VST QinQ mode\n", vf);
3038                 return -EPROTONOSUPPORT;
3039         }
3040         port = mlx4_slaves_closest_port(dev, slave, port);
3041         vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
3042         vf_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
3043
3044         if (!mlx4_valid_vf_state_change(dev, port, vf_admin, vlan, qos))
3045                 return -EPERM;
3046
3047         if ((0 == vlan) && (0 == qos))
3048                 vf_admin->default_vlan = MLX4_VGT;
3049         else
3050                 vf_admin->default_vlan = vlan;
3051         vf_admin->default_qos = qos;
3052         vf_admin->vlan_proto = proto;
3053
3054         /* If rate was configured prior to VST, we saved the configured rate
3055          * in vf_admin->rate and now, if priority supported we enforce the QoS
3056          */
3057         if (mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin) &&
3058             vf_admin->tx_rate)
3059                 vf_admin->qos_vport = slave;
3060
3061         /* Try to activate new vf state without restart,
3062          * this option is not supported while moving to VST QinQ mode.
3063          */
3064         if ((proto == htons(ETH_P_8021AD) &&
3065              vf_oper->state.vlan_proto != proto) ||
3066             mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
3067                 mlx4_info(dev,
3068                           "updating vf %d port %d config will take effect on next VF restart\n",
3069                           vf, port);
3070         return 0;
3071 }
3072 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
3073
3074 int mlx4_set_vf_rate(struct mlx4_dev *dev, int port, int vf, int min_tx_rate,
3075                      int max_tx_rate)
3076 {
3077         int err;
3078         int slave;
3079         struct mlx4_vport_state *vf_admin;
3080         struct mlx4_priv *priv = mlx4_priv(dev);
3081
3082         if (!mlx4_is_master(dev) ||
3083             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP))
3084                 return -EPROTONOSUPPORT;
3085
3086         if (min_tx_rate) {
3087                 mlx4_info(dev, "Minimum BW share not supported\n");
3088                 return -EPROTONOSUPPORT;
3089         }
3090
3091         slave = mlx4_get_slave_indx(dev, vf);
3092         if (slave < 0)
3093                 return -EINVAL;
3094
3095         port = mlx4_slaves_closest_port(dev, slave, port);
3096         vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
3097
3098         err = mlx4_set_vport_qos(priv, slave, port, max_tx_rate);
3099         if (err) {
3100                 mlx4_info(dev, "vf %d failed to set rate %d\n", vf,
3101                           max_tx_rate);
3102                 return err;
3103         }
3104
3105         vf_admin->tx_rate = max_tx_rate;
3106         /* if VF is not in supported mode (VST with supported prio),
3107          * we do not change vport configuration for its QPs, but save
3108          * the rate, so it will be enforced when it moves to supported
3109          * mode next time.
3110          */
3111         if (!mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin)) {
3112                 mlx4_info(dev,
3113                           "rate set for VF %d when not in valid state\n", vf);
3114
3115                 if (vf_admin->default_vlan != MLX4_VGT)
3116                         mlx4_info(dev, "VST priority not supported by QoS\n");
3117                 else
3118                         mlx4_info(dev, "VF in VGT mode (needed VST)\n");
3119
3120                 mlx4_info(dev,
3121                           "rate %d take affect when VF moves to valid state\n",
3122                           max_tx_rate);
3123                 return 0;
3124         }
3125
3126         /* If user sets rate 0 assigning default vport for its QPs */
3127         vf_admin->qos_vport = max_tx_rate ? slave : MLX4_VPP_DEFAULT_VPORT;
3128
3129         if (priv->mfunc.master.slave_state[slave].active &&
3130             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)
3131                 mlx4_master_immediate_activate_vlan_qos(priv, slave, port);
3132
3133         return 0;
3134 }
3135 EXPORT_SYMBOL_GPL(mlx4_set_vf_rate);
3136
3137  /* mlx4_get_slave_default_vlan -
3138  * return true if VST ( default vlan)
3139  * if VST, will return vlan & qos (if not NULL)
3140  */
3141 bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
3142                                  u16 *vlan, u8 *qos)
3143 {
3144         struct mlx4_vport_oper_state *vp_oper;
3145         struct mlx4_priv *priv;
3146
3147         priv = mlx4_priv(dev);
3148         port = mlx4_slaves_closest_port(dev, slave, port);
3149         vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
3150
3151         if (MLX4_VGT != vp_oper->state.default_vlan) {
3152                 if (vlan)
3153                         *vlan = vp_oper->state.default_vlan;
3154                 if (qos)
3155                         *qos = vp_oper->state.default_qos;
3156                 return true;
3157         }
3158         return false;
3159 }
3160 EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
3161
3162 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
3163 {
3164         struct mlx4_priv *priv = mlx4_priv(dev);
3165         struct mlx4_vport_state *s_info;
3166         int slave;
3167         u8 mac[ETH_ALEN];
3168
3169         if ((!mlx4_is_master(dev)) ||
3170             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
3171                 return -EPROTONOSUPPORT;
3172
3173         slave = mlx4_get_slave_indx(dev, vf);
3174         if (slave < 0)
3175                 return -EINVAL;
3176
3177         port = mlx4_slaves_closest_port(dev, slave, port);
3178         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3179
3180         mlx4_u64_to_mac(mac, s_info->mac);
3181         if (setting && !is_valid_ether_addr(mac)) {
3182                 mlx4_info(dev, "Illegal MAC with spoofchk\n");
3183                 return -EPERM;
3184         }
3185
3186         s_info->spoofchk = setting;
3187
3188         return 0;
3189 }
3190 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
3191
3192 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
3193 {
3194         struct mlx4_priv *priv = mlx4_priv(dev);
3195         struct mlx4_vport_state *s_info;
3196         int slave;
3197
3198         if (!mlx4_is_master(dev))
3199                 return -EPROTONOSUPPORT;
3200
3201         slave = mlx4_get_slave_indx(dev, vf);
3202         if (slave < 0)
3203                 return -EINVAL;
3204
3205         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3206         ivf->vf = vf;
3207
3208         /* need to convert it to a func */
3209         ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
3210         ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
3211         ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
3212         ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
3213         ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
3214         ivf->mac[5] = ((s_info->mac)  & 0xff);
3215
3216         ivf->vlan               = s_info->default_vlan;
3217         ivf->qos                = s_info->default_qos;
3218         ivf->vlan_proto         = s_info->vlan_proto;
3219
3220         if (mlx4_is_vf_vst_and_prio_qos(dev, port, s_info))
3221                 ivf->max_tx_rate = s_info->tx_rate;
3222         else
3223                 ivf->max_tx_rate = 0;
3224
3225         ivf->min_tx_rate        = 0;
3226         ivf->spoofchk           = s_info->spoofchk;
3227         ivf->linkstate          = s_info->link_state;
3228
3229         return 0;
3230 }
3231 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
3232
3233 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
3234 {
3235         struct mlx4_priv *priv = mlx4_priv(dev);
3236         struct mlx4_vport_state *s_info;
3237         int slave;
3238         u8 link_stat_event;
3239
3240         slave = mlx4_get_slave_indx(dev, vf);
3241         if (slave < 0)
3242                 return -EINVAL;
3243
3244         port = mlx4_slaves_closest_port(dev, slave, port);
3245         switch (link_state) {
3246         case IFLA_VF_LINK_STATE_AUTO:
3247                 /* get current link state */
3248                 if (!priv->sense.do_sense_port[port])
3249                         link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
3250                 else
3251                         link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
3252             break;
3253
3254         case IFLA_VF_LINK_STATE_ENABLE:
3255                 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
3256             break;
3257
3258         case IFLA_VF_LINK_STATE_DISABLE:
3259                 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
3260             break;
3261
3262         default:
3263                 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
3264                           link_state, slave, port);
3265                 return -EINVAL;
3266         };
3267         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3268         s_info->link_state = link_state;
3269
3270         /* send event */
3271         mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
3272
3273         if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
3274                 mlx4_dbg(dev,
3275                          "updating vf %d port %d no link state HW enforcment\n",
3276                          vf, port);
3277         return 0;
3278 }
3279 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
3280
3281 int mlx4_get_counter_stats(struct mlx4_dev *dev, int counter_index,
3282                            struct mlx4_counter *counter_stats, int reset)
3283 {
3284         struct mlx4_cmd_mailbox *mailbox = NULL;
3285         struct mlx4_counter *tmp_counter;
3286         int err;
3287         u32 if_stat_in_mod;
3288
3289         if (!counter_stats)
3290                 return -EINVAL;
3291
3292         if (counter_index == MLX4_SINK_COUNTER_INDEX(dev))
3293                 return 0;
3294
3295         mailbox = mlx4_alloc_cmd_mailbox(dev);
3296         if (IS_ERR(mailbox))
3297                 return PTR_ERR(mailbox);
3298
3299         memset(mailbox->buf, 0, sizeof(struct mlx4_counter));
3300         if_stat_in_mod = counter_index;
3301         if (reset)
3302                 if_stat_in_mod |= MLX4_QUERY_IF_STAT_RESET;
3303         err = mlx4_cmd_box(dev, 0, mailbox->dma,
3304                            if_stat_in_mod, 0,
3305                            MLX4_CMD_QUERY_IF_STAT,
3306                            MLX4_CMD_TIME_CLASS_C,
3307                            MLX4_CMD_NATIVE);
3308         if (err) {
3309                 mlx4_dbg(dev, "%s: failed to read statistics for counter index %d\n",
3310                          __func__, counter_index);
3311                 goto if_stat_out;
3312         }
3313         tmp_counter = (struct mlx4_counter *)mailbox->buf;
3314         counter_stats->counter_mode = tmp_counter->counter_mode;
3315         if (counter_stats->counter_mode == 0) {
3316                 counter_stats->rx_frames =
3317                         cpu_to_be64(be64_to_cpu(counter_stats->rx_frames) +
3318                                     be64_to_cpu(tmp_counter->rx_frames));
3319                 counter_stats->tx_frames =
3320                         cpu_to_be64(be64_to_cpu(counter_stats->tx_frames) +
3321                                     be64_to_cpu(tmp_counter->tx_frames));
3322                 counter_stats->rx_bytes =
3323                         cpu_to_be64(be64_to_cpu(counter_stats->rx_bytes) +
3324                                     be64_to_cpu(tmp_counter->rx_bytes));
3325                 counter_stats->tx_bytes =
3326                         cpu_to_be64(be64_to_cpu(counter_stats->tx_bytes) +
3327                                     be64_to_cpu(tmp_counter->tx_bytes));
3328         }
3329
3330 if_stat_out:
3331         mlx4_free_cmd_mailbox(dev, mailbox);
3332
3333         return err;
3334 }
3335 EXPORT_SYMBOL_GPL(mlx4_get_counter_stats);
3336
3337 int mlx4_get_vf_stats(struct mlx4_dev *dev, int port, int vf_idx,
3338                       struct ifla_vf_stats *vf_stats)
3339 {
3340         struct mlx4_counter tmp_vf_stats;
3341         int slave;
3342         int err = 0;
3343
3344         if (!vf_stats)
3345                 return -EINVAL;
3346
3347         if (!mlx4_is_master(dev))
3348                 return -EPROTONOSUPPORT;
3349
3350         slave = mlx4_get_slave_indx(dev, vf_idx);
3351         if (slave < 0)
3352                 return -EINVAL;
3353
3354         port = mlx4_slaves_closest_port(dev, slave, port);
3355         err = mlx4_calc_vf_counters(dev, slave, port, &tmp_vf_stats);
3356         if (!err && tmp_vf_stats.counter_mode == 0) {
3357                 vf_stats->rx_packets = be64_to_cpu(tmp_vf_stats.rx_frames);
3358                 vf_stats->tx_packets = be64_to_cpu(tmp_vf_stats.tx_frames);
3359                 vf_stats->rx_bytes = be64_to_cpu(tmp_vf_stats.rx_bytes);
3360                 vf_stats->tx_bytes = be64_to_cpu(tmp_vf_stats.tx_bytes);
3361         }
3362
3363         return err;
3364 }
3365 EXPORT_SYMBOL_GPL(mlx4_get_vf_stats);
3366
3367 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port)
3368 {
3369         struct mlx4_priv *priv = mlx4_priv(dev);
3370
3371         if (slave < 1 || slave >= dev->num_slaves ||
3372             port < 1 || port > MLX4_MAX_PORTS)
3373                 return 0;
3374
3375         return priv->mfunc.master.vf_oper[slave].smi_enabled[port] ==
3376                 MLX4_VF_SMI_ENABLED;
3377 }
3378 EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled);
3379
3380 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port)
3381 {
3382         struct mlx4_priv *priv = mlx4_priv(dev);
3383
3384         if (slave == mlx4_master_func_num(dev))
3385                 return 1;
3386
3387         if (slave < 1 || slave >= dev->num_slaves ||
3388             port < 1 || port > MLX4_MAX_PORTS)
3389                 return 0;
3390
3391         return priv->mfunc.master.vf_admin[slave].enable_smi[port] ==
3392                 MLX4_VF_SMI_ENABLED;
3393 }
3394 EXPORT_SYMBOL_GPL(mlx4_vf_get_enable_smi_admin);
3395
3396 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
3397                                  int enabled)
3398 {
3399         struct mlx4_priv *priv = mlx4_priv(dev);
3400         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
3401                         &priv->dev, slave);
3402         int min_port = find_first_bit(actv_ports.ports,
3403                                       priv->dev.caps.num_ports) + 1;
3404         int max_port = min_port - 1 +
3405                 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
3406
3407         if (slave == mlx4_master_func_num(dev))
3408                 return 0;
3409
3410         if (slave < 1 || slave >= dev->num_slaves ||
3411             port < 1 || port > MLX4_MAX_PORTS ||
3412             enabled < 0 || enabled > 1)
3413                 return -EINVAL;
3414
3415         if (min_port == max_port && dev->caps.num_ports > 1) {
3416                 mlx4_info(dev, "SMI access disallowed for single ported VFs\n");
3417                 return -EPROTONOSUPPORT;
3418         }
3419
3420         priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled;
3421         return 0;
3422 }
3423 EXPORT_SYMBOL_GPL(mlx4_vf_set_enable_smi_admin);