1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/if_vlan.h>
23 #include <linux/reset.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26 #include <linux/pinctrl/devinfo.h>
28 #include "mtk_eth_soc.h"
30 static int mtk_msg_level = -1;
31 module_param_named(msg_level, mtk_msg_level, int, 0);
32 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
34 #define MTK_ETHTOOL_STAT(x) { #x, \
35 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
37 /* strings used by ethtool */
38 static const struct mtk_ethtool_stats {
39 char str[ETH_GSTRING_LEN];
41 } mtk_ethtool_stats[] = {
42 MTK_ETHTOOL_STAT(tx_bytes),
43 MTK_ETHTOOL_STAT(tx_packets),
44 MTK_ETHTOOL_STAT(tx_skip),
45 MTK_ETHTOOL_STAT(tx_collisions),
46 MTK_ETHTOOL_STAT(rx_bytes),
47 MTK_ETHTOOL_STAT(rx_packets),
48 MTK_ETHTOOL_STAT(rx_overflow),
49 MTK_ETHTOOL_STAT(rx_fcs_errors),
50 MTK_ETHTOOL_STAT(rx_short_errors),
51 MTK_ETHTOOL_STAT(rx_long_errors),
52 MTK_ETHTOOL_STAT(rx_checksum_errors),
53 MTK_ETHTOOL_STAT(rx_flow_control_packets),
56 static const char * const mtk_clks_source_name[] = {
57 "ethif", "esw", "gp0", "gp1", "gp2", "trgpll", "sgmii_tx250m",
58 "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll"
61 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
63 __raw_writel(val, eth->base + reg);
66 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
68 return __raw_readl(eth->base + reg);
71 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
73 unsigned long t_start = jiffies;
76 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
78 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
83 dev_err(eth->dev, "mdio: MDIO timeout\n");
87 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
88 u32 phy_register, u32 write_data)
90 if (mtk_mdio_busy_wait(eth))
95 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
96 (phy_register << PHY_IAC_REG_SHIFT) |
97 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
100 if (mtk_mdio_busy_wait(eth))
106 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
110 if (mtk_mdio_busy_wait(eth))
113 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
114 (phy_reg << PHY_IAC_REG_SHIFT) |
115 (phy_addr << PHY_IAC_ADDR_SHIFT),
118 if (mtk_mdio_busy_wait(eth))
121 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
126 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
127 int phy_reg, u16 val)
129 struct mtk_eth *eth = bus->priv;
131 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
134 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
136 struct mtk_eth *eth = bus->priv;
138 return _mtk_mdio_read(eth, phy_addr, phy_reg);
141 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
146 val = (speed == SPEED_1000) ?
147 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
148 mtk_w32(eth, val, INTF_MODE);
150 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
151 ETHSYS_TRGMII_CLK_SEL362_5,
152 ETHSYS_TRGMII_CLK_SEL362_5);
154 val = (speed == SPEED_1000) ? 250000000 : 500000000;
155 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
157 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
159 val = (speed == SPEED_1000) ?
160 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
161 mtk_w32(eth, val, TRGMII_RCK_CTRL);
163 val = (speed == SPEED_1000) ?
164 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
165 mtk_w32(eth, val, TRGMII_TCK_CTRL);
168 static void mtk_gmac_sgmii_hw_setup(struct mtk_eth *eth, int mac_id)
172 /* Setup the link timer and QPHY power up inside SGMIISYS */
173 regmap_write(eth->sgmiisys, SGMSYS_PCS_LINK_TIMER,
174 SGMII_LINK_TIMER_DEFAULT);
176 regmap_read(eth->sgmiisys, SGMSYS_SGMII_MODE, &val);
177 val |= SGMII_REMOTE_FAULT_DIS;
178 regmap_write(eth->sgmiisys, SGMSYS_SGMII_MODE, val);
180 regmap_read(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, &val);
181 val |= SGMII_AN_RESTART;
182 regmap_write(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, val);
184 regmap_read(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
185 val &= ~SGMII_PHYA_PWD;
186 regmap_write(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, val);
188 /* Determine MUX for which GMAC uses the SGMII interface */
189 if (MTK_HAS_CAPS(eth->soc->caps, MTK_DUAL_GMAC_SHARED_SGMII)) {
190 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
191 val &= ~SYSCFG0_SGMII_MASK;
192 val |= !mac_id ? SYSCFG0_SGMII_GMAC1 : SYSCFG0_SGMII_GMAC2;
193 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
195 dev_info(eth->dev, "setup shared sgmii for gmac=%d\n",
199 /* Setup the GMAC1 going through SGMII path when SoC also support
202 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC1_ESW | MTK_GMAC1_SGMII) &&
204 mtk_w32(eth, 0, MTK_MAC_MISC);
205 dev_info(eth->dev, "setup gmac1 going through sgmii");
209 static void mtk_phy_link_adjust(struct net_device *dev)
211 struct mtk_mac *mac = netdev_priv(dev);
212 u16 lcl_adv = 0, rmt_adv = 0;
214 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
215 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
216 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
219 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
222 switch (dev->phydev->speed) {
224 mcr |= MAC_MCR_SPEED_1000;
227 mcr |= MAC_MCR_SPEED_100;
231 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) &&
232 !mac->id && !mac->trgmii)
233 mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed);
235 if (dev->phydev->link)
236 mcr |= MAC_MCR_FORCE_LINK;
238 if (dev->phydev->duplex) {
239 mcr |= MAC_MCR_FORCE_DPX;
241 if (dev->phydev->pause)
242 rmt_adv = LPA_PAUSE_CAP;
243 if (dev->phydev->asym_pause)
244 rmt_adv |= LPA_PAUSE_ASYM;
246 lcl_adv = linkmode_adv_to_lcl_adv_t(dev->phydev->advertising);
247 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
249 if (flowctrl & FLOW_CTRL_TX)
250 mcr |= MAC_MCR_FORCE_TX_FC;
251 if (flowctrl & FLOW_CTRL_RX)
252 mcr |= MAC_MCR_FORCE_RX_FC;
254 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
255 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
256 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
259 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
261 if (!of_phy_is_fixed_link(mac->of_node))
262 phy_print_status(dev->phydev);
265 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
266 struct device_node *phy_node)
268 struct phy_device *phydev;
271 phy_mode = of_get_phy_mode(phy_node);
273 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
277 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
278 mtk_phy_link_adjust, 0, phy_mode);
280 dev_err(eth->dev, "could not connect to PHY\n");
285 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
286 mac->id, phydev_name(phydev), phydev->phy_id,
292 static int mtk_phy_connect(struct net_device *dev)
294 struct mtk_mac *mac = netdev_priv(dev);
296 struct device_node *np;
300 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
301 if (!np && of_phy_is_fixed_link(mac->of_node))
302 if (!of_phy_register_fixed_link(mac->of_node))
303 np = of_node_get(mac->of_node);
308 switch (of_get_phy_mode(np)) {
309 case PHY_INTERFACE_MODE_TRGMII:
311 case PHY_INTERFACE_MODE_RGMII_TXID:
312 case PHY_INTERFACE_MODE_RGMII_RXID:
313 case PHY_INTERFACE_MODE_RGMII_ID:
314 case PHY_INTERFACE_MODE_RGMII:
316 case PHY_INTERFACE_MODE_SGMII:
317 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII))
318 mtk_gmac_sgmii_hw_setup(eth, mac->id);
320 case PHY_INTERFACE_MODE_MII:
323 case PHY_INTERFACE_MODE_REVMII:
326 case PHY_INTERFACE_MODE_RMII:
335 /* put the gmac into the right mode */
336 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
337 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
338 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
339 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
341 /* couple phydev to net_device */
342 if (mtk_phy_connect_node(eth, mac, np))
350 if (of_phy_is_fixed_link(mac->of_node))
351 of_phy_deregister_fixed_link(mac->of_node);
353 dev_err(eth->dev, "%s: invalid phy\n", __func__);
357 static int mtk_mdio_init(struct mtk_eth *eth)
359 struct device_node *mii_np;
362 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
364 dev_err(eth->dev, "no %s child node found", "mdio-bus");
368 if (!of_device_is_available(mii_np)) {
373 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
379 eth->mii_bus->name = "mdio";
380 eth->mii_bus->read = mtk_mdio_read;
381 eth->mii_bus->write = mtk_mdio_write;
382 eth->mii_bus->priv = eth;
383 eth->mii_bus->parent = eth->dev;
385 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
386 ret = of_mdiobus_register(eth->mii_bus, mii_np);
393 static void mtk_mdio_cleanup(struct mtk_eth *eth)
398 mdiobus_unregister(eth->mii_bus);
401 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
406 spin_lock_irqsave(ð->tx_irq_lock, flags);
407 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
408 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
409 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
412 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
417 spin_lock_irqsave(ð->tx_irq_lock, flags);
418 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
419 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
420 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
423 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
428 spin_lock_irqsave(ð->rx_irq_lock, flags);
429 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
430 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK);
431 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
434 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
439 spin_lock_irqsave(ð->rx_irq_lock, flags);
440 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
441 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK);
442 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
445 static int mtk_set_mac_address(struct net_device *dev, void *p)
447 int ret = eth_mac_addr(dev, p);
448 struct mtk_mac *mac = netdev_priv(dev);
449 const char *macaddr = dev->dev_addr;
454 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
457 spin_lock_bh(&mac->hw->page_lock);
458 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
459 MTK_GDMA_MAC_ADRH(mac->id));
460 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
461 (macaddr[4] << 8) | macaddr[5],
462 MTK_GDMA_MAC_ADRL(mac->id));
463 spin_unlock_bh(&mac->hw->page_lock);
468 void mtk_stats_update_mac(struct mtk_mac *mac)
470 struct mtk_hw_stats *hw_stats = mac->hw_stats;
471 unsigned int base = MTK_GDM1_TX_GBCNT;
474 base += hw_stats->reg_offset;
476 u64_stats_update_begin(&hw_stats->syncp);
478 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
479 stats = mtk_r32(mac->hw, base + 0x04);
481 hw_stats->rx_bytes += (stats << 32);
482 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
483 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
484 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
485 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
486 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
487 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
488 hw_stats->rx_flow_control_packets +=
489 mtk_r32(mac->hw, base + 0x24);
490 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
491 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
492 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
493 stats = mtk_r32(mac->hw, base + 0x34);
495 hw_stats->tx_bytes += (stats << 32);
496 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
497 u64_stats_update_end(&hw_stats->syncp);
500 static void mtk_stats_update(struct mtk_eth *eth)
504 for (i = 0; i < MTK_MAC_COUNT; i++) {
505 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
507 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
508 mtk_stats_update_mac(eth->mac[i]);
509 spin_unlock(ð->mac[i]->hw_stats->stats_lock);
514 static void mtk_get_stats64(struct net_device *dev,
515 struct rtnl_link_stats64 *storage)
517 struct mtk_mac *mac = netdev_priv(dev);
518 struct mtk_hw_stats *hw_stats = mac->hw_stats;
521 if (netif_running(dev) && netif_device_present(dev)) {
522 if (spin_trylock_bh(&hw_stats->stats_lock)) {
523 mtk_stats_update_mac(mac);
524 spin_unlock_bh(&hw_stats->stats_lock);
529 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
530 storage->rx_packets = hw_stats->rx_packets;
531 storage->tx_packets = hw_stats->tx_packets;
532 storage->rx_bytes = hw_stats->rx_bytes;
533 storage->tx_bytes = hw_stats->tx_bytes;
534 storage->collisions = hw_stats->tx_collisions;
535 storage->rx_length_errors = hw_stats->rx_short_errors +
536 hw_stats->rx_long_errors;
537 storage->rx_over_errors = hw_stats->rx_overflow;
538 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
539 storage->rx_errors = hw_stats->rx_checksum_errors;
540 storage->tx_aborted_errors = hw_stats->tx_skip;
541 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
543 storage->tx_errors = dev->stats.tx_errors;
544 storage->rx_dropped = dev->stats.rx_dropped;
545 storage->tx_dropped = dev->stats.tx_dropped;
548 static inline int mtk_max_frag_size(int mtu)
550 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
551 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
552 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
554 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
555 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
558 static inline int mtk_max_buf_size(int frag_size)
560 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
561 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
563 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
568 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
569 struct mtk_rx_dma *dma_rxd)
571 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
572 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
573 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
574 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
577 /* the qdma core needs scratch memory to be setup */
578 static int mtk_init_fq_dma(struct mtk_eth *eth)
580 dma_addr_t phy_ring_tail;
581 int cnt = MTK_DMA_SIZE;
585 eth->scratch_ring = dma_alloc_coherent(eth->dev,
586 cnt * sizeof(struct mtk_tx_dma),
587 ð->phy_scratch_ring,
589 if (unlikely(!eth->scratch_ring))
592 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
594 if (unlikely(!eth->scratch_head))
597 dma_addr = dma_map_single(eth->dev,
598 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
600 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
603 phy_ring_tail = eth->phy_scratch_ring +
604 (sizeof(struct mtk_tx_dma) * (cnt - 1));
606 for (i = 0; i < cnt; i++) {
607 eth->scratch_ring[i].txd1 =
608 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
610 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
611 ((i + 1) * sizeof(struct mtk_tx_dma)));
612 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
615 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
616 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
617 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
618 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
623 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
625 void *ret = ring->dma;
627 return ret + (desc - ring->phys);
630 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
631 struct mtk_tx_dma *txd)
633 int idx = txd - ring->dma;
635 return &ring->buf[idx];
638 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
640 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
641 dma_unmap_single(eth->dev,
642 dma_unmap_addr(tx_buf, dma_addr0),
643 dma_unmap_len(tx_buf, dma_len0),
645 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
646 dma_unmap_page(eth->dev,
647 dma_unmap_addr(tx_buf, dma_addr0),
648 dma_unmap_len(tx_buf, dma_len0),
653 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
654 dev_kfree_skb_any(tx_buf->skb);
658 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
659 int tx_num, struct mtk_tx_ring *ring, bool gso)
661 struct mtk_mac *mac = netdev_priv(dev);
662 struct mtk_eth *eth = mac->hw;
663 struct mtk_tx_dma *itxd, *txd;
664 struct mtk_tx_buf *itx_buf, *tx_buf;
665 dma_addr_t mapped_addr;
666 unsigned int nr_frags;
670 itxd = ring->next_free;
671 if (itxd == ring->last_free)
674 /* set the forward port */
675 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
678 itx_buf = mtk_desc_to_tx_buf(ring, itxd);
679 memset(itx_buf, 0, sizeof(*itx_buf));
684 /* TX Checksum offload */
685 if (skb->ip_summed == CHECKSUM_PARTIAL)
686 txd4 |= TX_DMA_CHKSUM;
688 /* VLAN header offload */
689 if (skb_vlan_tag_present(skb))
690 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
692 mapped_addr = dma_map_single(eth->dev, skb->data,
693 skb_headlen(skb), DMA_TO_DEVICE);
694 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
697 WRITE_ONCE(itxd->txd1, mapped_addr);
698 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
699 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
701 dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr);
702 dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb));
706 nr_frags = skb_shinfo(skb)->nr_frags;
707 for (i = 0; i < nr_frags; i++) {
708 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
709 unsigned int offset = 0;
710 int frag_size = skb_frag_size(frag);
713 bool last_frag = false;
714 unsigned int frag_map_size;
716 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
717 if (txd == ring->last_free)
721 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
722 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
725 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
728 if (i == nr_frags - 1 &&
729 (frag_size - frag_map_size) == 0)
732 WRITE_ONCE(txd->txd1, mapped_addr);
733 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
734 TX_DMA_PLEN0(frag_map_size) |
735 last_frag * TX_DMA_LS0));
736 WRITE_ONCE(txd->txd4, fport);
738 tx_buf = mtk_desc_to_tx_buf(ring, txd);
739 memset(tx_buf, 0, sizeof(*tx_buf));
740 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
741 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
742 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
745 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
746 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
747 frag_size -= frag_map_size;
748 offset += frag_map_size;
752 /* store skb to cleanup */
755 WRITE_ONCE(itxd->txd4, txd4);
756 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
757 (!nr_frags * TX_DMA_LS0)));
759 netdev_sent_queue(dev, skb->len);
760 skb_tx_timestamp(skb);
762 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
763 atomic_sub(n_desc, &ring->free_count);
765 /* make sure that all changes to the dma ring are flushed before we
770 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
771 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
777 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
780 mtk_tx_unmap(eth, tx_buf);
782 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
783 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
784 } while (itxd != txd);
789 static inline int mtk_cal_txd_req(struct sk_buff *skb)
792 struct skb_frag_struct *frag;
795 if (skb_is_gso(skb)) {
796 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
797 frag = &skb_shinfo(skb)->frags[i];
798 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
801 nfrags += skb_shinfo(skb)->nr_frags;
807 static int mtk_queue_stopped(struct mtk_eth *eth)
811 for (i = 0; i < MTK_MAC_COUNT; i++) {
814 if (netif_queue_stopped(eth->netdev[i]))
821 static void mtk_wake_queue(struct mtk_eth *eth)
825 for (i = 0; i < MTK_MAC_COUNT; i++) {
828 netif_wake_queue(eth->netdev[i]);
832 static void mtk_stop_queue(struct mtk_eth *eth)
836 for (i = 0; i < MTK_MAC_COUNT; i++) {
839 netif_stop_queue(eth->netdev[i]);
843 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
845 struct mtk_mac *mac = netdev_priv(dev);
846 struct mtk_eth *eth = mac->hw;
847 struct mtk_tx_ring *ring = ð->tx_ring;
848 struct net_device_stats *stats = &dev->stats;
852 /* normally we can rely on the stack not calling this more than once,
853 * however we have 2 queues running on the same ring so we need to lock
856 spin_lock(ð->page_lock);
858 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
861 tx_num = mtk_cal_txd_req(skb);
862 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
864 netif_err(eth, tx_queued, dev,
865 "Tx Ring full when queue awake!\n");
866 spin_unlock(ð->page_lock);
867 return NETDEV_TX_BUSY;
870 /* TSO: fill MSS info in tcp checksum field */
871 if (skb_is_gso(skb)) {
872 if (skb_cow_head(skb, 0)) {
873 netif_warn(eth, tx_err, dev,
874 "GSO expand head fail.\n");
878 if (skb_shinfo(skb)->gso_type &
879 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
881 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
885 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
888 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
891 spin_unlock(ð->page_lock);
896 spin_unlock(ð->page_lock);
898 dev_kfree_skb_any(skb);
902 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
905 struct mtk_rx_ring *ring;
909 return ð->rx_ring[0];
911 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
912 ring = ð->rx_ring[i];
913 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
914 if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
915 ring->calc_idx_update = true;
923 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
925 struct mtk_rx_ring *ring;
929 ring = ð->rx_ring[0];
930 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
932 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
933 ring = ð->rx_ring[i];
934 if (ring->calc_idx_update) {
935 ring->calc_idx_update = false;
936 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
942 static int mtk_poll_rx(struct napi_struct *napi, int budget,
945 struct mtk_rx_ring *ring;
949 struct mtk_rx_dma *rxd, trxd;
952 while (done < budget) {
953 struct net_device *netdev;
958 ring = mtk_get_rx_ring(eth);
962 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
963 rxd = &ring->dma[idx];
964 data = ring->data[idx];
966 mtk_rx_get_desc(&trxd, rxd);
967 if (!(trxd.rxd2 & RX_DMA_DONE))
970 /* find out which mac the packet come from. values start at 1 */
971 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
975 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
979 netdev = eth->netdev[mac];
981 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
984 /* alloc new buffer */
985 new_data = napi_alloc_frag(ring->frag_size);
986 if (unlikely(!new_data)) {
987 netdev->stats.rx_dropped++;
990 dma_addr = dma_map_single(eth->dev,
991 new_data + NET_SKB_PAD,
994 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
995 skb_free_frag(new_data);
996 netdev->stats.rx_dropped++;
1001 skb = build_skb(data, ring->frag_size);
1002 if (unlikely(!skb)) {
1003 skb_free_frag(new_data);
1004 netdev->stats.rx_dropped++;
1007 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
1009 dma_unmap_single(eth->dev, trxd.rxd1,
1010 ring->buf_size, DMA_FROM_DEVICE);
1011 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1013 skb_put(skb, pktlen);
1014 if (trxd.rxd4 & RX_DMA_L4_VALID)
1015 skb->ip_summed = CHECKSUM_UNNECESSARY;
1017 skb_checksum_none_assert(skb);
1018 skb->protocol = eth_type_trans(skb, netdev);
1020 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
1021 RX_DMA_VID(trxd.rxd3))
1022 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1023 RX_DMA_VID(trxd.rxd3));
1024 skb_record_rx_queue(skb, 0);
1025 napi_gro_receive(napi, skb);
1027 ring->data[idx] = new_data;
1028 rxd->rxd1 = (unsigned int)dma_addr;
1031 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
1033 ring->calc_idx = idx;
1040 /* make sure that all changes to the dma ring are flushed before
1044 mtk_update_rx_cpu_idx(eth);
1050 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
1052 struct mtk_tx_ring *ring = ð->tx_ring;
1053 struct mtk_tx_dma *desc;
1054 struct sk_buff *skb;
1055 struct mtk_tx_buf *tx_buf;
1056 unsigned int done[MTK_MAX_DEVS];
1057 unsigned int bytes[MTK_MAX_DEVS];
1061 memset(done, 0, sizeof(done));
1062 memset(bytes, 0, sizeof(bytes));
1064 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
1065 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
1067 desc = mtk_qdma_phys_to_virt(ring, cpu);
1069 while ((cpu != dma) && budget) {
1070 u32 next_cpu = desc->txd2;
1073 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
1074 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
1077 tx_buf = mtk_desc_to_tx_buf(ring, desc);
1078 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
1085 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1086 bytes[mac] += skb->len;
1090 mtk_tx_unmap(eth, tx_buf);
1092 ring->last_free = desc;
1093 atomic_inc(&ring->free_count);
1098 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1100 for (i = 0; i < MTK_MAC_COUNT; i++) {
1101 if (!eth->netdev[i] || !done[i])
1103 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1107 if (mtk_queue_stopped(eth) &&
1108 (atomic_read(&ring->free_count) > ring->thresh))
1109 mtk_wake_queue(eth);
1114 static void mtk_handle_status_irq(struct mtk_eth *eth)
1116 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
1118 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
1119 mtk_stats_update(eth);
1120 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
1125 static int mtk_napi_tx(struct napi_struct *napi, int budget)
1127 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
1131 mtk_handle_status_irq(eth);
1132 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
1133 tx_done = mtk_poll_tx(eth, budget);
1135 if (unlikely(netif_msg_intr(eth))) {
1136 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1137 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1139 "done tx %d, intr 0x%08x/0x%x\n",
1140 tx_done, status, mask);
1143 if (tx_done == budget)
1146 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1147 if (status & MTK_TX_DONE_INT)
1150 napi_complete(napi);
1151 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1156 static int mtk_napi_rx(struct napi_struct *napi, int budget)
1158 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1161 int remain_budget = budget;
1163 mtk_handle_status_irq(eth);
1166 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
1167 rx_done = mtk_poll_rx(napi, remain_budget, eth);
1169 if (unlikely(netif_msg_intr(eth))) {
1170 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1171 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
1173 "done rx %d, intr 0x%08x/0x%x\n",
1174 rx_done, status, mask);
1176 if (rx_done == remain_budget)
1179 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1180 if (status & MTK_RX_DONE_INT) {
1181 remain_budget -= rx_done;
1184 napi_complete(napi);
1185 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1187 return rx_done + budget - remain_budget;
1190 static int mtk_tx_alloc(struct mtk_eth *eth)
1192 struct mtk_tx_ring *ring = ð->tx_ring;
1193 int i, sz = sizeof(*ring->dma);
1195 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1200 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz,
1201 &ring->phys, GFP_ATOMIC);
1205 for (i = 0; i < MTK_DMA_SIZE; i++) {
1206 int next = (i + 1) % MTK_DMA_SIZE;
1207 u32 next_ptr = ring->phys + next * sz;
1209 ring->dma[i].txd2 = next_ptr;
1210 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1213 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1214 ring->next_free = &ring->dma[0];
1215 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1216 ring->thresh = MAX_SKB_FRAGS;
1218 /* make sure that all changes to the dma ring are flushed before we
1223 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1224 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1226 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1229 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1231 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1239 static void mtk_tx_clean(struct mtk_eth *eth)
1241 struct mtk_tx_ring *ring = ð->tx_ring;
1245 for (i = 0; i < MTK_DMA_SIZE; i++)
1246 mtk_tx_unmap(eth, &ring->buf[i]);
1252 dma_free_coherent(eth->dev,
1253 MTK_DMA_SIZE * sizeof(*ring->dma),
1260 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
1262 struct mtk_rx_ring *ring;
1263 int rx_data_len, rx_dma_size;
1267 if (rx_flag == MTK_RX_FLAGS_QDMA) {
1270 ring = ð->rx_ring_qdma;
1273 ring = ð->rx_ring[ring_no];
1276 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
1277 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
1278 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
1280 rx_data_len = ETH_DATA_LEN;
1281 rx_dma_size = MTK_DMA_SIZE;
1284 ring->frag_size = mtk_max_frag_size(rx_data_len);
1285 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1286 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
1291 for (i = 0; i < rx_dma_size; i++) {
1292 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1297 ring->dma = dma_alloc_coherent(eth->dev,
1298 rx_dma_size * sizeof(*ring->dma),
1299 &ring->phys, GFP_ATOMIC);
1303 for (i = 0; i < rx_dma_size; i++) {
1304 dma_addr_t dma_addr = dma_map_single(eth->dev,
1305 ring->data[i] + NET_SKB_PAD,
1308 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1310 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1312 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1314 ring->dma_size = rx_dma_size;
1315 ring->calc_idx_update = false;
1316 ring->calc_idx = rx_dma_size - 1;
1317 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
1318 /* make sure that all changes to the dma ring are flushed before we
1323 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);
1324 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);
1325 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);
1326 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);
1331 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
1335 if (ring->data && ring->dma) {
1336 for (i = 0; i < ring->dma_size; i++) {
1339 if (!ring->dma[i].rxd1)
1341 dma_unmap_single(eth->dev,
1345 skb_free_frag(ring->data[i]);
1352 dma_free_coherent(eth->dev,
1353 ring->dma_size * sizeof(*ring->dma),
1360 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
1363 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
1364 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
1366 /* set LRO rings to auto-learn modes */
1367 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
1369 /* validate LRO ring */
1370 ring_ctrl_dw2 |= MTK_RING_VLD;
1372 /* set AGE timer (unit: 20us) */
1373 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
1374 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
1376 /* set max AGG timer (unit: 20us) */
1377 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
1379 /* set max LRO AGG count */
1380 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
1381 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
1383 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1384 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
1385 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
1386 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
1389 /* IPv4 checksum update enable */
1390 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
1392 /* switch priority comparison to packet count mode */
1393 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
1395 /* bandwidth threshold setting */
1396 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
1398 /* auto-learn score delta setting */
1399 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
1401 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1402 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
1403 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
1405 /* set HW LRO mode & the max aggregation count for rx packets */
1406 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
1408 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
1409 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
1412 lro_ctrl_dw0 |= MTK_LRO_EN;
1414 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
1415 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
1420 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
1425 /* relinquish lro rings, flush aggregated packets */
1426 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
1428 /* wait for relinquishments done */
1429 for (i = 0; i < 10; i++) {
1430 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
1431 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
1438 /* invalidate lro rings */
1439 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1440 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
1442 /* disable HW LRO */
1443 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
1446 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
1450 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1452 /* invalidate the IP setting */
1453 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1455 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
1457 /* validate the IP setting */
1458 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1461 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
1465 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1467 /* invalidate the IP setting */
1468 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1470 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
1473 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
1478 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1479 if (mac->hwlro_ip[i])
1486 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
1487 struct ethtool_rxnfc *cmd)
1489 struct ethtool_rx_flow_spec *fsp =
1490 (struct ethtool_rx_flow_spec *)&cmd->fs;
1491 struct mtk_mac *mac = netdev_priv(dev);
1492 struct mtk_eth *eth = mac->hw;
1495 if ((fsp->flow_type != TCP_V4_FLOW) ||
1496 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
1497 (fsp->location > 1))
1500 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
1501 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1503 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1505 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
1510 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
1511 struct ethtool_rxnfc *cmd)
1513 struct ethtool_rx_flow_spec *fsp =
1514 (struct ethtool_rx_flow_spec *)&cmd->fs;
1515 struct mtk_mac *mac = netdev_priv(dev);
1516 struct mtk_eth *eth = mac->hw;
1519 if (fsp->location > 1)
1522 mac->hwlro_ip[fsp->location] = 0;
1523 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1525 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1527 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1532 static void mtk_hwlro_netdev_disable(struct net_device *dev)
1534 struct mtk_mac *mac = netdev_priv(dev);
1535 struct mtk_eth *eth = mac->hw;
1538 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1539 mac->hwlro_ip[i] = 0;
1540 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
1542 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1545 mac->hwlro_ip_cnt = 0;
1548 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
1549 struct ethtool_rxnfc *cmd)
1551 struct mtk_mac *mac = netdev_priv(dev);
1552 struct ethtool_rx_flow_spec *fsp =
1553 (struct ethtool_rx_flow_spec *)&cmd->fs;
1555 /* only tcp dst ipv4 is meaningful, others are meaningless */
1556 fsp->flow_type = TCP_V4_FLOW;
1557 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
1558 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
1560 fsp->h_u.tcp_ip4_spec.ip4src = 0;
1561 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
1562 fsp->h_u.tcp_ip4_spec.psrc = 0;
1563 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
1564 fsp->h_u.tcp_ip4_spec.pdst = 0;
1565 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
1566 fsp->h_u.tcp_ip4_spec.tos = 0;
1567 fsp->m_u.tcp_ip4_spec.tos = 0xff;
1572 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
1573 struct ethtool_rxnfc *cmd,
1576 struct mtk_mac *mac = netdev_priv(dev);
1580 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1581 if (mac->hwlro_ip[i]) {
1587 cmd->rule_cnt = cnt;
1592 static netdev_features_t mtk_fix_features(struct net_device *dev,
1593 netdev_features_t features)
1595 if (!(features & NETIF_F_LRO)) {
1596 struct mtk_mac *mac = netdev_priv(dev);
1597 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1600 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
1602 features |= NETIF_F_LRO;
1609 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
1613 if (!((dev->features ^ features) & NETIF_F_LRO))
1616 if (!(features & NETIF_F_LRO))
1617 mtk_hwlro_netdev_disable(dev);
1622 /* wait for DMA to finish whatever it is doing before we start using it again */
1623 static int mtk_dma_busy_wait(struct mtk_eth *eth)
1625 unsigned long t_start = jiffies;
1628 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1629 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1631 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1635 dev_err(eth->dev, "DMA init timeout\n");
1639 static int mtk_dma_init(struct mtk_eth *eth)
1644 if (mtk_dma_busy_wait(eth))
1647 /* QDMA needs scratch memory for internal reordering of the
1650 err = mtk_init_fq_dma(eth);
1654 err = mtk_tx_alloc(eth);
1658 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
1662 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
1667 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1668 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
1672 err = mtk_hwlro_rx_init(eth);
1677 /* Enable random early drop and set drop threshold automatically */
1678 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1680 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1685 static void mtk_dma_free(struct mtk_eth *eth)
1689 for (i = 0; i < MTK_MAC_COUNT; i++)
1691 netdev_reset_queue(eth->netdev[i]);
1692 if (eth->scratch_ring) {
1693 dma_free_coherent(eth->dev,
1694 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1696 eth->phy_scratch_ring);
1697 eth->scratch_ring = NULL;
1698 eth->phy_scratch_ring = 0;
1701 mtk_rx_clean(eth, ð->rx_ring[0]);
1702 mtk_rx_clean(eth, ð->rx_ring_qdma);
1705 mtk_hwlro_rx_uninit(eth);
1706 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1707 mtk_rx_clean(eth, ð->rx_ring[i]);
1710 kfree(eth->scratch_head);
1713 static void mtk_tx_timeout(struct net_device *dev)
1715 struct mtk_mac *mac = netdev_priv(dev);
1716 struct mtk_eth *eth = mac->hw;
1718 eth->netdev[mac->id]->stats.tx_errors++;
1719 netif_err(eth, tx_err, dev,
1720 "transmit timed out\n");
1721 schedule_work(ð->pending_work);
1724 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
1726 struct mtk_eth *eth = _eth;
1728 if (likely(napi_schedule_prep(ð->rx_napi))) {
1729 __napi_schedule(ð->rx_napi);
1730 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
1736 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1738 struct mtk_eth *eth = _eth;
1740 if (likely(napi_schedule_prep(ð->tx_napi))) {
1741 __napi_schedule(ð->tx_napi);
1742 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1748 #ifdef CONFIG_NET_POLL_CONTROLLER
1749 static void mtk_poll_controller(struct net_device *dev)
1751 struct mtk_mac *mac = netdev_priv(dev);
1752 struct mtk_eth *eth = mac->hw;
1754 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1755 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
1756 mtk_handle_irq_rx(eth->irq[2], dev);
1757 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1758 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1762 static int mtk_start_dma(struct mtk_eth *eth)
1766 err = mtk_dma_init(eth);
1773 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
1774 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO |
1775 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1780 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1781 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
1787 static int mtk_open(struct net_device *dev)
1789 struct mtk_mac *mac = netdev_priv(dev);
1790 struct mtk_eth *eth = mac->hw;
1792 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1793 if (!refcount_read(ð->dma_refcnt)) {
1794 int err = mtk_start_dma(eth);
1799 napi_enable(ð->tx_napi);
1800 napi_enable(ð->rx_napi);
1801 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1802 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1803 refcount_set(ð->dma_refcnt, 1);
1806 refcount_inc(ð->dma_refcnt);
1808 phy_start(dev->phydev);
1809 netif_start_queue(dev);
1814 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1819 /* stop the dma engine */
1820 spin_lock_bh(ð->page_lock);
1821 val = mtk_r32(eth, glo_cfg);
1822 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1824 spin_unlock_bh(ð->page_lock);
1826 /* wait for dma stop */
1827 for (i = 0; i < 10; i++) {
1828 val = mtk_r32(eth, glo_cfg);
1829 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1837 static int mtk_stop(struct net_device *dev)
1839 struct mtk_mac *mac = netdev_priv(dev);
1840 struct mtk_eth *eth = mac->hw;
1842 netif_tx_disable(dev);
1843 phy_stop(dev->phydev);
1845 /* only shutdown DMA if this is the last user */
1846 if (!refcount_dec_and_test(ð->dma_refcnt))
1849 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1850 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
1851 napi_disable(ð->tx_napi);
1852 napi_disable(ð->rx_napi);
1854 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1855 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG);
1862 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
1864 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1868 usleep_range(1000, 1100);
1869 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1875 static void mtk_clk_disable(struct mtk_eth *eth)
1879 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
1880 clk_disable_unprepare(eth->clks[clk]);
1883 static int mtk_clk_enable(struct mtk_eth *eth)
1887 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
1888 ret = clk_prepare_enable(eth->clks[clk]);
1890 goto err_disable_clks;
1897 clk_disable_unprepare(eth->clks[clk]);
1902 static int mtk_hw_init(struct mtk_eth *eth)
1906 if (test_and_set_bit(MTK_HW_INIT, ð->state))
1909 pm_runtime_enable(eth->dev);
1910 pm_runtime_get_sync(eth->dev);
1912 ret = mtk_clk_enable(eth);
1914 goto err_disable_pm;
1916 ethsys_reset(eth, RSTCTRL_FE);
1917 ethsys_reset(eth, RSTCTRL_PPE);
1919 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
1920 for (i = 0; i < MTK_MAC_COUNT; i++) {
1923 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id);
1924 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id);
1926 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
1929 /* Set GE2 driving and slew rate */
1930 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1933 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1936 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1939 /* Set linkdown as the default for each GMAC. Its own MCR would be set
1940 * up with the more appropriate value when mtk_phy_link_adjust call is
1943 for (i = 0; i < MTK_MAC_COUNT; i++)
1944 mtk_w32(eth, 0, MTK_MAC_MCR(i));
1946 /* Indicates CDM to parse the MTK special tag from CPU
1947 * which also is working out for untag packets.
1949 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
1950 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
1952 /* Enable RX VLan Offloading */
1953 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1955 /* enable interrupt delay for RX */
1956 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
1958 /* disable delay and normal interrupt */
1959 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1960 mtk_tx_irq_disable(eth, ~0);
1961 mtk_rx_irq_disable(eth, ~0);
1962 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1963 mtk_w32(eth, 0, MTK_RST_GL);
1965 /* FE int grouping */
1966 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1967 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1968 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1969 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1970 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
1972 for (i = 0; i < 2; i++) {
1973 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1975 /* setup the forward port to send frame to PDMA */
1978 /* Enable RX checksum */
1979 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1981 /* setup the mac dma */
1982 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1988 pm_runtime_put_sync(eth->dev);
1989 pm_runtime_disable(eth->dev);
1994 static int mtk_hw_deinit(struct mtk_eth *eth)
1996 if (!test_and_clear_bit(MTK_HW_INIT, ð->state))
1999 mtk_clk_disable(eth);
2001 pm_runtime_put_sync(eth->dev);
2002 pm_runtime_disable(eth->dev);
2007 static int __init mtk_init(struct net_device *dev)
2009 struct mtk_mac *mac = netdev_priv(dev);
2010 struct mtk_eth *eth = mac->hw;
2011 const char *mac_addr;
2013 mac_addr = of_get_mac_address(mac->of_node);
2015 ether_addr_copy(dev->dev_addr, mac_addr);
2017 /* If the mac address is invalid, use random mac address */
2018 if (!is_valid_ether_addr(dev->dev_addr)) {
2019 eth_hw_addr_random(dev);
2020 dev_err(eth->dev, "generated random MAC address %pM\n",
2024 return mtk_phy_connect(dev);
2027 static void mtk_uninit(struct net_device *dev)
2029 struct mtk_mac *mac = netdev_priv(dev);
2030 struct mtk_eth *eth = mac->hw;
2032 phy_disconnect(dev->phydev);
2033 if (of_phy_is_fixed_link(mac->of_node))
2034 of_phy_deregister_fixed_link(mac->of_node);
2035 mtk_tx_irq_disable(eth, ~0);
2036 mtk_rx_irq_disable(eth, ~0);
2039 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2045 return phy_mii_ioctl(dev->phydev, ifr, cmd);
2053 static void mtk_pending_work(struct work_struct *work)
2055 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
2057 unsigned long restart = 0;
2061 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
2063 while (test_and_set_bit_lock(MTK_RESETTING, ð->state))
2066 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
2067 /* stop all devices to make sure that dma is properly shut down */
2068 for (i = 0; i < MTK_MAC_COUNT; i++) {
2069 if (!eth->netdev[i])
2071 mtk_stop(eth->netdev[i]);
2072 __set_bit(i, &restart);
2074 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
2076 /* restart underlying hardware such as power, clock, pin mux
2077 * and the connected phy
2082 pinctrl_select_state(eth->dev->pins->p,
2083 eth->dev->pins->default_state);
2086 for (i = 0; i < MTK_MAC_COUNT; i++) {
2088 of_phy_is_fixed_link(eth->mac[i]->of_node))
2090 err = phy_init_hw(eth->netdev[i]->phydev);
2092 dev_err(eth->dev, "%s: PHY init failed.\n",
2093 eth->netdev[i]->name);
2096 /* restart DMA and enable IRQs */
2097 for (i = 0; i < MTK_MAC_COUNT; i++) {
2098 if (!test_bit(i, &restart))
2100 err = mtk_open(eth->netdev[i]);
2102 netif_alert(eth, ifup, eth->netdev[i],
2103 "Driver up/down cycle failed, closing device.\n");
2104 dev_close(eth->netdev[i]);
2108 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
2110 clear_bit_unlock(MTK_RESETTING, ð->state);
2115 static int mtk_free_dev(struct mtk_eth *eth)
2119 for (i = 0; i < MTK_MAC_COUNT; i++) {
2120 if (!eth->netdev[i])
2122 free_netdev(eth->netdev[i]);
2128 static int mtk_unreg_dev(struct mtk_eth *eth)
2132 for (i = 0; i < MTK_MAC_COUNT; i++) {
2133 if (!eth->netdev[i])
2135 unregister_netdev(eth->netdev[i]);
2141 static int mtk_cleanup(struct mtk_eth *eth)
2145 cancel_work_sync(ð->pending_work);
2150 static int mtk_get_link_ksettings(struct net_device *ndev,
2151 struct ethtool_link_ksettings *cmd)
2153 struct mtk_mac *mac = netdev_priv(ndev);
2155 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2158 phy_ethtool_ksettings_get(ndev->phydev, cmd);
2163 static int mtk_set_link_ksettings(struct net_device *ndev,
2164 const struct ethtool_link_ksettings *cmd)
2166 struct mtk_mac *mac = netdev_priv(ndev);
2168 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2171 return phy_ethtool_ksettings_set(ndev->phydev, cmd);
2174 static void mtk_get_drvinfo(struct net_device *dev,
2175 struct ethtool_drvinfo *info)
2177 struct mtk_mac *mac = netdev_priv(dev);
2179 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
2180 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
2181 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
2184 static u32 mtk_get_msglevel(struct net_device *dev)
2186 struct mtk_mac *mac = netdev_priv(dev);
2188 return mac->hw->msg_enable;
2191 static void mtk_set_msglevel(struct net_device *dev, u32 value)
2193 struct mtk_mac *mac = netdev_priv(dev);
2195 mac->hw->msg_enable = value;
2198 static int mtk_nway_reset(struct net_device *dev)
2200 struct mtk_mac *mac = netdev_priv(dev);
2202 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2205 return genphy_restart_aneg(dev->phydev);
2208 static u32 mtk_get_link(struct net_device *dev)
2210 struct mtk_mac *mac = netdev_priv(dev);
2213 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2216 err = genphy_update_link(dev->phydev);
2218 return ethtool_op_get_link(dev);
2220 return dev->phydev->link;
2223 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2227 switch (stringset) {
2229 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
2230 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
2231 data += ETH_GSTRING_LEN;
2237 static int mtk_get_sset_count(struct net_device *dev, int sset)
2241 return ARRAY_SIZE(mtk_ethtool_stats);
2247 static void mtk_get_ethtool_stats(struct net_device *dev,
2248 struct ethtool_stats *stats, u64 *data)
2250 struct mtk_mac *mac = netdev_priv(dev);
2251 struct mtk_hw_stats *hwstats = mac->hw_stats;
2252 u64 *data_src, *data_dst;
2256 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2259 if (netif_running(dev) && netif_device_present(dev)) {
2260 if (spin_trylock_bh(&hwstats->stats_lock)) {
2261 mtk_stats_update_mac(mac);
2262 spin_unlock_bh(&hwstats->stats_lock);
2266 data_src = (u64 *)hwstats;
2270 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2272 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2273 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2274 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2277 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2280 int ret = -EOPNOTSUPP;
2283 case ETHTOOL_GRXRINGS:
2284 if (dev->features & NETIF_F_LRO) {
2285 cmd->data = MTK_MAX_RX_RING_NUM;
2289 case ETHTOOL_GRXCLSRLCNT:
2290 if (dev->features & NETIF_F_LRO) {
2291 struct mtk_mac *mac = netdev_priv(dev);
2293 cmd->rule_cnt = mac->hwlro_ip_cnt;
2297 case ETHTOOL_GRXCLSRULE:
2298 if (dev->features & NETIF_F_LRO)
2299 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
2301 case ETHTOOL_GRXCLSRLALL:
2302 if (dev->features & NETIF_F_LRO)
2303 ret = mtk_hwlro_get_fdir_all(dev, cmd,
2313 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2315 int ret = -EOPNOTSUPP;
2318 case ETHTOOL_SRXCLSRLINS:
2319 if (dev->features & NETIF_F_LRO)
2320 ret = mtk_hwlro_add_ipaddr(dev, cmd);
2322 case ETHTOOL_SRXCLSRLDEL:
2323 if (dev->features & NETIF_F_LRO)
2324 ret = mtk_hwlro_del_ipaddr(dev, cmd);
2333 static const struct ethtool_ops mtk_ethtool_ops = {
2334 .get_link_ksettings = mtk_get_link_ksettings,
2335 .set_link_ksettings = mtk_set_link_ksettings,
2336 .get_drvinfo = mtk_get_drvinfo,
2337 .get_msglevel = mtk_get_msglevel,
2338 .set_msglevel = mtk_set_msglevel,
2339 .nway_reset = mtk_nway_reset,
2340 .get_link = mtk_get_link,
2341 .get_strings = mtk_get_strings,
2342 .get_sset_count = mtk_get_sset_count,
2343 .get_ethtool_stats = mtk_get_ethtool_stats,
2344 .get_rxnfc = mtk_get_rxnfc,
2345 .set_rxnfc = mtk_set_rxnfc,
2348 static const struct net_device_ops mtk_netdev_ops = {
2349 .ndo_init = mtk_init,
2350 .ndo_uninit = mtk_uninit,
2351 .ndo_open = mtk_open,
2352 .ndo_stop = mtk_stop,
2353 .ndo_start_xmit = mtk_start_xmit,
2354 .ndo_set_mac_address = mtk_set_mac_address,
2355 .ndo_validate_addr = eth_validate_addr,
2356 .ndo_do_ioctl = mtk_do_ioctl,
2357 .ndo_tx_timeout = mtk_tx_timeout,
2358 .ndo_get_stats64 = mtk_get_stats64,
2359 .ndo_fix_features = mtk_fix_features,
2360 .ndo_set_features = mtk_set_features,
2361 #ifdef CONFIG_NET_POLL_CONTROLLER
2362 .ndo_poll_controller = mtk_poll_controller,
2366 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
2368 struct mtk_mac *mac;
2369 const __be32 *_id = of_get_property(np, "reg", NULL);
2373 dev_err(eth->dev, "missing mac id\n");
2377 id = be32_to_cpup(_id);
2378 if (id >= MTK_MAC_COUNT) {
2379 dev_err(eth->dev, "%d is not a valid mac id\n", id);
2383 if (eth->netdev[id]) {
2384 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
2388 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2389 if (!eth->netdev[id]) {
2390 dev_err(eth->dev, "alloc_etherdev failed\n");
2393 mac = netdev_priv(eth->netdev[id]);
2399 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
2400 mac->hwlro_ip_cnt = 0;
2402 mac->hw_stats = devm_kzalloc(eth->dev,
2403 sizeof(*mac->hw_stats),
2405 if (!mac->hw_stats) {
2406 dev_err(eth->dev, "failed to allocate counter memory\n");
2410 spin_lock_init(&mac->hw_stats->stats_lock);
2411 u64_stats_init(&mac->hw_stats->syncp);
2412 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2414 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
2415 eth->netdev[id]->watchdog_timeo = 5 * HZ;
2416 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2417 eth->netdev[id]->base_addr = (unsigned long)eth->base;
2419 eth->netdev[id]->hw_features = MTK_HW_FEATURES;
2421 eth->netdev[id]->hw_features |= NETIF_F_LRO;
2423 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
2424 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2425 eth->netdev[id]->features |= MTK_HW_FEATURES;
2426 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
2428 eth->netdev[id]->irq = eth->irq[0];
2429 eth->netdev[id]->dev.of_node = np;
2434 free_netdev(eth->netdev[id]);
2438 static int mtk_probe(struct platform_device *pdev)
2440 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2441 struct device_node *mac_np;
2442 struct mtk_eth *eth;
2446 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2450 eth->soc = of_device_get_match_data(&pdev->dev);
2452 eth->dev = &pdev->dev;
2453 eth->base = devm_ioremap_resource(&pdev->dev, res);
2454 if (IS_ERR(eth->base))
2455 return PTR_ERR(eth->base);
2457 spin_lock_init(ð->page_lock);
2458 spin_lock_init(ð->tx_irq_lock);
2459 spin_lock_init(ð->rx_irq_lock);
2461 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2463 if (IS_ERR(eth->ethsys)) {
2464 dev_err(&pdev->dev, "no ethsys regmap found\n");
2465 return PTR_ERR(eth->ethsys);
2468 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
2470 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2471 "mediatek,sgmiisys");
2472 if (IS_ERR(eth->sgmiisys)) {
2473 dev_err(&pdev->dev, "no sgmiisys regmap found\n");
2474 return PTR_ERR(eth->sgmiisys);
2478 if (eth->soc->required_pctl) {
2479 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2481 if (IS_ERR(eth->pctl)) {
2482 dev_err(&pdev->dev, "no pctl regmap found\n");
2483 return PTR_ERR(eth->pctl);
2487 for (i = 0; i < 3; i++) {
2488 eth->irq[i] = platform_get_irq(pdev, i);
2489 if (eth->irq[i] < 0) {
2490 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
2494 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
2495 eth->clks[i] = devm_clk_get(eth->dev,
2496 mtk_clks_source_name[i]);
2497 if (IS_ERR(eth->clks[i])) {
2498 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
2499 return -EPROBE_DEFER;
2500 if (eth->soc->required_clks & BIT(i)) {
2501 dev_err(&pdev->dev, "clock %s not found\n",
2502 mtk_clks_source_name[i]);
2505 eth->clks[i] = NULL;
2509 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
2510 INIT_WORK(ð->pending_work, mtk_pending_work);
2512 err = mtk_hw_init(eth);
2516 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
2518 for_each_child_of_node(pdev->dev.of_node, mac_np) {
2519 if (!of_device_is_compatible(mac_np,
2520 "mediatek,eth-mac"))
2523 if (!of_device_is_available(mac_np))
2526 err = mtk_add_mac(eth, mac_np);
2531 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
2532 dev_name(eth->dev), eth);
2536 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
2537 dev_name(eth->dev), eth);
2541 err = mtk_mdio_init(eth);
2545 for (i = 0; i < MTK_MAX_DEVS; i++) {
2546 if (!eth->netdev[i])
2549 err = register_netdev(eth->netdev[i]);
2551 dev_err(eth->dev, "error bringing up device\n");
2552 goto err_deinit_mdio;
2554 netif_info(eth, probe, eth->netdev[i],
2555 "mediatek frame engine at 0x%08lx, irq %d\n",
2556 eth->netdev[i]->base_addr, eth->irq[0]);
2559 /* we run 2 devices on the same DMA ring so we need a dummy device
2562 init_dummy_netdev(ð->dummy_dev);
2563 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx,
2565 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx,
2568 platform_set_drvdata(pdev, eth);
2573 mtk_mdio_cleanup(eth);
2582 static int mtk_remove(struct platform_device *pdev)
2584 struct mtk_eth *eth = platform_get_drvdata(pdev);
2587 /* stop all devices to make sure that dma is properly shut down */
2588 for (i = 0; i < MTK_MAC_COUNT; i++) {
2589 if (!eth->netdev[i])
2591 mtk_stop(eth->netdev[i]);
2596 netif_napi_del(ð->tx_napi);
2597 netif_napi_del(ð->rx_napi);
2599 mtk_mdio_cleanup(eth);
2604 static const struct mtk_soc_data mt2701_data = {
2605 .caps = MTK_GMAC1_TRGMII | MTK_HWLRO,
2606 .required_clks = MT7623_CLKS_BITMAP,
2607 .required_pctl = true,
2610 static const struct mtk_soc_data mt7622_data = {
2611 .caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW | MTK_HWLRO,
2612 .required_clks = MT7622_CLKS_BITMAP,
2613 .required_pctl = false,
2616 static const struct mtk_soc_data mt7623_data = {
2617 .caps = MTK_GMAC1_TRGMII | MTK_HWLRO,
2618 .required_clks = MT7623_CLKS_BITMAP,
2619 .required_pctl = true,
2622 const struct of_device_id of_mtk_match[] = {
2623 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
2624 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
2625 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
2628 MODULE_DEVICE_TABLE(of, of_mtk_match);
2630 static struct platform_driver mtk_driver = {
2632 .remove = mtk_remove,
2634 .name = "mtk_soc_eth",
2635 .of_match_table = of_mtk_match,
2639 module_platform_driver(mtk_driver);
2641 MODULE_LICENSE("GPL");
2642 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2643 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");