drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4 #include "ixgbe_x540.h"
   5 #include "ixgbe_type.h"
   6 #include "ixgbe_common.h"
   7 #include "ixgbe_phy.h"
   8
   9 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed);
  10 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *);
  11 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *);
  12 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *);
  13 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *);
  14
  15 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
  16 {
  17         struct ixgbe_mac_info *mac = &hw->mac;
  18         struct ixgbe_phy_info *phy = &hw->phy;
  19         struct ixgbe_link_info *link = &hw->link;
  20
  21         /* Start with X540 invariants, since so simular */
  22         ixgbe_get_invariants_X540(hw);
  23
  24         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
  25                 phy->ops.set_phy_power = NULL;
  26
  27         link->addr = IXGBE_CS4227;
  28
  29         return 0;
  30 }
  31
  32 static s32 ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw)
  33 {
  34         struct ixgbe_phy_info *phy = &hw->phy;
  35
  36         /* Start with X540 invariants, since so similar */
  37         ixgbe_get_invariants_X540(hw);
  38
  39         phy->ops.set_phy_power = NULL;
  40
  41         return 0;
  42 }
  43
  44 static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw)
  45 {
  46         struct ixgbe_mac_info *mac = &hw->mac;
  47         struct ixgbe_phy_info *phy = &hw->phy;
  48
  49         /* Start with X540 invariants, since so simular */
  50         ixgbe_get_invariants_X540(hw);
  51
  52         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
  53                 phy->ops.set_phy_power = NULL;
  54
  55         return 0;
  56 }
  57
  58 static s32 ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw)
  59 {
  60         struct ixgbe_phy_info *phy = &hw->phy;
  61
  62         /* Start with X540 invariants, since so similar */
  63         ixgbe_get_invariants_X540(hw);
  64
  65         phy->ops.set_phy_power = NULL;
  66
  67         return 0;
  68 }
  69
  70 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
  71  *  @hw: pointer to hardware structure
  72  **/
  73 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
  74 {
  75         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  76
  77         if (hw->bus.lan_id) {
  78                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
  79                 esdp |= IXGBE_ESDP_SDP1_DIR;
  80         }
  81         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
  82         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
  83         IXGBE_WRITE_FLUSH(hw);
  84 }
  85
  86 /**
  87  * ixgbe_read_cs4227 - Read CS4227 register
  88  * @hw: pointer to hardware structure
  89  * @reg: register number to write
  90  * @value: pointer to receive value read
  91  *
  92  * Returns status code
  93  */
  94 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  95 {
  96         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
  97 }
  98
  99 /**
 100  * ixgbe_write_cs4227 - Write CS4227 register
 101  * @hw: pointer to hardware structure
 102  * @reg: register number to write
 103  * @value: value to write to register
 104  *
 105  * Returns status code
 106  */
 107 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 108 {
 109         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 110 }
 111
 112 /**
 113  * ixgbe_read_pe - Read register from port expander
 114  * @hw: pointer to hardware structure
 115  * @reg: register number to read
 116  * @value: pointer to receive read value
 117  *
 118  * Returns status code
 119  */
 120 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 121 {
 122         s32 status;
 123
 124         status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
 125         if (status)
 126                 hw_err(hw, "port expander access failed with %d\n", status);
 127         return status;
 128 }
 129
 130 /**
 131  * ixgbe_write_pe - Write register to port expander
 132  * @hw: pointer to hardware structure
 133  * @reg: register number to write
 134  * @value: value to write
 135  *
 136  * Returns status code
 137  */
 138 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 139 {
 140         s32 status;
 141
 142         status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
 143                                                        value);
 144         if (status)
 145                 hw_err(hw, "port expander access failed with %d\n", status);
 146         return status;
 147 }
 148
 149 /**
 150  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 151  * @hw: pointer to hardware structure
 152  *
 153  * This function assumes that the caller has acquired the proper semaphore.
 154  * Returns error code
 155  */
 156 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 157 {
 158         s32 status;
 159         u32 retry;
 160         u16 value;
 161         u8 reg;
 162
 163         /* Trigger hard reset. */
 164         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 165         if (status)
 166                 return status;
 167         reg |= IXGBE_PE_BIT1;
 168         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 169         if (status)
 170                 return status;
 171
 172         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 173         if (status)
 174                 return status;
 175         reg &= ~IXGBE_PE_BIT1;
 176         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 177         if (status)
 178                 return status;
 179
 180         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 181         if (status)
 182                 return status;
 183         reg &= ~IXGBE_PE_BIT1;
 184         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 185         if (status)
 186                 return status;
 187
 188         usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
 189
 190         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 191         if (status)
 192                 return status;
 193         reg |= IXGBE_PE_BIT1;
 194         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 195         if (status)
 196                 return status;
 197
 198         /* Wait for the reset to complete. */
 199         msleep(IXGBE_CS4227_RESET_DELAY);
 200         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 201                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 202                                            &value);
 203                 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
 204                         break;
 205                 msleep(IXGBE_CS4227_CHECK_DELAY);
 206         }
 207         if (retry == IXGBE_CS4227_RETRIES) {
 208                 hw_err(hw, "CS4227 reset did not complete\n");
 209                 return IXGBE_ERR_PHY;
 210         }
 211
 212         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 213         if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 214                 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
 215                 return IXGBE_ERR_PHY;
 216         }
 217
 218         return 0;
 219 }
 220
 221 /**
 222  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 223  * @hw: pointer to hardware structure
 224  */
 225 static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 226 {
 227         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 228         s32 status;
 229         u16 value;
 230         u8 retry;
 231
 232         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 233                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 234                 if (status) {
 235                         hw_err(hw, "semaphore failed with %d\n", status);
 236                         msleep(IXGBE_CS4227_CHECK_DELAY);
 237                         continue;
 238                 }
 239
 240                 /* Get status of reset flow. */
 241                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 242                 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
 243                         goto out;
 244
 245                 if (status || value != IXGBE_CS4227_RESET_PENDING)
 246                         break;
 247
 248                 /* Reset is pending. Wait and check again. */
 249                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 250                 msleep(IXGBE_CS4227_CHECK_DELAY);
 251         }
 252         /* If still pending, assume other instance failed. */
 253         if (retry == IXGBE_CS4227_RETRIES) {
 254                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 255                 if (status) {
 256                         hw_err(hw, "semaphore failed with %d\n", status);
 257                         return;
 258                 }
 259         }
 260
 261         /* Reset the CS4227. */
 262         status = ixgbe_reset_cs4227(hw);
 263         if (status) {
 264                 hw_err(hw, "CS4227 reset failed: %d", status);
 265                 goto out;
 266         }
 267
 268         /* Reset takes so long, temporarily release semaphore in case the
 269          * other driver instance is waiting for the reset indication.
 270          */
 271         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 272                            IXGBE_CS4227_RESET_PENDING);
 273         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 274         usleep_range(10000, 12000);
 275         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276         if (status) {
 277                 hw_err(hw, "semaphore failed with %d", status);
 278                 return;
 279         }
 280
 281         /* Record completion for next time. */
 282         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 283                                     IXGBE_CS4227_RESET_COMPLETE);
 284
 285 out:
 286         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 287         msleep(hw->eeprom.semaphore_delay);
 288 }
 289
 290 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
 291  *  @hw: pointer to hardware structure
 292  *
 293  *  Returns error code
 294  */
 295 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 296 {
 297         switch (hw->device_id) {
 298         case IXGBE_DEV_ID_X550EM_A_SFP:
 299                 if (hw->bus.lan_id)
 300                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 301                 else
 302                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 303                 return ixgbe_identify_module_generic(hw);
 304         case IXGBE_DEV_ID_X550EM_X_SFP:
 305                 /* set up for CS4227 usage */
 306                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 307                 ixgbe_setup_mux_ctl(hw);
 308                 ixgbe_check_cs4227(hw);
 309                 /* Fallthrough */
 310         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 311                 return ixgbe_identify_module_generic(hw);
 312         case IXGBE_DEV_ID_X550EM_X_KX4:
 313                 hw->phy.type = ixgbe_phy_x550em_kx4;
 314                 break;
 315         case IXGBE_DEV_ID_X550EM_X_XFI:
 316                 hw->phy.type = ixgbe_phy_x550em_xfi;
 317                 break;
 318         case IXGBE_DEV_ID_X550EM_X_KR:
 319         case IXGBE_DEV_ID_X550EM_A_KR:
 320         case IXGBE_DEV_ID_X550EM_A_KR_L:
 321                 hw->phy.type = ixgbe_phy_x550em_kr;
 322                 break;
 323         case IXGBE_DEV_ID_X550EM_A_10G_T:
 324                 if (hw->bus.lan_id)
 325                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 326                 else
 327                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 328                 /* Fallthrough */
 329         case IXGBE_DEV_ID_X550EM_X_10G_T:
 330                 return ixgbe_identify_phy_generic(hw);
 331         case IXGBE_DEV_ID_X550EM_X_1G_T:
 332                 hw->phy.type = ixgbe_phy_ext_1g_t;
 333                 break;
 334         case IXGBE_DEV_ID_X550EM_A_1G_T:
 335         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 336                 hw->phy.type = ixgbe_phy_fw;
 337                 hw->phy.ops.read_reg = NULL;
 338                 hw->phy.ops.write_reg = NULL;
 339                 if (hw->bus.lan_id)
 340                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 341                 else
 342                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 343                 break;
 344         default:
 345                 break;
 346         }
 347         return 0;
 348 }
 349
 350 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 351                                      u32 device_type, u16 *phy_data)
 352 {
 353         return IXGBE_NOT_IMPLEMENTED;
 354 }
 355
 356 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 357                                       u32 device_type, u16 phy_data)
 358 {
 359         return IXGBE_NOT_IMPLEMENTED;
 360 }
 361
 362 /**
 363  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 364  * @hw: pointer to the hardware structure
 365  * @addr: I2C bus address to read from
 366  * @reg: I2C device register to read from
 367  * @val: pointer to location to receive read value
 368  *
 369  * Returns an error code on error.
 370  **/
 371 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 372                                            u16 reg, u16 *val)
 373 {
 374         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 375 }
 376
 377 /**
 378  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 379  * @hw: pointer to the hardware structure
 380  * @addr: I2C bus address to read from
 381  * @reg: I2C device register to read from
 382  * @val: pointer to location to receive read value
 383  *
 384  * Returns an error code on error.
 385  **/
 386 static s32
 387 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 388                                          u16 reg, u16 *val)
 389 {
 390         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 391 }
 392
 393 /**
 394  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 395  * @hw: pointer to the hardware structure
 396  * @addr: I2C bus address to write to
 397  * @reg: I2C device register to write to
 398  * @val: value to write
 399  *
 400  * Returns an error code on error.
 401  **/
 402 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 403                                             u8 addr, u16 reg, u16 val)
 404 {
 405         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 406 }
 407
 408 /**
 409  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 410  * @hw: pointer to the hardware structure
 411  * @addr: I2C bus address to write to
 412  * @reg: I2C device register to write to
 413  * @val: value to write
 414  *
 415  * Returns an error code on error.
 416  **/
 417 static s32
 418 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 419                                           u8 addr, u16 reg, u16 val)
 420 {
 421         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 422 }
 423
 424 /**
 425  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 426  * @hw: pointer to hardware structure
 427  * @activity: activity to perform
 428  * @data: Pointer to 4 32-bit words of data
 429  */
 430 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 431                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 432 {
 433         union {
 434                 struct ixgbe_hic_phy_activity_req cmd;
 435                 struct ixgbe_hic_phy_activity_resp rsp;
 436         } hic;
 437         u16 retries = FW_PHY_ACT_RETRIES;
 438         s32 rc;
 439         u32 i;
 440
 441         do {
 442                 memset(&hic, 0, sizeof(hic));
 443                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 444                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 445                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 446                 hic.cmd.port_number = hw->bus.lan_id;
 447                 hic.cmd.activity_id = cpu_to_le16(activity);
 448                 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i)
 449                         hic.cmd.data[i] = cpu_to_be32((*data)[i]);
 450
 451                 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
 452                                                   IXGBE_HI_COMMAND_TIMEOUT,
 453                                                   true);
 454                 if (rc)
 455                         return rc;
 456                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 457                     FW_CEM_RESP_STATUS_SUCCESS) {
 458                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 459                                 (*data)[i] = be32_to_cpu(hic.rsp.data[i]);
 460                         return 0;
 461                 }
 462                 usleep_range(20, 30);
 463                 --retries;
 464         } while (retries > 0);
 465
 466         return IXGBE_ERR_HOST_INTERFACE_COMMAND;
 467 }
 468
 469 static const struct {
 470         u16 fw_speed;
 471         ixgbe_link_speed phy_speed;
 472 } ixgbe_fw_map[] = {
 473         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 474         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 475         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 476         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 477         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 478         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 479 };
 480
 481 /**
 482  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 483  * @hw: pointer to hardware structure
 484  *
 485  * Returns error code
 486  */
 487 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 488 {
 489         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 490         u16 phy_speeds;
 491         u16 phy_id_lo;
 492         s32 rc;
 493         u16 i;
 494
 495         if (hw->phy.id)
 496                 return 0;
 497
 498         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 499         if (rc)
 500                 return rc;
 501
 502         hw->phy.speeds_supported = 0;
 503         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 504         for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
 505                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 506                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 507         }
 508
 509         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 510         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 511         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 512         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 513         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 514                 return IXGBE_ERR_PHY_ADDR_INVALID;
 515
 516         hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 517         hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
 518                                        IXGBE_LINK_SPEED_1GB_FULL;
 519         hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 520         return 0;
 521 }
 522
 523 /**
 524  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 525  * @hw: pointer to hardware structure
 526  *
 527  * Returns error code
 528  */
 529 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 530 {
 531         if (hw->bus.lan_id)
 532                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 533         else
 534                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 535
 536         hw->phy.type = ixgbe_phy_fw;
 537         hw->phy.ops.read_reg = NULL;
 538         hw->phy.ops.write_reg = NULL;
 539         return ixgbe_get_phy_id_fw(hw);
 540 }
 541
 542 /**
 543  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 544  * @hw: pointer to hardware structure
 545  *
 546  * Returns error code
 547  */
 548 static s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 549 {
 550         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 551
 552         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 553         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 554 }
 555
 556 /**
 557  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 558  * @hw: pointer to hardware structure
 559  */
 560 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 561 {
 562         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 563         s32 rc;
 564         u16 i;
 565
 566         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 567                 return 0;
 568
 569         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 570                 hw_err(hw, "rx_pause not valid in strict IEEE mode\n");
 571                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
 572         }
 573
 574         switch (hw->fc.requested_mode) {
 575         case ixgbe_fc_full:
 576                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 577                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 578                 break;
 579         case ixgbe_fc_rx_pause:
 580                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 581                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 582                 break;
 583         case ixgbe_fc_tx_pause:
 584                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 585                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 586                 break;
 587         default:
 588                 break;
 589         }
 590
 591         for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
 592                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 593                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 594         }
 595         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 596
 597         if (hw->phy.eee_speeds_advertised)
 598                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 599
 600         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 601         if (rc)
 602                 return rc;
 603         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 604                 return IXGBE_ERR_OVERTEMP;
 605         return 0;
 606 }
 607
 608 /**
 609  * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs
 610  * @hw: pointer to hardware structure
 611  *
 612  * Called at init time to set up flow control.
 613  */
 614 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 615 {
 616         if (hw->fc.requested_mode == ixgbe_fc_default)
 617                 hw->fc.requested_mode = ixgbe_fc_full;
 618
 619         return ixgbe_setup_fw_link(hw);
 620 }
 621
 622 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 623  *  @hw: pointer to hardware structure
 624  *
 625  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 626  *  ixgbe_hw struct in order to set up EEPROM access.
 627  **/
 628 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 629 {
 630         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 631         u32 eec;
 632         u16 eeprom_size;
 633
 634         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 635                 eeprom->semaphore_delay = 10;
 636                 eeprom->type = ixgbe_flash;
 637
 638                 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 639                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 640                                     IXGBE_EEC_SIZE_SHIFT);
 641                 eeprom->word_size = BIT(eeprom_size +
 642                                         IXGBE_EEPROM_WORD_SIZE_SHIFT);
 643
 644                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 645                        eeprom->type, eeprom->word_size);
 646         }
 647
 648         return 0;
 649 }
 650
 651 /**
 652  * ixgbe_iosf_wait - Wait for IOSF command completion
 653  * @hw: pointer to hardware structure
 654  * @ctrl: pointer to location to receive final IOSF control value
 655  *
 656  * Return: failing status on timeout
 657  *
 658  * Note: ctrl can be NULL if the IOSF control register value is not needed
 659  */
 660 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 661 {
 662         u32 i, command;
 663
 664         /* Check every 10 usec to see if the address cycle completed.
 665          * The SB IOSF BUSY bit will clear when the operation is
 666          * complete.
 667          */
 668         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 669                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 670                 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
 671                         break;
 672                 udelay(10);
 673         }
 674         if (ctrl)
 675                 *ctrl = command;
 676         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 677                 hw_dbg(hw, "IOSF wait timed out\n");
 678                 return IXGBE_ERR_PHY;
 679         }
 680
 681         return 0;
 682 }
 683
 684 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
 685  *  IOSF device
 686  *  @hw: pointer to hardware structure
 687  *  @reg_addr: 32 bit PHY register to write
 688  *  @device_type: 3 bit device type
 689  *  @phy_data: Pointer to read data from the register
 690  **/
 691 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 692                                        u32 device_type, u32 *data)
 693 {
 694         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 695         u32 command, error;
 696         s32 ret;
 697
 698         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
 699         if (ret)
 700                 return ret;
 701
 702         ret = ixgbe_iosf_wait(hw, NULL);
 703         if (ret)
 704                 goto out;
 705
 706         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 707                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 708
 709         /* Write IOSF control register */
 710         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 711
 712         ret = ixgbe_iosf_wait(hw, &command);
 713
 714         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 715                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 716                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 717                 hw_dbg(hw, "Failed to read, error %x\n", error);
 718                 return IXGBE_ERR_PHY;
 719         }
 720
 721         if (!ret)
 722                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 723
 724 out:
 725         hw->mac.ops.release_swfw_sync(hw, gssr);
 726         return ret;
 727 }
 728
 729 /**
 730  * ixgbe_get_phy_token - Get the token for shared PHY access
 731  * @hw: Pointer to hardware structure
 732  */
 733 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
 734 {
 735         struct ixgbe_hic_phy_token_req token_cmd;
 736         s32 status;
 737
 738         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 739         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 740         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 741         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 742         token_cmd.port_number = hw->bus.lan_id;
 743         token_cmd.command_type = FW_PHY_TOKEN_REQ;
 744         token_cmd.pad = 0;
 745         status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
 746                                               IXGBE_HI_COMMAND_TIMEOUT,
 747                                               true);
 748         if (status)
 749                 return status;
 750         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 751                 return 0;
 752         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
 753                 return IXGBE_ERR_FW_RESP_INVALID;
 754
 755         return IXGBE_ERR_TOKEN_RETRY;
 756 }
 757
 758 /**
 759  * ixgbe_put_phy_token - Put the token for shared PHY access
 760  * @hw: Pointer to hardware structure
 761  */
 762 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
 763 {
 764         struct ixgbe_hic_phy_token_req token_cmd;
 765         s32 status;
 766
 767         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 768         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 769         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 770         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 771         token_cmd.port_number = hw->bus.lan_id;
 772         token_cmd.command_type = FW_PHY_TOKEN_REL;
 773         token_cmd.pad = 0;
 774         status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
 775                                               IXGBE_HI_COMMAND_TIMEOUT,
 776                                               true);
 777         if (status)
 778                 return status;
 779         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 780                 return 0;
 781         return IXGBE_ERR_FW_RESP_INVALID;
 782 }
 783
 784 /**
 785  *  ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
 786  *  @hw: pointer to hardware structure
 787  *  @reg_addr: 32 bit PHY register to write
 788  *  @device_type: 3 bit device type
 789  *  @data: Data to write to the register
 790  **/
 791 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 792                                          __always_unused u32 device_type,
 793                                          u32 data)
 794 {
 795         struct ixgbe_hic_internal_phy_req write_cmd;
 796
 797         memset(&write_cmd, 0, sizeof(write_cmd));
 798         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
 799         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
 800         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 801         write_cmd.port_number = hw->bus.lan_id;
 802         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
 803         write_cmd.address = cpu_to_be16(reg_addr);
 804         write_cmd.write_data = cpu_to_be32(data);
 805
 806         return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd),
 807                                             IXGBE_HI_COMMAND_TIMEOUT, false);
 808 }
 809
 810 /**
 811  *  ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
 812  *  @hw: pointer to hardware structure
 813  *  @reg_addr: 32 bit PHY register to write
 814  *  @device_type: 3 bit device type
 815  *  @data: Pointer to read data from the register
 816  **/
 817 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 818                                         __always_unused u32 device_type,
 819                                         u32 *data)
 820 {
 821         union {
 822                 struct ixgbe_hic_internal_phy_req cmd;
 823                 struct ixgbe_hic_internal_phy_resp rsp;
 824         } hic;
 825         s32 status;
 826
 827         memset(&hic, 0, sizeof(hic));
 828         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
 829         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
 830         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 831         hic.cmd.port_number = hw->bus.lan_id;
 832         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
 833         hic.cmd.address = cpu_to_be16(reg_addr);
 834
 835         status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
 836                                               IXGBE_HI_COMMAND_TIMEOUT, true);
 837
 838         /* Extract the register value from the response. */
 839         *data = be32_to_cpu(hic.rsp.read_data);
 840
 841         return status;
 842 }
 843
 844 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
 845  *  @hw: pointer to hardware structure
 846  *  @offset: offset of  word in the EEPROM to read
 847  *  @words: number of words
 848  *  @data: word(s) read from the EEPROM
 849  *
 850  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
 851  **/
 852 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 853                                             u16 offset, u16 words, u16 *data)
 854 {
 855         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
 856         struct ixgbe_hic_read_shadow_ram buffer;
 857         u32 current_word = 0;
 858         u16 words_to_read;
 859         s32 status;
 860         u32 i;
 861
 862         /* Take semaphore for the entire operation. */
 863         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
 864         if (status) {
 865                 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
 866                 return status;
 867         }
 868
 869         while (words) {
 870                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
 871                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
 872                 else
 873                         words_to_read = words;
 874
 875                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 876                 buffer.hdr.req.buf_lenh = 0;
 877                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 878                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 879
 880                 /* convert offset from words to bytes */
 881                 buffer.address = (__force u32)cpu_to_be32((offset +
 882                                                            current_word) * 2);
 883                 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2);
 884                 buffer.pad2 = 0;
 885                 buffer.pad3 = 0;
 886
 887                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
 888                                             IXGBE_HI_COMMAND_TIMEOUT);
 889                 if (status) {
 890                         hw_dbg(hw, "Host interface command failed\n");
 891                         goto out;
 892                 }
 893
 894                 for (i = 0; i < words_to_read; i++) {
 895                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
 896                                   2 * i;
 897                         u32 value = IXGBE_READ_REG(hw, reg);
 898
 899                         data[current_word] = (u16)(value & 0xffff);
 900                         current_word++;
 901                         i++;
 902                         if (i < words_to_read) {
 903                                 value >>= 16;
 904                                 data[current_word] = (u16)(value & 0xffff);
 905                                 current_word++;
 906                         }
 907                 }
 908                 words -= words_to_read;
 909         }
 910
 911 out:
 912         hw->mac.ops.release_swfw_sync(hw, mask);
 913         return status;
 914 }
 915
 916 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
 917  *  @hw: pointer to hardware structure
 918  *  @ptr: pointer offset in eeprom
 919  *  @size: size of section pointed by ptr, if 0 first word will be used as size
 920  *  @csum: address of checksum to update
 921  *
 922  *  Returns error status for any failure
 923  **/
 924 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
 925                                    u16 size, u16 *csum, u16 *buffer,
 926                                    u32 buffer_size)
 927 {
 928         u16 buf[256];
 929         s32 status;
 930         u16 length, bufsz, i, start;
 931         u16 *local_buffer;
 932
 933         bufsz = ARRAY_SIZE(buf);
 934
 935         /* Read a chunk at the pointer location */
 936         if (!buffer) {
 937                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
 938                 if (status) {
 939                         hw_dbg(hw, "Failed to read EEPROM image\n");
 940                         return status;
 941                 }
 942                 local_buffer = buf;
 943         } else {
 944                 if (buffer_size < ptr)
 945                         return  IXGBE_ERR_PARAM;
 946                 local_buffer = &buffer[ptr];
 947         }
 948
 949         if (size) {
 950                 start = 0;
 951                 length = size;
 952         } else {
 953                 start = 1;
 954                 length = local_buffer[0];
 955
 956                 /* Skip pointer section if length is invalid. */
 957                 if (length == 0xFFFF || length == 0 ||
 958                     (ptr + length) >= hw->eeprom.word_size)
 959                         return 0;
 960         }
 961
 962         if (buffer && ((u32)start + (u32)length > buffer_size))
 963                 return IXGBE_ERR_PARAM;
 964
 965         for (i = start; length; i++, length--) {
 966                 if (i == bufsz && !buffer) {
 967                         ptr += bufsz;
 968                         i = 0;
 969                         if (length < bufsz)
 970                                 bufsz = length;
 971
 972                         /* Read a chunk at the pointer location */
 973                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
 974                                                                   bufsz, buf);
 975                         if (status) {
 976                                 hw_dbg(hw, "Failed to read EEPROM image\n");
 977                                 return status;
 978                         }
 979                 }
 980                 *csum += local_buffer[i];
 981         }
 982         return 0;
 983 }
 984
 985 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
 986  *  @hw: pointer to hardware structure
 987  *  @buffer: pointer to buffer containing calculated checksum
 988  *  @buffer_size: size of buffer
 989  *
 990  *  Returns a negative error code on error, or the 16-bit checksum
 991  **/
 992 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
 993                                     u32 buffer_size)
 994 {
 995         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
 996         u16 *local_buffer;
 997         s32 status;
 998         u16 checksum = 0;
 999         u16 pointer, i, size;
1000
1001         hw->eeprom.ops.init_params(hw);
1002
1003         if (!buffer) {
1004                 /* Read pointer area */
1005                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1006                                                 IXGBE_EEPROM_LAST_WORD + 1,
1007                                                 eeprom_ptrs);
1008                 if (status) {
1009                         hw_dbg(hw, "Failed to read EEPROM image\n");
1010                         return status;
1011                 }
1012                 local_buffer = eeprom_ptrs;
1013         } else {
1014                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
1015                         return IXGBE_ERR_PARAM;
1016                 local_buffer = buffer;
1017         }
1018
1019         /* For X550 hardware include 0x0-0x41 in the checksum, skip the
1020          * checksum word itself
1021          */
1022         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1023                 if (i != IXGBE_EEPROM_CHECKSUM)
1024                         checksum += local_buffer[i];
1025
1026         /* Include all data from pointers 0x3, 0x6-0xE.  This excludes the
1027          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1028          */
1029         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1030                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1031                         continue;
1032
1033                 pointer = local_buffer[i];
1034
1035                 /* Skip pointer section if the pointer is invalid. */
1036                 if (pointer == 0xFFFF || pointer == 0 ||
1037                     pointer >= hw->eeprom.word_size)
1038                         continue;
1039
1040                 switch (i) {
1041                 case IXGBE_PCIE_GENERAL_PTR:
1042                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1043                         break;
1044                 case IXGBE_PCIE_CONFIG0_PTR:
1045                 case IXGBE_PCIE_CONFIG1_PTR:
1046                         size = IXGBE_PCIE_CONFIG_SIZE;
1047                         break;
1048                 default:
1049                         size = 0;
1050                         break;
1051                 }
1052
1053                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
1054                                                  buffer, buffer_size);
1055                 if (status)
1056                         return status;
1057         }
1058
1059         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1060
1061         return (s32)checksum;
1062 }
1063
1064 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1065  *  @hw: pointer to hardware structure
1066  *
1067  *  Returns a negative error code on error, or the 16-bit checksum
1068  **/
1069 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1070 {
1071         return ixgbe_calc_checksum_X550(hw, NULL, 0);
1072 }
1073
1074 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1075  *  @hw: pointer to hardware structure
1076  *  @offset: offset of  word in the EEPROM to read
1077  *  @data: word read from the EEPROM
1078  *
1079  *   Reads a 16 bit word from the EEPROM using the hostif.
1080  **/
1081 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
1082 {
1083         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
1084         struct ixgbe_hic_read_shadow_ram buffer;
1085         s32 status;
1086
1087         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1088         buffer.hdr.req.buf_lenh = 0;
1089         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1090         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1091
1092         /* convert offset from words to bytes */
1093         buffer.address = (__force u32)cpu_to_be32(offset * 2);
1094         /* one word */
1095         buffer.length = (__force u16)cpu_to_be16(sizeof(u16));
1096
1097         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
1098         if (status)
1099                 return status;
1100
1101         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
1102                                     IXGBE_HI_COMMAND_TIMEOUT);
1103         if (!status) {
1104                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1105                                                   FW_NVM_DATA_OFFSET);
1106         }
1107
1108         hw->mac.ops.release_swfw_sync(hw, mask);
1109         return status;
1110 }
1111
1112 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1113  *  @hw: pointer to hardware structure
1114  *  @checksum_val: calculated checksum
1115  *
1116  *  Performs checksum calculation and validates the EEPROM checksum.  If the
1117  *  caller does not need checksum_val, the value can be NULL.
1118  **/
1119 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
1120                                                u16 *checksum_val)
1121 {
1122         s32 status;
1123         u16 checksum;
1124         u16 read_checksum = 0;
1125
1126         /* Read the first word from the EEPROM. If this times out or fails, do
1127          * not continue or we could be in for a very long wait while every
1128          * EEPROM read fails
1129          */
1130         status = hw->eeprom.ops.read(hw, 0, &checksum);
1131         if (status) {
1132                 hw_dbg(hw, "EEPROM read failed\n");
1133                 return status;
1134         }
1135
1136         status = hw->eeprom.ops.calc_checksum(hw);
1137         if (status < 0)
1138                 return status;
1139
1140         checksum = (u16)(status & 0xffff);
1141
1142         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1143                                            &read_checksum);
1144         if (status)
1145                 return status;
1146
1147         /* Verify read checksum from EEPROM is the same as
1148          * calculated checksum
1149          */
1150         if (read_checksum != checksum) {
1151                 status = IXGBE_ERR_EEPROM_CHECKSUM;
1152                 hw_dbg(hw, "Invalid EEPROM checksum");
1153         }
1154
1155         /* If the user cares, return the calculated checksum */
1156         if (checksum_val)
1157                 *checksum_val = checksum;
1158
1159         return status;
1160 }
1161
1162 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1163  *  @hw: pointer to hardware structure
1164  *  @offset: offset of  word in the EEPROM to write
1165  *  @data: word write to the EEPROM
1166  *
1167  *  Write a 16 bit word to the EEPROM using the hostif.
1168  **/
1169 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1170                                            u16 data)
1171 {
1172         s32 status;
1173         struct ixgbe_hic_write_shadow_ram buffer;
1174
1175         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1176         buffer.hdr.req.buf_lenh = 0;
1177         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1178         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1179
1180         /* one word */
1181         buffer.length = cpu_to_be16(sizeof(u16));
1182         buffer.data = data;
1183         buffer.address = cpu_to_be32(offset * 2);
1184
1185         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1186                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1187         return status;
1188 }
1189
1190 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1191  *  @hw: pointer to hardware structure
1192  *  @offset: offset of  word in the EEPROM to write
1193  *  @data: word write to the EEPROM
1194  *
1195  *  Write a 16 bit word to the EEPROM using the hostif.
1196  **/
1197 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
1198 {
1199         s32 status = 0;
1200
1201         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
1202                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1203                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1204         } else {
1205                 hw_dbg(hw, "write ee hostif failed to get semaphore");
1206                 status = IXGBE_ERR_SWFW_SYNC;
1207         }
1208
1209         return status;
1210 }
1211
1212 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1213  *  @hw: pointer to hardware structure
1214  *
1215  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1216  **/
1217 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1218 {
1219         s32 status = 0;
1220         union ixgbe_hic_hdr2 buffer;
1221
1222         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
1223         buffer.req.buf_lenh = 0;
1224         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
1225         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
1226
1227         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1228                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1229         return status;
1230 }
1231
1232 /**
1233  * ixgbe_get_bus_info_X550em - Set PCI bus info
1234  * @hw: pointer to hardware structure
1235  *
1236  * Sets bus link width and speed to unknown because X550em is
1237  * not a PCI device.
1238  **/
1239 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1240 {
1241         hw->bus.type  = ixgbe_bus_type_internal;
1242         hw->bus.width = ixgbe_bus_width_unknown;
1243         hw->bus.speed = ixgbe_bus_speed_unknown;
1244
1245         hw->mac.ops.set_lan_id(hw);
1246
1247         return 0;
1248 }
1249
1250 /**
1251  * ixgbe_fw_recovery_mode - Check FW NVM recovery mode
1252  * @hw: pointer t hardware structure
1253  *
1254  * Returns true if in FW NVM recovery mode.
1255  */
1256 static bool ixgbe_fw_recovery_mode_X550(struct ixgbe_hw *hw)
1257 {
1258         u32 fwsm;
1259
1260         fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
1261         return !!(fwsm & IXGBE_FWSM_FW_NVM_RECOVERY_MODE);
1262 }
1263
1264 /** ixgbe_disable_rx_x550 - Disable RX unit
1265  *
1266  *  Enables the Rx DMA unit for x550
1267  **/
1268 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1269 {
1270         u32 rxctrl, pfdtxgswc;
1271         s32 status;
1272         struct ixgbe_hic_disable_rxen fw_cmd;
1273
1274         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1275         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1276                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1277                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1278                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1279                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1280                         hw->mac.set_lben = true;
1281                 } else {
1282                         hw->mac.set_lben = false;
1283                 }
1284
1285                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1286                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1287                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1288                 fw_cmd.port_number = hw->bus.lan_id;
1289
1290                 status = ixgbe_host_interface_command(hw, &fw_cmd,
1291                                         sizeof(struct ixgbe_hic_disable_rxen),
1292                                         IXGBE_HI_COMMAND_TIMEOUT, true);
1293
1294                 /* If we fail - disable RX using register write */
1295                 if (status) {
1296                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1297                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1298                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1299                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1300                         }
1301                 }
1302         }
1303 }
1304
1305 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1306  *  @hw: pointer to hardware structure
1307  *
1308  *  After writing EEPROM to shadow RAM using EEWR register, software calculates
1309  *  checksum and updates the EEPROM and instructs the hardware to update
1310  *  the flash.
1311  **/
1312 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1313 {
1314         s32 status;
1315         u16 checksum = 0;
1316
1317         /* Read the first word from the EEPROM. If this times out or fails, do
1318          * not continue or we could be in for a very long wait while every
1319          * EEPROM read fails
1320          */
1321         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1322         if (status) {
1323                 hw_dbg(hw, "EEPROM read failed\n");
1324                 return status;
1325         }
1326
1327         status = ixgbe_calc_eeprom_checksum_X550(hw);
1328         if (status < 0)
1329                 return status;
1330
1331         checksum = (u16)(status & 0xffff);
1332
1333         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1334                                             checksum);
1335         if (status)
1336                 return status;
1337
1338         status = ixgbe_update_flash_X550(hw);
1339
1340         return status;
1341 }
1342
1343 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1344  *  @hw: pointer to hardware structure
1345  *  @offset: offset of  word in the EEPROM to write
1346  *  @words: number of words
1347  *  @data: word(s) write to the EEPROM
1348  *
1349  *
1350  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1351  **/
1352 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1353                                              u16 offset, u16 words,
1354                                              u16 *data)
1355 {
1356         s32 status = 0;
1357         u32 i = 0;
1358
1359         /* Take semaphore for the entire operation. */
1360         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1361         if (status) {
1362                 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1363                 return status;
1364         }
1365
1366         for (i = 0; i < words; i++) {
1367                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1368                                                          data[i]);
1369                 if (status) {
1370                         hw_dbg(hw, "Eeprom buffered write failed\n");
1371                         break;
1372                 }
1373         }
1374
1375         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1376
1377         return status;
1378 }
1379
1380 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1381  *  IOSF device
1382  *
1383  *  @hw: pointer to hardware structure
1384  *  @reg_addr: 32 bit PHY register to write
1385  *  @device_type: 3 bit device type
1386  *  @data: Data to write to the register
1387  **/
1388 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1389                                         u32 device_type, u32 data)
1390 {
1391         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1392         u32 command, error;
1393         s32 ret;
1394
1395         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1396         if (ret)
1397                 return ret;
1398
1399         ret = ixgbe_iosf_wait(hw, NULL);
1400         if (ret)
1401                 goto out;
1402
1403         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1404                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1405
1406         /* Write IOSF control register */
1407         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1408
1409         /* Write IOSF data register */
1410         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1411
1412         ret = ixgbe_iosf_wait(hw, &command);
1413
1414         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1415                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1416                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1417                 hw_dbg(hw, "Failed to write, error %x\n", error);
1418                 return IXGBE_ERR_PHY;
1419         }
1420
1421 out:
1422         hw->mac.ops.release_swfw_sync(hw, gssr);
1423         return ret;
1424 }
1425
1426 /**
1427  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
1428  *  @hw: pointer to hardware structure
1429  *
1430  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
1431  **/
1432 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
1433 {
1434         s32 status;
1435         u32 reg_val;
1436
1437         /* Disable training protocol FSM. */
1438         status = ixgbe_read_iosf_sb_reg_x550(hw,
1439                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1440                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1441         if (status)
1442                 return status;
1443
1444         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1445         status = ixgbe_write_iosf_sb_reg_x550(hw,
1446                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1447                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1448         if (status)
1449                 return status;
1450
1451         /* Disable Flex from training TXFFE. */
1452         status = ixgbe_read_iosf_sb_reg_x550(hw,
1453                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1454                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1455         if (status)
1456                 return status;
1457
1458         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1459         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1460         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1461         status = ixgbe_write_iosf_sb_reg_x550(hw,
1462                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1463                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1464         if (status)
1465                 return status;
1466
1467         status = ixgbe_read_iosf_sb_reg_x550(hw,
1468                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1469                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1470         if (status)
1471                 return status;
1472
1473         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1474         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1475         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1476         status = ixgbe_write_iosf_sb_reg_x550(hw,
1477                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1478                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1479         if (status)
1480                 return status;
1481
1482         /* Enable override for coefficients. */
1483         status = ixgbe_read_iosf_sb_reg_x550(hw,
1484                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1485                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1486         if (status)
1487                 return status;
1488
1489         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1490         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1491         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1492         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1493         status = ixgbe_write_iosf_sb_reg_x550(hw,
1494                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1495                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1496         return status;
1497 }
1498
1499 /**
1500  *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1501  *  internal PHY
1502  *  @hw: pointer to hardware structure
1503  **/
1504 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1505 {
1506         s32 status;
1507         u32 link_ctrl;
1508
1509         /* Restart auto-negotiation. */
1510         status = hw->mac.ops.read_iosf_sb_reg(hw,
1511                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1512                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1513
1514         if (status) {
1515                 hw_dbg(hw, "Auto-negotiation did not complete\n");
1516                 return status;
1517         }
1518
1519         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1520         status = hw->mac.ops.write_iosf_sb_reg(hw,
1521                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1522                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1523
1524         if (hw->mac.type == ixgbe_mac_x550em_a) {
1525                 u32 flx_mask_st20;
1526
1527                 /* Indicate to FW that AN restart has been asserted */
1528                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1529                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1530                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1531
1532                 if (status) {
1533                         hw_dbg(hw, "Auto-negotiation did not complete\n");
1534                         return status;
1535                 }
1536
1537                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1538                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1539                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1540                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1541         }
1542
1543         return status;
1544 }
1545
1546 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1547  *  @hw: pointer to hardware structure
1548  *  @speed: the link speed to force
1549  *
1550  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1551  *  internal and external PHY at a specific speed, without autonegotiation.
1552  **/
1553 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1554 {
1555         struct ixgbe_mac_info *mac = &hw->mac;
1556         s32 status;
1557         u32 reg_val;
1558
1559         /* iXFI is only supported with X552 */
1560         if (mac->type != ixgbe_mac_X550EM_x)
1561                 return IXGBE_ERR_LINK_SETUP;
1562
1563         /* Disable AN and force speed to 10G Serial. */
1564         status = ixgbe_read_iosf_sb_reg_x550(hw,
1565                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1566                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1567         if (status)
1568                 return status;
1569
1570         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1571         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1572
1573         /* Select forced link speed for internal PHY. */
1574         switch (*speed) {
1575         case IXGBE_LINK_SPEED_10GB_FULL:
1576                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1577                 break;
1578         case IXGBE_LINK_SPEED_1GB_FULL:
1579                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1580                 break;
1581         default:
1582                 /* Other link speeds are not supported by internal KR PHY. */
1583                 return IXGBE_ERR_LINK_SETUP;
1584         }
1585
1586         status = ixgbe_write_iosf_sb_reg_x550(hw,
1587                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1588                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1589         if (status)
1590                 return status;
1591
1592         /* Additional configuration needed for x550em_x */
1593         if (hw->mac.type == ixgbe_mac_X550EM_x) {
1594                 status = ixgbe_setup_ixfi_x550em_x(hw);
1595                 if (status)
1596                         return status;
1597         }
1598
1599         /* Toggle port SW reset by AN reset. */
1600         status = ixgbe_restart_an_internal_phy_x550em(hw);
1601
1602         return status;
1603 }
1604
1605 /**
1606  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1607  *  @hw: pointer to hardware structure
1608  *  @linear: true if SFP module is linear
1609  */
1610 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1611 {
1612         switch (hw->phy.sfp_type) {
1613         case ixgbe_sfp_type_not_present:
1614                 return IXGBE_ERR_SFP_NOT_PRESENT;
1615         case ixgbe_sfp_type_da_cu_core0:
1616         case ixgbe_sfp_type_da_cu_core1:
1617                 *linear = true;
1618                 break;
1619         case ixgbe_sfp_type_srlr_core0:
1620         case ixgbe_sfp_type_srlr_core1:
1621         case ixgbe_sfp_type_da_act_lmt_core0:
1622         case ixgbe_sfp_type_da_act_lmt_core1:
1623         case ixgbe_sfp_type_1g_sx_core0:
1624         case ixgbe_sfp_type_1g_sx_core1:
1625         case ixgbe_sfp_type_1g_lx_core0:
1626         case ixgbe_sfp_type_1g_lx_core1:
1627                 *linear = false;
1628                 break;
1629         case ixgbe_sfp_type_unknown:
1630         case ixgbe_sfp_type_1g_cu_core0:
1631         case ixgbe_sfp_type_1g_cu_core1:
1632         default:
1633                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1634         }
1635
1636         return 0;
1637 }
1638
1639 /**
1640  * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1641  * @hw: pointer to hardware structure
1642  * @speed: the link speed to force
1643  * @autoneg_wait_to_complete: unused
1644  *
1645  * Configures the extern PHY and the integrated KR PHY for SFP support.
1646  */
1647 static s32
1648 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1649                                 ixgbe_link_speed speed,
1650                                 __always_unused bool autoneg_wait_to_complete)
1651 {
1652         s32 status;
1653         u16 reg_slice, reg_val;
1654         bool setup_linear = false;
1655
1656         /* Check if SFP module is supported and linear */
1657         status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1658
1659         /* If no SFP module present, then return success. Return success since
1660          * there is no reason to configure CS4227 and SFP not present error is
1661          * not accepted in the setup MAC link flow.
1662          */
1663         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
1664                 return 0;
1665
1666         if (status)
1667                 return status;
1668
1669         /* Configure internal PHY for KR/KX. */
1670         ixgbe_setup_kr_speed_x550em(hw, speed);
1671
1672         /* Configure CS4227 LINE side to proper mode. */
1673         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1674         if (setup_linear)
1675                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1676         else
1677                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1678
1679         status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1680                                          reg_val);
1681
1682         return status;
1683 }
1684
1685 /**
1686  * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
1687  * @hw: pointer to hardware structure
1688  * @speed: the link speed to force
1689  *
1690  * Configures the integrated PHY for native SFI mode. Used to connect the
1691  * internal PHY directly to an SFP cage, without autonegotiation.
1692  **/
1693 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1694 {
1695         struct ixgbe_mac_info *mac = &hw->mac;
1696         s32 status;
1697         u32 reg_val;
1698
1699         /* Disable all AN and force speed to 10G Serial. */
1700         status = mac->ops.read_iosf_sb_reg(hw,
1701                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1702                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1703         if (status)
1704                 return status;
1705
1706         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1707         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1708         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1709         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1710
1711         /* Select forced link speed for internal PHY. */
1712         switch (*speed) {
1713         case IXGBE_LINK_SPEED_10GB_FULL:
1714                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
1715                 break;
1716         case IXGBE_LINK_SPEED_1GB_FULL:
1717                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1718                 break;
1719         default:
1720                 /* Other link speeds are not supported by internal PHY. */
1721                 return IXGBE_ERR_LINK_SETUP;
1722         }
1723
1724         status = mac->ops.write_iosf_sb_reg(hw,
1725                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1726                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1727
1728         /* Toggle port SW reset by AN reset. */
1729         status = ixgbe_restart_an_internal_phy_x550em(hw);
1730
1731         return status;
1732 }
1733
1734 /**
1735  * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
1736  * @hw: pointer to hardware structure
1737  * @speed: link speed
1738  * @autoneg_wait_to_complete: unused
1739  *
1740  * Configure the the integrated PHY for native SFP support.
1741  */
1742 static s32
1743 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1744                            __always_unused bool autoneg_wait_to_complete)
1745 {
1746         bool setup_linear = false;
1747         u32 reg_phy_int;
1748         s32 ret_val;
1749
1750         /* Check if SFP module is supported and linear */
1751         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1752
1753         /* If no SFP module present, then return success. Return success since
1754          * SFP not present error is not excepted in the setup MAC link flow.
1755          */
1756         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1757                 return 0;
1758
1759         if (ret_val)
1760                 return ret_val;
1761
1762         /* Configure internal PHY for native SFI based on module type */
1763         ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
1764                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1765                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
1766         if (ret_val)
1767                 return ret_val;
1768
1769         reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
1770         if (!setup_linear)
1771                 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
1772
1773         ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
1774                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1775                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
1776         if (ret_val)
1777                 return ret_val;
1778
1779         /* Setup SFI internal link. */
1780         return ixgbe_setup_sfi_x550a(hw, &speed);
1781 }
1782
1783 /**
1784  * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
1785  * @hw: pointer to hardware structure
1786  * @speed: link speed
1787  * @autoneg_wait_to_complete: unused
1788  *
1789  * Configure the the integrated PHY for SFP support.
1790  */
1791 static s32
1792 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1793                                __always_unused bool autoneg_wait_to_complete)
1794 {
1795         u32 reg_slice, slice_offset;
1796         bool setup_linear = false;
1797         u16 reg_phy_ext;
1798         s32 ret_val;
1799
1800         /* Check if SFP module is supported and linear */
1801         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1802
1803         /* If no SFP module present, then return success. Return success since
1804          * SFP not present error is not excepted in the setup MAC link flow.
1805          */
1806         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1807                 return 0;
1808
1809         if (ret_val)
1810                 return ret_val;
1811
1812         /* Configure internal PHY for KR/KX. */
1813         ixgbe_setup_kr_speed_x550em(hw, speed);
1814
1815         if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE)
1816                 return IXGBE_ERR_PHY_ADDR_INVALID;
1817
1818         /* Get external PHY SKU id */
1819         ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
1820                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
1821         if (ret_val)
1822                 return ret_val;
1823
1824         /* When configuring quad port CS4223, the MAC instance is part
1825          * of the slice offset.
1826          */
1827         if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
1828                 slice_offset = (hw->bus.lan_id +
1829                                 (hw->bus.instance_id << 1)) << 12;
1830         else
1831                 slice_offset = hw->bus.lan_id << 12;
1832
1833         /* Configure CS4227/CS4223 LINE side to proper mode. */
1834         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
1835
1836         ret_val = hw->phy.ops.read_reg(hw, reg_slice,
1837                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
1838         if (ret_val)
1839                 return ret_val;
1840
1841         reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
1842                          (IXGBE_CS4227_EDC_MODE_SR << 1));
1843
1844         if (setup_linear)
1845                 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1846         else
1847                 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1848
1849         ret_val = hw->phy.ops.write_reg(hw, reg_slice,
1850                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
1851         if (ret_val)
1852                 return ret_val;
1853
1854         /* Flush previous write with a read */
1855         return hw->phy.ops.read_reg(hw, reg_slice,
1856                                     IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
1857 }
1858
1859 /**
1860  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1861  * @hw: pointer to hardware structure
1862  * @speed: new link speed
1863  * @autoneg_wait: true when waiting for completion is needed
1864  *
1865  * Setup internal/external PHY link speed based on link speed, then set
1866  * external PHY auto advertised link speed.
1867  *
1868  * Returns error status for any failure
1869  **/
1870 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1871                                          ixgbe_link_speed speed,
1872                                          bool autoneg_wait)
1873 {
1874         s32 status;
1875         ixgbe_link_speed force_speed;
1876
1877         /* Setup internal/external PHY link speed to iXFI (10G), unless
1878          * only 1G is auto advertised then setup KX link.
1879          */
1880         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1881                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1882         else
1883                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1884
1885         /* If X552 and internal link mode is XFI, then setup XFI internal link.
1886          */
1887         if (hw->mac.type == ixgbe_mac_X550EM_x &&
1888             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1889                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1890
1891                 if (status)
1892                         return status;
1893         }
1894
1895         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1896 }
1897
1898 /** ixgbe_check_link_t_X550em - Determine link and speed status
1899   * @hw: pointer to hardware structure
1900   * @speed: pointer to link speed
1901   * @link_up: true when link is up
1902   * @link_up_wait_to_complete: bool used to wait for link up or not
1903   *
1904   * Check that both the MAC and X557 external PHY have link.
1905   **/
1906 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1907                                      ixgbe_link_speed *speed,
1908                                      bool *link_up,
1909                                      bool link_up_wait_to_complete)
1910 {
1911         u32 status;
1912         u16 i, autoneg_status;
1913
1914         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1915                 return IXGBE_ERR_CONFIG;
1916
1917         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1918                                               link_up_wait_to_complete);
1919
1920         /* If check link fails or MAC link is not up, then return */
1921         if (status || !(*link_up))
1922                 return status;
1923
1924         /* MAC link is up, so check external PHY link.
1925          * Link status is latching low, and can only be used to detect link
1926          * drop, and not the current status of the link without performing
1927          * back-to-back reads.
1928          */
1929         for (i = 0; i < 2; i++) {
1930                 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
1931                                               &autoneg_status);
1932
1933                 if (status)
1934                         return status;
1935         }
1936
1937         /* If external PHY link is not up, then indicate link not up */
1938         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1939                 *link_up = false;
1940
1941         return 0;
1942 }
1943
1944 /**
1945  * ixgbe_setup_sgmii - Set up link for sgmii
1946  * @hw: pointer to hardware structure
1947  * @speed: unused
1948  * @autoneg_wait_to_complete: unused
1949  */
1950 static s32
1951 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed,
1952                   __always_unused bool autoneg_wait_to_complete)
1953 {
1954         struct ixgbe_mac_info *mac = &hw->mac;
1955         u32 lval, sval, flx_val;
1956         s32 rc;
1957
1958         rc = mac->ops.read_iosf_sb_reg(hw,
1959                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1960                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1961         if (rc)
1962                 return rc;
1963
1964         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1965         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1966         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1967         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1968         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1969         rc = mac->ops.write_iosf_sb_reg(hw,
1970                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1971                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1972         if (rc)
1973                 return rc;
1974
1975         rc = mac->ops.read_iosf_sb_reg(hw,
1976                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1977                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1978         if (rc)
1979                 return rc;
1980
1981         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1982         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1983         rc = mac->ops.write_iosf_sb_reg(hw,
1984                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1985                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1986         if (rc)
1987                 return rc;
1988
1989         rc = mac->ops.read_iosf_sb_reg(hw,
1990                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1991                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1992         if (rc)
1993                 return rc;
1994
1995         rc = mac->ops.read_iosf_sb_reg(hw,
1996                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1997                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1998         if (rc)
1999                 return rc;
2000
2001         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2002         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2003         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2004         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2005         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2006
2007         rc = mac->ops.write_iosf_sb_reg(hw,
2008                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2009                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2010         if (rc)
2011                 return rc;
2012
2013         rc = ixgbe_restart_an_internal_phy_x550em(hw);
2014         return rc;
2015 }
2016
2017 /**
2018  * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
2019  * @hw: pointer to hardware structure
2020  * @speed: the link speed to force
2021  * @autoneg_wait: true when waiting for completion is needed
2022  */
2023 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
2024                                 bool autoneg_wait)
2025 {
2026         struct ixgbe_mac_info *mac = &hw->mac;
2027         u32 lval, sval, flx_val;
2028         s32 rc;
2029
2030         rc = mac->ops.read_iosf_sb_reg(hw,
2031                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2032                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
2033         if (rc)
2034                 return rc;
2035
2036         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2037         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2038         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
2039         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
2040         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2041         rc = mac->ops.write_iosf_sb_reg(hw,
2042                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2043                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2044         if (rc)
2045                 return rc;
2046
2047         rc = mac->ops.read_iosf_sb_reg(hw,
2048                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2049                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
2050         if (rc)
2051                 return rc;
2052
2053         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
2054         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
2055         rc = mac->ops.write_iosf_sb_reg(hw,
2056                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2057                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
2058         if (rc)
2059                 return rc;
2060
2061         rc = mac->ops.write_iosf_sb_reg(hw,
2062                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2063                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2064         if (rc)
2065                 return rc;
2066
2067         rc = mac->ops.read_iosf_sb_reg(hw,
2068                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2069                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2070         if (rc)
2071                 return rc;
2072
2073         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2074         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2075         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2076         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2077         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2078
2079         rc = mac->ops.write_iosf_sb_reg(hw,
2080                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2081                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2082         if (rc)
2083                 return rc;
2084
2085         ixgbe_restart_an_internal_phy_x550em(hw);
2086
2087         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
2088 }
2089
2090 /**
2091  * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
2092  * @hw: pointer to hardware structure
2093  *
2094  * Enable flow control according to IEEE clause 37.
2095  */
2096 static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
2097 {
2098         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2099         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
2100         ixgbe_link_speed speed;
2101         bool link_up;
2102
2103         /* AN should have completed when the cable was plugged in.
2104          * Look for reasons to bail out.  Bail out if:
2105          * - FC autoneg is disabled, or if
2106          * - link is not up.
2107          */
2108         if (hw->fc.disable_fc_autoneg)
2109                 goto out;
2110
2111         hw->mac.ops.check_link(hw, &speed, &link_up, false);
2112         if (!link_up)
2113                 goto out;
2114
2115         /* Check if auto-negotiation has completed */
2116         status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
2117         if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
2118                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2119                 goto out;
2120         }
2121
2122         /* Negotiate the flow control */
2123         status = ixgbe_negotiate_fc(hw, info[0], info[0],
2124                                     FW_PHY_ACT_GET_LINK_INFO_FC_RX,
2125                                     FW_PHY_ACT_GET_LINK_INFO_FC_TX,
2126                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
2127                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
2128
2129 out:
2130         if (!status) {
2131                 hw->fc.fc_was_autonegged = true;
2132         } else {
2133                 hw->fc.fc_was_autonegged = false;
2134                 hw->fc.current_mode = hw->fc.requested_mode;
2135         }
2136 }
2137
2138 /** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers
2139  *  @hw: pointer to hardware structure
2140  **/
2141 static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw)
2142 {
2143         struct ixgbe_mac_info *mac = &hw->mac;
2144
2145         switch (mac->ops.get_media_type(hw)) {
2146         case ixgbe_media_type_fiber:
2147                 mac->ops.setup_fc = NULL;
2148                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
2149                 break;
2150         case ixgbe_media_type_copper:
2151                 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T &&
2152                     hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) {
2153                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2154                         break;
2155                 }
2156                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
2157                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
2158                 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
2159                 mac->ops.check_link = ixgbe_check_mac_link_generic;
2160                 break;
2161         case ixgbe_media_type_backplane:
2162                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
2163                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
2164                 break;
2165         default:
2166                 break;
2167         }
2168 }
2169
2170 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
2171  *  @hw: pointer to hardware structure
2172  **/
2173 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
2174 {
2175         struct ixgbe_mac_info *mac = &hw->mac;
2176
2177         mac->ops.setup_fc = ixgbe_setup_fc_x550em;
2178
2179         switch (mac->ops.get_media_type(hw)) {
2180         case ixgbe_media_type_fiber:
2181                 /* CS4227 does not support autoneg, so disable the laser control
2182                  * functions for SFP+ fiber
2183                  */
2184                 mac->ops.disable_tx_laser = NULL;
2185                 mac->ops.enable_tx_laser = NULL;
2186                 mac->ops.flap_tx_laser = NULL;
2187                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
2188                 switch (hw->device_id) {
2189                 case IXGBE_DEV_ID_X550EM_A_SFP_N:
2190                         mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n;
2191                         break;
2192                 case IXGBE_DEV_ID_X550EM_A_SFP:
2193                         mac->ops.setup_mac_link =
2194                                                 ixgbe_setup_mac_link_sfp_x550a;
2195                         break;
2196                 default:
2197                         mac->ops.setup_mac_link =
2198                                                 ixgbe_setup_mac_link_sfp_x550em;
2199                         break;
2200                 }
2201                 mac->ops.set_rate_select_speed =
2202                                         ixgbe_set_soft_rate_select_speed;
2203                 break;
2204         case ixgbe_media_type_copper:
2205                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
2206                         break;
2207                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2208                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
2209                 mac->ops.check_link = ixgbe_check_link_t_X550em;
2210                 break;
2211         case ixgbe_media_type_backplane:
2212                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
2213                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
2214                         mac->ops.setup_link = ixgbe_setup_sgmii;
2215                 break;
2216         default:
2217                 break;
2218         }
2219
2220         /* Additional modification for X550em_a devices */
2221         if (hw->mac.type == ixgbe_mac_x550em_a)
2222                 ixgbe_init_mac_link_ops_X550em_a(hw);
2223 }
2224
2225 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
2226  * @hw: pointer to hardware structure
2227  */
2228 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
2229 {
2230         s32 status;
2231         bool linear;
2232
2233         /* Check if SFP module is supported */
2234         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
2235         if (status)
2236                 return status;
2237
2238         ixgbe_init_mac_link_ops_X550em(hw);
2239         hw->phy.ops.reset = NULL;
2240
2241         return 0;
2242 }
2243
2244 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
2245  * @hw: pointer to hardware structure
2246  * @speed: pointer to link speed
2247  * @autoneg: true when autoneg or autotry is enabled
2248  **/
2249 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
2250                                               ixgbe_link_speed *speed,
2251                                               bool *autoneg)
2252 {
2253         if (hw->phy.type == ixgbe_phy_fw) {
2254                 *autoneg = true;
2255                 *speed = hw->phy.speeds_supported;
2256                 return 0;
2257         }
2258
2259         /* SFP */
2260         if (hw->phy.media_type == ixgbe_media_type_fiber) {
2261                 /* CS4227 SFP must not enable auto-negotiation */
2262                 *autoneg = false;
2263
2264                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
2265                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
2266                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2267                         return 0;
2268                 }
2269
2270                 /* Link capabilities are based on SFP */
2271                 if (hw->phy.multispeed_fiber)
2272                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
2273                                  IXGBE_LINK_SPEED_1GB_FULL;
2274                 else
2275                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
2276         } else {
2277                 switch (hw->phy.type) {
2278                 case ixgbe_phy_x550em_kx4:
2279                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
2280                                  IXGBE_LINK_SPEED_2_5GB_FULL |
2281                                  IXGBE_LINK_SPEED_10GB_FULL;
2282                         break;
2283                 case ixgbe_phy_x550em_xfi:
2284                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
2285                                  IXGBE_LINK_SPEED_10GB_FULL;
2286                         break;
2287                 case ixgbe_phy_ext_1g_t:
2288                 case ixgbe_phy_sgmii:
2289                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2290                         break;
2291                 case ixgbe_phy_x550em_kr:
2292                         if (hw->mac.type == ixgbe_mac_x550em_a) {
2293                                 /* check different backplane modes */
2294                                 if (hw->phy.nw_mng_if_sel &
2295                                     IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
2296                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
2297                                         break;
2298                                 } else if (hw->device_id ==
2299                                            IXGBE_DEV_ID_X550EM_A_KR_L) {
2300                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2301                                         break;
2302                                 }
2303                         }
2304                         /* fall through */
2305                 default:
2306                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
2307                                  IXGBE_LINK_SPEED_1GB_FULL;
2308                         break;
2309                 }
2310                 *autoneg = true;
2311         }
2312         return 0;
2313 }
2314
2315 /**
2316  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2317  * @hw: pointer to hardware structure
2318  * @lsc: pointer to boolean flag which indicates whether external Base T
2319  *       PHY interrupt is lsc
2320  *
2321  * Determime if external Base T PHY interrupt cause is high temperature
2322  * failure alarm or link status change.
2323  *
2324  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2325  * failure alarm, else return PHY access status.
2326  **/
2327 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
2328 {
2329         u32 status;
2330         u16 reg;
2331
2332         *lsc = false;
2333
2334         /* Vendor alarm triggered */
2335         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2336                                       MDIO_MMD_VEND1,
2337                                       &reg);
2338
2339         if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2340                 return status;
2341
2342         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2343         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2344                                       MDIO_MMD_VEND1,
2345                                       &reg);
2346
2347         if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2348                                 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2349                 return status;
2350
2351         /* Global alarm triggered */
2352         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2353                                       MDIO_MMD_VEND1,
2354                                       &reg);
2355
2356         if (status)
2357                 return status;
2358
2359         /* If high temperature failure, then return over temp error and exit */
2360         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2361                 /* power down the PHY in case the PHY FW didn't already */
2362                 ixgbe_set_copper_phy_power(hw, false);
2363                 return IXGBE_ERR_OVERTEMP;
2364         }
2365         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2366                 /*  device fault alarm triggered */
2367                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2368                                           MDIO_MMD_VEND1,
2369                                           &reg);
2370                 if (status)
2371                         return status;
2372
2373                 /* if device fault was due to high temp alarm handle and exit */
2374                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2375                         /* power down the PHY in case the PHY FW didn't */
2376                         ixgbe_set_copper_phy_power(hw, false);
2377                         return IXGBE_ERR_OVERTEMP;
2378                 }
2379         }
2380
2381         /* Vendor alarm 2 triggered */
2382         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2383                                       MDIO_MMD_AN, &reg);
2384
2385         if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2386                 return status;
2387
2388         /* link connect/disconnect event occurred */
2389         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2390                                       MDIO_MMD_AN, &reg);
2391
2392         if (status)
2393                 return status;
2394
2395         /* Indicate LSC */
2396         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2397                 *lsc = true;
2398
2399         return 0;
2400 }
2401
2402 /**
2403  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2404  * @hw: pointer to hardware structure
2405  *
2406  * Enable link status change and temperature failure alarm for the external
2407  * Base T PHY
2408  *
2409  * Returns PHY access status
2410  **/
2411 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2412 {
2413         u32 status;
2414         u16 reg;
2415         bool lsc;
2416
2417         /* Clear interrupt flags */
2418         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2419
2420         /* Enable link status change alarm */
2421
2422         /* Enable the LASI interrupts on X552 devices to receive notifications
2423          * of the link configurations of the external PHY and correspondingly
2424          * support the configuration of the internal iXFI link, since iXFI does
2425          * not support auto-negotiation. This is not required for X553 devices
2426          * having KR support, which performs auto-negotiations and which is used
2427          * as the internal link to the external PHY. Hence adding a check here
2428          * to avoid enabling LASI interrupts for X553 devices.
2429          */
2430         if (hw->mac.type != ixgbe_mac_x550em_a) {
2431                 status = hw->phy.ops.read_reg(hw,
2432                                             IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2433                                             MDIO_MMD_AN, &reg);
2434                 if (status)
2435                         return status;
2436
2437                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2438
2439                 status = hw->phy.ops.write_reg(hw,
2440                                             IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2441                                             MDIO_MMD_AN, reg);
2442                 if (status)
2443                         return status;
2444         }
2445
2446         /* Enable high temperature failure and global fault alarms */
2447         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2448                                       MDIO_MMD_VEND1,
2449                                       &reg);
2450         if (status)
2451                 return status;
2452
2453         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2454                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2455
2456         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2457                                        MDIO_MMD_VEND1,
2458                                        reg);
2459         if (status)
2460                 return status;
2461
2462         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2463         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2464                                       MDIO_MMD_VEND1,
2465                                       &reg);
2466         if (status)
2467                 return status;
2468
2469         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2470                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2471
2472         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2473                                        MDIO_MMD_VEND1,
2474                                        reg);
2475         if (status)
2476                 return status;
2477
2478         /* Enable chip-wide vendor alarm */
2479         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2480                                       MDIO_MMD_VEND1,
2481                                       &reg);
2482         if (status)
2483                 return status;
2484
2485         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2486
2487         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2488                                        MDIO_MMD_VEND1,
2489                                        reg);
2490
2491         return status;
2492 }
2493
2494 /**
2495  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2496  * @hw: pointer to hardware structure
2497  *
2498  * Handle external Base T PHY interrupt. If high temperature
2499  * failure alarm then return error, else if link status change
2500  * then setup internal/external PHY link
2501  *
2502  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2503  * failure alarm, else return PHY access status.
2504  **/
2505 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2506 {
2507         struct ixgbe_phy_info *phy = &hw->phy;
2508         bool lsc;
2509         u32 status;
2510
2511         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2512         if (status)
2513                 return status;
2514
2515         if (lsc && phy->ops.setup_internal_link)
2516                 return phy->ops.setup_internal_link(hw);
2517
2518         return 0;
2519 }
2520
2521 /**
2522  * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2523  * @hw: pointer to hardware structure
2524  * @speed: link speed
2525  *
2526  * Configures the integrated KR PHY.
2527  **/
2528 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2529                                        ixgbe_link_speed speed)
2530 {
2531         s32 status;
2532         u32 reg_val;
2533
2534         status = hw->mac.ops.read_iosf_sb_reg(hw,
2535                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2536                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2537         if (status)
2538                 return status;
2539
2540         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2541         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2542                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2543
2544         /* Advertise 10G support. */
2545         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2546                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2547
2548         /* Advertise 1G support. */
2549         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2550                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2551
2552         status = hw->mac.ops.write_iosf_sb_reg(hw,
2553                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2554                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2555
2556         if (hw->mac.type == ixgbe_mac_x550em_a) {
2557                 /* Set lane mode  to KR auto negotiation */
2558                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2559                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2560                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2561
2562                 if (status)
2563                         return status;
2564
2565                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2566                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2567                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2568                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2569                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2570
2571                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2572                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2573                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2574         }
2575
2576         return ixgbe_restart_an_internal_phy_x550em(hw);
2577 }
2578
2579 /**
2580  * ixgbe_setup_kr_x550em - Configure the KR PHY
2581  * @hw: pointer to hardware structure
2582  **/
2583 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2584 {
2585         /* leave link alone for 2.5G */
2586         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2587                 return 0;
2588
2589         if (ixgbe_check_reset_blocked(hw))
2590                 return 0;
2591
2592         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2593 }
2594
2595 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2596  *  @hw: address of hardware structure
2597  *  @link_up: address of boolean to indicate link status
2598  *
2599  *  Returns error code if unable to get link status.
2600  **/
2601 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2602 {
2603         u32 ret;
2604         u16 autoneg_status;
2605
2606         *link_up = false;
2607
2608         /* read this twice back to back to indicate current status */
2609         ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2610                                    &autoneg_status);
2611         if (ret)
2612                 return ret;
2613
2614         ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2615                                    &autoneg_status);
2616         if (ret)
2617                 return ret;
2618
2619         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2620
2621         return 0;
2622 }
2623
2624 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2625  *  @hw: point to hardware structure
2626  *
2627  *  Configures the link between the integrated KR PHY and the external X557 PHY
2628  *  The driver will call this function when it gets a link status change
2629  *  interrupt from the X557 PHY. This function configures the link speed
2630  *  between the PHYs to match the link speed of the BASE-T link.
2631  *
2632  * A return of a non-zero value indicates an error, and the base driver should
2633  * not report link up.
2634  **/
2635 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2636 {
2637         ixgbe_link_speed force_speed;
2638         bool link_up;
2639         u32 status;
2640         u16 speed;
2641
2642         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2643                 return IXGBE_ERR_CONFIG;
2644
2645         if (!(hw->mac.type == ixgbe_mac_X550EM_x &&
2646               !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) {
2647                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2648                         IXGBE_LINK_SPEED_1GB_FULL;
2649                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2650         }
2651
2652         /* If link is not up, then there is no setup necessary so return  */
2653         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2654         if (status)
2655                 return status;
2656
2657         if (!link_up)
2658                 return 0;
2659
2660         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2661                                       MDIO_MMD_AN,
2662                                       &speed);
2663         if (status)
2664                 return status;
2665
2666         /* If link is not still up, then no setup is necessary so return */
2667         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2668         if (status)
2669                 return status;
2670
2671         if (!link_up)
2672                 return 0;
2673
2674         /* clear everything but the speed and duplex bits */
2675         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2676
2677         switch (speed) {
2678         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2679                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2680                 break;
2681         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2682                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2683                 break;
2684         default:
2685                 /* Internal PHY does not support anything else */
2686                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2687         }
2688
2689         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2690 }
2691
2692 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2693  *  @hw: pointer to hardware structure
2694  **/
2695 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2696 {
2697         s32 status;
2698
2699         status = ixgbe_reset_phy_generic(hw);
2700
2701         if (status)
2702                 return status;
2703
2704         /* Configure Link Status Alarm and Temperature Threshold interrupts */
2705         return ixgbe_enable_lasi_ext_t_x550em(hw);
2706 }
2707
2708 /**
2709  *  ixgbe_led_on_t_x550em - Turns on the software controllable LEDs.
2710  *  @hw: pointer to hardware structure
2711  *  @led_idx: led number to turn on
2712  **/
2713 static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2714 {
2715         u16 phy_data;
2716
2717         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2718                 return IXGBE_ERR_PARAM;
2719
2720         /* To turn on the LED, set mode to ON. */
2721         hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2722                              MDIO_MMD_VEND1, &phy_data);
2723         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
2724         hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2725                               MDIO_MMD_VEND1, phy_data);
2726
2727         return 0;
2728 }
2729
2730 /**
2731  *  ixgbe_led_off_t_x550em - Turns off the software controllable LEDs.
2732  *  @hw: pointer to hardware structure
2733  *  @led_idx: led number to turn off
2734  **/
2735 static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2736 {
2737         u16 phy_data;
2738
2739         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2740                 return IXGBE_ERR_PARAM;
2741
2742         /* To turn on the LED, set mode to ON. */
2743         hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2744                              MDIO_MMD_VEND1, &phy_data);
2745         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
2746         hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2747                               MDIO_MMD_VEND1, phy_data);
2748
2749         return 0;
2750 }
2751
2752 /**
2753  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
2754  *  @hw: pointer to the HW structure
2755  *  @maj: driver version major number
2756  *  @min: driver version minor number
2757  *  @build: driver version build number
2758  *  @sub: driver version sub build number
2759  *  @len: length of driver_ver string
2760  *  @driver_ver: driver string
2761  *
2762  *  Sends driver version number to firmware through the manageability
2763  *  block.  On success return 0
2764  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
2765  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
2766  **/
2767 static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
2768                                      u8 build, u8 sub, u16 len,
2769                                      const char *driver_ver)
2770 {
2771         struct ixgbe_hic_drv_info2 fw_cmd;
2772         s32 ret_val;
2773         int i;
2774
2775         if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string)))
2776                 return IXGBE_ERR_INVALID_ARGUMENT;
2777
2778         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
2779         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
2780         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
2781         fw_cmd.port_num = (u8)hw->bus.func;
2782         fw_cmd.ver_maj = maj;
2783         fw_cmd.ver_min = min;
2784         fw_cmd.ver_build = build;
2785         fw_cmd.ver_sub = sub;
2786         fw_cmd.hdr.checksum = 0;
2787         memcpy(fw_cmd.driver_string, driver_ver, len);
2788         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
2789                               (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
2790
2791         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
2792                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2793                                                        sizeof(fw_cmd),
2794                                                        IXGBE_HI_COMMAND_TIMEOUT,
2795                                                        true);
2796                 if (ret_val)
2797                         continue;
2798
2799                 if (fw_cmd.hdr.cmd_or_resp.ret_status !=
2800                     FW_CEM_RESP_STATUS_SUCCESS)
2801                         return IXGBE_ERR_HOST_INTERFACE_COMMAND;
2802                 return 0;
2803         }
2804
2805         return ret_val;
2806 }
2807
2808 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
2809  *  @hw: pointer to hardware structure
2810  *  @lcd_speed: pointer to lowest common link speed
2811  *
2812  *  Determine lowest common link speed with link partner.
2813  **/
2814 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
2815                                   ixgbe_link_speed *lcd_speed)
2816 {
2817         u16 an_lp_status;
2818         s32 status;
2819         u16 word = hw->eeprom.ctrl_word_3;
2820
2821         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2822
2823         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2824                                       MDIO_MMD_AN,
2825                                       &an_lp_status);
2826         if (status)
2827                 return status;
2828
2829         /* If link partner advertised 1G, return 1G */
2830         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2831                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2832                 return status;
2833         }
2834
2835         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2836         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2837             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2838                 return status;
2839
2840         /* Link partner not capable of lower speeds, return 10G */
2841         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2842         return status;
2843 }
2844
2845 /**
2846  * ixgbe_setup_fc_x550em - Set up flow control
2847  * @hw: pointer to hardware structure
2848  */
2849 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
2850 {
2851         bool pause, asm_dir;
2852         u32 reg_val;
2853         s32 rc = 0;
2854
2855         /* Validate the requested mode */
2856         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2857                 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2858                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2859         }
2860
2861         /* 10gig parts do not have a word in the EEPROM to determine the
2862          * default flow control setting, so we explicitly set it to full.
2863          */
2864         if (hw->fc.requested_mode == ixgbe_fc_default)
2865                 hw->fc.requested_mode = ixgbe_fc_full;
2866
2867         /* Determine PAUSE and ASM_DIR bits. */
2868         switch (hw->fc.requested_mode) {
2869         case ixgbe_fc_none:
2870                 pause = false;
2871                 asm_dir = false;
2872                 break;
2873         case ixgbe_fc_tx_pause:
2874                 pause = false;
2875                 asm_dir = true;
2876                 break;
2877         case ixgbe_fc_rx_pause:
2878                 /* Rx Flow control is enabled and Tx Flow control is
2879                  * disabled by software override. Since there really
2880                  * isn't a way to advertise that we are capable of RX
2881                  * Pause ONLY, we will advertise that we support both
2882                  * symmetric and asymmetric Rx PAUSE, as such we fall
2883                  * through to the fc_full statement.  Later, we will
2884                  * disable the adapter's ability to send PAUSE frames.
2885                  */
2886                 /* Fallthrough */
2887         case ixgbe_fc_full:
2888                 pause = true;
2889                 asm_dir = true;
2890                 break;
2891         default:
2892                 hw_err(hw, "Flow control param set incorrectly\n");
2893                 return IXGBE_ERR_CONFIG;
2894         }
2895
2896         switch (hw->device_id) {
2897         case IXGBE_DEV_ID_X550EM_X_KR:
2898         case IXGBE_DEV_ID_X550EM_A_KR:
2899         case IXGBE_DEV_ID_X550EM_A_KR_L:
2900                 rc = hw->mac.ops.read_iosf_sb_reg(hw,
2901                                             IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2902                                             IXGBE_SB_IOSF_TARGET_KR_PHY,
2903                                             &reg_val);
2904                 if (rc)
2905                         return rc;
2906
2907                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2908                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2909                 if (pause)
2910                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2911                 if (asm_dir)
2912                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2913                 rc = hw->mac.ops.write_iosf_sb_reg(hw,
2914                                             IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2915                                             IXGBE_SB_IOSF_TARGET_KR_PHY,
2916                                             reg_val);
2917
2918                 /* This device does not fully support AN. */
2919                 hw->fc.disable_fc_autoneg = true;
2920                 break;
2921         case IXGBE_DEV_ID_X550EM_X_XFI:
2922                 hw->fc.disable_fc_autoneg = true;
2923                 break;
2924         default:
2925                 break;
2926         }
2927         return rc;
2928 }
2929
2930 /**
2931  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
2932  *  @hw: pointer to hardware structure
2933  **/
2934 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
2935 {
2936         u32 link_s1, lp_an_page_low, an_cntl_1;
2937         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2938         ixgbe_link_speed speed;
2939         bool link_up;
2940
2941         /* AN should have completed when the cable was plugged in.
2942          * Look for reasons to bail out.  Bail out if:
2943          * - FC autoneg is disabled, or if
2944          * - link is not up.
2945          */
2946         if (hw->fc.disable_fc_autoneg) {
2947                 hw_err(hw, "Flow control autoneg is disabled");
2948                 goto out;
2949         }
2950
2951         hw->mac.ops.check_link(hw, &speed, &link_up, false);
2952         if (!link_up) {
2953                 hw_err(hw, "The link is down");
2954                 goto out;
2955         }
2956
2957         /* Check at auto-negotiation has completed */
2958         status = hw->mac.ops.read_iosf_sb_reg(hw,
2959                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
2960                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
2961
2962         if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
2963                 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2964                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2965                 goto out;
2966         }
2967
2968         /* Read the 10g AN autoc and LP ability registers and resolve
2969          * local flow control settings accordingly
2970          */
2971         status = hw->mac.ops.read_iosf_sb_reg(hw,
2972                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2973                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
2974
2975         if (status) {
2976                 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2977                 goto out;
2978         }
2979
2980         status = hw->mac.ops.read_iosf_sb_reg(hw,
2981                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
2982                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
2983
2984         if (status) {
2985                 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2986                 goto out;
2987         }
2988
2989         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
2990                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
2991                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
2992                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
2993                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
2994
2995 out:
2996         if (!status) {
2997                 hw->fc.fc_was_autonegged = true;
2998         } else {
2999                 hw->fc.fc_was_autonegged = false;
3000                 hw->fc.current_mode = hw->fc.requested_mode;
3001         }
3002 }
3003
3004 /**
3005  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
3006  *  @hw: pointer to hardware structure
3007  **/
3008 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
3009 {
3010         hw->fc.fc_was_autonegged = false;
3011         hw->fc.current_mode = hw->fc.requested_mode;
3012 }
3013
3014 /** ixgbe_enter_lplu_x550em - Transition to low power states
3015  *  @hw: pointer to hardware structure
3016  *
3017  *  Configures Low Power Link Up on transition to low power states
3018  *  (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
3019  *  the X557 PHY immediately prior to entering LPLU.
3020  **/
3021 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3022 {
3023         u16 an_10g_cntl_reg, autoneg_reg, speed;
3024         s32 status;
3025         ixgbe_link_speed lcd_speed;
3026         u32 save_autoneg;
3027         bool link_up;
3028
3029         /* If blocked by MNG FW, then don't restart AN */
3030         if (ixgbe_check_reset_blocked(hw))
3031                 return 0;
3032
3033         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3034         if (status)
3035                 return status;
3036
3037         status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
3038                                      &hw->eeprom.ctrl_word_3);
3039         if (status)
3040                 return status;
3041
3042         /* If link is down, LPLU disabled in NVM, WoL disabled, or
3043          * manageability disabled, then force link down by entering
3044          * low power mode.
3045          */
3046         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3047             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3048                 return ixgbe_set_copper_phy_power(hw, false);
3049
3050         /* Determine LCD */
3051         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3052         if (status)
3053                 return status;
3054
3055         /* If no valid LCD link speed, then force link down and exit. */
3056         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3057                 return ixgbe_set_copper_phy_power(hw, false);
3058
3059         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3060                                       MDIO_MMD_AN,
3061                                       &speed);
3062         if (status)
3063                 return status;
3064
3065         /* If no link now, speed is invalid so take link down */
3066         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3067         if (status)
3068                 return ixgbe_set_copper_phy_power(hw, false);
3069
3070         /* clear everything but the speed bits */
3071         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3072
3073         /* If current speed is already LCD, then exit. */
3074         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3075              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3076             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3077              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3078                 return status;
3079
3080         /* Clear AN completed indication */
3081         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3082                                       MDIO_MMD_AN,
3083                                       &autoneg_reg);
3084         if (status)
3085                 return status;
3086
3087         status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
3088                                       MDIO_MMD_AN,
3089                                       &an_10g_cntl_reg);
3090         if (status)
3091                 return status;
3092
3093         status = hw->phy.ops.read_reg(hw,
3094                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3095                                       MDIO_MMD_AN,
3096                                       &autoneg_reg);
3097         if (status)
3098                 return status;
3099
3100         save_autoneg = hw->phy.autoneg_advertised;
3101
3102         /* Setup link at least common link speed */
3103         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3104
3105         /* restore autoneg from before setting lplu speed */
3106         hw->phy.autoneg_advertised = save_autoneg;
3107
3108         return status;
3109 }
3110
3111 /**
3112  * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
3113  * @hw: pointer to hardware structure
3114  */
3115 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
3116 {
3117         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3118         s32 rc;
3119
3120         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
3121                 return 0;
3122
3123         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
3124         if (rc)
3125                 return rc;
3126         memset(store, 0, sizeof(store));
3127
3128         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
3129         if (rc)
3130                 return rc;
3131
3132         return ixgbe_setup_fw_link(hw);
3133 }
3134
3135 /**
3136  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
3137  * @hw: pointer to hardware structure
3138  */
3139 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
3140 {
3141         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3142         s32 rc;
3143
3144         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
3145         if (rc)
3146                 return rc;
3147
3148         if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
3149                 ixgbe_shutdown_fw_phy(hw);
3150                 return IXGBE_ERR_OVERTEMP;
3151         }
3152         return 0;
3153 }
3154
3155 /**
3156  * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
3157  * @hw: pointer to hardware structure
3158  *
3159  * Read NW_MNG_IF_SEL register and save field values.
3160  */
3161 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
3162 {
3163         /* Save NW management interface connected on board. This is used
3164          * to determine internal PHY mode.
3165          */
3166         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3167
3168         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
3169          * PHY address. This register field was has only been used for X552.
3170          */
3171         if (hw->mac.type == ixgbe_mac_x550em_a &&
3172             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
3173                 hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel &
3174                                       IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
3175                                      IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
3176         }
3177 }
3178
3179 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
3180  *  @hw: pointer to hardware structure
3181  *
3182  *  Initialize any function pointers that were not able to be
3183  *  set during init_shared_code because the PHY/SFP type was
3184  *  not known.  Perform the SFP init if necessary.
3185  **/
3186 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
3187 {
3188         struct ixgbe_phy_info *phy = &hw->phy;
3189         s32 ret_val;
3190
3191         hw->mac.ops.set_lan_id(hw);
3192
3193         ixgbe_read_mng_if_sel_x550em(hw);
3194
3195         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
3196                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
3197                 ixgbe_setup_mux_ctl(hw);
3198         }
3199
3200         /* Identify the PHY or SFP module */
3201         ret_val = phy->ops.identify(hw);
3202         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
3203             ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
3204                 return ret_val;
3205
3206         /* Setup function pointers based on detected hardware */
3207         ixgbe_init_mac_link_ops_X550em(hw);
3208         if (phy->sfp_type != ixgbe_sfp_type_unknown)
3209                 phy->ops.reset = NULL;
3210
3211         /* Set functions pointers based on phy type */
3212         switch (hw->phy.type) {
3213         case ixgbe_phy_x550em_kx4:
3214                 phy->ops.setup_link = NULL;
3215                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3216                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3217                 break;
3218         case ixgbe_phy_x550em_kr:
3219                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
3220                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3221                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3222                 break;
3223         case ixgbe_phy_x550em_xfi:
3224                 /* link is managed by HW */
3225                 phy->ops.setup_link = NULL;
3226                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3227                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3228                 break;
3229         case ixgbe_phy_x550em_ext_t:
3230                 /* Save NW management interface connected on board. This is used
3231                  * to determine internal PHY mode
3232                  */
3233                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3234
3235                 /* If internal link mode is XFI, then setup iXFI internal link,
3236                  * else setup KR now.
3237                  */
3238                 phy->ops.setup_internal_link =
3239                                               ixgbe_setup_internal_phy_t_x550em;
3240
3241                 /* setup SW LPLU only for first revision */
3242                 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3243                     !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
3244                       IXGBE_FUSES0_REV_MASK))
3245                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
3246
3247                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
3248                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
3249                 break;
3250         case ixgbe_phy_sgmii:
3251                 phy->ops.setup_link = NULL;
3252                 break;
3253         case ixgbe_phy_fw:
3254                 phy->ops.setup_link = ixgbe_setup_fw_link;
3255                 phy->ops.reset = ixgbe_reset_phy_fw;
3256                 break;
3257         case ixgbe_phy_ext_1g_t:
3258                 phy->ops.setup_link = NULL;
3259                 phy->ops.read_reg = NULL;
3260                 phy->ops.write_reg = NULL;
3261                 phy->ops.reset = NULL;
3262                 break;
3263         default:
3264                 break;
3265         }
3266
3267         return ret_val;
3268 }
3269
3270 /** ixgbe_get_media_type_X550em - Get media type
3271  *  @hw: pointer to hardware structure
3272  *
3273  *  Returns the media type (fiber, copper, backplane)
3274  *
3275  */
3276 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
3277 {
3278         enum ixgbe_media_type media_type;
3279
3280         /* Detect if there is a copper PHY attached. */
3281         switch (hw->device_id) {
3282         case IXGBE_DEV_ID_X550EM_A_SGMII:
3283         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3284                 hw->phy.type = ixgbe_phy_sgmii;
3285                 /* Fallthrough */
3286         case IXGBE_DEV_ID_X550EM_X_KR:
3287         case IXGBE_DEV_ID_X550EM_X_KX4:
3288         case IXGBE_DEV_ID_X550EM_X_XFI:
3289         case IXGBE_DEV_ID_X550EM_A_KR:
3290         case IXGBE_DEV_ID_X550EM_A_KR_L:
3291                 media_type = ixgbe_media_type_backplane;
3292                 break;
3293         case IXGBE_DEV_ID_X550EM_X_SFP:
3294         case IXGBE_DEV_ID_X550EM_A_SFP:
3295         case IXGBE_DEV_ID_X550EM_A_SFP_N:
3296                 media_type = ixgbe_media_type_fiber;
3297                 break;
3298         case IXGBE_DEV_ID_X550EM_X_1G_T:
3299         case IXGBE_DEV_ID_X550EM_X_10G_T:
3300         case IXGBE_DEV_ID_X550EM_A_10G_T:
3301         case IXGBE_DEV_ID_X550EM_A_1G_T:
3302         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3303                 media_type = ixgbe_media_type_copper;
3304                 break;
3305         default:
3306                 media_type = ixgbe_media_type_unknown;
3307                 break;
3308         }
3309         return media_type;
3310 }
3311
3312 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
3313  ** @hw: pointer to hardware structure
3314  **/
3315 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
3316 {
3317         s32 status;
3318         u16 reg;
3319
3320         status = hw->phy.ops.read_reg(hw,
3321                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
3322                                       MDIO_MMD_PMAPMD,
3323                                       &reg);
3324         if (status)
3325                 return status;
3326
3327         /* If PHY FW reset completed bit is set then this is the first
3328          * SW instance after a power on so the PHY FW must be un-stalled.
3329          */
3330         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
3331                 status = hw->phy.ops.read_reg(hw,
3332                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
3333                                         MDIO_MMD_VEND1,
3334                                         &reg);
3335                 if (status)
3336                         return status;
3337
3338                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
3339
3340                 status = hw->phy.ops.write_reg(hw,
3341                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
3342                                         MDIO_MMD_VEND1,
3343                                         reg);
3344                 if (status)
3345                         return status;
3346         }
3347
3348         return status;
3349 }
3350
3351 /**
3352  * ixgbe_set_mdio_speed - Set MDIO clock speed
3353  * @hw: pointer to hardware structure
3354  */
3355 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
3356 {
3357         u32 hlreg0;
3358
3359         switch (hw->device_id) {
3360         case IXGBE_DEV_ID_X550EM_X_10G_T:
3361         case IXGBE_DEV_ID_X550EM_A_SGMII:
3362         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3363         case IXGBE_DEV_ID_X550EM_A_10G_T:
3364         case IXGBE_DEV_ID_X550EM_A_SFP:
3365                 /* Config MDIO clock speed before the first MDIO PHY access */
3366                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3367                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
3368                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3369                 break;
3370         case IXGBE_DEV_ID_X550EM_A_1G_T:
3371         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3372                 /* Select fast MDIO clock speed for these devices */
3373                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3374                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
3375                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3376                 break;
3377         default:
3378                 break;
3379         }
3380 }
3381
3382 /**  ixgbe_reset_hw_X550em - Perform hardware reset
3383  **  @hw: pointer to hardware structure
3384  **
3385  **  Resets the hardware by resetting the transmit and receive units, masks
3386  **  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3387  **  reset.
3388  **/
3389 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
3390 {
3391         ixgbe_link_speed link_speed;
3392         s32 status;
3393         u32 ctrl = 0;
3394         u32 i;
3395         bool link_up = false;
3396         u32 swfw_mask = hw->phy.phy_semaphore_mask;
3397
3398         /* Call adapter stop to disable Tx/Rx and clear interrupts */
3399         status = hw->mac.ops.stop_adapter(hw);
3400         if (status)
3401                 return status;
3402
3403         /* flush pending Tx transactions */
3404         ixgbe_clear_tx_pending(hw);
3405
3406         /* PHY ops must be identified and initialized prior to reset */
3407         status = hw->phy.ops.init(hw);
3408         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED ||
3409             status == IXGBE_ERR_PHY_ADDR_INVALID)
3410                 return status;
3411
3412         /* start the external PHY */
3413         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
3414                 status = ixgbe_init_ext_t_x550em(hw);
3415                 if (status)
3416                         return status;
3417         }
3418
3419         /* Setup SFP module if there is one present. */
3420         if (hw->phy.sfp_setup_needed) {
3421                 status = hw->mac.ops.setup_sfp(hw);
3422                 hw->phy.sfp_setup_needed = false;
3423         }
3424
3425         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
3426                 return status;
3427
3428         /* Reset PHY */
3429         if (!hw->phy.reset_disable && hw->phy.ops.reset)
3430                 hw->phy.ops.reset(hw);
3431
3432 mac_reset_top:
3433         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
3434          * If link reset is used when link is up, it might reset the PHY when
3435          * mng is using it.  If link is down or the flag to force full link
3436          * reset is set, then perform link reset.
3437          */
3438         ctrl = IXGBE_CTRL_LNK_RST;
3439
3440         if (!hw->force_full_reset) {
3441                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3442                 if (link_up)
3443                         ctrl = IXGBE_CTRL_RST;
3444         }
3445
3446         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
3447         if (status) {
3448                 hw_dbg(hw, "semaphore failed with %d", status);
3449                 return IXGBE_ERR_SWFW_SYNC;
3450         }
3451
3452         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
3453         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3454         IXGBE_WRITE_FLUSH(hw);
3455         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3456         usleep_range(1000, 1200);
3457
3458         /* Poll for reset bit to self-clear meaning reset is complete */
3459         for (i = 0; i < 10; i++) {
3460                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3461                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
3462                         break;
3463                 udelay(1);
3464         }
3465
3466         if (ctrl & IXGBE_CTRL_RST_MASK) {
3467                 status = IXGBE_ERR_RESET_FAILED;
3468                 hw_dbg(hw, "Reset polling failed to complete.\n");
3469         }
3470
3471         msleep(50);
3472
3473         /* Double resets are required for recovery from certain error
3474          * clear the multicast table.  Also reset num_rar_entries to 128,
3475          * since we modify this value when programming the SAN MAC address.
3476          */
3477         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3478                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3479                 goto mac_reset_top;
3480         }
3481
3482         /* Store the permanent mac address */
3483         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
3484
3485         /* Store MAC address from RAR0, clear receive address registers, and
3486          * clear the multicast table.  Also reset num_rar_entries to 128,
3487          * since we modify this value when programming the SAN MAC address.
3488          */
3489         hw->mac.num_rar_entries = 128;
3490         hw->mac.ops.init_rx_addrs(hw);
3491
3492         ixgbe_set_mdio_speed(hw);
3493
3494         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
3495                 ixgbe_setup_mux_ctl(hw);
3496
3497         return status;
3498 }
3499
3500 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
3501  *      anti-spoofing
3502  *  @hw:  pointer to hardware structure
3503  *  @enable: enable or disable switch for Ethertype anti-spoofing
3504  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
3505  **/
3506 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
3507                                                    bool enable, int vf)
3508 {
3509         int vf_target_reg = vf >> 3;
3510         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
3511         u32 pfvfspoof;
3512
3513         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3514         if (enable)
3515                 pfvfspoof |= BIT(vf_target_shift);
3516         else
3517                 pfvfspoof &= ~BIT(vf_target_shift);
3518
3519         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3520 }
3521
3522 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
3523  *  @hw: pointer to hardware structure
3524  *  @enable: enable or disable source address pruning
3525  *  @pool: Rx pool to set source address pruning for
3526  **/
3527 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
3528                                                   bool enable,
3529                                                   unsigned int pool)
3530 {
3531         u64 pfflp;
3532
3533         /* max rx pool is 63 */
3534         if (pool > 63)
3535                 return;
3536
3537         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
3538         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
3539
3540         if (enable)
3541                 pfflp |= (1ULL << pool);
3542         else
3543                 pfflp &= ~(1ULL << pool);
3544
3545         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
3546         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
3547 }
3548
3549 /**
3550  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
3551  *  @hw: pointer to hardware structure
3552  *
3553  *  Called at init time to set up flow control.
3554  **/
3555 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
3556 {
3557         s32 status = 0;
3558         u32 an_cntl = 0;
3559
3560         /* Validate the requested mode */
3561         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3562                 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3563                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3564         }
3565
3566         if (hw->fc.requested_mode == ixgbe_fc_default)
3567                 hw->fc.requested_mode = ixgbe_fc_full;
3568
3569         /* Set up the 1G and 10G flow control advertisement registers so the
3570          * HW will be able to do FC autoneg once the cable is plugged in.  If
3571          * we link at 10G, the 1G advertisement is harmless and vice versa.
3572          */
3573         status = hw->mac.ops.read_iosf_sb_reg(hw,
3574                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3575                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
3576
3577         if (status) {
3578                 hw_dbg(hw, "Auto-Negotiation did not complete\n");
3579                 return status;
3580         }
3581
3582         /* The possible values of fc.requested_mode are:
3583          * 0: Flow control is completely disabled
3584          * 1: Rx flow control is enabled (we can receive pause frames,
3585          *    but not send pause frames).
3586          * 2: Tx flow control is enabled (we can send pause frames but
3587          *    we do not support receiving pause frames).
3588          * 3: Both Rx and Tx flow control (symmetric) are enabled.
3589          * other: Invalid.
3590          */
3591         switch (hw->fc.requested_mode) {
3592         case ixgbe_fc_none:
3593                 /* Flow control completely disabled by software override. */
3594                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3595                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3596                 break;
3597         case ixgbe_fc_tx_pause:
3598                 /* Tx Flow control is enabled, and Rx Flow control is
3599                  * disabled by software override.
3600                  */
3601                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3602                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3603                 break;
3604         case ixgbe_fc_rx_pause:
3605                 /* Rx Flow control is enabled and Tx Flow control is
3606                  * disabled by software override. Since there really
3607                  * isn't a way to advertise that we are capable of RX
3608                  * Pause ONLY, we will advertise that we support both
3609                  * symmetric and asymmetric Rx PAUSE, as such we fall
3610                  * through to the fc_full statement.  Later, we will
3611                  * disable the adapter's ability to send PAUSE frames.
3612                  */
3613         case ixgbe_fc_full:
3614                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3615                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3616                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3617                 break;
3618         default:
3619                 hw_err(hw, "Flow control param set incorrectly\n");
3620                 return IXGBE_ERR_CONFIG;
3621         }
3622
3623         status = hw->mac.ops.write_iosf_sb_reg(hw,
3624                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3625                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
3626
3627         /* Restart auto-negotiation. */
3628         status = ixgbe_restart_an_internal_phy_x550em(hw);
3629
3630         return status;
3631 }
3632
3633 /**
3634  * ixgbe_set_mux - Set mux for port 1 access with CS4227
3635  * @hw: pointer to hardware structure
3636  * @state: set mux if 1, clear if 0
3637  */
3638 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3639 {
3640         u32 esdp;
3641
3642         if (!hw->bus.lan_id)
3643                 return;
3644         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3645         if (state)
3646                 esdp |= IXGBE_ESDP_SDP1;
3647         else
3648                 esdp &= ~IXGBE_ESDP_SDP1;
3649         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3650         IXGBE_WRITE_FLUSH(hw);
3651 }
3652
3653 /**
3654  * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3655  * @hw: pointer to hardware structure
3656  * @mask: Mask to specify which semaphore to acquire
3657  *
3658  * Acquires the SWFW semaphore and sets the I2C MUX
3659  */
3660 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3661 {
3662         s32 status;
3663
3664         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3665         if (status)
3666                 return status;
3667
3668         if (mask & IXGBE_GSSR_I2C_MASK)
3669                 ixgbe_set_mux(hw, 1);
3670
3671         return 0;
3672 }
3673
3674 /**
3675  * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3676  * @hw: pointer to hardware structure
3677  * @mask: Mask to specify which semaphore to release
3678  *
3679  * Releases the SWFW semaphore and sets the I2C MUX
3680  */
3681 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3682 {
3683         if (mask & IXGBE_GSSR_I2C_MASK)
3684                 ixgbe_set_mux(hw, 0);
3685
3686         ixgbe_release_swfw_sync_X540(hw, mask);
3687 }
3688
3689 /**
3690  * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
3691  * @hw: pointer to hardware structure
3692  * @mask: Mask to specify which semaphore to acquire
3693  *
3694  * Acquires the SWFW semaphore and get the shared PHY token as needed
3695  */
3696 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3697 {
3698         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3699         int retries = FW_PHY_TOKEN_RETRIES;
3700         s32 status;
3701
3702         while (--retries) {
3703                 status = 0;
3704                 if (hmask)
3705                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3706                 if (status)
3707                         return status;
3708                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3709                         return 0;
3710
3711                 status = ixgbe_get_phy_token(hw);
3712                 if (!status)
3713                         return 0;
3714                 if (hmask)
3715                         ixgbe_release_swfw_sync_X540(hw, hmask);
3716                 if (status != IXGBE_ERR_TOKEN_RETRY)
3717                         return status;
3718                 msleep(FW_PHY_TOKEN_DELAY);
3719         }
3720
3721         return status;
3722 }
3723
3724 /**
3725  * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
3726  * @hw: pointer to hardware structure
3727  * @mask: Mask to specify which semaphore to release
3728  *
3729  * Release the SWFW semaphore and puts the shared PHY token as needed
3730  */
3731 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3732 {
3733         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3734
3735         if (mask & IXGBE_GSSR_TOKEN_SM)
3736                 ixgbe_put_phy_token(hw);
3737
3738         if (hmask)
3739                 ixgbe_release_swfw_sync_X540(hw, hmask);
3740 }
3741
3742 /**
3743  * ixgbe_read_phy_reg_x550a - Reads specified PHY register
3744  * @hw: pointer to hardware structure
3745  * @reg_addr: 32 bit address of PHY register to read
3746  * @device_type: 5 bit device type
3747  * @phy_data: Pointer to read data from PHY register
3748  *
3749  * Reads a value from a specified PHY register using the SWFW lock and PHY
3750  * Token. The PHY Token is needed since the MDIO is shared between to MAC
3751  * instances.
3752  */
3753 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3754                                     u32 device_type, u16 *phy_data)
3755 {
3756         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3757         s32 status;
3758
3759         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3760                 return IXGBE_ERR_SWFW_SYNC;
3761
3762         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
3763
3764         hw->mac.ops.release_swfw_sync(hw, mask);
3765
3766         return status;
3767 }
3768
3769 /**
3770  * ixgbe_write_phy_reg_x550a - Writes specified PHY register
3771  * @hw: pointer to hardware structure
3772  * @reg_addr: 32 bit PHY register to write
3773  * @device_type: 5 bit device type
3774  * @phy_data: Data to write to the PHY register
3775  *
3776  * Writes a value to specified PHY register using the SWFW lock and PHY Token.
3777  * The PHY Token is needed since the MDIO is shared between to MAC instances.
3778  */
3779 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3780                                      u32 device_type, u16 phy_data)
3781 {
3782         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3783         s32 status;
3784
3785         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3786                 return IXGBE_ERR_SWFW_SYNC;
3787
3788         status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
3789         hw->mac.ops.release_swfw_sync(hw, mask);
3790
3791         return status;
3792 }
3793
3794 #define X550_COMMON_MAC \
3795         .init_hw                        = &ixgbe_init_hw_generic, \
3796         .start_hw                       = &ixgbe_start_hw_X540, \
3797         .clear_hw_cntrs                 = &ixgbe_clear_hw_cntrs_generic, \
3798         .enable_rx_dma                  = &ixgbe_enable_rx_dma_generic, \
3799         .get_mac_addr                   = &ixgbe_get_mac_addr_generic, \
3800         .get_device_caps                = &ixgbe_get_device_caps_generic, \
3801         .stop_adapter                   = &ixgbe_stop_adapter_generic, \
3802         .set_lan_id                     = &ixgbe_set_lan_id_multi_port_pcie, \
3803         .read_analog_reg8               = NULL, \
3804         .write_analog_reg8              = NULL, \
3805         .set_rxpba                      = &ixgbe_set_rxpba_generic, \
3806         .check_link                     = &ixgbe_check_mac_link_generic, \
3807         .blink_led_start                = &ixgbe_blink_led_start_X540, \
3808         .blink_led_stop                 = &ixgbe_blink_led_stop_X540, \
3809         .set_rar                        = &ixgbe_set_rar_generic, \
3810         .clear_rar                      = &ixgbe_clear_rar_generic, \
3811         .set_vmdq                       = &ixgbe_set_vmdq_generic, \
3812         .set_vmdq_san_mac               = &ixgbe_set_vmdq_san_mac_generic, \
3813         .clear_vmdq                     = &ixgbe_clear_vmdq_generic, \
3814         .init_rx_addrs                  = &ixgbe_init_rx_addrs_generic, \
3815         .update_mc_addr_list            = &ixgbe_update_mc_addr_list_generic, \
3816         .enable_mc                      = &ixgbe_enable_mc_generic, \
3817         .disable_mc                     = &ixgbe_disable_mc_generic, \
3818         .clear_vfta                     = &ixgbe_clear_vfta_generic, \
3819         .set_vfta                       = &ixgbe_set_vfta_generic, \
3820         .fc_enable                      = &ixgbe_fc_enable_generic, \
3821         .set_fw_drv_ver                 = &ixgbe_set_fw_drv_ver_x550, \
3822         .init_uta_tables                = &ixgbe_init_uta_tables_generic, \
3823         .set_mac_anti_spoofing          = &ixgbe_set_mac_anti_spoofing, \
3824         .set_vlan_anti_spoofing         = &ixgbe_set_vlan_anti_spoofing, \
3825         .set_source_address_pruning     = \
3826                                 &ixgbe_set_source_address_pruning_X550, \
3827         .set_ethertype_anti_spoofing    = \
3828                                 &ixgbe_set_ethertype_anti_spoofing_X550, \
3829         .disable_rx_buff                = &ixgbe_disable_rx_buff_generic, \
3830         .enable_rx_buff                 = &ixgbe_enable_rx_buff_generic, \
3831         .get_thermal_sensor_data        = NULL, \
3832         .init_thermal_sensor_thresh     = NULL, \
3833         .fw_recovery_mode               = &ixgbe_fw_recovery_mode_X550, \
3834         .enable_rx                      = &ixgbe_enable_rx_generic, \
3835         .disable_rx                     = &ixgbe_disable_rx_x550, \
3836
3837 static const struct ixgbe_mac_operations mac_ops_X550 = {
3838         X550_COMMON_MAC
3839         .led_on                 = ixgbe_led_on_generic,
3840         .led_off                = ixgbe_led_off_generic,
3841         .init_led_link_act      = ixgbe_init_led_link_act_generic,
3842         .reset_hw               = &ixgbe_reset_hw_X540,
3843         .get_media_type         = &ixgbe_get_media_type_X540,
3844         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
3845         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
3846         .setup_link             = &ixgbe_setup_mac_link_X540,
3847         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
3848         .get_bus_info           = &ixgbe_get_bus_info_generic,
3849         .setup_sfp              = NULL,
3850         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X540,
3851         .release_swfw_sync      = &ixgbe_release_swfw_sync_X540,
3852         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
3853         .prot_autoc_read        = prot_autoc_read_generic,
3854         .prot_autoc_write       = prot_autoc_write_generic,
3855         .setup_fc               = ixgbe_setup_fc_generic,
3856         .fc_autoneg             = ixgbe_fc_autoneg,
3857 };
3858
3859 static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
3860         X550_COMMON_MAC
3861         .led_on                 = ixgbe_led_on_t_x550em,
3862         .led_off                = ixgbe_led_off_t_x550em,
3863         .init_led_link_act      = ixgbe_init_led_link_act_generic,
3864         .reset_hw               = &ixgbe_reset_hw_X550em,
3865         .get_media_type         = &ixgbe_get_media_type_X550em,
3866         .get_san_mac_addr       = NULL,
3867         .get_wwn_prefix         = NULL,
3868         .setup_link             = &ixgbe_setup_mac_link_X540,
3869         .get_link_capabilities  = &ixgbe_get_link_capabilities_X550em,
3870         .get_bus_info           = &ixgbe_get_bus_info_X550em,
3871         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
3872         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X550em,
3873         .release_swfw_sync      = &ixgbe_release_swfw_sync_X550em,
3874         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
3875         .setup_fc               = NULL, /* defined later */
3876         .fc_autoneg             = ixgbe_fc_autoneg,
3877         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550,
3878         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550,
3879 };
3880
3881 static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = {
3882         X550_COMMON_MAC
3883         .led_on                 = NULL,
3884         .led_off                = NULL,
3885         .init_led_link_act      = NULL,
3886         .reset_hw               = &ixgbe_reset_hw_X550em,
3887         .get_media_type         = &ixgbe_get_media_type_X550em,
3888         .get_san_mac_addr       = NULL,
3889         .get_wwn_prefix         = NULL,
3890         .setup_link             = &ixgbe_setup_mac_link_X540,
3891         .get_link_capabilities  = &ixgbe_get_link_capabilities_X550em,
3892         .get_bus_info           = &ixgbe_get_bus_info_X550em,
3893         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
3894         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X550em,
3895         .release_swfw_sync      = &ixgbe_release_swfw_sync_X550em,
3896         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
3897         .setup_fc               = NULL,
3898         .fc_autoneg             = ixgbe_fc_autoneg,
3899         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550,
3900         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550,
3901 };
3902
3903 static const struct ixgbe_mac_operations mac_ops_x550em_a = {
3904         X550_COMMON_MAC
3905         .led_on                 = ixgbe_led_on_t_x550em,
3906         .led_off                = ixgbe_led_off_t_x550em,
3907         .init_led_link_act      = ixgbe_init_led_link_act_generic,
3908         .reset_hw               = ixgbe_reset_hw_X550em,
3909         .get_media_type         = ixgbe_get_media_type_X550em,
3910         .get_san_mac_addr       = NULL,
3911         .get_wwn_prefix         = NULL,
3912         .setup_link             = &ixgbe_setup_mac_link_X540,
3913         .get_link_capabilities  = ixgbe_get_link_capabilities_X550em,
3914         .get_bus_info           = ixgbe_get_bus_info_X550em,
3915         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
3916         .acquire_swfw_sync      = ixgbe_acquire_swfw_sync_x550em_a,
3917         .release_swfw_sync      = ixgbe_release_swfw_sync_x550em_a,
3918         .setup_fc               = ixgbe_setup_fc_x550em,
3919         .fc_autoneg             = ixgbe_fc_autoneg,
3920         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550a,
3921         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550a,
3922 };
3923
3924 static const struct ixgbe_mac_operations mac_ops_x550em_a_fw = {
3925         X550_COMMON_MAC
3926         .led_on                 = ixgbe_led_on_generic,
3927         .led_off                = ixgbe_led_off_generic,
3928         .init_led_link_act      = ixgbe_init_led_link_act_generic,
3929         .reset_hw               = ixgbe_reset_hw_X550em,
3930         .get_media_type         = ixgbe_get_media_type_X550em,
3931         .get_san_mac_addr       = NULL,
3932         .get_wwn_prefix         = NULL,
3933         .setup_link             = NULL, /* defined later */
3934         .get_link_capabilities  = ixgbe_get_link_capabilities_X550em,
3935         .get_bus_info           = ixgbe_get_bus_info_X550em,
3936         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
3937         .acquire_swfw_sync      = ixgbe_acquire_swfw_sync_x550em_a,
3938         .release_swfw_sync      = ixgbe_release_swfw_sync_x550em_a,
3939         .setup_fc               = ixgbe_setup_fc_x550em,
3940         .fc_autoneg             = ixgbe_fc_autoneg,
3941         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550a,
3942         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550a,
3943 };
3944
3945 #define X550_COMMON_EEP \
3946         .read                   = &ixgbe_read_ee_hostif_X550, \
3947         .read_buffer            = &ixgbe_read_ee_hostif_buffer_X550, \
3948         .write                  = &ixgbe_write_ee_hostif_X550, \
3949         .write_buffer           = &ixgbe_write_ee_hostif_buffer_X550, \
3950         .validate_checksum      = &ixgbe_validate_eeprom_checksum_X550, \
3951         .update_checksum        = &ixgbe_update_eeprom_checksum_X550, \
3952         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X550, \
3953
3954 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
3955         X550_COMMON_EEP
3956         .init_params            = &ixgbe_init_eeprom_params_X550,
3957 };
3958
3959 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
3960         X550_COMMON_EEP
3961         .init_params            = &ixgbe_init_eeprom_params_X540,
3962 };
3963
3964 #define X550_COMMON_PHY \
3965         .identify_sfp           = &ixgbe_identify_module_generic, \
3966         .reset                  = NULL, \
3967         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic, \
3968         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic, \
3969         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic, \
3970         .read_i2c_sff8472       = &ixgbe_read_i2c_sff8472_generic, \
3971         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic, \
3972         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic, \
3973         .setup_link             = &ixgbe_setup_phy_link_generic, \
3974         .set_phy_power          = NULL,
3975
3976 static const struct ixgbe_phy_operations phy_ops_X550 = {
3977         X550_COMMON_PHY
3978         .check_overtemp         = &ixgbe_tn_check_overtemp,
3979         .init                   = NULL,
3980         .identify               = &ixgbe_identify_phy_generic,
3981         .read_reg               = &ixgbe_read_phy_reg_generic,
3982         .write_reg              = &ixgbe_write_phy_reg_generic,
3983 };
3984
3985 static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
3986         X550_COMMON_PHY
3987         .check_overtemp         = &ixgbe_tn_check_overtemp,
3988         .init                   = &ixgbe_init_phy_ops_X550em,
3989         .identify               = &ixgbe_identify_phy_x550em,
3990         .read_reg               = &ixgbe_read_phy_reg_generic,
3991         .write_reg              = &ixgbe_write_phy_reg_generic,
3992 };
3993
3994 static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = {
3995         X550_COMMON_PHY
3996         .check_overtemp         = NULL,
3997         .init                   = ixgbe_init_phy_ops_X550em,
3998         .identify               = ixgbe_identify_phy_x550em,
3999         .read_reg               = NULL,
4000         .write_reg              = NULL,
4001         .read_reg_mdi           = NULL,
4002         .write_reg_mdi          = NULL,
4003 };
4004
4005 static const struct ixgbe_phy_operations phy_ops_x550em_a = {
4006         X550_COMMON_PHY
4007         .check_overtemp         = &ixgbe_tn_check_overtemp,
4008         .init                   = &ixgbe_init_phy_ops_X550em,
4009         .identify               = &ixgbe_identify_phy_x550em,
4010         .read_reg               = &ixgbe_read_phy_reg_x550a,
4011         .write_reg              = &ixgbe_write_phy_reg_x550a,
4012         .read_reg_mdi           = &ixgbe_read_phy_reg_mdi,
4013         .write_reg_mdi          = &ixgbe_write_phy_reg_mdi,
4014 };
4015
4016 static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = {
4017         X550_COMMON_PHY
4018         .check_overtemp         = ixgbe_check_overtemp_fw,
4019         .init                   = ixgbe_init_phy_ops_X550em,
4020         .identify               = ixgbe_identify_phy_fw,
4021         .read_reg               = NULL,
4022         .write_reg              = NULL,
4023         .read_reg_mdi           = NULL,
4024         .write_reg_mdi          = NULL,
4025 };
4026
4027 static const struct ixgbe_link_operations link_ops_x550em_x = {
4028         .read_link              = &ixgbe_read_i2c_combined_generic,
4029         .read_link_unlocked     = &ixgbe_read_i2c_combined_generic_unlocked,
4030         .write_link             = &ixgbe_write_i2c_combined_generic,
4031         .write_link_unlocked    = &ixgbe_write_i2c_combined_generic_unlocked,
4032 };
4033
4034 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
4035         IXGBE_MVALS_INIT(X550)
4036 };
4037
4038 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
4039         IXGBE_MVALS_INIT(X550EM_x)
4040 };
4041
4042 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = {
4043         IXGBE_MVALS_INIT(X550EM_a)
4044 };
4045
4046 const struct ixgbe_info ixgbe_X550_info = {
4047         .mac                    = ixgbe_mac_X550,
4048         .get_invariants         = &ixgbe_get_invariants_X540,
4049         .mac_ops                = &mac_ops_X550,
4050         .eeprom_ops             = &eeprom_ops_X550,
4051         .phy_ops                = &phy_ops_X550,
4052         .mbx_ops                = &mbx_ops_generic,
4053         .mvals                  = ixgbe_mvals_X550,
4054 };
4055
4056 const struct ixgbe_info ixgbe_X550EM_x_info = {
4057         .mac                    = ixgbe_mac_X550EM_x,
4058         .get_invariants         = &ixgbe_get_invariants_X550_x,
4059         .mac_ops                = &mac_ops_X550EM_x,
4060         .eeprom_ops             = &eeprom_ops_X550EM_x,
4061         .phy_ops                = &phy_ops_X550EM_x,
4062         .mbx_ops                = &mbx_ops_generic,
4063         .mvals                  = ixgbe_mvals_X550EM_x,
4064         .link_ops               = &link_ops_x550em_x,
4065 };
4066
4067 const struct ixgbe_info ixgbe_x550em_x_fw_info = {
4068         .mac                    = ixgbe_mac_X550EM_x,
4069         .get_invariants         = ixgbe_get_invariants_X550_x_fw,
4070         .mac_ops                = &mac_ops_X550EM_x_fw,
4071         .eeprom_ops             = &eeprom_ops_X550EM_x,
4072         .phy_ops                = &phy_ops_x550em_x_fw,
4073         .mbx_ops                = &mbx_ops_generic,
4074         .mvals                  = ixgbe_mvals_X550EM_x,
4075 };
4076
4077 const struct ixgbe_info ixgbe_x550em_a_info = {
4078         .mac                    = ixgbe_mac_x550em_a,
4079         .get_invariants         = &ixgbe_get_invariants_X550_a,
4080         .mac_ops                = &mac_ops_x550em_a,
4081         .eeprom_ops             = &eeprom_ops_X550EM_x,
4082         .phy_ops                = &phy_ops_x550em_a,
4083         .mbx_ops                = &mbx_ops_generic,
4084         .mvals                  = ixgbe_mvals_x550em_a,
4085 };
4086
4087 const struct ixgbe_info ixgbe_x550em_a_fw_info = {
4088         .mac                    = ixgbe_mac_x550em_a,
4089         .get_invariants         = ixgbe_get_invariants_X550_a_fw,
4090         .mac_ops                = &mac_ops_x550em_a_fw,
4091         .eeprom_ops             = &eeprom_ops_X550EM_x,
4092         .phy_ops                = &phy_ops_x550em_a_fw,
4093         .mbx_ops                = &mbx_ops_generic,
4094         .mvals                  = ixgbe_mvals_x550em_a,
4095 };