1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
7 #include <linux/types.h>
8 #include <linux/errno.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/netdevice.h>
12 #include <linux/compiler.h>
13 #include <linux/etherdevice.h>
14 #include <linux/skbuff.h>
15 #include <linux/cpumask.h>
16 #include <linux/rtnetlink.h>
17 #include <linux/if_vlan.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/pci.h>
20 #include <linux/workqueue.h>
21 #include <linux/aer.h>
22 #include <linux/interrupt.h>
23 #include <linux/ethtool.h>
24 #include <linux/timer.h>
25 #include <linux/delay.h>
26 #include <linux/bitmap.h>
27 #include <linux/log2.h>
29 #include <linux/ipv6.h>
30 #include <linux/if_bridge.h>
31 #include <linux/avf/virtchnl.h>
33 #include "ice_devids.h"
36 #include "ice_switch.h"
37 #include "ice_common.h"
38 #include "ice_sched.h"
39 #include "ice_virtchnl_pf.h"
40 #include "ice_sriov.h"
42 extern const char ice_drv_ver[];
44 #define ICE_DFLT_NUM_DESC 128
45 #define ICE_REQ_DESC_MULTIPLE 32
46 #define ICE_MIN_NUM_DESC ICE_REQ_DESC_MULTIPLE
47 #define ICE_MAX_NUM_DESC 8160
48 #define ICE_DFLT_TRAFFIC_CLASS BIT(0)
49 #define ICE_INT_NAME_STR_LEN (IFNAMSIZ + 16)
50 #define ICE_ETHTOOL_FWVER_LEN 32
52 #define ICE_MBXQ_LEN 64
53 #define ICE_MIN_MSIX 2
54 #define ICE_NO_VSI 0xffff
55 #define ICE_MAX_VSI_ALLOC 130
56 #define ICE_MAX_TXQS 2048
57 #define ICE_MAX_RXQS 2048
58 #define ICE_VSI_MAP_CONTIG 0
59 #define ICE_VSI_MAP_SCATTER 1
60 #define ICE_MAX_SCATTER_TXQS 16
61 #define ICE_MAX_SCATTER_RXQS 16
62 #define ICE_Q_WAIT_RETRY_LIMIT 10
63 #define ICE_Q_WAIT_MAX_RETRY (5 * ICE_Q_WAIT_RETRY_LIMIT)
64 #define ICE_MAX_LG_RSS_QS 256
65 #define ICE_MAX_SMALL_RSS_QS 8
66 #define ICE_RES_VALID_BIT 0x8000
67 #define ICE_RES_MISC_VEC_ID (ICE_RES_VALID_BIT - 1)
68 #define ICE_INVAL_Q_INDEX 0xffff
69 #define ICE_INVAL_VFID 256
70 #define ICE_MAX_VF_COUNT 256
71 #define ICE_MAX_QS_PER_VF 256
72 #define ICE_MIN_QS_PER_VF 1
73 #define ICE_DFLT_QS_PER_VF 4
74 #define ICE_MAX_BASE_QS_PER_VF 16
75 #define ICE_MAX_INTR_PER_VF 65
76 #define ICE_MIN_INTR_PER_VF (ICE_MIN_QS_PER_VF + 1)
77 #define ICE_DFLT_INTR_PER_VF (ICE_DFLT_QS_PER_VF + 1)
79 #define ICE_MAX_RESET_WAIT 20
81 #define ICE_VSIQF_HKEY_ARRAY_SIZE ((VSIQF_HKEY_MAX_INDEX + 1) * 4)
83 #define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
85 #define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - \
86 ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
88 #define ICE_UP_TABLE_TRANSLATE(val, i) \
89 (((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \
90 ICE_AQ_VSI_UP_TABLE_UP##i##_M)
92 #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i]))
93 #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i]))
94 #define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i]))
96 /* Macro for each VSI in a PF */
97 #define ice_for_each_vsi(pf, i) \
98 for ((i) = 0; (i) < (pf)->num_alloc_vsi; (i)++)
100 /* Macros for each tx/rx ring in a VSI */
101 #define ice_for_each_txq(vsi, i) \
102 for ((i) = 0; (i) < (vsi)->num_txq; (i)++)
104 #define ice_for_each_rxq(vsi, i) \
105 for ((i) = 0; (i) < (vsi)->num_rxq; (i)++)
107 /* Macros for each allocated tx/rx ring whether used or not in a VSI */
108 #define ice_for_each_alloc_txq(vsi, i) \
109 for ((i) = 0; (i) < (vsi)->alloc_txq; (i)++)
111 #define ice_for_each_alloc_rxq(vsi, i) \
112 for ((i) = 0; (i) < (vsi)->alloc_rxq; (i)++)
120 u8 numtc; /* Total number of enabled TCs */
121 u8 ena_tc; /* TX map */
122 struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS];
125 struct ice_res_tracker {
133 u16 sw_id; /* switch ID for this switch */
134 u16 bridge_mode; /* VEB/VEPA/Port Virtualizer */
140 __ICE_PREPARED_FOR_RESET, /* set by driver when prepared */
141 __ICE_RESET_OICR_RECV, /* set by driver after rcv reset OICR */
142 __ICE_PFR_REQ, /* set by driver and peers */
143 __ICE_CORER_REQ, /* set by driver and peers */
144 __ICE_GLOBR_REQ, /* set by driver and peers */
145 __ICE_CORER_RECV, /* set by OICR handler */
146 __ICE_GLOBR_RECV, /* set by OICR handler */
147 __ICE_EMPR_RECV, /* set by OICR handler */
148 __ICE_SUSPENDED, /* set on module remove path */
149 __ICE_RESET_FAILED, /* set by reset/rebuild */
150 /* When checking for the PF to be in a nominal operating state, the
151 * bits that are grouped at the beginning of the list need to be
152 * checked. Bits occurring before __ICE_STATE_NOMINAL_CHECK_BITS will
153 * be checked. If you need to add a bit into consideration for nominal
154 * operating state, it must be added before
155 * __ICE_STATE_NOMINAL_CHECK_BITS. Do not move this entry's position
156 * without appropriate consideration.
158 __ICE_STATE_NOMINAL_CHECK_BITS,
159 __ICE_ADMINQ_EVENT_PENDING,
160 __ICE_MAILBOXQ_EVENT_PENDING,
161 __ICE_MDD_EVENT_PENDING,
162 __ICE_VFLR_EVENT_PENDING,
163 __ICE_FLTR_OVERFLOW_PROMISC,
168 __ICE_STATE_NBITS /* must be last */
172 ICE_VSI_FLAG_UMAC_FLTR_CHANGED,
173 ICE_VSI_FLAG_MMAC_FLTR_CHANGED,
174 ICE_VSI_FLAG_VLAN_FLTR_CHANGED,
175 ICE_VSI_FLAG_PROMISC_CHANGED,
176 ICE_VSI_FLAG_NBITS /* must be last */
179 /* struct that defines a VSI, associated with a dev */
181 struct net_device *netdev;
182 struct ice_sw *vsw; /* switch this VSI is on */
183 struct ice_pf *back; /* back pointer to PF */
184 struct ice_port_info *port_info; /* back pointer to port_info */
185 struct ice_ring **rx_rings; /* rx ring array */
186 struct ice_ring **tx_rings; /* tx ring array */
187 struct ice_q_vector **q_vectors; /* q_vector array */
189 irqreturn_t (*irq_handler)(int irq, void *data);
192 DECLARE_BITMAP(state, __ICE_STATE_NBITS);
193 DECLARE_BITMAP(flags, ICE_VSI_FLAG_NBITS);
194 unsigned int current_netdev_flags;
200 int sw_base_vector; /* Irq base for OS reserved vectors */
201 int hw_base_vector; /* HW (absolute) index of a vector */
202 enum ice_vsi_type type;
203 u16 vsi_num; /* HW (absolute) index of this VSI */
204 u16 idx; /* software index in pf->vsi[] */
206 /* Interrupt thresholds */
209 s16 vf_id; /* VF ID for SR-IOV VSIs */
212 u16 rss_table_size; /* HW RSS table size */
213 u16 rss_size; /* Allocated RSS queues */
214 u8 *rss_hkey_user; /* User configured hash keys */
215 u8 *rss_lut_user; /* User configured lookup table entries */
216 u8 rss_lut_type; /* used to configure Get/Set RSS LUT AQ call */
221 struct ice_aqc_vsi_props info; /* VSI properties */
224 struct rtnl_link_stats64 net_stats;
225 struct ice_eth_stats eth_stats;
226 struct ice_eth_stats eth_stats_prev;
228 struct list_head tmp_sync_list; /* MAC filters to be synced */
229 struct list_head tmp_unsync_list; /* MAC filters to be unsynced */
232 u8 current_isup; /* Sync 'link up' logging */
233 u8 stat_offsets_loaded;
235 /* queue information */
236 u8 tx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
237 u8 rx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
238 u16 txq_map[ICE_MAX_TXQS]; /* index in pf->avail_txqs */
239 u16 rxq_map[ICE_MAX_RXQS]; /* index in pf->avail_rxqs */
240 u16 alloc_txq; /* Allocated Tx queues */
241 u16 num_txq; /* Used Tx queues */
242 u16 alloc_rxq; /* Allocated Rx queues */
243 u16 num_rxq; /* Used Rx queues */
245 struct ice_tc_cfg tc_cfg;
246 } ____cacheline_internodealigned_in_smp;
248 /* struct that defines an interrupt vector */
249 struct ice_q_vector {
251 cpumask_t affinity_mask;
252 struct napi_struct napi;
253 struct ice_ring_container rx;
254 struct ice_ring_container tx;
255 struct irq_affinity_notify affinity_notify;
256 u16 v_idx; /* index in the vsi->q_vector array. */
257 u8 num_ring_tx; /* total number of tx rings in vector */
258 u8 num_ring_rx; /* total number of rx rings in vector */
259 char name[ICE_INT_NAME_STR_LEN];
260 /* in usecs, need to use ice_intrl_to_usecs_reg() before writing this
261 * value to the device
264 } ____cacheline_internodealigned_in_smp;
271 ICE_FLAG_SRIOV_CAPABLE,
272 ICE_PF_FLAGS_NBITS /* must be last */
276 struct pci_dev *pdev;
278 /* OS reserved IRQ details */
279 struct msix_entry *msix_entries;
280 struct ice_res_tracker *sw_irq_tracker;
282 /* HW reserved Interrupts for this PF */
283 struct ice_res_tracker *hw_irq_tracker;
285 struct ice_vsi **vsi; /* VSIs created by the driver */
286 struct ice_sw *first_sw; /* first switch created by firmware */
287 /* Virtchnl/SR-IOV config info */
289 int num_alloc_vfs; /* actual number of VFs allocated */
290 u16 num_vfs_supported; /* num VFs supported for this PF */
291 u16 num_vf_qps; /* num queue pairs per VF */
292 u16 num_vf_msix; /* num vectors per VF */
293 DECLARE_BITMAP(state, __ICE_STATE_NBITS);
294 DECLARE_BITMAP(avail_txqs, ICE_MAX_TXQS);
295 DECLARE_BITMAP(avail_rxqs, ICE_MAX_RXQS);
296 DECLARE_BITMAP(flags, ICE_PF_FLAGS_NBITS);
297 unsigned long serv_tmr_period;
298 unsigned long serv_tmr_prev;
299 struct timer_list serv_tmr;
300 struct work_struct serv_task;
301 struct mutex avail_q_mutex; /* protects access to avail_[rx|tx]qs */
302 struct mutex sw_mutex; /* lock for protecting VSI alloc flow */
304 u32 hw_csum_rx_error;
305 u32 sw_oicr_idx; /* Other interrupt cause SW vector index */
306 u32 num_avail_sw_msix; /* remaining MSIX SW vectors left unclaimed */
307 u32 hw_oicr_idx; /* Other interrupt cause vector HW index */
308 u32 num_avail_hw_msix; /* remaining HW MSIX vectors left unclaimed */
309 u32 num_lan_msix; /* Total MSIX vectors for base driver */
310 u16 num_lan_tx; /* num lan tx queues setup */
311 u16 num_lan_rx; /* num lan rx queues setup */
312 u16 q_left_tx; /* remaining num tx queues left unclaimed */
313 u16 q_left_rx; /* remaining num rx queues left unclaimed */
314 u16 next_vsi; /* Next free slot in pf->vsi[] - 0-based! */
316 u16 corer_count; /* Core reset count */
317 u16 globr_count; /* Global reset count */
318 u16 empr_count; /* EMP reset count */
319 u16 pfr_count; /* PF reset count */
321 struct ice_hw_port_stats stats;
322 struct ice_hw_port_stats stats_prev;
324 u8 stat_prev_loaded; /* has previous stats been loaded */
325 u32 tx_timeout_count;
326 unsigned long tx_timeout_last_recovery;
327 u32 tx_timeout_recovery_level;
328 char int_name[ICE_INT_NAME_STR_LEN];
331 struct ice_netdev_priv {
336 * ice_irq_dynamic_ena - Enable default interrupt generation settings
337 * @hw: pointer to hw struct
338 * @vsi: pointer to vsi struct, can be NULL
339 * @q_vector: pointer to q_vector, can be NULL
341 static inline void ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi,
342 struct ice_q_vector *q_vector)
344 u32 vector = (vsi && q_vector) ? vsi->hw_base_vector + q_vector->v_idx :
345 ((struct ice_pf *)hw->back)->hw_oicr_idx;
346 int itr = ICE_ITR_NONE;
349 /* clear the PBA here, as this function is meant to clean out all
350 * previous interrupts and enable the interrupt
352 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
353 (itr << GLINT_DYN_CTL_ITR_INDX_S);
355 if (test_bit(__ICE_DOWN, vsi->state))
357 wr32(hw, GLINT_DYN_CTL(vector), val);
360 static inline void ice_vsi_set_tc_cfg(struct ice_vsi *vsi)
362 vsi->tc_cfg.ena_tc = ICE_DFLT_TRAFFIC_CLASS;
363 vsi->tc_cfg.numtc = 1;
366 void ice_set_ethtool_ops(struct net_device *netdev);
367 int ice_up(struct ice_vsi *vsi);
368 int ice_down(struct ice_vsi *vsi);
369 int ice_set_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
370 int ice_get_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
371 void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size);
372 void ice_print_link_msg(struct ice_vsi *vsi, bool isup);
373 void ice_napi_del(struct ice_vsi *vsi);