drivers/net/ethernet/intel/i40evf/i40e_type.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
   3
   4 #ifndef _I40E_TYPE_H_
   5 #define _I40E_TYPE_H_
   6
   7 #include "i40e_status.h"
   8 #include "i40e_osdep.h"
   9 #include "i40e_register.h"
  10 #include "i40e_adminq.h"
  11 #include "i40e_hmc.h"
  12 #include "i40e_lan_hmc.h"
  13 #include "i40e_devids.h"
  14
  15 /* I40E_MASK is a macro used on 32 bit registers */
  16 #define I40E_MASK(mask, shift) ((u32)(mask) << (shift))
  17
  18 #define I40E_MAX_VSI_QP                 16
  19 #define I40E_MAX_VF_VSI                 3
  20 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  21 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  22
  23 /* Max default timeout in ms, */
  24 #define I40E_MAX_NVM_TIMEOUT            18000
  25
  26 /* Max timeout in ms for the phy to respond */
  27 #define I40E_MAX_PHY_TIMEOUT            500
  28
  29 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  30 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  31
  32 /* forward declaration */
  33 struct i40e_hw;
  34 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  35
  36 /* Data type manipulation macros. */
  37
  38 #define I40E_DESC_UNUSED(R)     \
  39         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  40         (R)->next_to_clean - (R)->next_to_use - 1)
  41
  42 /* bitfields for Tx queue mapping in QTX_CTL */
  43 #define I40E_QTX_CTL_VF_QUEUE   0x0
  44 #define I40E_QTX_CTL_VM_QUEUE   0x1
  45 #define I40E_QTX_CTL_PF_QUEUE   0x2
  46
  47 /* debug masks - set these bits in hw->debug_mask to control output */
  48 enum i40e_debug_mask {
  49         I40E_DEBUG_INIT                 = 0x00000001,
  50         I40E_DEBUG_RELEASE              = 0x00000002,
  51
  52         I40E_DEBUG_LINK                 = 0x00000010,
  53         I40E_DEBUG_PHY                  = 0x00000020,
  54         I40E_DEBUG_HMC                  = 0x00000040,
  55         I40E_DEBUG_NVM                  = 0x00000080,
  56         I40E_DEBUG_LAN                  = 0x00000100,
  57         I40E_DEBUG_FLOW                 = 0x00000200,
  58         I40E_DEBUG_DCB                  = 0x00000400,
  59         I40E_DEBUG_DIAG                 = 0x00000800,
  60         I40E_DEBUG_FD                   = 0x00001000,
  61         I40E_DEBUG_PACKAGE              = 0x00002000,
  62
  63         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
  64         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
  65         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
  66         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
  67         I40E_DEBUG_AQ                   = 0x0F000000,
  68
  69         I40E_DEBUG_USER                 = 0xF0000000,
  70
  71         I40E_DEBUG_ALL                  = 0xFFFFFFFF
  72 };
  73
  74 /* These are structs for managing the hardware information and the operations.
  75  * The structures of function pointers are filled out at init time when we
  76  * know for sure exactly which hardware we're working with.  This gives us the
  77  * flexibility of using the same main driver code but adapting to slightly
  78  * different hardware needs as new parts are developed.  For this architecture,
  79  * the Firmware and AdminQ are intended to insulate the driver from most of the
  80  * future changes, but these structures will also do part of the job.
  81  */
  82 enum i40e_mac_type {
  83         I40E_MAC_UNKNOWN = 0,
  84         I40E_MAC_XL710,
  85         I40E_MAC_VF,
  86         I40E_MAC_X722,
  87         I40E_MAC_X722_VF,
  88         I40E_MAC_GENERIC,
  89 };
  90
  91 enum i40e_media_type {
  92         I40E_MEDIA_TYPE_UNKNOWN = 0,
  93         I40E_MEDIA_TYPE_FIBER,
  94         I40E_MEDIA_TYPE_BASET,
  95         I40E_MEDIA_TYPE_BACKPLANE,
  96         I40E_MEDIA_TYPE_CX4,
  97         I40E_MEDIA_TYPE_DA,
  98         I40E_MEDIA_TYPE_VIRTUAL
  99 };
 100
 101 enum i40e_fc_mode {
 102         I40E_FC_NONE = 0,
 103         I40E_FC_RX_PAUSE,
 104         I40E_FC_TX_PAUSE,
 105         I40E_FC_FULL,
 106         I40E_FC_PFC,
 107         I40E_FC_DEFAULT
 108 };
 109
 110 enum i40e_set_fc_aq_failures {
 111         I40E_SET_FC_AQ_FAIL_NONE = 0,
 112         I40E_SET_FC_AQ_FAIL_GET = 1,
 113         I40E_SET_FC_AQ_FAIL_SET = 2,
 114         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 115         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 116 };
 117
 118 enum i40e_vsi_type {
 119         I40E_VSI_MAIN   = 0,
 120         I40E_VSI_VMDQ1  = 1,
 121         I40E_VSI_VMDQ2  = 2,
 122         I40E_VSI_CTRL   = 3,
 123         I40E_VSI_FCOE   = 4,
 124         I40E_VSI_MIRROR = 5,
 125         I40E_VSI_SRIOV  = 6,
 126         I40E_VSI_FDIR   = 7,
 127         I40E_VSI_TYPE_UNKNOWN
 128 };
 129
 130 enum i40e_queue_type {
 131         I40E_QUEUE_TYPE_RX = 0,
 132         I40E_QUEUE_TYPE_TX,
 133         I40E_QUEUE_TYPE_PE_CEQ,
 134         I40E_QUEUE_TYPE_UNKNOWN
 135 };
 136
 137 struct i40e_link_status {
 138         enum i40e_aq_phy_type phy_type;
 139         enum i40e_aq_link_speed link_speed;
 140         u8 link_info;
 141         u8 an_info;
 142         u8 req_fec_info;
 143         u8 fec_info;
 144         u8 ext_info;
 145         u8 loopback;
 146         /* is Link Status Event notification to SW enabled */
 147         bool lse_enable;
 148         u16 max_frame_size;
 149         bool crc_enable;
 150         u8 pacing;
 151         u8 requested_speeds;
 152         u8 module_type[3];
 153         /* 1st byte: module identifier */
 154 #define I40E_MODULE_TYPE_SFP            0x03
 155 #define I40E_MODULE_TYPE_QSFP           0x0D
 156         /* 2nd byte: ethernet compliance codes for 10/40G */
 157 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 158 #define I40E_MODULE_TYPE_40G_LR4        0x02
 159 #define I40E_MODULE_TYPE_40G_SR4        0x04
 160 #define I40E_MODULE_TYPE_40G_CR4        0x08
 161 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 162 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 163 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 164 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 165         /* 3rd byte: ethernet compliance codes for 1G */
 166 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 167 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 168 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 169 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 170 };
 171
 172 struct i40e_phy_info {
 173         struct i40e_link_status link_info;
 174         struct i40e_link_status link_info_old;
 175         bool get_link_info;
 176         enum i40e_media_type media_type;
 177         /* all the phy types the NVM is capable of */
 178         u64 phy_types;
 179 };
 180
 181 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 182 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 183 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 184 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 185 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 186 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 187 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 188 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 189 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 190 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 191 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 192 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 193 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 194 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 195 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 196 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 197 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 198 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 199 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 200 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 201 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 202 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 203 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 204 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 205 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 206 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 207 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 208                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 209 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 210 /* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
 211  * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
 212  * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
 213  * a shift is needed to adjust for this with values larger than 31. The
 214  * only affected values are I40E_PHY_TYPE_25GBASE_*.
 215  */
 216 #define I40E_PHY_TYPE_OFFSET 1
 217 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
 218                                              I40E_PHY_TYPE_OFFSET)
 219 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
 220                                              I40E_PHY_TYPE_OFFSET)
 221 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
 222                                              I40E_PHY_TYPE_OFFSET)
 223 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
 224                                              I40E_PHY_TYPE_OFFSET)
 225 #define I40E_HW_CAP_MAX_GPIO                    30
 226 /* Capabilities of a PF or a VF or the whole device */
 227 struct i40e_hw_capabilities {
 228         u32  switch_mode;
 229 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 230 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 231 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 232
 233         u32  management_mode;
 234         u32  mng_protocols_over_mctp;
 235 #define I40E_MNG_PROTOCOL_PLDM          0x2
 236 #define I40E_MNG_PROTOCOL_OEM_COMMANDS  0x4
 237 #define I40E_MNG_PROTOCOL_NCSI          0x8
 238         u32  npar_enable;
 239         u32  os2bmc;
 240         u32  valid_functions;
 241         bool sr_iov_1_1;
 242         bool vmdq;
 243         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 244         bool evb_802_1_qbh; /* Bridge Port Extension */
 245         bool dcb;
 246         bool fcoe;
 247         bool iscsi; /* Indicates iSCSI enabled */
 248         bool flex10_enable;
 249         bool flex10_capable;
 250         u32  flex10_mode;
 251 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 252 #define I40E_FLEX10_MODE_DCC            0x1
 253 #define I40E_FLEX10_MODE_DCI            0x2
 254
 255         u32 flex10_status;
 256 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 257 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 258
 259         bool sec_rev_disabled;
 260         bool update_disabled;
 261 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 262 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 263
 264         bool mgmt_cem;
 265         bool ieee_1588;
 266         bool iwarp;
 267         bool fd;
 268         u32 fd_filters_guaranteed;
 269         u32 fd_filters_best_effort;
 270         bool rss;
 271         u32 rss_table_size;
 272         u32 rss_table_entry_width;
 273         bool led[I40E_HW_CAP_MAX_GPIO];
 274         bool sdp[I40E_HW_CAP_MAX_GPIO];
 275         u32 nvm_image_type;
 276         u32 num_flow_director_filters;
 277         u32 num_vfs;
 278         u32 vf_base_id;
 279         u32 num_vsis;
 280         u32 num_rx_qp;
 281         u32 num_tx_qp;
 282         u32 base_queue;
 283         u32 num_msix_vectors;
 284         u32 num_msix_vectors_vf;
 285         u32 led_pin_num;
 286         u32 sdp_pin_num;
 287         u32 mdio_port_num;
 288         u32 mdio_port_mode;
 289         u8 rx_buf_chain_len;
 290         u32 enabled_tcmap;
 291         u32 maxtc;
 292         u64 wr_csr_prot;
 293 };
 294
 295 struct i40e_mac_info {
 296         enum i40e_mac_type type;
 297         u8 addr[ETH_ALEN];
 298         u8 perm_addr[ETH_ALEN];
 299         u8 san_addr[ETH_ALEN];
 300         u16 max_fcoeq;
 301 };
 302
 303 enum i40e_aq_resources_ids {
 304         I40E_NVM_RESOURCE_ID = 1
 305 };
 306
 307 enum i40e_aq_resource_access_type {
 308         I40E_RESOURCE_READ = 1,
 309         I40E_RESOURCE_WRITE
 310 };
 311
 312 struct i40e_nvm_info {
 313         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 314         u32 timeout;              /* [ms] */
 315         u16 sr_size;              /* Shadow RAM size in words */
 316         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 317         u16 version;              /* NVM package version */
 318         u32 eetrack;              /* NVM data version */
 319         u32 oem_ver;              /* OEM version info */
 320 };
 321
 322 /* definitions used in NVM update support */
 323
 324 enum i40e_nvmupd_cmd {
 325         I40E_NVMUPD_INVALID,
 326         I40E_NVMUPD_READ_CON,
 327         I40E_NVMUPD_READ_SNT,
 328         I40E_NVMUPD_READ_LCB,
 329         I40E_NVMUPD_READ_SA,
 330         I40E_NVMUPD_WRITE_ERA,
 331         I40E_NVMUPD_WRITE_CON,
 332         I40E_NVMUPD_WRITE_SNT,
 333         I40E_NVMUPD_WRITE_LCB,
 334         I40E_NVMUPD_WRITE_SA,
 335         I40E_NVMUPD_CSUM_CON,
 336         I40E_NVMUPD_CSUM_SA,
 337         I40E_NVMUPD_CSUM_LCB,
 338         I40E_NVMUPD_STATUS,
 339         I40E_NVMUPD_EXEC_AQ,
 340         I40E_NVMUPD_GET_AQ_RESULT,
 341         I40E_NVMUPD_GET_AQ_EVENT,
 342 };
 343
 344 enum i40e_nvmupd_state {
 345         I40E_NVMUPD_STATE_INIT,
 346         I40E_NVMUPD_STATE_READING,
 347         I40E_NVMUPD_STATE_WRITING,
 348         I40E_NVMUPD_STATE_INIT_WAIT,
 349         I40E_NVMUPD_STATE_WRITE_WAIT,
 350         I40E_NVMUPD_STATE_ERROR
 351 };
 352
 353 /* nvm_access definition and its masks/shifts need to be accessible to
 354  * application, core driver, and shared code.  Where is the right file?
 355  */
 356 #define I40E_NVM_READ   0xB
 357 #define I40E_NVM_WRITE  0xC
 358
 359 #define I40E_NVM_MOD_PNT_MASK 0xFF
 360
 361 #define I40E_NVM_TRANS_SHIFT                    8
 362 #define I40E_NVM_TRANS_MASK                     (0xf << I40E_NVM_TRANS_SHIFT)
 363 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT       12
 364 #define I40E_NVM_PRESERVATION_FLAGS_MASK \
 365                                 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
 366 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED    0x01
 367 #define I40E_NVM_PRESERVATION_FLAGS_ALL         0x02
 368 #define I40E_NVM_CON                            0x0
 369 #define I40E_NVM_SNT                            0x1
 370 #define I40E_NVM_LCB                            0x2
 371 #define I40E_NVM_SA                             (I40E_NVM_SNT | I40E_NVM_LCB)
 372 #define I40E_NVM_ERA                            0x4
 373 #define I40E_NVM_CSUM                           0x8
 374 #define I40E_NVM_AQE                            0xe
 375 #define I40E_NVM_EXEC                           0xf
 376
 377 #define I40E_NVM_ADAPT_SHIFT    16
 378 #define I40E_NVM_ADAPT_MASK     (0xffff << I40E_NVM_ADAPT_SHIFT)
 379
 380 #define I40E_NVMUPD_MAX_DATA    4096
 381 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 382
 383 struct i40e_nvm_access {
 384         u32 command;
 385         u32 config;
 386         u32 offset;     /* in bytes */
 387         u32 data_size;  /* in bytes */
 388         u8 data[1];
 389 };
 390
 391 /* (Q)SFP module access definitions */
 392 #define I40E_I2C_EEPROM_DEV_ADDR        0xA0
 393 #define I40E_I2C_EEPROM_DEV_ADDR2       0xA2
 394 #define I40E_MODULE_TYPE_ADDR           0x00
 395 #define I40E_MODULE_REVISION_ADDR       0x01
 396 #define I40E_MODULE_SFF_8472_COMP       0x5E
 397 #define I40E_MODULE_SFF_8472_SWAP       0x5C
 398 #define I40E_MODULE_SFF_ADDR_MODE       0x04
 399 #define I40E_MODULE_TYPE_QSFP_PLUS      0x0D
 400 #define I40E_MODULE_TYPE_QSFP28         0x11
 401 #define I40E_MODULE_QSFP_MAX_LEN        640
 402
 403 /* PCI bus types */
 404 enum i40e_bus_type {
 405         i40e_bus_type_unknown = 0,
 406         i40e_bus_type_pci,
 407         i40e_bus_type_pcix,
 408         i40e_bus_type_pci_express,
 409         i40e_bus_type_reserved
 410 };
 411
 412 /* PCI bus speeds */
 413 enum i40e_bus_speed {
 414         i40e_bus_speed_unknown  = 0,
 415         i40e_bus_speed_33       = 33,
 416         i40e_bus_speed_66       = 66,
 417         i40e_bus_speed_100      = 100,
 418         i40e_bus_speed_120      = 120,
 419         i40e_bus_speed_133      = 133,
 420         i40e_bus_speed_2500     = 2500,
 421         i40e_bus_speed_5000     = 5000,
 422         i40e_bus_speed_8000     = 8000,
 423         i40e_bus_speed_reserved
 424 };
 425
 426 /* PCI bus widths */
 427 enum i40e_bus_width {
 428         i40e_bus_width_unknown  = 0,
 429         i40e_bus_width_pcie_x1  = 1,
 430         i40e_bus_width_pcie_x2  = 2,
 431         i40e_bus_width_pcie_x4  = 4,
 432         i40e_bus_width_pcie_x8  = 8,
 433         i40e_bus_width_32       = 32,
 434         i40e_bus_width_64       = 64,
 435         i40e_bus_width_reserved
 436 };
 437
 438 /* Bus parameters */
 439 struct i40e_bus_info {
 440         enum i40e_bus_speed speed;
 441         enum i40e_bus_width width;
 442         enum i40e_bus_type type;
 443
 444         u16 func;
 445         u16 device;
 446         u16 lan_id;
 447         u16 bus_id;
 448 };
 449
 450 /* Flow control (FC) parameters */
 451 struct i40e_fc_info {
 452         enum i40e_fc_mode current_mode; /* FC mode in effect */
 453         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 454 };
 455
 456 #define I40E_MAX_TRAFFIC_CLASS          8
 457 #define I40E_MAX_USER_PRIORITY          8
 458 #define I40E_DCBX_MAX_APPS              32
 459 #define I40E_LLDPDU_SIZE                1500
 460
 461 /* IEEE 802.1Qaz ETS Configuration data */
 462 struct i40e_ieee_ets_config {
 463         u8 willing;
 464         u8 cbs;
 465         u8 maxtcs;
 466         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 467         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 468         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 469 };
 470
 471 /* IEEE 802.1Qaz ETS Recommendation data */
 472 struct i40e_ieee_ets_recommend {
 473         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 474         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 475         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 476 };
 477
 478 /* IEEE 802.1Qaz PFC Configuration data */
 479 struct i40e_ieee_pfc_config {
 480         u8 willing;
 481         u8 mbc;
 482         u8 pfccap;
 483         u8 pfcenable;
 484 };
 485
 486 /* IEEE 802.1Qaz Application Priority data */
 487 struct i40e_ieee_app_priority_table {
 488         u8  priority;
 489         u8  selector;
 490         u16 protocolid;
 491 };
 492
 493 struct i40e_dcbx_config {
 494         u32 numapps;
 495         u32 tlv_status; /* CEE mode TLV status */
 496         struct i40e_ieee_ets_config etscfg;
 497         struct i40e_ieee_ets_recommend etsrec;
 498         struct i40e_ieee_pfc_config pfc;
 499         struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
 500 };
 501
 502 /* Port hardware description */
 503 struct i40e_hw {
 504         u8 __iomem *hw_addr;
 505         void *back;
 506
 507         /* subsystem structs */
 508         struct i40e_phy_info phy;
 509         struct i40e_mac_info mac;
 510         struct i40e_bus_info bus;
 511         struct i40e_nvm_info nvm;
 512         struct i40e_fc_info fc;
 513
 514         /* pci info */
 515         u16 device_id;
 516         u16 vendor_id;
 517         u16 subsystem_device_id;
 518         u16 subsystem_vendor_id;
 519         u8 revision_id;
 520         u8 port;
 521         bool adapter_stopped;
 522
 523         /* capabilities for entire device and PCI func */
 524         struct i40e_hw_capabilities dev_caps;
 525         struct i40e_hw_capabilities func_caps;
 526
 527         /* Flow Director shared filter space */
 528         u16 fdir_shared_filter_count;
 529
 530         /* device profile info */
 531         u8  pf_id;
 532         u16 main_vsi_seid;
 533
 534         /* for multi-function MACs */
 535         u16 partition_id;
 536         u16 num_partitions;
 537         u16 num_ports;
 538
 539         /* Closest numa node to the device */
 540         u16 numa_node;
 541
 542         /* Admin Queue info */
 543         struct i40e_adminq_info aq;
 544
 545         /* state of nvm update process */
 546         enum i40e_nvmupd_state nvmupd_state;
 547         struct i40e_aq_desc nvm_wb_desc;
 548         struct i40e_aq_desc nvm_aq_event_desc;
 549         struct i40e_virt_mem nvm_buff;
 550         bool nvm_release_on_done;
 551         u16 nvm_wait_opcode;
 552
 553         /* HMC info */
 554         struct i40e_hmc_info hmc; /* HMC info struct */
 555
 556         /* LLDP/DCBX Status */
 557         u16 dcbx_status;
 558
 559 #define I40E_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)
 560 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
 561
 562         /* DCBX info */
 563         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 564         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 565         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 566
 567         /* Used in set switch config AQ command */
 568         u16 switch_tag;
 569         u16 first_tag;
 570         u16 second_tag;
 571
 572         /* debug mask */
 573         u32 debug_mask;
 574         char err_str[16];
 575 };
 576
 577 static inline bool i40e_is_vf(struct i40e_hw *hw)
 578 {
 579         return (hw->mac.type == I40E_MAC_VF ||
 580                 hw->mac.type == I40E_MAC_X722_VF);
 581 }
 582
 583 struct i40e_driver_version {
 584         u8 major_version;
 585         u8 minor_version;
 586         u8 build_version;
 587         u8 subbuild_version;
 588         u8 driver_string[32];
 589 };
 590
 591 /* RX Descriptors */
 592 union i40e_16byte_rx_desc {
 593         struct {
 594                 __le64 pkt_addr; /* Packet buffer address */
 595                 __le64 hdr_addr; /* Header buffer address */
 596         } read;
 597         struct {
 598                 struct {
 599                         struct {
 600                                 union {
 601                                         __le16 mirroring_status;
 602                                         __le16 fcoe_ctx_id;
 603                                 } mirr_fcoe;
 604                                 __le16 l2tag1;
 605                         } lo_dword;
 606                         union {
 607                                 __le32 rss; /* RSS Hash */
 608                                 __le32 fd_id; /* Flow director filter id */
 609                                 __le32 fcoe_param; /* FCoE DDP Context id */
 610                         } hi_dword;
 611                 } qword0;
 612                 struct {
 613                         /* ext status/error/pktype/length */
 614                         __le64 status_error_len;
 615                 } qword1;
 616         } wb;  /* writeback */
 617 };
 618
 619 union i40e_32byte_rx_desc {
 620         struct {
 621                 __le64  pkt_addr; /* Packet buffer address */
 622                 __le64  hdr_addr; /* Header buffer address */
 623                         /* bit 0 of hdr_buffer_addr is DD bit */
 624                 __le64  rsvd1;
 625                 __le64  rsvd2;
 626         } read;
 627         struct {
 628                 struct {
 629                         struct {
 630                                 union {
 631                                         __le16 mirroring_status;
 632                                         __le16 fcoe_ctx_id;
 633                                 } mirr_fcoe;
 634                                 __le16 l2tag1;
 635                         } lo_dword;
 636                         union {
 637                                 __le32 rss; /* RSS Hash */
 638                                 __le32 fcoe_param; /* FCoE DDP Context id */
 639                                 /* Flow director filter id in case of
 640                                  * Programming status desc WB
 641                                  */
 642                                 __le32 fd_id;
 643                         } hi_dword;
 644                 } qword0;
 645                 struct {
 646                         /* status/error/pktype/length */
 647                         __le64 status_error_len;
 648                 } qword1;
 649                 struct {
 650                         __le16 ext_status; /* extended status */
 651                         __le16 rsvd;
 652                         __le16 l2tag2_1;
 653                         __le16 l2tag2_2;
 654                 } qword2;
 655                 struct {
 656                         union {
 657                                 __le32 flex_bytes_lo;
 658                                 __le32 pe_status;
 659                         } lo_dword;
 660                         union {
 661                                 __le32 flex_bytes_hi;
 662                                 __le32 fd_id;
 663                         } hi_dword;
 664                 } qword3;
 665         } wb;  /* writeback */
 666 };
 667
 668 enum i40e_rx_desc_status_bits {
 669         /* Note: These are predefined bit offsets */
 670         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 671         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 672         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 673         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 674         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 675         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 676         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 677         /* Note: Bit 8 is reserved in X710 and XL710 */
 678         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 679         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 680         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 681         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 682         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 683         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 684         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 685         /* Note: For non-tunnel packets INT_UDP_0 is the right status for
 686          * UDP header
 687          */
 688         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 689         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 690 };
 691
 692 #define I40E_RXD_QW1_STATUS_SHIFT       0
 693 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
 694                                          << I40E_RXD_QW1_STATUS_SHIFT)
 695
 696 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 697 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 698                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 699
 700 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 701 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
 702                                     BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 703
 704 enum i40e_rx_desc_fltstat_values {
 705         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 706         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 707         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 708         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 709 };
 710
 711 #define I40E_RXD_QW1_ERROR_SHIFT        19
 712 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 713
 714 enum i40e_rx_desc_error_bits {
 715         /* Note: These are predefined bit offsets */
 716         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 717         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 718         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 719         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 720         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 721         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 722         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 723         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 724         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 725 };
 726
 727 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 728         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 729         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 730         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 731         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 732         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 733 };
 734
 735 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 736 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 737
 738 /* Packet type non-ip values */
 739 enum i40e_rx_l2_ptype {
 740         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 741         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 742         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 743         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 744         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 745         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 746         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 747         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 748         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 749         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 750         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 751         I40E_RX_PTYPE_L2_ARP                            = 11,
 752         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 753         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 754         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 755         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 756         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 757         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 758         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 759         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 760         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 761         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 762         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 763         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 764         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 765         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 766 };
 767
 768 struct i40e_rx_ptype_decoded {
 769         u32 ptype:8;
 770         u32 known:1;
 771         u32 outer_ip:1;
 772         u32 outer_ip_ver:1;
 773         u32 outer_frag:1;
 774         u32 tunnel_type:3;
 775         u32 tunnel_end_prot:2;
 776         u32 tunnel_end_frag:1;
 777         u32 inner_prot:4;
 778         u32 payload_layer:3;
 779 };
 780
 781 enum i40e_rx_ptype_outer_ip {
 782         I40E_RX_PTYPE_OUTER_L2  = 0,
 783         I40E_RX_PTYPE_OUTER_IP  = 1
 784 };
 785
 786 enum i40e_rx_ptype_outer_ip_ver {
 787         I40E_RX_PTYPE_OUTER_NONE        = 0,
 788         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 789         I40E_RX_PTYPE_OUTER_IPV6        = 1
 790 };
 791
 792 enum i40e_rx_ptype_outer_fragmented {
 793         I40E_RX_PTYPE_NOT_FRAG  = 0,
 794         I40E_RX_PTYPE_FRAG      = 1
 795 };
 796
 797 enum i40e_rx_ptype_tunnel_type {
 798         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 799         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 800         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 801         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 802         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 803 };
 804
 805 enum i40e_rx_ptype_tunnel_end_prot {
 806         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 807         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 808         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 809 };
 810
 811 enum i40e_rx_ptype_inner_prot {
 812         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 813         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 814         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 815         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 816         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 817         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 818 };
 819
 820 enum i40e_rx_ptype_payload_layer {
 821         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 822         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 823         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 824         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 825 };
 826
 827 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 828 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 829                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 830
 831 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 832 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 833                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 834
 835 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 836 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 837
 838 enum i40e_rx_desc_ext_status_bits {
 839         /* Note: These are predefined bit offsets */
 840         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 841         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 842         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 843         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 844         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 845         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 846         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 847 };
 848
 849 enum i40e_rx_desc_pe_status_bits {
 850         /* Note: These are predefined bit offsets */
 851         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 852         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 853         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 854         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 855         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 856         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 857         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 858         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 859         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 860 };
 861
 862 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 863 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 864
 865 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 866 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 867                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 868
 869 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 870 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 871                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 872
 873 enum i40e_rx_prog_status_desc_status_bits {
 874         /* Note: These are predefined bit offsets */
 875         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 876         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 877 };
 878
 879 enum i40e_rx_prog_status_desc_prog_id_masks {
 880         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 881         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 882         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 883 };
 884
 885 enum i40e_rx_prog_status_desc_error_bits {
 886         /* Note: These are predefined bit offsets */
 887         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 888         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 889         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 890         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 891 };
 892
 893 /* TX Descriptor */
 894 struct i40e_tx_desc {
 895         __le64 buffer_addr; /* Address of descriptor's data buf */
 896         __le64 cmd_type_offset_bsz;
 897 };
 898
 899 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 900 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 901
 902 enum i40e_tx_desc_dtype_value {
 903         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 904         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 905         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 906         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 907         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 908         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 909         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 910         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 911         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 912         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 913 };
 914
 915 #define I40E_TXD_QW1_CMD_SHIFT  4
 916 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 917
 918 enum i40e_tx_desc_cmd_bits {
 919         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 920         I40E_TX_DESC_CMD_RS                     = 0x0002,
 921         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 922         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 923         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 924         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 925         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 926         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 927         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 928         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 929         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 930         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 931         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 932         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 933         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 934         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 935         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 936         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 937 };
 938
 939 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 940 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 941                                          I40E_TXD_QW1_OFFSET_SHIFT)
 942
 943 enum i40e_tx_desc_length_fields {
 944         /* Note: These are predefined bit offsets */
 945         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 946         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 947         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 948 };
 949
 950 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 951 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 952                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 953
 954 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 955 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 956
 957 /* Context descriptors */
 958 struct i40e_tx_context_desc {
 959         __le32 tunneling_params;
 960         __le16 l2tag2;
 961         __le16 rsvd;
 962         __le64 type_cmd_tso_mss;
 963 };
 964
 965 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
 966 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
 967
 968 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 969 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
 970
 971 enum i40e_tx_ctx_desc_cmd_bits {
 972         I40E_TX_CTX_DESC_TSO            = 0x01,
 973         I40E_TX_CTX_DESC_TSYN           = 0x02,
 974         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
 975         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 976         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 977         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 978         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 979         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 980         I40E_TX_CTX_DESC_SWPE           = 0x40
 981 };
 982
 983 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
 984 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
 985                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
 986
 987 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
 988 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
 989                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
 990
 991 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
 992 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
 993
 994 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
 995 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
 996                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
 997
 998 enum i40e_tx_ctx_desc_eipt_offload {
 999         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1000         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1001         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1002         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1003 };
1004
1005 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1006 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1007                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1008
1009 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1010 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1011
1012 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1013 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1014
1015 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1016 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
1017                                        BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1018
1019 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1020
1021 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1022 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1023                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1024
1025 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1026 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1027                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1028
1029 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1030 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1031 struct i40e_filter_program_desc {
1032         __le32 qindex_flex_ptype_vsi;
1033         __le32 rsvd;
1034         __le32 dtype_cmd_cntindex;
1035         __le32 fd_id;
1036 };
1037 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1038 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1039                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1040 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1041 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1042                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1043 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1044 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1045                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1046
1047 /* Packet Classifier Types for filters */
1048 enum i40e_filter_pctype {
1049         /* Note: Values 0-28 are reserved for future use.
1050          * Value 29, 30, 32 are not supported on XL710 and X710.
1051          */
1052         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1053         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1054         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1055         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1056         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1057         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1058         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1059         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1060         /* Note: Values 37-38 are reserved for future use.
1061          * Value 39, 40, 42 are not supported on XL710 and X710.
1062          */
1063         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1064         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1065         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1066         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1067         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1068         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1069         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1070         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1071         /* Note: Value 47 is reserved for future use */
1072         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1073         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1074         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1075         /* Note: Values 51-62 are reserved for future use */
1076         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1077 };
1078
1079 enum i40e_filter_program_desc_dest {
1080         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1081         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1082         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1083 };
1084
1085 enum i40e_filter_program_desc_fd_status {
1086         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1087         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1088         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1089         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1090 };
1091
1092 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1093 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1094                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1095
1096 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1097 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1098                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1099
1100 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1101 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1102
1103 enum i40e_filter_program_desc_pcmd {
1104         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1105         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1106 };
1107
1108 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1109 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1110
1111 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1112 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1113
1114 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1115                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1116 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1117                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1118
1119 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1120 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1121                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1122
1123 enum i40e_filter_type {
1124         I40E_FLOW_DIRECTOR_FLTR = 0,
1125         I40E_PE_QUAD_HASH_FLTR = 1,
1126         I40E_ETHERTYPE_FLTR,
1127         I40E_FCOE_CTX_FLTR,
1128         I40E_MAC_VLAN_FLTR,
1129         I40E_HASH_FLTR
1130 };
1131
1132 struct i40e_vsi_context {
1133         u16 seid;
1134         u16 uplink_seid;
1135         u16 vsi_number;
1136         u16 vsis_allocated;
1137         u16 vsis_unallocated;
1138         u16 flags;
1139         u8 pf_num;
1140         u8 vf_num;
1141         u8 connection_type;
1142         struct i40e_aqc_vsi_properties_data info;
1143 };
1144
1145 struct i40e_veb_context {
1146         u16 seid;
1147         u16 uplink_seid;
1148         u16 veb_number;
1149         u16 vebs_allocated;
1150         u16 vebs_unallocated;
1151         u16 flags;
1152         struct i40e_aqc_get_veb_parameters_completion info;
1153 };
1154
1155 /* Statistics collected by each port, VSI, VEB, and S-channel */
1156 struct i40e_eth_stats {
1157         u64 rx_bytes;                   /* gorc */
1158         u64 rx_unicast;                 /* uprc */
1159         u64 rx_multicast;               /* mprc */
1160         u64 rx_broadcast;               /* bprc */
1161         u64 rx_discards;                /* rdpc */
1162         u64 rx_unknown_protocol;        /* rupp */
1163         u64 tx_bytes;                   /* gotc */
1164         u64 tx_unicast;                 /* uptc */
1165         u64 tx_multicast;               /* mptc */
1166         u64 tx_broadcast;               /* bptc */
1167         u64 tx_discards;                /* tdpc */
1168         u64 tx_errors;                  /* tepc */
1169 };
1170
1171 /* Statistics collected per VEB per TC */
1172 struct i40e_veb_tc_stats {
1173         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1174         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1175         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1176         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1177 };
1178
1179 /* Statistics collected by the MAC */
1180 struct i40e_hw_port_stats {
1181         /* eth stats collected by the port */
1182         struct i40e_eth_stats eth;
1183
1184         /* additional port specific stats */
1185         u64 tx_dropped_link_down;       /* tdold */
1186         u64 crc_errors;                 /* crcerrs */
1187         u64 illegal_bytes;              /* illerrc */
1188         u64 error_bytes;                /* errbc */
1189         u64 mac_local_faults;           /* mlfc */
1190         u64 mac_remote_faults;          /* mrfc */
1191         u64 rx_length_errors;           /* rlec */
1192         u64 link_xon_rx;                /* lxonrxc */
1193         u64 link_xoff_rx;               /* lxoffrxc */
1194         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1195         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1196         u64 link_xon_tx;                /* lxontxc */
1197         u64 link_xoff_tx;               /* lxofftxc */
1198         u64 priority_xon_tx[8];         /* pxontxc[8] */
1199         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1200         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1201         u64 rx_size_64;                 /* prc64 */
1202         u64 rx_size_127;                /* prc127 */
1203         u64 rx_size_255;                /* prc255 */
1204         u64 rx_size_511;                /* prc511 */
1205         u64 rx_size_1023;               /* prc1023 */
1206         u64 rx_size_1522;               /* prc1522 */
1207         u64 rx_size_big;                /* prc9522 */
1208         u64 rx_undersize;               /* ruc */
1209         u64 rx_fragments;               /* rfc */
1210         u64 rx_oversize;                /* roc */
1211         u64 rx_jabber;                  /* rjc */
1212         u64 tx_size_64;                 /* ptc64 */
1213         u64 tx_size_127;                /* ptc127 */
1214         u64 tx_size_255;                /* ptc255 */
1215         u64 tx_size_511;                /* ptc511 */
1216         u64 tx_size_1023;               /* ptc1023 */
1217         u64 tx_size_1522;               /* ptc1522 */
1218         u64 tx_size_big;                /* ptc9522 */
1219         u64 mac_short_packet_dropped;   /* mspdc */
1220         u64 checksum_error;             /* xec */
1221         /* flow director stats */
1222         u64 fd_atr_match;
1223         u64 fd_sb_match;
1224         u64 fd_atr_tunnel_match;
1225         u32 fd_atr_status;
1226         u32 fd_sb_status;
1227         /* EEE LPI */
1228         u32 tx_lpi_status;
1229         u32 rx_lpi_status;
1230         u64 tx_lpi_count;               /* etlpic */
1231         u64 rx_lpi_count;               /* erlpic */
1232 };
1233
1234 /* Checksum and Shadow RAM pointers */
1235 #define I40E_SR_NVM_CONTROL_WORD                0x00
1236 #define I40E_EMP_MODULE_PTR                     0x0F
1237 #define I40E_SR_EMP_MODULE_PTR                  0x48
1238 #define I40E_NVM_OEM_VER_OFF                    0x83
1239 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1240 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1241 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1242 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1243 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1244 #define I40E_SR_VPD_PTR                         0x2F
1245 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1246 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1247
1248 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1249 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1250 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1251 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1252 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1253 #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID   BIT(5)
1254 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE          BIT(12)
1255 #define I40E_PTR_TYPE                           BIT(15)
1256
1257 /* Shadow RAM related */
1258 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1259 #define I40E_SR_WORDS_IN_1KB            512
1260 /* Checksum should be calculated such that after adding all the words,
1261  * including the checksum word itself, the sum should be 0xBABA.
1262  */
1263 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1264
1265 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1266
1267 enum i40e_switch_element_types {
1268         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1269         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1270         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1271         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1272         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1273         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1274         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1275         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1276         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1277 };
1278
1279 /* Supported EtherType filters */
1280 enum i40e_ether_type_index {
1281         I40E_ETHER_TYPE_1588            = 0,
1282         I40E_ETHER_TYPE_FIP             = 1,
1283         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1284         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1285         I40E_ETHER_TYPE_LLDP            = 4,
1286         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1287         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1288         I40E_ETHER_TYPE_QCN_CNM         = 7,
1289         I40E_ETHER_TYPE_8021X           = 8,
1290         I40E_ETHER_TYPE_ARP             = 9,
1291         I40E_ETHER_TYPE_RSV1            = 10,
1292         I40E_ETHER_TYPE_RSV2            = 11,
1293 };
1294
1295 /* Filter context base size is 1K */
1296 #define I40E_HASH_FILTER_BASE_SIZE      1024
1297 /* Supported Hash filter values */
1298 enum i40e_hash_filter_size {
1299         I40E_HASH_FILTER_SIZE_1K        = 0,
1300         I40E_HASH_FILTER_SIZE_2K        = 1,
1301         I40E_HASH_FILTER_SIZE_4K        = 2,
1302         I40E_HASH_FILTER_SIZE_8K        = 3,
1303         I40E_HASH_FILTER_SIZE_16K       = 4,
1304         I40E_HASH_FILTER_SIZE_32K       = 5,
1305         I40E_HASH_FILTER_SIZE_64K       = 6,
1306         I40E_HASH_FILTER_SIZE_128K      = 7,
1307         I40E_HASH_FILTER_SIZE_256K      = 8,
1308         I40E_HASH_FILTER_SIZE_512K      = 9,
1309         I40E_HASH_FILTER_SIZE_1M        = 10,
1310 };
1311
1312 /* DMA context base size is 0.5K */
1313 #define I40E_DMA_CNTX_BASE_SIZE         512
1314 /* Supported DMA context values */
1315 enum i40e_dma_cntx_size {
1316         I40E_DMA_CNTX_SIZE_512          = 0,
1317         I40E_DMA_CNTX_SIZE_1K           = 1,
1318         I40E_DMA_CNTX_SIZE_2K           = 2,
1319         I40E_DMA_CNTX_SIZE_4K           = 3,
1320         I40E_DMA_CNTX_SIZE_8K           = 4,
1321         I40E_DMA_CNTX_SIZE_16K          = 5,
1322         I40E_DMA_CNTX_SIZE_32K          = 6,
1323         I40E_DMA_CNTX_SIZE_64K          = 7,
1324         I40E_DMA_CNTX_SIZE_128K         = 8,
1325         I40E_DMA_CNTX_SIZE_256K         = 9,
1326 };
1327
1328 /* Supported Hash look up table (LUT) sizes */
1329 enum i40e_hash_lut_size {
1330         I40E_HASH_LUT_SIZE_128          = 0,
1331         I40E_HASH_LUT_SIZE_512          = 1,
1332 };
1333
1334 /* Structure to hold a per PF filter control settings */
1335 struct i40e_filter_control_settings {
1336         /* number of PE Quad Hash filter buckets */
1337         enum i40e_hash_filter_size pe_filt_num;
1338         /* number of PE Quad Hash contexts */
1339         enum i40e_dma_cntx_size pe_cntx_num;
1340         /* number of FCoE filter buckets */
1341         enum i40e_hash_filter_size fcoe_filt_num;
1342         /* number of FCoE DDP contexts */
1343         enum i40e_dma_cntx_size fcoe_cntx_num;
1344         /* size of the Hash LUT */
1345         enum i40e_hash_lut_size hash_lut_size;
1346         /* enable FDIR filters for PF and its VFs */
1347         bool enable_fdir;
1348         /* enable Ethertype filters for PF and its VFs */
1349         bool enable_ethtype;
1350         /* enable MAC/VLAN filters for PF and its VFs */
1351         bool enable_macvlan;
1352 };
1353
1354 /* Structure to hold device level control filter counts */
1355 struct i40e_control_filter_stats {
1356         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1357         u16 etype_used;       /* Used perfect EtherType filters */
1358         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1359         u16 etype_free;       /* Un-used perfect EtherType filters */
1360 };
1361
1362 enum i40e_reset_type {
1363         I40E_RESET_POR          = 0,
1364         I40E_RESET_CORER        = 1,
1365         I40E_RESET_GLOBR        = 2,
1366         I40E_RESET_EMPR         = 3,
1367 };
1368
1369 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1370 #define I40E_NVM_LLDP_CFG_PTR   0x06
1371 #define I40E_SR_LLDP_CFG_PTR    0x31
1372
1373 /* RSS Hash Table Size */
1374 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1375
1376 /* INPUT SET MASK for RSS, flow director and flexible payload */
1377 #define I40E_FD_INSET_L3_SRC_SHIFT              47
1378 #define I40E_FD_INSET_L3_SRC_WORD_MASK          (0x3ULL << \
1379                                                  I40E_FD_INSET_L3_SRC_SHIFT)
1380 #define I40E_FD_INSET_L3_DST_SHIFT              35
1381 #define I40E_FD_INSET_L3_DST_WORD_MASK          (0x3ULL << \
1382                                                  I40E_FD_INSET_L3_DST_SHIFT)
1383 #define I40E_FD_INSET_L4_SRC_SHIFT              34
1384 #define I40E_FD_INSET_L4_SRC_WORD_MASK          (0x1ULL << \
1385                                                  I40E_FD_INSET_L4_SRC_SHIFT)
1386 #define I40E_FD_INSET_L4_DST_SHIFT              33
1387 #define I40E_FD_INSET_L4_DST_WORD_MASK          (0x1ULL << \
1388                                                  I40E_FD_INSET_L4_DST_SHIFT)
1389 #define I40E_FD_INSET_VERIFY_TAG_SHIFT          31
1390 #define I40E_FD_INSET_VERIFY_TAG_WORD_MASK      (0x3ULL << \
1391                                                  I40E_FD_INSET_VERIFY_TAG_SHIFT)
1392
1393 #define I40E_FD_INSET_FLEX_WORD50_SHIFT         17
1394 #define I40E_FD_INSET_FLEX_WORD50_MASK          (0x1ULL << \
1395                                         I40E_FD_INSET_FLEX_WORD50_SHIFT)
1396 #define I40E_FD_INSET_FLEX_WORD51_SHIFT         16
1397 #define I40E_FD_INSET_FLEX_WORD51_MASK          (0x1ULL << \
1398                                         I40E_FD_INSET_FLEX_WORD51_SHIFT)
1399 #define I40E_FD_INSET_FLEX_WORD52_SHIFT         15
1400 #define I40E_FD_INSET_FLEX_WORD52_MASK          (0x1ULL << \
1401                                         I40E_FD_INSET_FLEX_WORD52_SHIFT)
1402 #define I40E_FD_INSET_FLEX_WORD53_SHIFT         14
1403 #define I40E_FD_INSET_FLEX_WORD53_MASK          (0x1ULL << \
1404                                         I40E_FD_INSET_FLEX_WORD53_SHIFT)
1405 #define I40E_FD_INSET_FLEX_WORD54_SHIFT         13
1406 #define I40E_FD_INSET_FLEX_WORD54_MASK          (0x1ULL << \
1407                                         I40E_FD_INSET_FLEX_WORD54_SHIFT)
1408 #define I40E_FD_INSET_FLEX_WORD55_SHIFT         12
1409 #define I40E_FD_INSET_FLEX_WORD55_MASK          (0x1ULL << \
1410                                         I40E_FD_INSET_FLEX_WORD55_SHIFT)
1411 #define I40E_FD_INSET_FLEX_WORD56_SHIFT         11
1412 #define I40E_FD_INSET_FLEX_WORD56_MASK          (0x1ULL << \
1413                                         I40E_FD_INSET_FLEX_WORD56_SHIFT)
1414 #define I40E_FD_INSET_FLEX_WORD57_SHIFT         10
1415 #define I40E_FD_INSET_FLEX_WORD57_MASK          (0x1ULL << \
1416                                         I40E_FD_INSET_FLEX_WORD57_SHIFT)
1417
1418 /* Version format for Dynamic Device Personalization(DDP) */
1419 struct i40e_ddp_version {
1420         u8 major;
1421         u8 minor;
1422         u8 update;
1423         u8 draft;
1424 };
1425
1426 #define I40E_DDP_NAME_SIZE      32
1427
1428 /* Package header */
1429 struct i40e_package_header {
1430         struct i40e_ddp_version version;
1431         u32 segment_count;
1432         u32 segment_offset[1];
1433 };
1434
1435 /* Generic segment header */
1436 struct i40e_generic_seg_header {
1437 #define SEGMENT_TYPE_METADATA   0x00000001
1438 #define SEGMENT_TYPE_NOTES      0x00000002
1439 #define SEGMENT_TYPE_I40E       0x00000011
1440 #define SEGMENT_TYPE_X722       0x00000012
1441         u32 type;
1442         struct i40e_ddp_version version;
1443         u32 size;
1444         char name[I40E_DDP_NAME_SIZE];
1445 };
1446
1447 struct i40e_metadata_segment {
1448         struct i40e_generic_seg_header header;
1449         struct i40e_ddp_version version;
1450         u32 track_id;
1451         char name[I40E_DDP_NAME_SIZE];
1452 };
1453
1454 struct i40e_device_id_entry {
1455         u32 vendor_dev_id;
1456         u32 sub_vendor_dev_id;
1457 };
1458
1459 struct i40e_profile_segment {
1460         struct i40e_generic_seg_header header;
1461         struct i40e_ddp_version version;
1462         char name[I40E_DDP_NAME_SIZE];
1463         u32 device_table_count;
1464         struct i40e_device_id_entry device_table[1];
1465 };
1466
1467 struct i40e_section_table {
1468         u32 section_count;
1469         u32 section_offset[1];
1470 };
1471
1472 struct i40e_profile_section_header {
1473         u16 tbl_size;
1474         u16 data_end;
1475         struct {
1476 #define SECTION_TYPE_INFO       0x00000010
1477 #define SECTION_TYPE_MMIO       0x00000800
1478 #define SECTION_TYPE_AQ         0x00000801
1479 #define SECTION_TYPE_NOTE       0x80000000
1480 #define SECTION_TYPE_NAME       0x80000001
1481                 u32 type;
1482                 u32 offset;
1483                 u32 size;
1484         } section;
1485 };
1486
1487 struct i40e_profile_info {
1488         u32 track_id;
1489         struct i40e_ddp_version version;
1490         u8 op;
1491 #define I40E_DDP_ADD_TRACKID            0x01
1492 #define I40E_DDP_REMOVE_TRACKID 0x02
1493         u8 reserved[7];
1494         u8 name[I40E_DDP_NAME_SIZE];
1495 };
1496 #endif /* _I40E_TYPE_H_ */