drivers/net/ethernet/intel/i40e/i40e_type.h

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 - 2015 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #ifndef _I40E_TYPE_H_
  28 #define _I40E_TYPE_H_
  29
  30 #include "i40e_status.h"
  31 #include "i40e_osdep.h"
  32 #include "i40e_register.h"
  33 #include "i40e_adminq.h"
  34 #include "i40e_hmc.h"
  35 #include "i40e_lan_hmc.h"
  36 #include "i40e_devids.h"
  37
  38 /* I40E_MASK is a macro used on 32 bit registers */
  39 #define I40E_MASK(mask, shift) ((u32)(mask) << (shift))
  40
  41 #define I40E_MAX_VSI_QP                 16
  42 #define I40E_MAX_VF_VSI                 3
  43 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  44 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  45
  46 /* Max default timeout in ms, */
  47 #define I40E_MAX_NVM_TIMEOUT            18000
  48
  49 /* Max timeout in ms for the phy to respond */
  50 #define I40E_MAX_PHY_TIMEOUT            500
  51
  52 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  53 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  54
  55 /* forward declaration */
  56 struct i40e_hw;
  57 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  58
  59 /* Data type manipulation macros. */
  60
  61 #define I40E_DESC_UNUSED(R)     \
  62         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  63         (R)->next_to_clean - (R)->next_to_use - 1)
  64
  65 /* bitfields for Tx queue mapping in QTX_CTL */
  66 #define I40E_QTX_CTL_VF_QUEUE   0x0
  67 #define I40E_QTX_CTL_VM_QUEUE   0x1
  68 #define I40E_QTX_CTL_PF_QUEUE   0x2
  69
  70 /* debug masks - set these bits in hw->debug_mask to control output */
  71 enum i40e_debug_mask {
  72         I40E_DEBUG_INIT                 = 0x00000001,
  73         I40E_DEBUG_RELEASE              = 0x00000002,
  74
  75         I40E_DEBUG_LINK                 = 0x00000010,
  76         I40E_DEBUG_PHY                  = 0x00000020,
  77         I40E_DEBUG_HMC                  = 0x00000040,
  78         I40E_DEBUG_NVM                  = 0x00000080,
  79         I40E_DEBUG_LAN                  = 0x00000100,
  80         I40E_DEBUG_FLOW                 = 0x00000200,
  81         I40E_DEBUG_DCB                  = 0x00000400,
  82         I40E_DEBUG_DIAG                 = 0x00000800,
  83         I40E_DEBUG_FD                   = 0x00001000,
  84         I40E_DEBUG_PACKAGE              = 0x00002000,
  85         I40E_DEBUG_IWARP                = 0x00F00000,
  86         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
  87         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
  88         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
  89         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
  90         I40E_DEBUG_AQ                   = 0x0F000000,
  91
  92         I40E_DEBUG_USER                 = 0xF0000000,
  93
  94         I40E_DEBUG_ALL                  = 0xFFFFFFFF
  95 };
  96
  97 #define I40E_MDIO_CLAUSE22_STCODE_MASK  I40E_MASK(1, \
  98                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
  99 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_MASK(1, \
 100                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 101 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_MASK(2, \
 102                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 103
 104 #define I40E_MDIO_CLAUSE45_STCODE_MASK  I40E_MASK(0, \
 105                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 106 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_MASK(0, \
 107                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 108 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_MASK(1, \
 109                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 110 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    I40E_MASK(2, \
 111                                                 I40E_GLGEN_MSCA_OPCODE_SHIFT)
 112 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_MASK(3, \
 113                                                 I40E_GLGEN_MSCA_OPCODE_SHIFT)
 114
 115 #define I40E_PHY_COM_REG_PAGE                   0x1E
 116 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 117 #define I40E_PHY_LED_MANUAL_ON                  0x100
 118 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 119 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 120 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 121
 122 /* These are structs for managing the hardware information and the operations.
 123  * The structures of function pointers are filled out at init time when we
 124  * know for sure exactly which hardware we're working with.  This gives us the
 125  * flexibility of using the same main driver code but adapting to slightly
 126  * different hardware needs as new parts are developed.  For this architecture,
 127  * the Firmware and AdminQ are intended to insulate the driver from most of the
 128  * future changes, but these structures will also do part of the job.
 129  */
 130 enum i40e_mac_type {
 131         I40E_MAC_UNKNOWN = 0,
 132         I40E_MAC_XL710,
 133         I40E_MAC_VF,
 134         I40E_MAC_X722,
 135         I40E_MAC_X722_VF,
 136         I40E_MAC_GENERIC,
 137 };
 138
 139 enum i40e_media_type {
 140         I40E_MEDIA_TYPE_UNKNOWN = 0,
 141         I40E_MEDIA_TYPE_FIBER,
 142         I40E_MEDIA_TYPE_BASET,
 143         I40E_MEDIA_TYPE_BACKPLANE,
 144         I40E_MEDIA_TYPE_CX4,
 145         I40E_MEDIA_TYPE_DA,
 146         I40E_MEDIA_TYPE_VIRTUAL
 147 };
 148
 149 enum i40e_fc_mode {
 150         I40E_FC_NONE = 0,
 151         I40E_FC_RX_PAUSE,
 152         I40E_FC_TX_PAUSE,
 153         I40E_FC_FULL,
 154         I40E_FC_PFC,
 155         I40E_FC_DEFAULT
 156 };
 157
 158 enum i40e_set_fc_aq_failures {
 159         I40E_SET_FC_AQ_FAIL_NONE = 0,
 160         I40E_SET_FC_AQ_FAIL_GET = 1,
 161         I40E_SET_FC_AQ_FAIL_SET = 2,
 162         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 163         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 164 };
 165
 166 enum i40e_vsi_type {
 167         I40E_VSI_MAIN   = 0,
 168         I40E_VSI_VMDQ1  = 1,
 169         I40E_VSI_VMDQ2  = 2,
 170         I40E_VSI_CTRL   = 3,
 171         I40E_VSI_FCOE   = 4,
 172         I40E_VSI_MIRROR = 5,
 173         I40E_VSI_SRIOV  = 6,
 174         I40E_VSI_FDIR   = 7,
 175         I40E_VSI_IWARP  = 8,
 176         I40E_VSI_TYPE_UNKNOWN
 177 };
 178
 179 enum i40e_queue_type {
 180         I40E_QUEUE_TYPE_RX = 0,
 181         I40E_QUEUE_TYPE_TX,
 182         I40E_QUEUE_TYPE_PE_CEQ,
 183         I40E_QUEUE_TYPE_UNKNOWN
 184 };
 185
 186 struct i40e_link_status {
 187         enum i40e_aq_phy_type phy_type;
 188         enum i40e_aq_link_speed link_speed;
 189         u8 link_info;
 190         u8 an_info;
 191         u8 req_fec_info;
 192         u8 fec_info;
 193         u8 ext_info;
 194         u8 loopback;
 195         /* is Link Status Event notification to SW enabled */
 196         bool lse_enable;
 197         u16 max_frame_size;
 198         bool crc_enable;
 199         u8 pacing;
 200         u8 requested_speeds;
 201         u8 module_type[3];
 202         /* 1st byte: module identifier */
 203 #define I40E_MODULE_TYPE_SFP            0x03
 204 #define I40E_MODULE_TYPE_QSFP           0x0D
 205         /* 2nd byte: ethernet compliance codes for 10/40G */
 206 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 207 #define I40E_MODULE_TYPE_40G_LR4        0x02
 208 #define I40E_MODULE_TYPE_40G_SR4        0x04
 209 #define I40E_MODULE_TYPE_40G_CR4        0x08
 210 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 211 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 212 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 213 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 214         /* 3rd byte: ethernet compliance codes for 1G */
 215 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 216 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 217 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 218 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 219 };
 220
 221 struct i40e_phy_info {
 222         struct i40e_link_status link_info;
 223         struct i40e_link_status link_info_old;
 224         bool get_link_info;
 225         enum i40e_media_type media_type;
 226         /* all the phy types the NVM is capable of */
 227         u64 phy_types;
 228 };
 229
 230 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 231 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 232 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 233 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 234 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 235 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 236 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 237 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 238 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 239 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 240 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 241 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 242 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 243 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 244 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 245 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 246 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 247 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 248 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 249 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 250 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 251 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 252 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 253 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 254 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 255 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 256 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 257                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 258 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 259 /* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
 260  * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
 261  * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
 262  * a shift is needed to adjust for this with values larger than 31. The
 263  * only affected values are I40E_PHY_TYPE_25GBASE_*.
 264  */
 265 #define I40E_PHY_TYPE_OFFSET 1
 266 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
 267                                              I40E_PHY_TYPE_OFFSET)
 268 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
 269                                              I40E_PHY_TYPE_OFFSET)
 270 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
 271                                              I40E_PHY_TYPE_OFFSET)
 272 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
 273                                              I40E_PHY_TYPE_OFFSET)
 274 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
 275                                              I40E_PHY_TYPE_OFFSET)
 276 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
 277                                              I40E_PHY_TYPE_OFFSET)
 278 #define I40E_HW_CAP_MAX_GPIO                    30
 279 /* Capabilities of a PF or a VF or the whole device */
 280 struct i40e_hw_capabilities {
 281         u32  switch_mode;
 282 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 283 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 284 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 285
 286         /* Cloud filter modes:
 287          * Mode1: Filter on L4 port only
 288          * Mode2: Filter for non-tunneled traffic
 289          * Mode3: Filter for tunnel traffic
 290          */
 291 #define I40E_CLOUD_FILTER_MODE1 0x6
 292 #define I40E_CLOUD_FILTER_MODE2 0x7
 293 #define I40E_CLOUD_FILTER_MODE3 0x8
 294 #define I40E_SWITCH_MODE_MASK   0xF
 295
 296         u32  management_mode;
 297         u32  mng_protocols_over_mctp;
 298 #define I40E_MNG_PROTOCOL_PLDM          0x2
 299 #define I40E_MNG_PROTOCOL_OEM_COMMANDS  0x4
 300 #define I40E_MNG_PROTOCOL_NCSI          0x8
 301         u32  npar_enable;
 302         u32  os2bmc;
 303         u32  valid_functions;
 304         bool sr_iov_1_1;
 305         bool vmdq;
 306         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 307         bool evb_802_1_qbh; /* Bridge Port Extension */
 308         bool dcb;
 309         bool fcoe;
 310         bool iscsi; /* Indicates iSCSI enabled */
 311         bool flex10_enable;
 312         bool flex10_capable;
 313         u32  flex10_mode;
 314 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 315 #define I40E_FLEX10_MODE_DCC            0x1
 316 #define I40E_FLEX10_MODE_DCI            0x2
 317
 318         u32 flex10_status;
 319 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 320 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 321
 322         bool sec_rev_disabled;
 323         bool update_disabled;
 324 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 325 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 326
 327         bool mgmt_cem;
 328         bool ieee_1588;
 329         bool iwarp;
 330         bool fd;
 331         u32 fd_filters_guaranteed;
 332         u32 fd_filters_best_effort;
 333         bool rss;
 334         u32 rss_table_size;
 335         u32 rss_table_entry_width;
 336         bool led[I40E_HW_CAP_MAX_GPIO];
 337         bool sdp[I40E_HW_CAP_MAX_GPIO];
 338         u32 nvm_image_type;
 339         u32 num_flow_director_filters;
 340         u32 num_vfs;
 341         u32 vf_base_id;
 342         u32 num_vsis;
 343         u32 num_rx_qp;
 344         u32 num_tx_qp;
 345         u32 base_queue;
 346         u32 num_msix_vectors;
 347         u32 num_msix_vectors_vf;
 348         u32 led_pin_num;
 349         u32 sdp_pin_num;
 350         u32 mdio_port_num;
 351         u32 mdio_port_mode;
 352         u8 rx_buf_chain_len;
 353         u32 enabled_tcmap;
 354         u32 maxtc;
 355         u64 wr_csr_prot;
 356 };
 357
 358 struct i40e_mac_info {
 359         enum i40e_mac_type type;
 360         u8 addr[ETH_ALEN];
 361         u8 perm_addr[ETH_ALEN];
 362         u8 san_addr[ETH_ALEN];
 363         u8 port_addr[ETH_ALEN];
 364         u16 max_fcoeq;
 365 };
 366
 367 enum i40e_aq_resources_ids {
 368         I40E_NVM_RESOURCE_ID = 1
 369 };
 370
 371 enum i40e_aq_resource_access_type {
 372         I40E_RESOURCE_READ = 1,
 373         I40E_RESOURCE_WRITE
 374 };
 375
 376 struct i40e_nvm_info {
 377         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 378         u32 timeout;              /* [ms] */
 379         u16 sr_size;              /* Shadow RAM size in words */
 380         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 381         u16 version;              /* NVM package version */
 382         u32 eetrack;              /* NVM data version */
 383         u32 oem_ver;              /* OEM version info */
 384 };
 385
 386 /* definitions used in NVM update support */
 387
 388 enum i40e_nvmupd_cmd {
 389         I40E_NVMUPD_INVALID,
 390         I40E_NVMUPD_READ_CON,
 391         I40E_NVMUPD_READ_SNT,
 392         I40E_NVMUPD_READ_LCB,
 393         I40E_NVMUPD_READ_SA,
 394         I40E_NVMUPD_WRITE_ERA,
 395         I40E_NVMUPD_WRITE_CON,
 396         I40E_NVMUPD_WRITE_SNT,
 397         I40E_NVMUPD_WRITE_LCB,
 398         I40E_NVMUPD_WRITE_SA,
 399         I40E_NVMUPD_CSUM_CON,
 400         I40E_NVMUPD_CSUM_SA,
 401         I40E_NVMUPD_CSUM_LCB,
 402         I40E_NVMUPD_STATUS,
 403         I40E_NVMUPD_EXEC_AQ,
 404         I40E_NVMUPD_GET_AQ_RESULT,
 405 };
 406
 407 enum i40e_nvmupd_state {
 408         I40E_NVMUPD_STATE_INIT,
 409         I40E_NVMUPD_STATE_READING,
 410         I40E_NVMUPD_STATE_WRITING,
 411         I40E_NVMUPD_STATE_INIT_WAIT,
 412         I40E_NVMUPD_STATE_WRITE_WAIT,
 413         I40E_NVMUPD_STATE_ERROR
 414 };
 415
 416 /* nvm_access definition and its masks/shifts need to be accessible to
 417  * application, core driver, and shared code.  Where is the right file?
 418  */
 419 #define I40E_NVM_READ   0xB
 420 #define I40E_NVM_WRITE  0xC
 421
 422 #define I40E_NVM_MOD_PNT_MASK 0xFF
 423
 424 #define I40E_NVM_TRANS_SHIFT    8
 425 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 426 #define I40E_NVM_CON            0x0
 427 #define I40E_NVM_SNT            0x1
 428 #define I40E_NVM_LCB            0x2
 429 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 430 #define I40E_NVM_ERA            0x4
 431 #define I40E_NVM_CSUM           0x8
 432 #define I40E_NVM_EXEC           0xf
 433
 434 #define I40E_NVM_ADAPT_SHIFT    16
 435 #define I40E_NVM_ADAPT_MASK     (0xffff << I40E_NVM_ADAPT_SHIFT)
 436
 437 #define I40E_NVMUPD_MAX_DATA    4096
 438 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 439
 440 struct i40e_nvm_access {
 441         u32 command;
 442         u32 config;
 443         u32 offset;     /* in bytes */
 444         u32 data_size;  /* in bytes */
 445         u8 data[1];
 446 };
 447
 448 /* (Q)SFP module access definitions */
 449 #define I40E_I2C_EEPROM_DEV_ADDR        0xA0
 450 #define I40E_I2C_EEPROM_DEV_ADDR2       0xA2
 451 #define I40E_MODULE_TYPE_ADDR           0x00
 452 #define I40E_MODULE_REVISION_ADDR       0x01
 453 #define I40E_MODULE_SFF_8472_COMP       0x5E
 454 #define I40E_MODULE_SFF_8472_SWAP       0x5C
 455 #define I40E_MODULE_SFF_ADDR_MODE       0x04
 456 #define I40E_MODULE_TYPE_QSFP_PLUS      0x0D
 457 #define I40E_MODULE_TYPE_QSFP28         0x11
 458 #define I40E_MODULE_QSFP_MAX_LEN        640
 459
 460 /* PCI bus types */
 461 enum i40e_bus_type {
 462         i40e_bus_type_unknown = 0,
 463         i40e_bus_type_pci,
 464         i40e_bus_type_pcix,
 465         i40e_bus_type_pci_express,
 466         i40e_bus_type_reserved
 467 };
 468
 469 /* PCI bus speeds */
 470 enum i40e_bus_speed {
 471         i40e_bus_speed_unknown  = 0,
 472         i40e_bus_speed_33       = 33,
 473         i40e_bus_speed_66       = 66,
 474         i40e_bus_speed_100      = 100,
 475         i40e_bus_speed_120      = 120,
 476         i40e_bus_speed_133      = 133,
 477         i40e_bus_speed_2500     = 2500,
 478         i40e_bus_speed_5000     = 5000,
 479         i40e_bus_speed_8000     = 8000,
 480         i40e_bus_speed_reserved
 481 };
 482
 483 /* PCI bus widths */
 484 enum i40e_bus_width {
 485         i40e_bus_width_unknown  = 0,
 486         i40e_bus_width_pcie_x1  = 1,
 487         i40e_bus_width_pcie_x2  = 2,
 488         i40e_bus_width_pcie_x4  = 4,
 489         i40e_bus_width_pcie_x8  = 8,
 490         i40e_bus_width_32       = 32,
 491         i40e_bus_width_64       = 64,
 492         i40e_bus_width_reserved
 493 };
 494
 495 /* Bus parameters */
 496 struct i40e_bus_info {
 497         enum i40e_bus_speed speed;
 498         enum i40e_bus_width width;
 499         enum i40e_bus_type type;
 500
 501         u16 func;
 502         u16 device;
 503         u16 lan_id;
 504         u16 bus_id;
 505 };
 506
 507 /* Flow control (FC) parameters */
 508 struct i40e_fc_info {
 509         enum i40e_fc_mode current_mode; /* FC mode in effect */
 510         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 511 };
 512
 513 #define I40E_MAX_TRAFFIC_CLASS          8
 514 #define I40E_MAX_USER_PRIORITY          8
 515 #define I40E_DCBX_MAX_APPS              32
 516 #define I40E_LLDPDU_SIZE                1500
 517 #define I40E_TLV_STATUS_OPER            0x1
 518 #define I40E_TLV_STATUS_SYNC            0x2
 519 #define I40E_TLV_STATUS_ERR             0x4
 520 #define I40E_CEE_OPER_MAX_APPS          3
 521 #define I40E_APP_PROTOID_FCOE           0x8906
 522 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 523 #define I40E_APP_PROTOID_FIP            0x8914
 524 #define I40E_APP_SEL_ETHTYPE            0x1
 525 #define I40E_APP_SEL_TCPIP              0x2
 526 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 527 #define I40E_CEE_APP_SEL_TCPIP          0x1
 528
 529 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 530 struct i40e_dcb_ets_config {
 531         u8 willing;
 532         u8 cbs;
 533         u8 maxtcs;
 534         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 535         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 536         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 537 };
 538
 539 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 540 struct i40e_dcb_pfc_config {
 541         u8 willing;
 542         u8 mbc;
 543         u8 pfccap;
 544         u8 pfcenable;
 545 };
 546
 547 /* CEE or IEEE 802.1Qaz Application Priority data */
 548 struct i40e_dcb_app_priority_table {
 549         u8  priority;
 550         u8  selector;
 551         u16 protocolid;
 552 };
 553
 554 struct i40e_dcbx_config {
 555         u8  dcbx_mode;
 556 #define I40E_DCBX_MODE_CEE      0x1
 557 #define I40E_DCBX_MODE_IEEE     0x2
 558         u8  app_mode;
 559 #define I40E_DCBX_APPS_NON_WILLING      0x1
 560         u32 numapps;
 561         u32 tlv_status; /* CEE mode TLV status */
 562         struct i40e_dcb_ets_config etscfg;
 563         struct i40e_dcb_ets_config etsrec;
 564         struct i40e_dcb_pfc_config pfc;
 565         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 566 };
 567
 568 /* Port hardware description */
 569 struct i40e_hw {
 570         u8 __iomem *hw_addr;
 571         void *back;
 572
 573         /* subsystem structs */
 574         struct i40e_phy_info phy;
 575         struct i40e_mac_info mac;
 576         struct i40e_bus_info bus;
 577         struct i40e_nvm_info nvm;
 578         struct i40e_fc_info fc;
 579
 580         /* pci info */
 581         u16 device_id;
 582         u16 vendor_id;
 583         u16 subsystem_device_id;
 584         u16 subsystem_vendor_id;
 585         u8 revision_id;
 586         u8 port;
 587         bool adapter_stopped;
 588
 589         /* capabilities for entire device and PCI func */
 590         struct i40e_hw_capabilities dev_caps;
 591         struct i40e_hw_capabilities func_caps;
 592
 593         /* Flow Director shared filter space */
 594         u16 fdir_shared_filter_count;
 595
 596         /* device profile info */
 597         u8  pf_id;
 598         u16 main_vsi_seid;
 599
 600         /* for multi-function MACs */
 601         u16 partition_id;
 602         u16 num_partitions;
 603         u16 num_ports;
 604
 605         /* Closest numa node to the device */
 606         u16 numa_node;
 607
 608         /* Admin Queue info */
 609         struct i40e_adminq_info aq;
 610
 611         /* state of nvm update process */
 612         enum i40e_nvmupd_state nvmupd_state;
 613         struct i40e_aq_desc nvm_wb_desc;
 614         struct i40e_virt_mem nvm_buff;
 615         bool nvm_release_on_done;
 616         u16 nvm_wait_opcode;
 617
 618         /* HMC info */
 619         struct i40e_hmc_info hmc; /* HMC info struct */
 620
 621         /* LLDP/DCBX Status */
 622         u16 dcbx_status;
 623
 624         /* DCBX info */
 625         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 626         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 627         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 628
 629 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 630 #define I40E_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)
 631 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
 632 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
 633         u64 flags;
 634
 635         /* Used in set switch config AQ command */
 636         u16 switch_tag;
 637         u16 first_tag;
 638         u16 second_tag;
 639
 640         /* debug mask */
 641         u32 debug_mask;
 642         char err_str[16];
 643 };
 644
 645 static inline bool i40e_is_vf(struct i40e_hw *hw)
 646 {
 647         return (hw->mac.type == I40E_MAC_VF ||
 648                 hw->mac.type == I40E_MAC_X722_VF);
 649 }
 650
 651 struct i40e_driver_version {
 652         u8 major_version;
 653         u8 minor_version;
 654         u8 build_version;
 655         u8 subbuild_version;
 656         u8 driver_string[32];
 657 };
 658
 659 /* RX Descriptors */
 660 union i40e_16byte_rx_desc {
 661         struct {
 662                 __le64 pkt_addr; /* Packet buffer address */
 663                 __le64 hdr_addr; /* Header buffer address */
 664         } read;
 665         struct {
 666                 struct {
 667                         struct {
 668                                 union {
 669                                         __le16 mirroring_status;
 670                                         __le16 fcoe_ctx_id;
 671                                 } mirr_fcoe;
 672                                 __le16 l2tag1;
 673                         } lo_dword;
 674                         union {
 675                                 __le32 rss; /* RSS Hash */
 676                                 __le32 fd_id; /* Flow director filter id */
 677                                 __le32 fcoe_param; /* FCoE DDP Context id */
 678                         } hi_dword;
 679                 } qword0;
 680                 struct {
 681                         /* ext status/error/pktype/length */
 682                         __le64 status_error_len;
 683                 } qword1;
 684         } wb;  /* writeback */
 685 };
 686
 687 union i40e_32byte_rx_desc {
 688         struct {
 689                 __le64  pkt_addr; /* Packet buffer address */
 690                 __le64  hdr_addr; /* Header buffer address */
 691                         /* bit 0 of hdr_buffer_addr is DD bit */
 692                 __le64  rsvd1;
 693                 __le64  rsvd2;
 694         } read;
 695         struct {
 696                 struct {
 697                         struct {
 698                                 union {
 699                                         __le16 mirroring_status;
 700                                         __le16 fcoe_ctx_id;
 701                                 } mirr_fcoe;
 702                                 __le16 l2tag1;
 703                         } lo_dword;
 704                         union {
 705                                 __le32 rss; /* RSS Hash */
 706                                 __le32 fcoe_param; /* FCoE DDP Context id */
 707                                 /* Flow director filter id in case of
 708                                  * Programming status desc WB
 709                                  */
 710                                 __le32 fd_id;
 711                         } hi_dword;
 712                 } qword0;
 713                 struct {
 714                         /* status/error/pktype/length */
 715                         __le64 status_error_len;
 716                 } qword1;
 717                 struct {
 718                         __le16 ext_status; /* extended status */
 719                         __le16 rsvd;
 720                         __le16 l2tag2_1;
 721                         __le16 l2tag2_2;
 722                 } qword2;
 723                 struct {
 724                         union {
 725                                 __le32 flex_bytes_lo;
 726                                 __le32 pe_status;
 727                         } lo_dword;
 728                         union {
 729                                 __le32 flex_bytes_hi;
 730                                 __le32 fd_id;
 731                         } hi_dword;
 732                 } qword3;
 733         } wb;  /* writeback */
 734 };
 735
 736 enum i40e_rx_desc_status_bits {
 737         /* Note: These are predefined bit offsets */
 738         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 739         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 740         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 741         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 742         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 743         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 744         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 745         /* Note: Bit 8 is reserved in X710 and XL710 */
 746         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 747         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 748         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 749         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 750         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 751         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 752         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 753         /* Note: For non-tunnel packets INT_UDP_0 is the right status for
 754          * UDP header
 755          */
 756         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 757         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 758 };
 759
 760 #define I40E_RXD_QW1_STATUS_SHIFT       0
 761 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
 762                                          << I40E_RXD_QW1_STATUS_SHIFT)
 763
 764 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 765 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 766                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 767
 768 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 769 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
 770                                     BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 771
 772 enum i40e_rx_desc_fltstat_values {
 773         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 774         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 775         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 776         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 777 };
 778
 779 #define I40E_RXD_QW1_ERROR_SHIFT        19
 780 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 781
 782 enum i40e_rx_desc_error_bits {
 783         /* Note: These are predefined bit offsets */
 784         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 785         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 786         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 787         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 788         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 789         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 790         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 791         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 792         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 793 };
 794
 795 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 796         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 797         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 798         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 799         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 800         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 801 };
 802
 803 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 804 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 805
 806 /* Packet type non-ip values */
 807 enum i40e_rx_l2_ptype {
 808         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 809         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 810         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 811         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 812         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 813         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 814         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 815         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 816         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 817         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 818         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 819         I40E_RX_PTYPE_L2_ARP                            = 11,
 820         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 821         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 822         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 823         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 824         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 825         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 826         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 827         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 828         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 829         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 830         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 831         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 832         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 833         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 834 };
 835
 836 struct i40e_rx_ptype_decoded {
 837         u32 ptype:8;
 838         u32 known:1;
 839         u32 outer_ip:1;
 840         u32 outer_ip_ver:1;
 841         u32 outer_frag:1;
 842         u32 tunnel_type:3;
 843         u32 tunnel_end_prot:2;
 844         u32 tunnel_end_frag:1;
 845         u32 inner_prot:4;
 846         u32 payload_layer:3;
 847 };
 848
 849 enum i40e_rx_ptype_outer_ip {
 850         I40E_RX_PTYPE_OUTER_L2  = 0,
 851         I40E_RX_PTYPE_OUTER_IP  = 1
 852 };
 853
 854 enum i40e_rx_ptype_outer_ip_ver {
 855         I40E_RX_PTYPE_OUTER_NONE        = 0,
 856         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 857         I40E_RX_PTYPE_OUTER_IPV6        = 1
 858 };
 859
 860 enum i40e_rx_ptype_outer_fragmented {
 861         I40E_RX_PTYPE_NOT_FRAG  = 0,
 862         I40E_RX_PTYPE_FRAG      = 1
 863 };
 864
 865 enum i40e_rx_ptype_tunnel_type {
 866         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 867         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 868         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 869         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 870         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 871 };
 872
 873 enum i40e_rx_ptype_tunnel_end_prot {
 874         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 875         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 876         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 877 };
 878
 879 enum i40e_rx_ptype_inner_prot {
 880         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 881         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 882         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 883         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 884         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 885         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 886 };
 887
 888 enum i40e_rx_ptype_payload_layer {
 889         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 890         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 891         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 892         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 893 };
 894
 895 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 896 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 897                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 898
 899 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 900 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 901                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 902
 903 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 904 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 905
 906 enum i40e_rx_desc_ext_status_bits {
 907         /* Note: These are predefined bit offsets */
 908         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 909         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 910         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 911         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 912         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 913         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 914         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 915 };
 916
 917 enum i40e_rx_desc_pe_status_bits {
 918         /* Note: These are predefined bit offsets */
 919         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 920         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 921         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 922         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 923         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 924         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 925         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 926         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 927         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 928 };
 929
 930 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 931 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 932
 933 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 934 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 935                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 936
 937 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 938 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 939                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 940
 941 enum i40e_rx_prog_status_desc_status_bits {
 942         /* Note: These are predefined bit offsets */
 943         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 944         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 945 };
 946
 947 enum i40e_rx_prog_status_desc_prog_id_masks {
 948         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 949         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 950         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 951 };
 952
 953 enum i40e_rx_prog_status_desc_error_bits {
 954         /* Note: These are predefined bit offsets */
 955         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 956         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 957         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 958         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 959 };
 960
 961 /* TX Descriptor */
 962 struct i40e_tx_desc {
 963         __le64 buffer_addr; /* Address of descriptor's data buf */
 964         __le64 cmd_type_offset_bsz;
 965 };
 966
 967 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 968 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 969
 970 enum i40e_tx_desc_dtype_value {
 971         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 972         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 973         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 974         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 975         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 976         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 977         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 978         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 979         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 980         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 981 };
 982
 983 #define I40E_TXD_QW1_CMD_SHIFT  4
 984 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 985
 986 enum i40e_tx_desc_cmd_bits {
 987         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 988         I40E_TX_DESC_CMD_RS                     = 0x0002,
 989         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 990         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 991         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 992         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 993         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 994         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 995         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 996         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 997         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 998         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 999         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1000         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1001         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1002         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1003         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1004         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1005 };
1006
1007 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1008 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1009                                          I40E_TXD_QW1_OFFSET_SHIFT)
1010
1011 enum i40e_tx_desc_length_fields {
1012         /* Note: These are predefined bit offsets */
1013         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1014         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1015         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1016 };
1017
1018 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1019 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1020                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1021
1022 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1023 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1024
1025 /* Context descriptors */
1026 struct i40e_tx_context_desc {
1027         __le32 tunneling_params;
1028         __le16 l2tag2;
1029         __le16 rsvd;
1030         __le64 type_cmd_tso_mss;
1031 };
1032
1033 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1034 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1035
1036 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1037 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1038
1039 enum i40e_tx_ctx_desc_cmd_bits {
1040         I40E_TX_CTX_DESC_TSO            = 0x01,
1041         I40E_TX_CTX_DESC_TSYN           = 0x02,
1042         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1043         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1044         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1045         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1046         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1047         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1048         I40E_TX_CTX_DESC_SWPE           = 0x40
1049 };
1050
1051 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1052 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1053                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1054
1055 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1056 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1057                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1058
1059 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1060 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1061
1062 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1063 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1064                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1065
1066 enum i40e_tx_ctx_desc_eipt_offload {
1067         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1068         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1069         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1070         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1071 };
1072
1073 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1074 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1075                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1076
1077 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1078 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1079
1080 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1081 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1082
1083 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1084 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
1085                                        BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1086
1087 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1088
1089 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1090 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1091                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1092
1093 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1094 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1095                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1096
1097 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1098 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1099 struct i40e_filter_program_desc {
1100         __le32 qindex_flex_ptype_vsi;
1101         __le32 rsvd;
1102         __le32 dtype_cmd_cntindex;
1103         __le32 fd_id;
1104 };
1105 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1106 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1107                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1108 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1109 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1110                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1111 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1112 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1113                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1114
1115 /* Packet Classifier Types for filters */
1116 enum i40e_filter_pctype {
1117         /* Note: Values 0-28 are reserved for future use.
1118          * Value 29, 30, 32 are not supported on XL710 and X710.
1119          */
1120         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1121         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1122         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1123         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1124         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1125         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1126         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1127         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1128         /* Note: Values 37-38 are reserved for future use.
1129          * Value 39, 40, 42 are not supported on XL710 and X710.
1130          */
1131         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1132         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1133         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1134         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1135         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1136         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1137         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1138         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1139         /* Note: Value 47 is reserved for future use */
1140         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1141         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1142         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1143         /* Note: Values 51-62 are reserved for future use */
1144         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1145 };
1146
1147 enum i40e_filter_program_desc_dest {
1148         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1149         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1150         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1151 };
1152
1153 enum i40e_filter_program_desc_fd_status {
1154         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1155         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1156         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1157         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1158 };
1159
1160 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1161 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1162                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1163
1164 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1165 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1166                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1167
1168 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1169 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1170
1171 enum i40e_filter_program_desc_pcmd {
1172         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1173         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1174 };
1175
1176 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1177 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1178
1179 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1180 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1181
1182 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1183                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1184 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1185                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1186
1187 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1188                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1189 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1190
1191 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1192                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1193 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1194
1195 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1196 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1197                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1198
1199 enum i40e_filter_type {
1200         I40E_FLOW_DIRECTOR_FLTR = 0,
1201         I40E_PE_QUAD_HASH_FLTR = 1,
1202         I40E_ETHERTYPE_FLTR,
1203         I40E_FCOE_CTX_FLTR,
1204         I40E_MAC_VLAN_FLTR,
1205         I40E_HASH_FLTR
1206 };
1207
1208 struct i40e_vsi_context {
1209         u16 seid;
1210         u16 uplink_seid;
1211         u16 vsi_number;
1212         u16 vsis_allocated;
1213         u16 vsis_unallocated;
1214         u16 flags;
1215         u8 pf_num;
1216         u8 vf_num;
1217         u8 connection_type;
1218         struct i40e_aqc_vsi_properties_data info;
1219 };
1220
1221 struct i40e_veb_context {
1222         u16 seid;
1223         u16 uplink_seid;
1224         u16 veb_number;
1225         u16 vebs_allocated;
1226         u16 vebs_unallocated;
1227         u16 flags;
1228         struct i40e_aqc_get_veb_parameters_completion info;
1229 };
1230
1231 /* Statistics collected by each port, VSI, VEB, and S-channel */
1232 struct i40e_eth_stats {
1233         u64 rx_bytes;                   /* gorc */
1234         u64 rx_unicast;                 /* uprc */
1235         u64 rx_multicast;               /* mprc */
1236         u64 rx_broadcast;               /* bprc */
1237         u64 rx_discards;                /* rdpc */
1238         u64 rx_unknown_protocol;        /* rupp */
1239         u64 tx_bytes;                   /* gotc */
1240         u64 tx_unicast;                 /* uptc */
1241         u64 tx_multicast;               /* mptc */
1242         u64 tx_broadcast;               /* bptc */
1243         u64 tx_discards;                /* tdpc */
1244         u64 tx_errors;                  /* tepc */
1245 };
1246
1247 /* Statistics collected per VEB per TC */
1248 struct i40e_veb_tc_stats {
1249         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1250         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1251         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1252         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1253 };
1254
1255 /* Statistics collected by the MAC */
1256 struct i40e_hw_port_stats {
1257         /* eth stats collected by the port */
1258         struct i40e_eth_stats eth;
1259
1260         /* additional port specific stats */
1261         u64 tx_dropped_link_down;       /* tdold */
1262         u64 crc_errors;                 /* crcerrs */
1263         u64 illegal_bytes;              /* illerrc */
1264         u64 error_bytes;                /* errbc */
1265         u64 mac_local_faults;           /* mlfc */
1266         u64 mac_remote_faults;          /* mrfc */
1267         u64 rx_length_errors;           /* rlec */
1268         u64 link_xon_rx;                /* lxonrxc */
1269         u64 link_xoff_rx;               /* lxoffrxc */
1270         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1271         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1272         u64 link_xon_tx;                /* lxontxc */
1273         u64 link_xoff_tx;               /* lxofftxc */
1274         u64 priority_xon_tx[8];         /* pxontxc[8] */
1275         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1276         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1277         u64 rx_size_64;                 /* prc64 */
1278         u64 rx_size_127;                /* prc127 */
1279         u64 rx_size_255;                /* prc255 */
1280         u64 rx_size_511;                /* prc511 */
1281         u64 rx_size_1023;               /* prc1023 */
1282         u64 rx_size_1522;               /* prc1522 */
1283         u64 rx_size_big;                /* prc9522 */
1284         u64 rx_undersize;               /* ruc */
1285         u64 rx_fragments;               /* rfc */
1286         u64 rx_oversize;                /* roc */
1287         u64 rx_jabber;                  /* rjc */
1288         u64 tx_size_64;                 /* ptc64 */
1289         u64 tx_size_127;                /* ptc127 */
1290         u64 tx_size_255;                /* ptc255 */
1291         u64 tx_size_511;                /* ptc511 */
1292         u64 tx_size_1023;               /* ptc1023 */
1293         u64 tx_size_1522;               /* ptc1522 */
1294         u64 tx_size_big;                /* ptc9522 */
1295         u64 mac_short_packet_dropped;   /* mspdc */
1296         u64 checksum_error;             /* xec */
1297         /* flow director stats */
1298         u64 fd_atr_match;
1299         u64 fd_sb_match;
1300         u64 fd_atr_tunnel_match;
1301         u32 fd_atr_status;
1302         u32 fd_sb_status;
1303         /* EEE LPI */
1304         u32 tx_lpi_status;
1305         u32 rx_lpi_status;
1306         u64 tx_lpi_count;               /* etlpic */
1307         u64 rx_lpi_count;               /* erlpic */
1308 };
1309
1310 /* Checksum and Shadow RAM pointers */
1311 #define I40E_SR_NVM_CONTROL_WORD                0x00
1312 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1313 #define I40E_SR_PBA_FLAGS                       0x15
1314 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1315 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1316 #define I40E_NVM_OEM_VER_OFF                    0x83
1317 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1318 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1319 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1320 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1321 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1322 #define I40E_SR_VPD_PTR                         0x2F
1323 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1324 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1325
1326 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1327 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1328 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1329 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1330 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1331
1332 /* Shadow RAM related */
1333 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1334 #define I40E_SR_WORDS_IN_1KB            512
1335 /* Checksum should be calculated such that after adding all the words,
1336  * including the checksum word itself, the sum should be 0xBABA.
1337  */
1338 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1339
1340 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1341
1342 enum i40e_switch_element_types {
1343         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1344         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1345         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1346         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1347         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1348         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1349         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1350         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1351         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1352 };
1353
1354 /* Supported EtherType filters */
1355 enum i40e_ether_type_index {
1356         I40E_ETHER_TYPE_1588            = 0,
1357         I40E_ETHER_TYPE_FIP             = 1,
1358         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1359         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1360         I40E_ETHER_TYPE_LLDP            = 4,
1361         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1362         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1363         I40E_ETHER_TYPE_QCN_CNM         = 7,
1364         I40E_ETHER_TYPE_8021X           = 8,
1365         I40E_ETHER_TYPE_ARP             = 9,
1366         I40E_ETHER_TYPE_RSV1            = 10,
1367         I40E_ETHER_TYPE_RSV2            = 11,
1368 };
1369
1370 /* Filter context base size is 1K */
1371 #define I40E_HASH_FILTER_BASE_SIZE      1024
1372 /* Supported Hash filter values */
1373 enum i40e_hash_filter_size {
1374         I40E_HASH_FILTER_SIZE_1K        = 0,
1375         I40E_HASH_FILTER_SIZE_2K        = 1,
1376         I40E_HASH_FILTER_SIZE_4K        = 2,
1377         I40E_HASH_FILTER_SIZE_8K        = 3,
1378         I40E_HASH_FILTER_SIZE_16K       = 4,
1379         I40E_HASH_FILTER_SIZE_32K       = 5,
1380         I40E_HASH_FILTER_SIZE_64K       = 6,
1381         I40E_HASH_FILTER_SIZE_128K      = 7,
1382         I40E_HASH_FILTER_SIZE_256K      = 8,
1383         I40E_HASH_FILTER_SIZE_512K      = 9,
1384         I40E_HASH_FILTER_SIZE_1M        = 10,
1385 };
1386
1387 /* DMA context base size is 0.5K */
1388 #define I40E_DMA_CNTX_BASE_SIZE         512
1389 /* Supported DMA context values */
1390 enum i40e_dma_cntx_size {
1391         I40E_DMA_CNTX_SIZE_512          = 0,
1392         I40E_DMA_CNTX_SIZE_1K           = 1,
1393         I40E_DMA_CNTX_SIZE_2K           = 2,
1394         I40E_DMA_CNTX_SIZE_4K           = 3,
1395         I40E_DMA_CNTX_SIZE_8K           = 4,
1396         I40E_DMA_CNTX_SIZE_16K          = 5,
1397         I40E_DMA_CNTX_SIZE_32K          = 6,
1398         I40E_DMA_CNTX_SIZE_64K          = 7,
1399         I40E_DMA_CNTX_SIZE_128K         = 8,
1400         I40E_DMA_CNTX_SIZE_256K         = 9,
1401 };
1402
1403 /* Supported Hash look up table (LUT) sizes */
1404 enum i40e_hash_lut_size {
1405         I40E_HASH_LUT_SIZE_128          = 0,
1406         I40E_HASH_LUT_SIZE_512          = 1,
1407 };
1408
1409 /* Structure to hold a per PF filter control settings */
1410 struct i40e_filter_control_settings {
1411         /* number of PE Quad Hash filter buckets */
1412         enum i40e_hash_filter_size pe_filt_num;
1413         /* number of PE Quad Hash contexts */
1414         enum i40e_dma_cntx_size pe_cntx_num;
1415         /* number of FCoE filter buckets */
1416         enum i40e_hash_filter_size fcoe_filt_num;
1417         /* number of FCoE DDP contexts */
1418         enum i40e_dma_cntx_size fcoe_cntx_num;
1419         /* size of the Hash LUT */
1420         enum i40e_hash_lut_size hash_lut_size;
1421         /* enable FDIR filters for PF and its VFs */
1422         bool enable_fdir;
1423         /* enable Ethertype filters for PF and its VFs */
1424         bool enable_ethtype;
1425         /* enable MAC/VLAN filters for PF and its VFs */
1426         bool enable_macvlan;
1427 };
1428
1429 /* Structure to hold device level control filter counts */
1430 struct i40e_control_filter_stats {
1431         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1432         u16 etype_used;       /* Used perfect EtherType filters */
1433         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1434         u16 etype_free;       /* Un-used perfect EtherType filters */
1435 };
1436
1437 enum i40e_reset_type {
1438         I40E_RESET_POR          = 0,
1439         I40E_RESET_CORER        = 1,
1440         I40E_RESET_GLOBR        = 2,
1441         I40E_RESET_EMPR         = 3,
1442 };
1443
1444 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1445 #define I40E_NVM_LLDP_CFG_PTR           0xD
1446 struct i40e_lldp_variables {
1447         u16 length;
1448         u16 adminstatus;
1449         u16 msgfasttx;
1450         u16 msgtxinterval;
1451         u16 txparams;
1452         u16 timers;
1453         u16 crc8;
1454 };
1455
1456 /* Offsets into Alternate Ram */
1457 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1458 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1459 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1460 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1461 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1462 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1463
1464 /* Alternate Ram Bandwidth Masks */
1465 #define I40E_ALT_BW_VALUE_MASK          0xFF
1466 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1467 #define I40E_ALT_BW_VALID_MASK          0x80000000
1468
1469 /* RSS Hash Table Size */
1470 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1471
1472 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1473 #define I40E_L3_SRC_SHIFT               47
1474 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1475 #define I40E_L3_V6_SRC_SHIFT            43
1476 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1477 #define I40E_L3_DST_SHIFT               35
1478 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1479 #define I40E_L3_V6_DST_SHIFT            35
1480 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1481 #define I40E_L4_SRC_SHIFT               34
1482 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1483 #define I40E_L4_DST_SHIFT               33
1484 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1485 #define I40E_VERIFY_TAG_SHIFT           31
1486 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1487
1488 #define I40E_FLEX_50_SHIFT              13
1489 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1490 #define I40E_FLEX_51_SHIFT              12
1491 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1492 #define I40E_FLEX_52_SHIFT              11
1493 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1494 #define I40E_FLEX_53_SHIFT              10
1495 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1496 #define I40E_FLEX_54_SHIFT              9
1497 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1498 #define I40E_FLEX_55_SHIFT              8
1499 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1500 #define I40E_FLEX_56_SHIFT              7
1501 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1502 #define I40E_FLEX_57_SHIFT              6
1503 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1504
1505 /* Version format for PPP */
1506 struct i40e_ppp_version {
1507         u8 major;
1508         u8 minor;
1509         u8 update;
1510         u8 draft;
1511 };
1512
1513 #define I40E_PPP_NAME_SIZE      32
1514
1515 /* Package header */
1516 struct i40e_package_header {
1517         struct i40e_ppp_version version;
1518         u32 segment_count;
1519         u32 segment_offset[1];
1520 };
1521
1522 /* Generic segment header */
1523 struct i40e_generic_seg_header {
1524 #define SEGMENT_TYPE_METADATA   0x00000001
1525 #define SEGMENT_TYPE_NOTES      0x00000002
1526 #define SEGMENT_TYPE_I40E       0x00000011
1527 #define SEGMENT_TYPE_X722       0x00000012
1528         u32 type;
1529         struct i40e_ppp_version version;
1530         u32 size;
1531         char name[I40E_PPP_NAME_SIZE];
1532 };
1533
1534 struct i40e_metadata_segment {
1535         struct i40e_generic_seg_header header;
1536         struct i40e_ppp_version version;
1537         u32 track_id;
1538         char name[I40E_PPP_NAME_SIZE];
1539 };
1540
1541 struct i40e_device_id_entry {
1542         u32 vendor_dev_id;
1543         u32 sub_vendor_dev_id;
1544 };
1545
1546 struct i40e_profile_segment {
1547         struct i40e_generic_seg_header header;
1548         struct i40e_ppp_version version;
1549         char name[I40E_PPP_NAME_SIZE];
1550         u32 device_table_count;
1551         struct i40e_device_id_entry device_table[1];
1552 };
1553
1554 struct i40e_section_table {
1555         u32 section_count;
1556         u32 section_offset[1];
1557 };
1558
1559 struct i40e_profile_section_header {
1560         u16 tbl_size;
1561         u16 data_end;
1562         struct {
1563 #define SECTION_TYPE_INFO       0x00000010
1564 #define SECTION_TYPE_MMIO       0x00000800
1565 #define SECTION_TYPE_AQ         0x00000801
1566 #define SECTION_TYPE_NOTE       0x80000000
1567 #define SECTION_TYPE_NAME       0x80000001
1568                 u32 type;
1569                 u32 offset;
1570                 u32 size;
1571         } section;
1572 };
1573
1574 struct i40e_profile_info {
1575         u32 track_id;
1576         struct i40e_ppp_version version;
1577         u8 op;
1578 #define I40E_PPP_ADD_TRACKID            0x01
1579 #define I40E_PPP_REMOVE_TRACKID 0x02
1580         u8 reserved[7];
1581         u8 name[I40E_PPP_NAME_SIZE];
1582 };
1583 #endif /* _I40E_TYPE_H_ */