1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/etherdevice.h>
7 #include "hclge_main.h"
10 enum hclge_shaper_level {
11 HCLGE_SHAPER_LVL_PRI = 0,
12 HCLGE_SHAPER_LVL_PG = 1,
13 HCLGE_SHAPER_LVL_PORT = 2,
14 HCLGE_SHAPER_LVL_QSET = 3,
15 HCLGE_SHAPER_LVL_CNT = 4,
16 HCLGE_SHAPER_LVL_VF = 0,
17 HCLGE_SHAPER_LVL_PF = 1,
20 #define HCLGE_TM_PFC_PKT_GET_CMD_NUM 3
21 #define HCLGE_TM_PFC_NUM_GET_PER_CMD 3
23 #define HCLGE_SHAPER_BS_U_DEF 5
24 #define HCLGE_SHAPER_BS_S_DEF 20
26 #define HCLGE_ETHER_MAX_RATE 100000
28 /* hclge_shaper_para_calc: calculate ir parameter for the shaper
29 * @ir: Rate to be config, its unit is Mbps
30 * @shaper_level: the shaper level. eg: port, pg, priority, queueset
31 * @ir_b: IR_B parameter of IR shaper
32 * @ir_u: IR_U parameter of IR shaper
33 * @ir_s: IR_S parameter of IR shaper
37 * IR_b * (2 ^ IR_u) * 8
38 * IR(Mbps) = ------------------------- * CLOCK(1000Mbps)
41 * @return: 0: calculate sucessful, negative: fail
43 static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
44 u8 *ir_b, u8 *ir_u, u8 *ir_s)
46 const u16 tick_array[HCLGE_SHAPER_LVL_CNT] = {
47 6 * 256, /* Prioriy level */
48 6 * 32, /* Prioriy group level */
49 6 * 8, /* Port level */
50 6 * 256 /* Qset level */
52 u8 ir_u_calc = 0, ir_s_calc = 0;
57 if (shaper_level >= HCLGE_SHAPER_LVL_CNT)
60 tick = tick_array[shaper_level];
63 * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0
64 * the formula is changed to:
66 * ir_calc = ---------------- * 1000
69 ir_calc = (1008000 + (tick >> 1) - 1) / tick;
77 } else if (ir_calc > ir) {
78 /* Increasing the denominator to select ir_s value */
79 while (ir_calc > ir) {
81 ir_calc = 1008000 / (tick * (1 << ir_s_calc));
87 *ir_b = (ir * tick * (1 << ir_s_calc) + 4000) / 8000;
89 /* Increasing the numerator to select ir_u value */
92 while (ir_calc < ir) {
94 numerator = 1008000 * (1 << ir_u_calc);
95 ir_calc = (numerator + (tick >> 1)) / tick;
101 u32 denominator = (8000 * (1 << --ir_u_calc));
102 *ir_b = (ir * tick + (denominator >> 1)) / denominator;
112 static int hclge_pfc_stats_get(struct hclge_dev *hdev,
113 enum hclge_opcode_type opcode, u64 *stats)
115 struct hclge_desc desc[HCLGE_TM_PFC_PKT_GET_CMD_NUM];
118 if (!(opcode == HCLGE_OPC_QUERY_PFC_RX_PKT_CNT ||
119 opcode == HCLGE_OPC_QUERY_PFC_TX_PKT_CNT))
122 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM; i++) {
123 hclge_cmd_setup_basic_desc(&desc[i], opcode, true);
124 if (i != (HCLGE_TM_PFC_PKT_GET_CMD_NUM - 1))
125 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
127 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
130 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_TM_PFC_PKT_GET_CMD_NUM);
134 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM; i++) {
135 struct hclge_pfc_stats_cmd *pfc_stats =
136 (struct hclge_pfc_stats_cmd *)desc[i].data;
138 for (j = 0; j < HCLGE_TM_PFC_NUM_GET_PER_CMD; j++) {
139 u32 index = i * HCLGE_TM_PFC_PKT_GET_CMD_NUM + j;
141 if (index < HCLGE_MAX_TC_NUM)
143 le64_to_cpu(pfc_stats->pkt_num[j]);
149 int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats)
151 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_RX_PKT_CNT, stats);
154 int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats)
156 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_TX_PKT_CNT, stats);
159 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx)
161 struct hclge_desc desc;
163 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PAUSE_EN, false);
165 desc.data[0] = cpu_to_le32((tx ? HCLGE_TX_MAC_PAUSE_EN_MSK : 0) |
166 (rx ? HCLGE_RX_MAC_PAUSE_EN_MSK : 0));
168 return hclge_cmd_send(&hdev->hw, &desc, 1);
171 static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
174 struct hclge_desc desc;
175 struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)desc.data;
177 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PFC_PAUSE_EN, false);
179 pfc->tx_rx_en_bitmap = tx_rx_bitmap;
180 pfc->pri_en_bitmap = pfc_bitmap;
182 return hclge_cmd_send(&hdev->hw, &desc, 1);
185 static int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr,
186 u8 pause_trans_gap, u16 pause_trans_time)
188 struct hclge_cfg_pause_param_cmd *pause_param;
189 struct hclge_desc desc;
191 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
193 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, false);
195 ether_addr_copy(pause_param->mac_addr, addr);
196 ether_addr_copy(pause_param->mac_addr_extra, addr);
197 pause_param->pause_trans_gap = pause_trans_gap;
198 pause_param->pause_trans_time = cpu_to_le16(pause_trans_time);
200 return hclge_cmd_send(&hdev->hw, &desc, 1);
203 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr)
205 struct hclge_cfg_pause_param_cmd *pause_param;
206 struct hclge_desc desc;
211 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
213 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true);
215 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
219 trans_gap = pause_param->pause_trans_gap;
220 trans_time = le16_to_cpu(pause_param->pause_trans_time);
222 return hclge_pause_param_cfg(hdev, mac_addr, trans_gap,
226 static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id)
230 tc = hdev->tm_info.prio_tc[pri_id];
232 if (tc >= hdev->tm_info.num_tc)
236 * the register for priority has four bytes, the first bytes includes
237 * priority0 and priority1, the higher 4bit stands for priority1
238 * while the lower 4bit stands for priority0, as below:
239 * first byte: | pri_1 | pri_0 |
240 * second byte: | pri_3 | pri_2 |
241 * third byte: | pri_5 | pri_4 |
242 * fourth byte: | pri_7 | pri_6 |
244 pri[pri_id >> 1] |= tc << ((pri_id & 1) * 4);
249 static int hclge_up_to_tc_map(struct hclge_dev *hdev)
251 struct hclge_desc desc;
252 u8 *pri = (u8 *)desc.data;
256 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, false);
258 for (pri_id = 0; pri_id < HNAE3_MAX_USER_PRIO; pri_id++) {
259 ret = hclge_fill_pri_array(hdev, pri, pri_id);
264 return hclge_cmd_send(&hdev->hw, &desc, 1);
267 static int hclge_tm_pg_to_pri_map_cfg(struct hclge_dev *hdev,
268 u8 pg_id, u8 pri_bit_map)
270 struct hclge_pg_to_pri_link_cmd *map;
271 struct hclge_desc desc;
273 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_TO_PRI_LINK, false);
275 map = (struct hclge_pg_to_pri_link_cmd *)desc.data;
278 map->pri_bit_map = pri_bit_map;
280 return hclge_cmd_send(&hdev->hw, &desc, 1);
283 static int hclge_tm_qs_to_pri_map_cfg(struct hclge_dev *hdev,
286 struct hclge_qs_to_pri_link_cmd *map;
287 struct hclge_desc desc;
289 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_TO_PRI_LINK, false);
291 map = (struct hclge_qs_to_pri_link_cmd *)desc.data;
293 map->qs_id = cpu_to_le16(qs_id);
295 map->link_vld = HCLGE_TM_QS_PRI_LINK_VLD_MSK;
297 return hclge_cmd_send(&hdev->hw, &desc, 1);
300 static int hclge_tm_q_to_qs_map_cfg(struct hclge_dev *hdev,
303 struct hclge_nq_to_qs_link_cmd *map;
304 struct hclge_desc desc;
306 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NQ_TO_QS_LINK, false);
308 map = (struct hclge_nq_to_qs_link_cmd *)desc.data;
310 map->nq_id = cpu_to_le16(q_id);
311 map->qset_id = cpu_to_le16(qs_id | HCLGE_TM_Q_QS_LINK_VLD_MSK);
313 return hclge_cmd_send(&hdev->hw, &desc, 1);
316 static int hclge_tm_pg_weight_cfg(struct hclge_dev *hdev, u8 pg_id,
319 struct hclge_pg_weight_cmd *weight;
320 struct hclge_desc desc;
322 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_WEIGHT, false);
324 weight = (struct hclge_pg_weight_cmd *)desc.data;
326 weight->pg_id = pg_id;
329 return hclge_cmd_send(&hdev->hw, &desc, 1);
332 static int hclge_tm_pri_weight_cfg(struct hclge_dev *hdev, u8 pri_id,
335 struct hclge_priority_weight_cmd *weight;
336 struct hclge_desc desc;
338 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_WEIGHT, false);
340 weight = (struct hclge_priority_weight_cmd *)desc.data;
342 weight->pri_id = pri_id;
345 return hclge_cmd_send(&hdev->hw, &desc, 1);
348 static int hclge_tm_qs_weight_cfg(struct hclge_dev *hdev, u16 qs_id,
351 struct hclge_qs_weight_cmd *weight;
352 struct hclge_desc desc;
354 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_WEIGHT, false);
356 weight = (struct hclge_qs_weight_cmd *)desc.data;
358 weight->qs_id = cpu_to_le16(qs_id);
361 return hclge_cmd_send(&hdev->hw, &desc, 1);
364 static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev,
365 enum hclge_shap_bucket bucket, u8 pg_id,
366 u8 ir_b, u8 ir_u, u8 ir_s, u8 bs_b, u8 bs_s)
368 struct hclge_pg_shapping_cmd *shap_cfg_cmd;
369 enum hclge_opcode_type opcode;
370 struct hclge_desc desc;
371 u32 shapping_para = 0;
373 opcode = bucket ? HCLGE_OPC_TM_PG_P_SHAPPING :
374 HCLGE_OPC_TM_PG_C_SHAPPING;
375 hclge_cmd_setup_basic_desc(&desc, opcode, false);
377 shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data;
379 shap_cfg_cmd->pg_id = pg_id;
381 hclge_tm_set_field(shapping_para, IR_B, ir_b);
382 hclge_tm_set_field(shapping_para, IR_U, ir_u);
383 hclge_tm_set_field(shapping_para, IR_S, ir_s);
384 hclge_tm_set_field(shapping_para, BS_B, bs_b);
385 hclge_tm_set_field(shapping_para, BS_S, bs_s);
387 shap_cfg_cmd->pg_shapping_para = cpu_to_le32(shapping_para);
389 return hclge_cmd_send(&hdev->hw, &desc, 1);
392 static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev)
394 struct hclge_port_shapping_cmd *shap_cfg_cmd;
395 struct hclge_desc desc;
396 u32 shapping_para = 0;
400 ret = hclge_shaper_para_calc(HCLGE_ETHER_MAX_RATE,
401 HCLGE_SHAPER_LVL_PORT,
402 &ir_b, &ir_u, &ir_s);
406 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PORT_SHAPPING, false);
407 shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data;
409 hclge_tm_set_field(shapping_para, IR_B, ir_b);
410 hclge_tm_set_field(shapping_para, IR_U, ir_u);
411 hclge_tm_set_field(shapping_para, IR_S, ir_s);
412 hclge_tm_set_field(shapping_para, BS_B, HCLGE_SHAPER_BS_U_DEF);
413 hclge_tm_set_field(shapping_para, BS_S, HCLGE_SHAPER_BS_S_DEF);
415 shap_cfg_cmd->port_shapping_para = cpu_to_le32(shapping_para);
417 return hclge_cmd_send(&hdev->hw, &desc, 1);
420 static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev,
421 enum hclge_shap_bucket bucket, u8 pri_id,
422 u8 ir_b, u8 ir_u, u8 ir_s,
425 struct hclge_pri_shapping_cmd *shap_cfg_cmd;
426 enum hclge_opcode_type opcode;
427 struct hclge_desc desc;
428 u32 shapping_para = 0;
430 opcode = bucket ? HCLGE_OPC_TM_PRI_P_SHAPPING :
431 HCLGE_OPC_TM_PRI_C_SHAPPING;
433 hclge_cmd_setup_basic_desc(&desc, opcode, false);
435 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data;
437 shap_cfg_cmd->pri_id = pri_id;
439 hclge_tm_set_field(shapping_para, IR_B, ir_b);
440 hclge_tm_set_field(shapping_para, IR_U, ir_u);
441 hclge_tm_set_field(shapping_para, IR_S, ir_s);
442 hclge_tm_set_field(shapping_para, BS_B, bs_b);
443 hclge_tm_set_field(shapping_para, BS_S, bs_s);
445 shap_cfg_cmd->pri_shapping_para = cpu_to_le32(shapping_para);
447 return hclge_cmd_send(&hdev->hw, &desc, 1);
450 static int hclge_tm_pg_schd_mode_cfg(struct hclge_dev *hdev, u8 pg_id)
452 struct hclge_desc desc;
454 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_SCH_MODE_CFG, false);
456 if (hdev->tm_info.pg_info[pg_id].pg_sch_mode == HCLGE_SCH_MODE_DWRR)
457 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
461 desc.data[0] = cpu_to_le32(pg_id);
463 return hclge_cmd_send(&hdev->hw, &desc, 1);
466 static int hclge_tm_pri_schd_mode_cfg(struct hclge_dev *hdev, u8 pri_id)
468 struct hclge_desc desc;
470 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_SCH_MODE_CFG, false);
472 if (hdev->tm_info.tc_info[pri_id].tc_sch_mode == HCLGE_SCH_MODE_DWRR)
473 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
477 desc.data[0] = cpu_to_le32(pri_id);
479 return hclge_cmd_send(&hdev->hw, &desc, 1);
482 static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id, u8 mode)
484 struct hclge_desc desc;
486 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, false);
488 if (mode == HCLGE_SCH_MODE_DWRR)
489 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
493 desc.data[0] = cpu_to_le32(qs_id);
495 return hclge_cmd_send(&hdev->hw, &desc, 1);
498 static int hclge_tm_qs_bp_cfg(struct hclge_dev *hdev, u8 tc, u8 grp_id,
501 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd;
502 struct hclge_desc desc;
504 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_BP_TO_QSET_MAPPING,
507 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data;
509 bp_to_qs_map_cmd->tc_id = tc;
510 bp_to_qs_map_cmd->qs_group_id = grp_id;
511 bp_to_qs_map_cmd->qs_bit_map = cpu_to_le32(bit_map);
513 return hclge_cmd_send(&hdev->hw, &desc, 1);
516 static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport)
518 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
519 struct hclge_dev *hdev = vport->back;
522 vport->bw_limit = hdev->tm_info.pg_info[0].bw_limit;
524 min_t(u16, kinfo->num_tqps, hdev->tm_info.num_tc);
526 = min_t(u16, hdev->rss_size_max,
527 kinfo->num_tqps / kinfo->num_tc);
528 vport->qs_offset = hdev->tm_info.num_tc * vport->vport_id;
529 vport->dwrr = 100; /* 100 percent as init */
530 vport->alloc_rss_size = kinfo->rss_size;
532 for (i = 0; i < kinfo->num_tc; i++) {
533 if (hdev->hw_tc_map & BIT(i)) {
534 kinfo->tc_info[i].enable = true;
535 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
536 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
537 kinfo->tc_info[i].tc = i;
539 /* Set to default queue if TC is disable */
540 kinfo->tc_info[i].enable = false;
541 kinfo->tc_info[i].tqp_offset = 0;
542 kinfo->tc_info[i].tqp_count = 1;
543 kinfo->tc_info[i].tc = 0;
547 memcpy(kinfo->prio_tc, hdev->tm_info.prio_tc,
548 FIELD_SIZEOF(struct hnae3_knic_private_info, prio_tc));
551 static void hclge_tm_vport_info_update(struct hclge_dev *hdev)
553 struct hclge_vport *vport = hdev->vport;
556 for (i = 0; i < hdev->num_alloc_vport; i++) {
557 hclge_tm_vport_tc_info_update(vport);
563 static void hclge_tm_tc_info_init(struct hclge_dev *hdev)
567 for (i = 0; i < hdev->tm_info.num_tc; i++) {
568 hdev->tm_info.tc_info[i].tc_id = i;
569 hdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR;
570 hdev->tm_info.tc_info[i].pgid = 0;
571 hdev->tm_info.tc_info[i].bw_limit =
572 hdev->tm_info.pg_info[0].bw_limit;
575 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
576 hdev->tm_info.prio_tc[i] =
577 (i >= hdev->tm_info.num_tc) ? 0 : i;
579 /* DCB is enabled if we have more than 1 TC */
580 if (hdev->tm_info.num_tc > 1)
581 hdev->flag |= HCLGE_FLAG_DCB_ENABLE;
583 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;
586 static void hclge_tm_pg_info_init(struct hclge_dev *hdev)
590 for (i = 0; i < hdev->tm_info.num_pg; i++) {
593 hdev->tm_info.pg_dwrr[i] = i ? 0 : 100;
595 hdev->tm_info.pg_info[i].pg_id = i;
596 hdev->tm_info.pg_info[i].pg_sch_mode = HCLGE_SCH_MODE_DWRR;
598 hdev->tm_info.pg_info[i].bw_limit = HCLGE_ETHER_MAX_RATE;
603 hdev->tm_info.pg_info[i].tc_bit_map = hdev->hw_tc_map;
604 for (k = 0; k < hdev->tm_info.num_tc; k++)
605 hdev->tm_info.pg_info[i].tc_dwrr[k] = 100;
609 static void hclge_pfc_info_init(struct hclge_dev *hdev)
611 if (!(hdev->flag & HCLGE_FLAG_DCB_ENABLE)) {
612 if (hdev->fc_mode_last_time == HCLGE_FC_PFC)
613 dev_warn(&hdev->pdev->dev,
614 "DCB is disable, but last mode is FC_PFC\n");
616 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
617 } else if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) {
618 /* fc_mode_last_time record the last fc_mode when
619 * DCB is enabled, so that fc_mode can be set to
620 * the correct value when DCB is disabled.
622 hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
623 hdev->tm_info.fc_mode = HCLGE_FC_PFC;
627 static int hclge_tm_schd_info_init(struct hclge_dev *hdev)
629 if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) &&
630 (hdev->tm_info.num_pg != 1))
633 hclge_tm_pg_info_init(hdev);
635 hclge_tm_tc_info_init(hdev);
637 hclge_tm_vport_info_update(hdev);
639 hclge_pfc_info_init(hdev);
644 static int hclge_tm_pg_to_pri_map(struct hclge_dev *hdev)
649 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
652 for (i = 0; i < hdev->tm_info.num_pg; i++) {
654 ret = hclge_tm_pg_to_pri_map_cfg(
655 hdev, i, hdev->tm_info.pg_info[i].tc_bit_map);
663 static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev)
670 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
674 for (i = 0; i < hdev->tm_info.num_pg; i++) {
675 /* Calc shaper para */
676 ret = hclge_shaper_para_calc(
677 hdev->tm_info.pg_info[i].bw_limit,
679 &ir_b, &ir_u, &ir_s);
683 ret = hclge_tm_pg_shapping_cfg(hdev,
684 HCLGE_TM_SHAP_C_BUCKET, i,
685 0, 0, 0, HCLGE_SHAPER_BS_U_DEF,
686 HCLGE_SHAPER_BS_S_DEF);
690 ret = hclge_tm_pg_shapping_cfg(hdev,
691 HCLGE_TM_SHAP_P_BUCKET, i,
693 HCLGE_SHAPER_BS_U_DEF,
694 HCLGE_SHAPER_BS_S_DEF);
702 static int hclge_tm_pg_dwrr_cfg(struct hclge_dev *hdev)
708 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
712 for (i = 0; i < hdev->tm_info.num_pg; i++) {
714 ret = hclge_tm_pg_weight_cfg(hdev, i,
715 hdev->tm_info.pg_dwrr[i]);
723 static int hclge_vport_q_to_qs_map(struct hclge_dev *hdev,
724 struct hclge_vport *vport)
726 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
727 struct hnae3_queue **tqp = kinfo->tqp;
728 struct hnae3_tc_info *v_tc_info;
732 for (i = 0; i < kinfo->num_tc; i++) {
733 v_tc_info = &kinfo->tc_info[i];
734 for (j = 0; j < v_tc_info->tqp_count; j++) {
735 struct hnae3_queue *q = tqp[v_tc_info->tqp_offset + j];
737 ret = hclge_tm_q_to_qs_map_cfg(hdev,
738 hclge_get_queue_id(q),
739 vport->qs_offset + i);
748 static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev)
750 struct hclge_vport *vport = hdev->vport;
754 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
755 /* Cfg qs -> pri mapping, one by one mapping */
756 for (k = 0; k < hdev->num_alloc_vport; k++)
757 for (i = 0; i < hdev->tm_info.num_tc; i++) {
758 ret = hclge_tm_qs_to_pri_map_cfg(
759 hdev, vport[k].qs_offset + i, i);
763 } else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) {
764 /* Cfg qs -> pri mapping, qs = tc, pri = vf, 8 qs -> 1 pri */
765 for (k = 0; k < hdev->num_alloc_vport; k++)
766 for (i = 0; i < HNAE3_MAX_TC; i++) {
767 ret = hclge_tm_qs_to_pri_map_cfg(
768 hdev, vport[k].qs_offset + i, k);
776 /* Cfg q -> qs mapping */
777 for (i = 0; i < hdev->num_alloc_vport; i++) {
778 ret = hclge_vport_q_to_qs_map(hdev, vport);
788 static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev)
794 for (i = 0; i < hdev->tm_info.num_tc; i++) {
795 ret = hclge_shaper_para_calc(
796 hdev->tm_info.tc_info[i].bw_limit,
797 HCLGE_SHAPER_LVL_PRI,
798 &ir_b, &ir_u, &ir_s);
802 ret = hclge_tm_pri_shapping_cfg(
803 hdev, HCLGE_TM_SHAP_C_BUCKET, i,
804 0, 0, 0, HCLGE_SHAPER_BS_U_DEF,
805 HCLGE_SHAPER_BS_S_DEF);
809 ret = hclge_tm_pri_shapping_cfg(
810 hdev, HCLGE_TM_SHAP_P_BUCKET, i,
811 ir_b, ir_u, ir_s, HCLGE_SHAPER_BS_U_DEF,
812 HCLGE_SHAPER_BS_S_DEF);
820 static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport)
822 struct hclge_dev *hdev = vport->back;
826 ret = hclge_shaper_para_calc(vport->bw_limit, HCLGE_SHAPER_LVL_VF,
827 &ir_b, &ir_u, &ir_s);
831 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET,
833 0, 0, 0, HCLGE_SHAPER_BS_U_DEF,
834 HCLGE_SHAPER_BS_S_DEF);
838 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET,
841 HCLGE_SHAPER_BS_U_DEF,
842 HCLGE_SHAPER_BS_S_DEF);
849 static int hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport *vport)
851 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
852 struct hclge_dev *hdev = vport->back;
857 for (i = 0; i < kinfo->num_tc; i++) {
858 ret = hclge_shaper_para_calc(
859 hdev->tm_info.tc_info[i].bw_limit,
860 HCLGE_SHAPER_LVL_QSET,
861 &ir_b, &ir_u, &ir_s);
869 static int hclge_tm_pri_vnet_base_shaper_cfg(struct hclge_dev *hdev)
871 struct hclge_vport *vport = hdev->vport;
875 /* Need config vport shaper */
876 for (i = 0; i < hdev->num_alloc_vport; i++) {
877 ret = hclge_tm_pri_vnet_base_shaper_pri_cfg(vport);
881 ret = hclge_tm_pri_vnet_base_shaper_qs_cfg(vport);
891 static int hclge_tm_pri_shaper_cfg(struct hclge_dev *hdev)
895 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
896 ret = hclge_tm_pri_tc_base_shaper_cfg(hdev);
900 ret = hclge_tm_pri_vnet_base_shaper_cfg(hdev);
908 static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)
910 struct hclge_vport *vport = hdev->vport;
911 struct hclge_pg_info *pg_info;
916 for (i = 0; i < hdev->tm_info.num_tc; i++) {
918 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
919 dwrr = pg_info->tc_dwrr[i];
921 ret = hclge_tm_pri_weight_cfg(hdev, i, dwrr);
925 for (k = 0; k < hdev->num_alloc_vport; k++) {
926 ret = hclge_tm_qs_weight_cfg(
927 hdev, vport[k].qs_offset + i,
937 static int hclge_tm_pri_vnet_base_dwrr_pri_cfg(struct hclge_vport *vport)
939 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
940 struct hclge_dev *hdev = vport->back;
945 ret = hclge_tm_pri_weight_cfg(hdev, vport->vport_id, vport->dwrr);
950 for (i = 0; i < kinfo->num_tc; i++) {
951 ret = hclge_tm_qs_weight_cfg(
952 hdev, vport->qs_offset + i,
953 hdev->tm_info.pg_info[0].tc_dwrr[i]);
961 static int hclge_tm_pri_vnet_base_dwrr_cfg(struct hclge_dev *hdev)
963 struct hclge_vport *vport = hdev->vport;
967 for (i = 0; i < hdev->num_alloc_vport; i++) {
968 ret = hclge_tm_pri_vnet_base_dwrr_pri_cfg(vport);
978 static int hclge_tm_pri_dwrr_cfg(struct hclge_dev *hdev)
982 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
983 ret = hclge_tm_pri_tc_base_dwrr_cfg(hdev);
987 ret = hclge_tm_pri_vnet_base_dwrr_cfg(hdev);
995 int hclge_tm_map_cfg(struct hclge_dev *hdev)
999 ret = hclge_up_to_tc_map(hdev);
1003 ret = hclge_tm_pg_to_pri_map(hdev);
1007 return hclge_tm_pri_q_qs_cfg(hdev);
1010 static int hclge_tm_shaper_cfg(struct hclge_dev *hdev)
1014 ret = hclge_tm_port_shaper_cfg(hdev);
1018 ret = hclge_tm_pg_shaper_cfg(hdev);
1022 return hclge_tm_pri_shaper_cfg(hdev);
1025 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev)
1029 ret = hclge_tm_pg_dwrr_cfg(hdev);
1033 return hclge_tm_pri_dwrr_cfg(hdev);
1036 static int hclge_tm_lvl2_schd_mode_cfg(struct hclge_dev *hdev)
1041 /* Only being config on TC-Based scheduler mode */
1042 if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE)
1045 for (i = 0; i < hdev->tm_info.num_pg; i++) {
1046 ret = hclge_tm_pg_schd_mode_cfg(hdev, i);
1054 static int hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport *vport)
1056 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1057 struct hclge_dev *hdev = vport->back;
1061 ret = hclge_tm_pri_schd_mode_cfg(hdev, vport->vport_id);
1065 for (i = 0; i < kinfo->num_tc; i++) {
1066 u8 sch_mode = hdev->tm_info.tc_info[i].tc_sch_mode;
1068 ret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i,
1077 static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev)
1079 struct hclge_vport *vport = hdev->vport;
1083 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
1084 for (i = 0; i < hdev->tm_info.num_tc; i++) {
1085 ret = hclge_tm_pri_schd_mode_cfg(hdev, i);
1089 for (k = 0; k < hdev->num_alloc_vport; k++) {
1090 ret = hclge_tm_qs_schd_mode_cfg(
1091 hdev, vport[k].qs_offset + i,
1092 HCLGE_SCH_MODE_DWRR);
1098 for (i = 0; i < hdev->num_alloc_vport; i++) {
1099 ret = hclge_tm_schd_mode_vnet_base_cfg(vport);
1110 int hclge_tm_schd_mode_hw(struct hclge_dev *hdev)
1114 ret = hclge_tm_lvl2_schd_mode_cfg(hdev);
1118 return hclge_tm_lvl34_schd_mode_cfg(hdev);
1121 static int hclge_tm_schd_setup_hw(struct hclge_dev *hdev)
1125 /* Cfg tm mapping */
1126 ret = hclge_tm_map_cfg(hdev);
1131 ret = hclge_tm_shaper_cfg(hdev);
1136 ret = hclge_tm_dwrr_cfg(hdev);
1140 /* Cfg schd mode for each level schd */
1141 return hclge_tm_schd_mode_hw(hdev);
1144 static int hclge_pause_param_setup_hw(struct hclge_dev *hdev)
1146 struct hclge_mac *mac = &hdev->hw.mac;
1148 return hclge_pause_param_cfg(hdev, mac->mac_addr,
1149 HCLGE_DEFAULT_PAUSE_TRANS_GAP,
1150 HCLGE_DEFAULT_PAUSE_TRANS_TIME);
1153 static int hclge_pfc_setup_hw(struct hclge_dev *hdev)
1155 u8 enable_bitmap = 0;
1157 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
1158 enable_bitmap = HCLGE_TX_MAC_PAUSE_EN_MSK |
1159 HCLGE_RX_MAC_PAUSE_EN_MSK;
1161 return hclge_pfc_pause_en_cfg(hdev, enable_bitmap,
1162 hdev->tm_info.hw_pfc_map);
1165 /* Each Tc has a 1024 queue sets to backpress, it divides to
1166 * 32 group, each group contains 32 queue sets, which can be
1167 * represented by u32 bitmap.
1169 static int hclge_bp_setup_hw(struct hclge_dev *hdev, u8 tc)
1173 for (i = 0; i < HCLGE_BP_GRP_NUM; i++) {
1177 for (k = 0; k < hdev->num_alloc_vport; k++) {
1178 struct hclge_vport *vport = &hdev->vport[k];
1179 u16 qs_id = vport->qs_offset + tc;
1182 grp = hnae3_get_field(qs_id, HCLGE_BP_GRP_ID_M,
1184 sub_grp = hnae3_get_field(qs_id, HCLGE_BP_SUB_GRP_ID_M,
1185 HCLGE_BP_SUB_GRP_ID_S);
1187 qs_bitmap |= (1 << sub_grp);
1190 ret = hclge_tm_qs_bp_cfg(hdev, tc, i, qs_bitmap);
1198 static int hclge_mac_pause_setup_hw(struct hclge_dev *hdev)
1202 switch (hdev->tm_info.fc_mode) {
1207 case HCLGE_FC_RX_PAUSE:
1211 case HCLGE_FC_TX_PAUSE:
1228 return hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
1231 int hclge_pause_setup_hw(struct hclge_dev *hdev)
1236 ret = hclge_pause_param_setup_hw(hdev);
1240 ret = hclge_mac_pause_setup_hw(hdev);
1244 /* Only DCB-supported dev supports qset back pressure and pfc cmd */
1245 if (!hnae3_dev_dcb_supported(hdev))
1248 /* When MAC is GE Mode, hdev does not support pfc setting */
1249 ret = hclge_pfc_setup_hw(hdev);
1251 dev_warn(&hdev->pdev->dev, "set pfc pause failed:%d\n", ret);
1253 for (i = 0; i < hdev->tm_info.num_tc; i++) {
1254 ret = hclge_bp_setup_hw(hdev, i);
1262 int hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc)
1264 struct hclge_vport *vport = hdev->vport;
1265 struct hnae3_knic_private_info *kinfo;
1268 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
1269 if (prio_tc[i] >= hdev->tm_info.num_tc)
1271 hdev->tm_info.prio_tc[i] = prio_tc[i];
1273 for (k = 0; k < hdev->num_alloc_vport; k++) {
1274 kinfo = &vport[k].nic.kinfo;
1275 kinfo->prio_tc[i] = prio_tc[i];
1281 int hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc)
1285 for (i = 0; i < hdev->num_alloc_vport; i++) {
1286 if (num_tc > hdev->vport[i].alloc_tqps)
1290 hdev->tm_info.num_tc = num_tc;
1292 for (i = 0; i < hdev->tm_info.num_tc; i++)
1297 hdev->tm_info.num_tc = 1;
1300 hdev->hw_tc_map = bit_map;
1302 hclge_tm_schd_info_init(hdev);
1307 int hclge_tm_init_hw(struct hclge_dev *hdev)
1311 if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) &&
1312 (hdev->tx_sch_mode != HCLGE_FLAG_VNET_BASE_SCH_MODE))
1315 ret = hclge_tm_schd_setup_hw(hdev);
1319 ret = hclge_pause_setup_hw(hdev);
1326 int hclge_tm_schd_init(struct hclge_dev *hdev)
1330 /* fc_mode is HCLGE_FC_FULL on reset */
1331 hdev->tm_info.fc_mode = HCLGE_FC_FULL;
1332 hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
1334 ret = hclge_tm_schd_info_init(hdev);
1338 return hclge_tm_init_hw(hdev);