1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/dma-mapping.h>
5 #include <linux/slab.h>
7 #include <linux/device.h>
9 #include <linux/dma-direction.h>
10 #include "hclge_cmd.h"
12 #include "hclge_main.h"
14 #define hclge_is_csq(ring) ((ring)->flag & HCLGE_TYPE_CSQ)
16 #define cmq_ring_to_dev(ring) (&(ring)->dev->pdev->dev)
18 static int hclge_ring_space(struct hclge_cmq_ring *ring)
20 int ntu = ring->next_to_use;
21 int ntc = ring->next_to_clean;
22 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
24 return ring->desc_num - used - 1;
27 static int is_valid_csq_clean_head(struct hclge_cmq_ring *ring, int h)
29 int u = ring->next_to_use;
30 int c = ring->next_to_clean;
32 if (unlikely(h >= ring->desc_num))
35 return u > c ? (h > c && h <= u) : (h > c || h <= u);
38 static int hclge_alloc_cmd_desc(struct hclge_cmq_ring *ring)
40 int size = ring->desc_num * sizeof(struct hclge_desc);
42 ring->desc = dma_zalloc_coherent(cmq_ring_to_dev(ring),
43 size, &ring->desc_dma_addr,
51 static void hclge_free_cmd_desc(struct hclge_cmq_ring *ring)
53 int size = ring->desc_num * sizeof(struct hclge_desc);
56 dma_free_coherent(cmq_ring_to_dev(ring), size,
57 ring->desc, ring->desc_dma_addr);
62 static int hclge_alloc_cmd_queue(struct hclge_dev *hdev, int ring_type)
64 struct hclge_hw *hw = &hdev->hw;
65 struct hclge_cmq_ring *ring =
66 (ring_type == HCLGE_TYPE_CSQ) ? &hw->cmq.csq : &hw->cmq.crq;
69 ring->ring_type = ring_type;
72 ret = hclge_alloc_cmd_desc(ring);
74 dev_err(&hdev->pdev->dev, "descriptor %s alloc error %d\n",
75 (ring_type == HCLGE_TYPE_CSQ) ? "CSQ" : "CRQ", ret);
82 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read)
84 desc->flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN);
86 desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_WR);
88 desc->flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
91 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
92 enum hclge_opcode_type opcode, bool is_read)
94 memset((void *)desc, 0, sizeof(struct hclge_desc));
95 desc->opcode = cpu_to_le16(opcode);
96 desc->flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN);
99 desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_WR);
102 static void hclge_cmd_config_regs(struct hclge_cmq_ring *ring)
104 dma_addr_t dma = ring->desc_dma_addr;
105 struct hclge_dev *hdev = ring->dev;
106 struct hclge_hw *hw = &hdev->hw;
108 if (ring->ring_type == HCLGE_TYPE_CSQ) {
109 hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_L_REG,
111 hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_H_REG,
113 hclge_write_dev(hw, HCLGE_NIC_CSQ_DEPTH_REG,
114 (ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S) |
115 HCLGE_NIC_CMQ_ENABLE);
116 hclge_write_dev(hw, HCLGE_NIC_CSQ_HEAD_REG, 0);
117 hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, 0);
119 hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_L_REG,
121 hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_H_REG,
123 hclge_write_dev(hw, HCLGE_NIC_CRQ_DEPTH_REG,
124 (ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S) |
125 HCLGE_NIC_CMQ_ENABLE);
126 hclge_write_dev(hw, HCLGE_NIC_CRQ_HEAD_REG, 0);
127 hclge_write_dev(hw, HCLGE_NIC_CRQ_TAIL_REG, 0);
131 static void hclge_cmd_init_regs(struct hclge_hw *hw)
133 hclge_cmd_config_regs(&hw->cmq.csq);
134 hclge_cmd_config_regs(&hw->cmq.crq);
137 static int hclge_cmd_csq_clean(struct hclge_hw *hw)
139 struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw);
140 struct hclge_cmq_ring *csq = &hw->cmq.csq;
144 head = hclge_read_dev(hw, HCLGE_NIC_CSQ_HEAD_REG);
145 rmb(); /* Make sure head is ready before touch any data */
147 if (!is_valid_csq_clean_head(csq, head)) {
148 dev_warn(&hdev->pdev->dev, "wrong cmd head (%d, %d-%d)\n", head,
149 csq->next_to_use, csq->next_to_clean);
153 clean = (head - csq->next_to_clean + csq->desc_num) % csq->desc_num;
154 csq->next_to_clean = head;
158 static int hclge_cmd_csq_done(struct hclge_hw *hw)
160 u32 head = hclge_read_dev(hw, HCLGE_NIC_CSQ_HEAD_REG);
161 return head == hw->cmq.csq.next_to_use;
164 static bool hclge_is_special_opcode(u16 opcode)
166 /* these commands have several descriptors,
167 * and use the first one to save opcode and return value
169 u16 spec_opcode[3] = {HCLGE_OPC_STATS_64_BIT,
170 HCLGE_OPC_STATS_32_BIT, HCLGE_OPC_STATS_MAC};
173 for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
174 if (spec_opcode[i] == opcode)
182 * hclge_cmd_send - send command to command queue
183 * @hw: pointer to the hw struct
184 * @desc: prefilled descriptor for describing the command
185 * @num : the number of descriptors to be sent
187 * This is the main send command for command queue, it
188 * sends the queue, cleans the queue, etc
190 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
192 struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw);
193 struct hclge_desc *desc_to_use;
194 bool complete = false;
198 u16 opcode, desc_ret;
201 spin_lock_bh(&hw->cmq.csq.lock);
203 if (num > hclge_ring_space(&hw->cmq.csq) ||
204 test_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state)) {
205 spin_unlock_bh(&hw->cmq.csq.lock);
210 * Record the location of desc in the ring for this time
211 * which will be use for hardware to write back
213 ntc = hw->cmq.csq.next_to_use;
214 opcode = le16_to_cpu(desc[0].opcode);
215 while (handle < num) {
216 desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
217 *desc_to_use = desc[handle];
218 (hw->cmq.csq.next_to_use)++;
219 if (hw->cmq.csq.next_to_use == hw->cmq.csq.desc_num)
220 hw->cmq.csq.next_to_use = 0;
224 /* Write to hardware */
225 hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, hw->cmq.csq.next_to_use);
228 * If the command is sync, wait for the firmware to write back,
229 * if multi descriptors to be sent, use the first one to check
231 if (HCLGE_SEND_SYNC(le16_to_cpu(desc->flag))) {
233 if (hclge_cmd_csq_done(hw)) {
239 } while (timeout < hw->cmq.tx_timeout);
246 while (handle < num) {
247 /* Get the result of hardware write back */
248 desc_to_use = &hw->cmq.csq.desc[ntc];
249 desc[handle] = *desc_to_use;
251 if (likely(!hclge_is_special_opcode(opcode)))
252 desc_ret = le16_to_cpu(desc[handle].retval);
254 desc_ret = le16_to_cpu(desc[0].retval);
256 if (desc_ret == HCLGE_CMD_EXEC_SUCCESS)
260 hw->cmq.last_status = desc_ret;
263 if (ntc == hw->cmq.csq.desc_num)
268 /* Clean the command send queue */
269 handle = hclge_cmd_csq_clean(hw);
271 dev_warn(&hdev->pdev->dev,
272 "cleaned %d, need to clean %d\n", handle, num);
275 spin_unlock_bh(&hw->cmq.csq.lock);
280 static enum hclge_cmd_status hclge_cmd_query_firmware_version(
281 struct hclge_hw *hw, u32 *version)
283 struct hclge_query_version_cmd *resp;
284 struct hclge_desc desc;
287 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FW_VER, 1);
288 resp = (struct hclge_query_version_cmd *)desc.data;
290 ret = hclge_cmd_send(hw, &desc, 1);
292 *version = le32_to_cpu(resp->firmware);
297 int hclge_cmd_queue_init(struct hclge_dev *hdev)
301 /* Setup the queue entries for use cmd queue */
302 hdev->hw.cmq.csq.desc_num = HCLGE_NIC_CMQ_DESC_NUM;
303 hdev->hw.cmq.crq.desc_num = HCLGE_NIC_CMQ_DESC_NUM;
305 /* Setup Tx write back timeout */
306 hdev->hw.cmq.tx_timeout = HCLGE_CMDQ_TX_TIMEOUT;
308 /* Setup queue rings */
309 ret = hclge_alloc_cmd_queue(hdev, HCLGE_TYPE_CSQ);
311 dev_err(&hdev->pdev->dev,
312 "CSQ ring setup error %d\n", ret);
316 ret = hclge_alloc_cmd_queue(hdev, HCLGE_TYPE_CRQ);
318 dev_err(&hdev->pdev->dev,
319 "CRQ ring setup error %d\n", ret);
325 hclge_free_cmd_desc(&hdev->hw.cmq.csq);
329 int hclge_cmd_init(struct hclge_dev *hdev)
334 hdev->hw.cmq.csq.next_to_clean = 0;
335 hdev->hw.cmq.csq.next_to_use = 0;
336 hdev->hw.cmq.crq.next_to_clean = 0;
337 hdev->hw.cmq.crq.next_to_use = 0;
339 /* Setup the lock for command queue */
340 spin_lock_init(&hdev->hw.cmq.csq.lock);
341 spin_lock_init(&hdev->hw.cmq.crq.lock);
343 hclge_cmd_init_regs(&hdev->hw);
344 clear_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
346 ret = hclge_cmd_query_firmware_version(&hdev->hw, &version);
348 dev_err(&hdev->pdev->dev,
349 "firmware version query failed %d\n", ret);
352 hdev->fw_version = version;
354 dev_info(&hdev->pdev->dev, "The firmware version is %08x\n", version);
359 static void hclge_destroy_queue(struct hclge_cmq_ring *ring)
361 spin_lock(&ring->lock);
362 hclge_free_cmd_desc(ring);
363 spin_unlock(&ring->lock);
366 void hclge_destroy_cmd_queue(struct hclge_hw *hw)
368 hclge_destroy_queue(&hw->cmq.csq);
369 hclge_destroy_queue(&hw->cmq.crq);