drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c

   1 /*
   2  * Copyright (c) 2014-2015 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/netdevice.h>
  14 #include <linux/etherdevice.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_platform.h>
  19
  20 #include "hns_dsaf_ppe.h"
  21
  22 void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value)
  23 {
  24         dsaf_set_dev_bit(ppe_cb, PPEV2_CFG_TSO_EN_REG, 0, !!value);
  25 }
  26
  27 void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb,
  28                          const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM])
  29 {
  30         u32 key_item;
  31
  32         for (key_item = 0; key_item < HNS_PPEV2_RSS_KEY_NUM; key_item++)
  33                 dsaf_write_dev(ppe_cb, PPEV2_RSS_KEY_REG + key_item * 0x4,
  34                                rss_key[key_item]);
  35 }
  36
  37 void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb,
  38                              const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE])
  39 {
  40         int i;
  41         int reg_value;
  42
  43         for (i = 0; i < (HNS_PPEV2_RSS_IND_TBL_SIZE / 4); i++) {
  44                 reg_value = dsaf_read_dev(ppe_cb,
  45                                           PPEV2_INDRECTION_TBL_REG + i * 0x4);
  46
  47                 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M,
  48                                PPEV2_CFG_RSS_TBL_4N0_S,
  49                                rss_tab[i * 4 + 0] & 0x1F);
  50                 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M,
  51                                PPEV2_CFG_RSS_TBL_4N1_S,
  52                                 rss_tab[i * 4 + 1] & 0x1F);
  53                 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M,
  54                                PPEV2_CFG_RSS_TBL_4N2_S,
  55                                 rss_tab[i * 4 + 2] & 0x1F);
  56                 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M,
  57                                PPEV2_CFG_RSS_TBL_4N3_S,
  58                                 rss_tab[i * 4 + 3] & 0x1F);
  59                 dsaf_write_dev(
  60                         ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4, reg_value);
  61         }
  62 }
  63
  64 static void __iomem *
  65 hns_ppe_common_get_ioaddr(struct ppe_common_cb *ppe_common)
  66 {
  67         return ppe_common->dsaf_dev->ppe_base + PPE_COMMON_REG_OFFSET;
  68 }
  69
  70 /**
  71  * hns_ppe_common_get_cfg - get ppe common config
  72  * @dsaf_dev: dasf device
  73  * comm_index: common index
  74  * retuen 0 - success , negative --fail
  75  */
  76 static int hns_ppe_common_get_cfg(struct dsaf_device *dsaf_dev, int comm_index)
  77 {
  78         struct ppe_common_cb *ppe_common;
  79         int ppe_num;
  80
  81         if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
  82                 ppe_num = HNS_PPE_SERVICE_NW_ENGINE_NUM;
  83         else
  84                 ppe_num = HNS_PPE_DEBUG_NW_ENGINE_NUM;
  85
  86         ppe_common = devm_kzalloc(dsaf_dev->dev, sizeof(*ppe_common) +
  87                 ppe_num * sizeof(struct hns_ppe_cb), GFP_KERNEL);
  88         if (!ppe_common)
  89                 return -ENOMEM;
  90
  91         ppe_common->ppe_num = ppe_num;
  92         ppe_common->dsaf_dev = dsaf_dev;
  93         ppe_common->comm_index = comm_index;
  94         if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
  95                 ppe_common->ppe_mode = PPE_COMMON_MODE_SERVICE;
  96         else
  97                 ppe_common->ppe_mode = PPE_COMMON_MODE_DEBUG;
  98         ppe_common->dev = dsaf_dev->dev;
  99
 100         ppe_common->io_base = hns_ppe_common_get_ioaddr(ppe_common);
 101
 102         dsaf_dev->ppe_common[comm_index] = ppe_common;
 103
 104         return 0;
 105 }
 106
 107 static void
 108 hns_ppe_common_free_cfg(struct dsaf_device *dsaf_dev, u32 comm_index)
 109 {
 110         dsaf_dev->ppe_common[comm_index] = NULL;
 111 }
 112
 113 static void __iomem *hns_ppe_get_iobase(struct ppe_common_cb *ppe_common,
 114                                         int ppe_idx)
 115 {
 116         return ppe_common->dsaf_dev->ppe_base + ppe_idx * PPE_REG_OFFSET;
 117 }
 118
 119 static void hns_ppe_get_cfg(struct ppe_common_cb *ppe_common)
 120 {
 121         u32 i;
 122         struct hns_ppe_cb *ppe_cb;
 123         u32 ppe_num = ppe_common->ppe_num;
 124
 125         for (i = 0; i < ppe_num; i++) {
 126                 ppe_cb = &ppe_common->ppe_cb[i];
 127                 ppe_cb->dev = ppe_common->dev;
 128                 ppe_cb->next = NULL;
 129                 ppe_cb->ppe_common_cb = ppe_common;
 130                 ppe_cb->index = i;
 131                 ppe_cb->io_base = hns_ppe_get_iobase(ppe_common, i);
 132                 ppe_cb->virq = 0;
 133         }
 134 }
 135
 136 static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb *ppe_cb)
 137 {
 138         dsaf_set_dev_bit(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG,
 139                          PPE_CNT_CLR_CE_B, 1);
 140 }
 141
 142 static void hns_ppe_set_vlan_strip(struct hns_ppe_cb *ppe_cb, int en)
 143 {
 144         dsaf_write_dev(ppe_cb, PPEV2_VLAN_STRIP_EN_REG, en);
 145 }
 146
 147 /**
 148  * hns_ppe_checksum_hw - set ppe checksum caculate
 149  * @ppe_device: ppe device
 150  * @value: value
 151  */
 152 static void hns_ppe_checksum_hw(struct hns_ppe_cb *ppe_cb, u32 value)
 153 {
 154         dsaf_set_dev_field(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG,
 155                            0xfffffff, 0, value);
 156 }
 157
 158 static void hns_ppe_set_qid_mode(struct ppe_common_cb *ppe_common,
 159                                  enum ppe_qid_mode qid_mdoe)
 160 {
 161         dsaf_set_dev_field(ppe_common, PPE_COM_CFG_QID_MODE_REG,
 162                            PPE_CFG_QID_MODE_CF_QID_MODE_M,
 163                            PPE_CFG_QID_MODE_CF_QID_MODE_S, qid_mdoe);
 164 }
 165
 166 /**
 167  * hns_ppe_set_qid - set ppe qid
 168  * @ppe_common: ppe common device
 169  * @qid: queue id
 170  */
 171 static void hns_ppe_set_qid(struct ppe_common_cb *ppe_common, u32 qid)
 172 {
 173         u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
 174
 175         if (!dsaf_get_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
 176                             PPE_CFG_QID_MODE_DEF_QID_S)) {
 177                 dsaf_set_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
 178                                PPE_CFG_QID_MODE_DEF_QID_S, qid);
 179                 dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod);
 180         }
 181 }
 182
 183 /**
 184  * hns_ppe_set_port_mode - set port mode
 185  * @ppe_device: ppe device
 186  * @mode: port mode
 187  */
 188 static void hns_ppe_set_port_mode(struct hns_ppe_cb *ppe_cb,
 189                                   enum ppe_port_mode mode)
 190 {
 191         dsaf_write_dev(ppe_cb, PPE_CFG_XGE_MODE_REG, mode);
 192 }
 193
 194 /**
 195  * hns_ppe_common_init_hw - init ppe common device
 196  * @ppe_common: ppe common device
 197  *
 198  * Return 0 on success, negative on failure
 199  */
 200 static int hns_ppe_common_init_hw(struct ppe_common_cb *ppe_common)
 201 {
 202         enum ppe_qid_mode qid_mode;
 203         struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
 204         enum dsaf_mode dsaf_mode = dsaf_dev->dsaf_mode;
 205
 206         dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 0);
 207         msleep(100);
 208         dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 1);
 209         msleep(100);
 210
 211         if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) {
 212                 switch (dsaf_mode) {
 213                 case DSAF_MODE_ENABLE_FIX:
 214                 case DSAF_MODE_DISABLE_FIX:
 215                         qid_mode = PPE_QID_MODE0;
 216                         hns_ppe_set_qid(ppe_common, 0);
 217                         break;
 218                 case DSAF_MODE_ENABLE_0VM:
 219                 case DSAF_MODE_DISABLE_2PORT_64VM:
 220                         qid_mode = PPE_QID_MODE3;
 221                         break;
 222                 case DSAF_MODE_ENABLE_8VM:
 223                 case DSAF_MODE_DISABLE_2PORT_16VM:
 224                         qid_mode = PPE_QID_MODE4;
 225                         break;
 226                 case DSAF_MODE_ENABLE_16VM:
 227                 case DSAF_MODE_DISABLE_6PORT_0VM:
 228                         qid_mode = PPE_QID_MODE5;
 229                         break;
 230                 case DSAF_MODE_ENABLE_32VM:
 231                 case DSAF_MODE_DISABLE_6PORT_16VM:
 232                         qid_mode = PPE_QID_MODE2;
 233                         break;
 234                 case DSAF_MODE_ENABLE_128VM:
 235                 case DSAF_MODE_DISABLE_6PORT_4VM:
 236                         qid_mode = PPE_QID_MODE1;
 237                         break;
 238                 case DSAF_MODE_DISABLE_2PORT_8VM:
 239                         qid_mode = PPE_QID_MODE7;
 240                         break;
 241                 case DSAF_MODE_DISABLE_6PORT_2VM:
 242                         qid_mode = PPE_QID_MODE6;
 243                         break;
 244                 default:
 245                         dev_err(ppe_common->dev,
 246                                 "get ppe queue mode failed! dsaf_mode=%d\n",
 247                                 dsaf_mode);
 248                         return -EINVAL;
 249                 }
 250                 hns_ppe_set_qid_mode(ppe_common, qid_mode);
 251         }
 252
 253         dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG,
 254                          PPE_COMMON_CNT_CLR_CE_B, 1);
 255
 256         return 0;
 257 }
 258
 259 /*clr ppe exception irq*/
 260 static void hns_ppe_exc_irq_en(struct hns_ppe_cb *ppe_cb, int en)
 261 {
 262         u32 clr_vlue = 0xfffffffful;
 263         u32 msk_vlue = en ? 0xfffffffful : 0; /*1 is en, 0 is dis*/
 264         u32 vld_msk = 0;
 265
 266         /*only care bit 0,1,7*/
 267         dsaf_set_bit(vld_msk, 0, 1);
 268         dsaf_set_bit(vld_msk, 1, 1);
 269         dsaf_set_bit(vld_msk, 7, 1);
 270
 271         /*clr sts**/
 272         dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue);
 273
 274         /*for some reserved bits, so set 0**/
 275         dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk);
 276 }
 277
 278 int hns_ppe_wait_tx_fifo_clean(struct hns_ppe_cb *ppe_cb)
 279 {
 280         int wait_cnt;
 281         u32 val;
 282
 283         wait_cnt = 0;
 284         while (wait_cnt++ < HNS_MAX_WAIT_CNT) {
 285                 val = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG) & 0x3ffU;
 286                 if (!val)
 287                         break;
 288
 289                 usleep_range(100, 200);
 290         }
 291
 292         if (wait_cnt >= HNS_MAX_WAIT_CNT) {
 293                 dev_err(ppe_cb->dev, "hns ppe tx fifo clean wait timeout, still has %u pkt.\n",
 294                         val);
 295                 return -EBUSY;
 296         }
 297
 298         return 0;
 299 }
 300
 301 /**
 302  * ppe_init_hw - init ppe
 303  * @ppe_cb: ppe device
 304  */
 305 static void hns_ppe_init_hw(struct hns_ppe_cb *ppe_cb)
 306 {
 307         struct ppe_common_cb *ppe_common_cb = ppe_cb->ppe_common_cb;
 308         u32 port = ppe_cb->index;
 309         struct dsaf_device *dsaf_dev = ppe_common_cb->dsaf_dev;
 310         int i;
 311
 312         /* get default RSS key */
 313         netdev_rss_key_fill(ppe_cb->rss_key, HNS_PPEV2_RSS_KEY_SIZE);
 314
 315         dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0);
 316         mdelay(10);
 317         dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 1);
 318
 319         /* clr and msk except irq*/
 320         hns_ppe_exc_irq_en(ppe_cb, 0);
 321
 322         if (ppe_common_cb->ppe_mode == PPE_COMMON_MODE_DEBUG) {
 323                 hns_ppe_set_port_mode(ppe_cb, PPE_MODE_GE);
 324                 dsaf_write_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG, 0);
 325         } else {
 326                 hns_ppe_set_port_mode(ppe_cb, PPE_MODE_XGE);
 327         }
 328
 329         hns_ppe_checksum_hw(ppe_cb, 0xffffffff);
 330         hns_ppe_cnt_clr_ce(ppe_cb);
 331
 332         if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
 333                 hns_ppe_set_vlan_strip(ppe_cb, 0);
 334
 335                 dsaf_write_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG,
 336                                HNS_PPEV2_MAX_FRAME_LEN);
 337
 338                 /* set default RSS key in h/w */
 339                 hns_ppe_set_rss_key(ppe_cb, ppe_cb->rss_key);
 340
 341                 /* Set default indrection table in h/w */
 342                 for (i = 0; i < HNS_PPEV2_RSS_IND_TBL_SIZE; i++)
 343                         ppe_cb->rss_indir_table[i] = i;
 344                 hns_ppe_set_indir_table(ppe_cb, ppe_cb->rss_indir_table);
 345         }
 346 }
 347
 348 /**
 349  * ppe_uninit_hw - uninit ppe
 350  * @ppe_device: ppe device
 351  */
 352 static void hns_ppe_uninit_hw(struct hns_ppe_cb *ppe_cb)
 353 {
 354         u32 port;
 355
 356         if (ppe_cb->ppe_common_cb) {
 357                 struct dsaf_device *dsaf_dev = ppe_cb->ppe_common_cb->dsaf_dev;
 358
 359                 port = ppe_cb->index;
 360                 dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0);
 361         }
 362 }
 363
 364 static void hns_ppe_uninit_ex(struct ppe_common_cb *ppe_common)
 365 {
 366         u32 i;
 367
 368         for (i = 0; i < ppe_common->ppe_num; i++) {
 369                 if (ppe_common->dsaf_dev->mac_cb[i])
 370                         hns_ppe_uninit_hw(&ppe_common->ppe_cb[i]);
 371                 memset(&ppe_common->ppe_cb[i], 0, sizeof(struct hns_ppe_cb));
 372         }
 373 }
 374
 375 void hns_ppe_uninit(struct dsaf_device *dsaf_dev)
 376 {
 377         u32 i;
 378
 379         for (i = 0; i < HNS_PPE_COM_NUM; i++) {
 380                 if (dsaf_dev->ppe_common[i])
 381                         hns_ppe_uninit_ex(dsaf_dev->ppe_common[i]);
 382                 hns_rcb_common_free_cfg(dsaf_dev, i);
 383                 hns_ppe_common_free_cfg(dsaf_dev, i);
 384         }
 385 }
 386
 387 /**
 388  * hns_ppe_reset - reinit ppe/rcb hw
 389  * @dsaf_dev: dasf device
 390  * retuen void
 391  */
 392 void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index)
 393 {
 394         u32 i;
 395         int ret;
 396         struct ppe_common_cb *ppe_common;
 397
 398         ppe_common = dsaf_dev->ppe_common[ppe_common_index];
 399         ret = hns_ppe_common_init_hw(ppe_common);
 400         if (ret)
 401                 return;
 402
 403         for (i = 0; i < ppe_common->ppe_num; i++) {
 404                 /* We only need to initiate ppe when the port exists */
 405                 if (dsaf_dev->mac_cb[i])
 406                         hns_ppe_init_hw(&ppe_common->ppe_cb[i]);
 407         }
 408
 409         ret = hns_rcb_common_init_hw(dsaf_dev->rcb_common[ppe_common_index]);
 410         if (ret)
 411                 return;
 412
 413         hns_rcb_common_init_commit_hw(dsaf_dev->rcb_common[ppe_common_index]);
 414 }
 415
 416 void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb)
 417 {
 418         struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;
 419
 420         hw_stats->rx_pkts_from_sw
 421                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
 422         hw_stats->rx_pkts
 423                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
 424         hw_stats->rx_drop_no_bd
 425                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
 426         hw_stats->rx_alloc_buf_fail
 427                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
 428         hw_stats->rx_alloc_buf_wait
 429                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
 430         hw_stats->rx_drop_no_buf
 431                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
 432         hw_stats->rx_err_fifo_full
 433                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);
 434
 435         hw_stats->tx_bd_form_rcb
 436                 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
 437         hw_stats->tx_pkts_from_rcb
 438                 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
 439         hw_stats->tx_pkts
 440                 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
 441         hw_stats->tx_err_fifo_empty
 442                 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
 443         hw_stats->tx_err_checksum
 444                 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
 445 }
 446
 447 int hns_ppe_get_sset_count(int stringset)
 448 {
 449         if (stringset == ETH_SS_STATS)
 450                 return ETH_PPE_STATIC_NUM;
 451         return 0;
 452 }
 453
 454 int hns_ppe_get_regs_count(void)
 455 {
 456         return ETH_PPE_DUMP_NUM;
 457 }
 458
 459 /**
 460  * ppe_get_strings - get ppe srting
 461  * @ppe_device: ppe device
 462  * @stringset: string set type
 463  * @data: output string
 464  */
 465 void hns_ppe_get_strings(struct hns_ppe_cb *ppe_cb, int stringset, u8 *data)
 466 {
 467         char *buff = (char *)data;
 468         int index = ppe_cb->index;
 469
 470         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_sw_pkt", index);
 471         buff = buff + ETH_GSTRING_LEN;
 472         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_ok", index);
 473         buff = buff + ETH_GSTRING_LEN;
 474         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_drop_pkt_no_bd", index);
 475         buff = buff + ETH_GSTRING_LEN;
 476         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_fail", index);
 477         buff = buff + ETH_GSTRING_LEN;
 478         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_wait", index);
 479         buff = buff + ETH_GSTRING_LEN;
 480         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_drop_no_buf", index);
 481         buff = buff + ETH_GSTRING_LEN;
 482         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_err_fifo_full", index);
 483         buff = buff + ETH_GSTRING_LEN;
 484
 485         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_bd", index);
 486         buff = buff + ETH_GSTRING_LEN;
 487         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt", index);
 488         buff = buff + ETH_GSTRING_LEN;
 489         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_ok", index);
 490         buff = buff + ETH_GSTRING_LEN;
 491         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_fifo_empty", index);
 492         buff = buff + ETH_GSTRING_LEN;
 493         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_csum_fail", index);
 494 }
 495
 496 void hns_ppe_get_stats(struct hns_ppe_cb *ppe_cb, u64 *data)
 497 {
 498         u64 *regs_buff = data;
 499         struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;
 500
 501         regs_buff[0] = hw_stats->rx_pkts_from_sw;
 502         regs_buff[1] = hw_stats->rx_pkts;
 503         regs_buff[2] = hw_stats->rx_drop_no_bd;
 504         regs_buff[3] = hw_stats->rx_alloc_buf_fail;
 505         regs_buff[4] = hw_stats->rx_alloc_buf_wait;
 506         regs_buff[5] = hw_stats->rx_drop_no_buf;
 507         regs_buff[6] = hw_stats->rx_err_fifo_full;
 508
 509         regs_buff[7] = hw_stats->tx_bd_form_rcb;
 510         regs_buff[8] = hw_stats->tx_pkts_from_rcb;
 511         regs_buff[9] = hw_stats->tx_pkts;
 512         regs_buff[10] = hw_stats->tx_err_fifo_empty;
 513         regs_buff[11] = hw_stats->tx_err_checksum;
 514 }
 515
 516 /**
 517  * hns_ppe_init - init ppe device
 518  * @dsaf_dev: dasf device
 519  * retuen 0 - success , negative --fail
 520  */
 521 int hns_ppe_init(struct dsaf_device *dsaf_dev)
 522 {
 523         int ret;
 524         int i;
 525
 526         for (i = 0; i < HNS_PPE_COM_NUM; i++) {
 527                 ret = hns_ppe_common_get_cfg(dsaf_dev, i);
 528                 if (ret)
 529                         goto get_cfg_fail;
 530
 531                 ret = hns_rcb_common_get_cfg(dsaf_dev, i);
 532                 if (ret)
 533                         goto get_cfg_fail;
 534
 535                 hns_ppe_get_cfg(dsaf_dev->ppe_common[i]);
 536
 537                 ret = hns_rcb_get_cfg(dsaf_dev->rcb_common[i]);
 538                 if (ret)
 539                         goto get_cfg_fail;
 540         }
 541
 542         for (i = 0; i < HNS_PPE_COM_NUM; i++)
 543                 hns_ppe_reset_common(dsaf_dev, i);
 544
 545         return 0;
 546
 547 get_cfg_fail:
 548         for (i = 0; i < HNS_PPE_COM_NUM; i++) {
 549                 hns_rcb_common_free_cfg(dsaf_dev, i);
 550                 hns_ppe_common_free_cfg(dsaf_dev, i);
 551         }
 552
 553         return ret;
 554 }
 555
 556 void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void *data)
 557 {
 558         struct ppe_common_cb *ppe_common = ppe_cb->ppe_common_cb;
 559         u32 *regs = data;
 560         u32 i;
 561         u32 offset;
 562
 563         /* ppe common registers */
 564         regs[0] = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
 565         regs[1] = dsaf_read_dev(ppe_common, PPE_COM_INTEN_REG);
 566         regs[2] = dsaf_read_dev(ppe_common, PPE_COM_RINT_REG);
 567         regs[3] = dsaf_read_dev(ppe_common, PPE_COM_INTSTS_REG);
 568         regs[4] = dsaf_read_dev(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG);
 569
 570         for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) {
 571                 offset = PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 0x4 * i;
 572                 regs[5 + i] = dsaf_read_dev(ppe_common, offset);
 573                 offset = PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 0x4 * i;
 574                 regs[5 + i + DSAF_TOTAL_QUEUE_NUM]
 575                                 = dsaf_read_dev(ppe_common, offset);
 576                 offset = PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 0x4 * i;
 577                 regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 2]
 578                                 = dsaf_read_dev(ppe_common, offset);
 579                 offset = PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 0x4 * i;
 580                 regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 3]
 581                                 = dsaf_read_dev(ppe_common, offset);
 582         }
 583
 584         /* mark end of ppe regs */
 585         for (i = 521; i < 524; i++)
 586                 regs[i] = 0xeeeeeeee;
 587
 588         /* ppe channel registers */
 589         regs[525] = dsaf_read_dev(ppe_cb, PPE_CFG_TX_FIFO_THRSLD_REG);
 590         regs[526] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_THRSLD_REG);
 591         regs[527] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG);
 592         regs[528] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG);
 593         regs[529] = dsaf_read_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG);
 594         regs[530] = dsaf_read_dev(ppe_cb, PPE_CFG_BUS_CTRL_REG);
 595         regs[531] = dsaf_read_dev(ppe_cb, PPE_CFG_TNL_TO_BE_RST_REG);
 596         regs[532] = dsaf_read_dev(ppe_cb, PPE_CURR_TNL_CAN_RST_REG);
 597
 598         regs[533] = dsaf_read_dev(ppe_cb, PPE_CFG_XGE_MODE_REG);
 599         regs[534] = dsaf_read_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG);
 600         regs[535] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_MODE_REG);
 601         regs[536] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_VLAN_TAG_REG);
 602         regs[537] = dsaf_read_dev(ppe_cb, PPE_CFG_TAG_GEN_REG);
 603         regs[538] = dsaf_read_dev(ppe_cb, PPE_CFG_PARSE_TAG_REG);
 604         regs[539] = dsaf_read_dev(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG);
 605
 606         regs[540] = dsaf_read_dev(ppe_cb, PPE_INTEN_REG);
 607         regs[541] = dsaf_read_dev(ppe_cb, PPE_RINT_REG);
 608         regs[542] = dsaf_read_dev(ppe_cb, PPE_INTSTS_REG);
 609         regs[543] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_INT_REG);
 610
 611         regs[544] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME0_REG);
 612         regs[545] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME1_REG);
 613
 614         /* ppe static */
 615         regs[546] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
 616         regs[547] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
 617         regs[548] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
 618         regs[549] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
 619         regs[550] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
 620         regs[551] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
 621         regs[552] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
 622         regs[553] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
 623         regs[554] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
 624         regs[555] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
 625         regs[556] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
 626         regs[557] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);
 627
 628         regs[558] = dsaf_read_dev(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG);
 629         regs[559] = dsaf_read_dev(ppe_cb, PPE_CFG_AXI_DBG_REG);
 630         regs[560] = dsaf_read_dev(ppe_cb, PPE_HIS_PRO_ERR_REG);
 631         regs[561] = dsaf_read_dev(ppe_cb, PPE_HIS_TNL_FIFO_ERR_REG);
 632         regs[562] = dsaf_read_dev(ppe_cb, PPE_CURR_CFF_DATA_NUM_REG);
 633         regs[563] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_ST_REG);
 634         regs[564] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_ST_REG);
 635         regs[565] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO0_REG);
 636         regs[566] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO1_REG);
 637         regs[567] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG);
 638         regs[568] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO1_REG);
 639         regs[569] = dsaf_read_dev(ppe_cb, PPE_ECO0_REG);
 640         regs[570] = dsaf_read_dev(ppe_cb, PPE_ECO1_REG);
 641         regs[571] = dsaf_read_dev(ppe_cb, PPE_ECO2_REG);
 642
 643         /* mark end of ppe regs */
 644         for (i = 572; i < 576; i++)
 645                 regs[i] = 0xeeeeeeee;
 646 }