drivers/net/ethernet/hisilicon/hix5hd2_gmac.c

   1 /* Copyright (c) 2014 Linaro Ltd.
   2  * Copyright (c) 2014 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/of_device.h>
  15 #include <linux/of_net.h>
  16 #include <linux/of_mdio.h>
  17 #include <linux/reset.h>
  18 #include <linux/clk.h>
  19 #include <linux/circ_buf.h>
  20
  21 #define STATION_ADDR_LOW                0x0000
  22 #define STATION_ADDR_HIGH               0x0004
  23 #define MAC_DUPLEX_HALF_CTRL            0x0008
  24 #define MAX_FRM_SIZE                    0x003c
  25 #define PORT_MODE                       0x0040
  26 #define PORT_EN                         0x0044
  27 #define BITS_TX_EN                      BIT(2)
  28 #define BITS_RX_EN                      BIT(1)
  29 #define REC_FILT_CONTROL                0x0064
  30 #define BIT_CRC_ERR_PASS                BIT(5)
  31 #define BIT_PAUSE_FRM_PASS              BIT(4)
  32 #define BIT_VLAN_DROP_EN                BIT(3)
  33 #define BIT_BC_DROP_EN                  BIT(2)
  34 #define BIT_MC_MATCH_EN                 BIT(1)
  35 #define BIT_UC_MATCH_EN                 BIT(0)
  36 #define PORT_MC_ADDR_LOW                0x0068
  37 #define PORT_MC_ADDR_HIGH               0x006C
  38 #define CF_CRC_STRIP                    0x01b0
  39 #define MODE_CHANGE_EN                  0x01b4
  40 #define BIT_MODE_CHANGE_EN              BIT(0)
  41 #define COL_SLOT_TIME                   0x01c0
  42 #define RECV_CONTROL                    0x01e0
  43 #define BIT_STRIP_PAD_EN                BIT(3)
  44 #define BIT_RUNT_PKT_EN                 BIT(4)
  45 #define CONTROL_WORD                    0x0214
  46 #define MDIO_SINGLE_CMD                 0x03c0
  47 #define MDIO_SINGLE_DATA                0x03c4
  48 #define MDIO_CTRL                       0x03cc
  49 #define MDIO_RDATA_STATUS               0x03d0
  50
  51 #define MDIO_START                      BIT(20)
  52 #define MDIO_R_VALID                    BIT(0)
  53 #define MDIO_READ                       (BIT(17) | MDIO_START)
  54 #define MDIO_WRITE                      (BIT(16) | MDIO_START)
  55
  56 #define RX_FQ_START_ADDR                0x0500
  57 #define RX_FQ_DEPTH                     0x0504
  58 #define RX_FQ_WR_ADDR                   0x0508
  59 #define RX_FQ_RD_ADDR                   0x050c
  60 #define RX_FQ_VLDDESC_CNT               0x0510
  61 #define RX_FQ_ALEMPTY_TH                0x0514
  62 #define RX_FQ_REG_EN                    0x0518
  63 #define BITS_RX_FQ_START_ADDR_EN        BIT(2)
  64 #define BITS_RX_FQ_DEPTH_EN             BIT(1)
  65 #define BITS_RX_FQ_RD_ADDR_EN           BIT(0)
  66 #define RX_FQ_ALFULL_TH                 0x051c
  67 #define RX_BQ_START_ADDR                0x0520
  68 #define RX_BQ_DEPTH                     0x0524
  69 #define RX_BQ_WR_ADDR                   0x0528
  70 #define RX_BQ_RD_ADDR                   0x052c
  71 #define RX_BQ_FREE_DESC_CNT             0x0530
  72 #define RX_BQ_ALEMPTY_TH                0x0534
  73 #define RX_BQ_REG_EN                    0x0538
  74 #define BITS_RX_BQ_START_ADDR_EN        BIT(2)
  75 #define BITS_RX_BQ_DEPTH_EN             BIT(1)
  76 #define BITS_RX_BQ_WR_ADDR_EN           BIT(0)
  77 #define RX_BQ_ALFULL_TH                 0x053c
  78 #define TX_BQ_START_ADDR                0x0580
  79 #define TX_BQ_DEPTH                     0x0584
  80 #define TX_BQ_WR_ADDR                   0x0588
  81 #define TX_BQ_RD_ADDR                   0x058c
  82 #define TX_BQ_VLDDESC_CNT               0x0590
  83 #define TX_BQ_ALEMPTY_TH                0x0594
  84 #define TX_BQ_REG_EN                    0x0598
  85 #define BITS_TX_BQ_START_ADDR_EN        BIT(2)
  86 #define BITS_TX_BQ_DEPTH_EN             BIT(1)
  87 #define BITS_TX_BQ_RD_ADDR_EN           BIT(0)
  88 #define TX_BQ_ALFULL_TH                 0x059c
  89 #define TX_RQ_START_ADDR                0x05a0
  90 #define TX_RQ_DEPTH                     0x05a4
  91 #define TX_RQ_WR_ADDR                   0x05a8
  92 #define TX_RQ_RD_ADDR                   0x05ac
  93 #define TX_RQ_FREE_DESC_CNT             0x05b0
  94 #define TX_RQ_ALEMPTY_TH                0x05b4
  95 #define TX_RQ_REG_EN                    0x05b8
  96 #define BITS_TX_RQ_START_ADDR_EN        BIT(2)
  97 #define BITS_TX_RQ_DEPTH_EN             BIT(1)
  98 #define BITS_TX_RQ_WR_ADDR_EN           BIT(0)
  99 #define TX_RQ_ALFULL_TH                 0x05bc
 100 #define RAW_PMU_INT                     0x05c0
 101 #define ENA_PMU_INT                     0x05c4
 102 #define STATUS_PMU_INT                  0x05c8
 103 #define MAC_FIFO_ERR_IN                 BIT(30)
 104 #define TX_RQ_IN_TIMEOUT_INT            BIT(29)
 105 #define RX_BQ_IN_TIMEOUT_INT            BIT(28)
 106 #define TXOUTCFF_FULL_INT               BIT(27)
 107 #define TXOUTCFF_EMPTY_INT              BIT(26)
 108 #define TXCFF_FULL_INT                  BIT(25)
 109 #define TXCFF_EMPTY_INT                 BIT(24)
 110 #define RXOUTCFF_FULL_INT               BIT(23)
 111 #define RXOUTCFF_EMPTY_INT              BIT(22)
 112 #define RXCFF_FULL_INT                  BIT(21)
 113 #define RXCFF_EMPTY_INT                 BIT(20)
 114 #define TX_RQ_IN_INT                    BIT(19)
 115 #define TX_BQ_OUT_INT                   BIT(18)
 116 #define RX_BQ_IN_INT                    BIT(17)
 117 #define RX_FQ_OUT_INT                   BIT(16)
 118 #define TX_RQ_EMPTY_INT                 BIT(15)
 119 #define TX_RQ_FULL_INT                  BIT(14)
 120 #define TX_RQ_ALEMPTY_INT               BIT(13)
 121 #define TX_RQ_ALFULL_INT                BIT(12)
 122 #define TX_BQ_EMPTY_INT                 BIT(11)
 123 #define TX_BQ_FULL_INT                  BIT(10)
 124 #define TX_BQ_ALEMPTY_INT               BIT(9)
 125 #define TX_BQ_ALFULL_INT                BIT(8)
 126 #define RX_BQ_EMPTY_INT                 BIT(7)
 127 #define RX_BQ_FULL_INT                  BIT(6)
 128 #define RX_BQ_ALEMPTY_INT               BIT(5)
 129 #define RX_BQ_ALFULL_INT                BIT(4)
 130 #define RX_FQ_EMPTY_INT                 BIT(3)
 131 #define RX_FQ_FULL_INT                  BIT(2)
 132 #define RX_FQ_ALEMPTY_INT               BIT(1)
 133 #define RX_FQ_ALFULL_INT                BIT(0)
 134
 135 #define DEF_INT_MASK                    (RX_BQ_IN_INT | RX_BQ_IN_TIMEOUT_INT | \
 136                                         TX_RQ_IN_INT | TX_RQ_IN_TIMEOUT_INT)
 137
 138 #define DESC_WR_RD_ENA                  0x05cc
 139 #define IN_QUEUE_TH                     0x05d8
 140 #define OUT_QUEUE_TH                    0x05dc
 141 #define QUEUE_TX_BQ_SHIFT               16
 142 #define RX_BQ_IN_TIMEOUT_TH             0x05e0
 143 #define TX_RQ_IN_TIMEOUT_TH             0x05e4
 144 #define STOP_CMD                        0x05e8
 145 #define BITS_TX_STOP                    BIT(1)
 146 #define BITS_RX_STOP                    BIT(0)
 147 #define FLUSH_CMD                       0x05eC
 148 #define BITS_TX_FLUSH_CMD               BIT(5)
 149 #define BITS_RX_FLUSH_CMD               BIT(4)
 150 #define BITS_TX_FLUSH_FLAG_DOWN         BIT(3)
 151 #define BITS_TX_FLUSH_FLAG_UP           BIT(2)
 152 #define BITS_RX_FLUSH_FLAG_DOWN         BIT(1)
 153 #define BITS_RX_FLUSH_FLAG_UP           BIT(0)
 154 #define RX_CFF_NUM_REG                  0x05f0
 155 #define PMU_FSM_REG                     0x05f8
 156 #define RX_FIFO_PKT_IN_NUM              0x05fc
 157 #define RX_FIFO_PKT_OUT_NUM             0x0600
 158
 159 #define RGMII_SPEED_1000                0x2c
 160 #define RGMII_SPEED_100                 0x2f
 161 #define RGMII_SPEED_10                  0x2d
 162 #define MII_SPEED_100                   0x0f
 163 #define MII_SPEED_10                    0x0d
 164 #define GMAC_SPEED_1000                 0x05
 165 #define GMAC_SPEED_100                  0x01
 166 #define GMAC_SPEED_10                   0x00
 167 #define GMAC_FULL_DUPLEX                BIT(4)
 168
 169 #define RX_BQ_INT_THRESHOLD             0x01
 170 #define TX_RQ_INT_THRESHOLD             0x01
 171 #define RX_BQ_IN_TIMEOUT                0x10000
 172 #define TX_RQ_IN_TIMEOUT                0x50000
 173
 174 #define MAC_MAX_FRAME_SIZE              1600
 175 #define DESC_SIZE                       32
 176 #define RX_DESC_NUM                     1024
 177 #define TX_DESC_NUM                     1024
 178
 179 #define DESC_VLD_FREE                   0
 180 #define DESC_VLD_BUSY                   0x80000000
 181 #define DESC_FL_MID                     0
 182 #define DESC_FL_LAST                    0x20000000
 183 #define DESC_FL_FIRST                   0x40000000
 184 #define DESC_FL_FULL                    0x60000000
 185 #define DESC_DATA_LEN_OFF               16
 186 #define DESC_BUFF_LEN_OFF               0
 187 #define DESC_DATA_MASK                  0x7ff
 188 #define DESC_SG                         BIT(30)
 189 #define DESC_FRAGS_NUM_OFF              11
 190
 191 /* DMA descriptor ring helpers */
 192 #define dma_ring_incr(n, s)             (((n) + 1) & ((s) - 1))
 193 #define dma_cnt(n)                      ((n) >> 5)
 194 #define dma_byte(n)                     ((n) << 5)
 195
 196 #define HW_CAP_TSO                      BIT(0)
 197 #define GEMAC_V1                        0
 198 #define GEMAC_V2                        (GEMAC_V1 | HW_CAP_TSO)
 199 #define HAS_CAP_TSO(hw_cap)             ((hw_cap) & HW_CAP_TSO)
 200
 201 #define PHY_RESET_DELAYS_PROPERTY       "hisilicon,phy-reset-delays-us"
 202
 203 enum phy_reset_delays {
 204         PRE_DELAY,
 205         PULSE,
 206         POST_DELAY,
 207         DELAYS_NUM,
 208 };
 209
 210 struct hix5hd2_desc {
 211         __le32 buff_addr;
 212         __le32 cmd;
 213 } __aligned(32);
 214
 215 struct hix5hd2_desc_sw {
 216         struct hix5hd2_desc *desc;
 217         dma_addr_t      phys_addr;
 218         unsigned int    count;
 219         unsigned int    size;
 220 };
 221
 222 struct hix5hd2_sg_desc_ring {
 223         struct sg_desc *desc;
 224         dma_addr_t phys_addr;
 225 };
 226
 227 struct frags_info {
 228         __le32 addr;
 229         __le32 size;
 230 };
 231
 232 /* hardware supported max skb frags num */
 233 #define SG_MAX_SKB_FRAGS        17
 234 struct sg_desc {
 235         __le32 total_len;
 236         __le32 resvd0;
 237         __le32 linear_addr;
 238         __le32 linear_len;
 239         /* reserve one more frags for memory alignment */
 240         struct frags_info frags[SG_MAX_SKB_FRAGS + 1];
 241 };
 242
 243 #define QUEUE_NUMS      4
 244 struct hix5hd2_priv {
 245         struct hix5hd2_desc_sw pool[QUEUE_NUMS];
 246 #define rx_fq           pool[0]
 247 #define rx_bq           pool[1]
 248 #define tx_bq           pool[2]
 249 #define tx_rq           pool[3]
 250         struct hix5hd2_sg_desc_ring tx_ring;
 251
 252         void __iomem *base;
 253         void __iomem *ctrl_base;
 254
 255         struct sk_buff *tx_skb[TX_DESC_NUM];
 256         struct sk_buff *rx_skb[RX_DESC_NUM];
 257
 258         struct device *dev;
 259         struct net_device *netdev;
 260
 261         struct device_node *phy_node;
 262         phy_interface_t phy_mode;
 263
 264         unsigned long hw_cap;
 265         unsigned int speed;
 266         unsigned int duplex;
 267
 268         struct clk *mac_core_clk;
 269         struct clk *mac_ifc_clk;
 270         struct reset_control *mac_core_rst;
 271         struct reset_control *mac_ifc_rst;
 272         struct reset_control *phy_rst;
 273         u32 phy_reset_delays[DELAYS_NUM];
 274         struct mii_bus *bus;
 275         struct napi_struct napi;
 276         struct work_struct tx_timeout_task;
 277 };
 278
 279 static inline void hix5hd2_mac_interface_reset(struct hix5hd2_priv *priv)
 280 {
 281         if (!priv->mac_ifc_rst)
 282                 return;
 283
 284         reset_control_assert(priv->mac_ifc_rst);
 285         reset_control_deassert(priv->mac_ifc_rst);
 286 }
 287
 288 static void hix5hd2_config_port(struct net_device *dev, u32 speed, u32 duplex)
 289 {
 290         struct hix5hd2_priv *priv = netdev_priv(dev);
 291         u32 val;
 292
 293         priv->speed = speed;
 294         priv->duplex = duplex;
 295
 296         switch (priv->phy_mode) {
 297         case PHY_INTERFACE_MODE_RGMII:
 298                 if (speed == SPEED_1000)
 299                         val = RGMII_SPEED_1000;
 300                 else if (speed == SPEED_100)
 301                         val = RGMII_SPEED_100;
 302                 else
 303                         val = RGMII_SPEED_10;
 304                 break;
 305         case PHY_INTERFACE_MODE_MII:
 306                 if (speed == SPEED_100)
 307                         val = MII_SPEED_100;
 308                 else
 309                         val = MII_SPEED_10;
 310                 break;
 311         default:
 312                 netdev_warn(dev, "not supported mode\n");
 313                 val = MII_SPEED_10;
 314                 break;
 315         }
 316
 317         if (duplex)
 318                 val |= GMAC_FULL_DUPLEX;
 319         writel_relaxed(val, priv->ctrl_base);
 320         hix5hd2_mac_interface_reset(priv);
 321
 322         writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN);
 323         if (speed == SPEED_1000)
 324                 val = GMAC_SPEED_1000;
 325         else if (speed == SPEED_100)
 326                 val = GMAC_SPEED_100;
 327         else
 328                 val = GMAC_SPEED_10;
 329         writel_relaxed(val, priv->base + PORT_MODE);
 330         writel_relaxed(0, priv->base + MODE_CHANGE_EN);
 331         writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL);
 332 }
 333
 334 static void hix5hd2_set_desc_depth(struct hix5hd2_priv *priv, int rx, int tx)
 335 {
 336         writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN);
 337         writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH);
 338         writel_relaxed(0, priv->base + RX_FQ_REG_EN);
 339
 340         writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN);
 341         writel_relaxed(rx << 3, priv->base + RX_BQ_DEPTH);
 342         writel_relaxed(0, priv->base + RX_BQ_REG_EN);
 343
 344         writel_relaxed(BITS_TX_BQ_DEPTH_EN, priv->base + TX_BQ_REG_EN);
 345         writel_relaxed(tx << 3, priv->base + TX_BQ_DEPTH);
 346         writel_relaxed(0, priv->base + TX_BQ_REG_EN);
 347
 348         writel_relaxed(BITS_TX_RQ_DEPTH_EN, priv->base + TX_RQ_REG_EN);
 349         writel_relaxed(tx << 3, priv->base + TX_RQ_DEPTH);
 350         writel_relaxed(0, priv->base + TX_RQ_REG_EN);
 351 }
 352
 353 static void hix5hd2_set_rx_fq(struct hix5hd2_priv *priv, dma_addr_t phy_addr)
 354 {
 355         writel_relaxed(BITS_RX_FQ_START_ADDR_EN, priv->base + RX_FQ_REG_EN);
 356         writel_relaxed(phy_addr, priv->base + RX_FQ_START_ADDR);
 357         writel_relaxed(0, priv->base + RX_FQ_REG_EN);
 358 }
 359
 360 static void hix5hd2_set_rx_bq(struct hix5hd2_priv *priv, dma_addr_t phy_addr)
 361 {
 362         writel_relaxed(BITS_RX_BQ_START_ADDR_EN, priv->base + RX_BQ_REG_EN);
 363         writel_relaxed(phy_addr, priv->base + RX_BQ_START_ADDR);
 364         writel_relaxed(0, priv->base + RX_BQ_REG_EN);
 365 }
 366
 367 static void hix5hd2_set_tx_bq(struct hix5hd2_priv *priv, dma_addr_t phy_addr)
 368 {
 369         writel_relaxed(BITS_TX_BQ_START_ADDR_EN, priv->base + TX_BQ_REG_EN);
 370         writel_relaxed(phy_addr, priv->base + TX_BQ_START_ADDR);
 371         writel_relaxed(0, priv->base + TX_BQ_REG_EN);
 372 }
 373
 374 static void hix5hd2_set_tx_rq(struct hix5hd2_priv *priv, dma_addr_t phy_addr)
 375 {
 376         writel_relaxed(BITS_TX_RQ_START_ADDR_EN, priv->base + TX_RQ_REG_EN);
 377         writel_relaxed(phy_addr, priv->base + TX_RQ_START_ADDR);
 378         writel_relaxed(0, priv->base + TX_RQ_REG_EN);
 379 }
 380
 381 static void hix5hd2_set_desc_addr(struct hix5hd2_priv *priv)
 382 {
 383         hix5hd2_set_rx_fq(priv, priv->rx_fq.phys_addr);
 384         hix5hd2_set_rx_bq(priv, priv->rx_bq.phys_addr);
 385         hix5hd2_set_tx_rq(priv, priv->tx_rq.phys_addr);
 386         hix5hd2_set_tx_bq(priv, priv->tx_bq.phys_addr);
 387 }
 388
 389 static void hix5hd2_hw_init(struct hix5hd2_priv *priv)
 390 {
 391         u32 val;
 392
 393         /* disable and clear all interrupts */
 394         writel_relaxed(0, priv->base + ENA_PMU_INT);
 395         writel_relaxed(~0, priv->base + RAW_PMU_INT);
 396
 397         writel_relaxed(BIT_CRC_ERR_PASS, priv->base + REC_FILT_CONTROL);
 398         writel_relaxed(MAC_MAX_FRAME_SIZE, priv->base + CONTROL_WORD);
 399         writel_relaxed(0, priv->base + COL_SLOT_TIME);
 400
 401         val = RX_BQ_INT_THRESHOLD | TX_RQ_INT_THRESHOLD << QUEUE_TX_BQ_SHIFT;
 402         writel_relaxed(val, priv->base + IN_QUEUE_TH);
 403
 404         writel_relaxed(RX_BQ_IN_TIMEOUT, priv->base + RX_BQ_IN_TIMEOUT_TH);
 405         writel_relaxed(TX_RQ_IN_TIMEOUT, priv->base + TX_RQ_IN_TIMEOUT_TH);
 406
 407         hix5hd2_set_desc_depth(priv, RX_DESC_NUM, TX_DESC_NUM);
 408         hix5hd2_set_desc_addr(priv);
 409 }
 410
 411 static void hix5hd2_irq_enable(struct hix5hd2_priv *priv)
 412 {
 413         writel_relaxed(DEF_INT_MASK, priv->base + ENA_PMU_INT);
 414 }
 415
 416 static void hix5hd2_irq_disable(struct hix5hd2_priv *priv)
 417 {
 418         writel_relaxed(0, priv->base + ENA_PMU_INT);
 419 }
 420
 421 static void hix5hd2_port_enable(struct hix5hd2_priv *priv)
 422 {
 423         writel_relaxed(0xf, priv->base + DESC_WR_RD_ENA);
 424         writel_relaxed(BITS_RX_EN | BITS_TX_EN, priv->base + PORT_EN);
 425 }
 426
 427 static void hix5hd2_port_disable(struct hix5hd2_priv *priv)
 428 {
 429         writel_relaxed(~(u32)(BITS_RX_EN | BITS_TX_EN), priv->base + PORT_EN);
 430         writel_relaxed(0, priv->base + DESC_WR_RD_ENA);
 431 }
 432
 433 static void hix5hd2_hw_set_mac_addr(struct net_device *dev)
 434 {
 435         struct hix5hd2_priv *priv = netdev_priv(dev);
 436         unsigned char *mac = dev->dev_addr;
 437         u32 val;
 438
 439         val = mac[1] | (mac[0] << 8);
 440         writel_relaxed(val, priv->base + STATION_ADDR_HIGH);
 441
 442         val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
 443         writel_relaxed(val, priv->base + STATION_ADDR_LOW);
 444 }
 445
 446 static int hix5hd2_net_set_mac_address(struct net_device *dev, void *p)
 447 {
 448         int ret;
 449
 450         ret = eth_mac_addr(dev, p);
 451         if (!ret)
 452                 hix5hd2_hw_set_mac_addr(dev);
 453
 454         return ret;
 455 }
 456
 457 static void hix5hd2_adjust_link(struct net_device *dev)
 458 {
 459         struct hix5hd2_priv *priv = netdev_priv(dev);
 460         struct phy_device *phy = dev->phydev;
 461
 462         if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex)) {
 463                 hix5hd2_config_port(dev, phy->speed, phy->duplex);
 464                 phy_print_status(phy);
 465         }
 466 }
 467
 468 static void hix5hd2_rx_refill(struct hix5hd2_priv *priv)
 469 {
 470         struct hix5hd2_desc *desc;
 471         struct sk_buff *skb;
 472         u32 start, end, num, pos, i;
 473         u32 len = MAC_MAX_FRAME_SIZE;
 474         dma_addr_t addr;
 475
 476         /* software write pointer */
 477         start = dma_cnt(readl_relaxed(priv->base + RX_FQ_WR_ADDR));
 478         /* logic read pointer */
 479         end = dma_cnt(readl_relaxed(priv->base + RX_FQ_RD_ADDR));
 480         num = CIRC_SPACE(start, end, RX_DESC_NUM);
 481
 482         for (i = 0, pos = start; i < num; i++) {
 483                 if (priv->rx_skb[pos]) {
 484                         break;
 485                 } else {
 486                         skb = netdev_alloc_skb_ip_align(priv->netdev, len);
 487                         if (unlikely(skb == NULL))
 488                                 break;
 489                 }
 490
 491                 addr = dma_map_single(priv->dev, skb->data, len, DMA_FROM_DEVICE);
 492                 if (dma_mapping_error(priv->dev, addr)) {
 493                         dev_kfree_skb_any(skb);
 494                         break;
 495                 }
 496
 497                 desc = priv->rx_fq.desc + pos;
 498                 desc->buff_addr = cpu_to_le32(addr);
 499                 priv->rx_skb[pos] = skb;
 500                 desc->cmd = cpu_to_le32(DESC_VLD_FREE |
 501                                         (len - 1) << DESC_BUFF_LEN_OFF);
 502                 pos = dma_ring_incr(pos, RX_DESC_NUM);
 503         }
 504
 505         /* ensure desc updated */
 506         wmb();
 507
 508         if (pos != start)
 509                 writel_relaxed(dma_byte(pos), priv->base + RX_FQ_WR_ADDR);
 510 }
 511
 512 static int hix5hd2_rx(struct net_device *dev, int limit)
 513 {
 514         struct hix5hd2_priv *priv = netdev_priv(dev);
 515         struct sk_buff *skb;
 516         struct hix5hd2_desc *desc;
 517         dma_addr_t addr;
 518         u32 start, end, num, pos, i, len;
 519
 520         /* software read pointer */
 521         start = dma_cnt(readl_relaxed(priv->base + RX_BQ_RD_ADDR));
 522         /* logic write pointer */
 523         end = dma_cnt(readl_relaxed(priv->base + RX_BQ_WR_ADDR));
 524         num = CIRC_CNT(end, start, RX_DESC_NUM);
 525         if (num > limit)
 526                 num = limit;
 527
 528         /* ensure get updated desc */
 529         rmb();
 530         for (i = 0, pos = start; i < num; i++) {
 531                 skb = priv->rx_skb[pos];
 532                 if (unlikely(!skb)) {
 533                         netdev_err(dev, "inconsistent rx_skb\n");
 534                         break;
 535                 }
 536                 priv->rx_skb[pos] = NULL;
 537
 538                 desc = priv->rx_bq.desc + pos;
 539                 len = (le32_to_cpu(desc->cmd) >> DESC_DATA_LEN_OFF) &
 540                        DESC_DATA_MASK;
 541                 addr = le32_to_cpu(desc->buff_addr);
 542                 dma_unmap_single(priv->dev, addr, MAC_MAX_FRAME_SIZE,
 543                                  DMA_FROM_DEVICE);
 544
 545                 skb_put(skb, len);
 546                 if (skb->len > MAC_MAX_FRAME_SIZE) {
 547                         netdev_err(dev, "rcv len err, len = %d\n", skb->len);
 548                         dev->stats.rx_errors++;
 549                         dev->stats.rx_length_errors++;
 550                         dev_kfree_skb_any(skb);
 551                         goto next;
 552                 }
 553
 554                 skb->protocol = eth_type_trans(skb, dev);
 555                 napi_gro_receive(&priv->napi, skb);
 556                 dev->stats.rx_packets++;
 557                 dev->stats.rx_bytes += skb->len;
 558 next:
 559                 pos = dma_ring_incr(pos, RX_DESC_NUM);
 560         }
 561
 562         if (pos != start)
 563                 writel_relaxed(dma_byte(pos), priv->base + RX_BQ_RD_ADDR);
 564
 565         hix5hd2_rx_refill(priv);
 566
 567         return num;
 568 }
 569
 570 static void hix5hd2_clean_sg_desc(struct hix5hd2_priv *priv,
 571                                   struct sk_buff *skb, u32 pos)
 572 {
 573         struct sg_desc *desc;
 574         dma_addr_t addr;
 575         u32 len;
 576         int i;
 577
 578         desc = priv->tx_ring.desc + pos;
 579
 580         addr = le32_to_cpu(desc->linear_addr);
 581         len = le32_to_cpu(desc->linear_len);
 582         dma_unmap_single(priv->dev, addr, len, DMA_TO_DEVICE);
 583
 584         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 585                 addr = le32_to_cpu(desc->frags[i].addr);
 586                 len = le32_to_cpu(desc->frags[i].size);
 587                 dma_unmap_page(priv->dev, addr, len, DMA_TO_DEVICE);
 588         }
 589 }
 590
 591 static void hix5hd2_xmit_reclaim(struct net_device *dev)
 592 {
 593         struct sk_buff *skb;
 594         struct hix5hd2_desc *desc;
 595         struct hix5hd2_priv *priv = netdev_priv(dev);
 596         unsigned int bytes_compl = 0, pkts_compl = 0;
 597         u32 start, end, num, pos, i;
 598         dma_addr_t addr;
 599
 600         netif_tx_lock(dev);
 601
 602         /* software read */
 603         start = dma_cnt(readl_relaxed(priv->base + TX_RQ_RD_ADDR));
 604         /* logic write */
 605         end = dma_cnt(readl_relaxed(priv->base + TX_RQ_WR_ADDR));
 606         num = CIRC_CNT(end, start, TX_DESC_NUM);
 607
 608         for (i = 0, pos = start; i < num; i++) {
 609                 skb = priv->tx_skb[pos];
 610                 if (unlikely(!skb)) {
 611                         netdev_err(dev, "inconsistent tx_skb\n");
 612                         break;
 613                 }
 614
 615                 pkts_compl++;
 616                 bytes_compl += skb->len;
 617                 desc = priv->tx_rq.desc + pos;
 618
 619                 if (skb_shinfo(skb)->nr_frags) {
 620                         hix5hd2_clean_sg_desc(priv, skb, pos);
 621                 } else {
 622                         addr = le32_to_cpu(desc->buff_addr);
 623                         dma_unmap_single(priv->dev, addr, skb->len,
 624                                          DMA_TO_DEVICE);
 625                 }
 626
 627                 priv->tx_skb[pos] = NULL;
 628                 dev_consume_skb_any(skb);
 629                 pos = dma_ring_incr(pos, TX_DESC_NUM);
 630         }
 631
 632         if (pos != start)
 633                 writel_relaxed(dma_byte(pos), priv->base + TX_RQ_RD_ADDR);
 634
 635         netif_tx_unlock(dev);
 636
 637         if (pkts_compl || bytes_compl)
 638                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
 639
 640         if (unlikely(netif_queue_stopped(priv->netdev)) && pkts_compl)
 641                 netif_wake_queue(priv->netdev);
 642 }
 643
 644 static int hix5hd2_poll(struct napi_struct *napi, int budget)
 645 {
 646         struct hix5hd2_priv *priv = container_of(napi,
 647                                 struct hix5hd2_priv, napi);
 648         struct net_device *dev = priv->netdev;
 649         int work_done = 0, task = budget;
 650         int ints, num;
 651
 652         do {
 653                 hix5hd2_xmit_reclaim(dev);
 654                 num = hix5hd2_rx(dev, task);
 655                 work_done += num;
 656                 task -= num;
 657                 if ((work_done >= budget) || (num == 0))
 658                         break;
 659
 660                 ints = readl_relaxed(priv->base + RAW_PMU_INT);
 661                 writel_relaxed(ints, priv->base + RAW_PMU_INT);
 662         } while (ints & DEF_INT_MASK);
 663
 664         if (work_done < budget) {
 665                 napi_complete_done(napi, work_done);
 666                 hix5hd2_irq_enable(priv);
 667         }
 668
 669         return work_done;
 670 }
 671
 672 static irqreturn_t hix5hd2_interrupt(int irq, void *dev_id)
 673 {
 674         struct net_device *dev = (struct net_device *)dev_id;
 675         struct hix5hd2_priv *priv = netdev_priv(dev);
 676         int ints = readl_relaxed(priv->base + RAW_PMU_INT);
 677
 678         writel_relaxed(ints, priv->base + RAW_PMU_INT);
 679         if (likely(ints & DEF_INT_MASK)) {
 680                 hix5hd2_irq_disable(priv);
 681                 napi_schedule(&priv->napi);
 682         }
 683
 684         return IRQ_HANDLED;
 685 }
 686
 687 static u32 hix5hd2_get_desc_cmd(struct sk_buff *skb, unsigned long hw_cap)
 688 {
 689         u32 cmd = 0;
 690
 691         if (HAS_CAP_TSO(hw_cap)) {
 692                 if (skb_shinfo(skb)->nr_frags)
 693                         cmd |= DESC_SG;
 694                 cmd |= skb_shinfo(skb)->nr_frags << DESC_FRAGS_NUM_OFF;
 695         } else {
 696                 cmd |= DESC_FL_FULL |
 697                         ((skb->len & DESC_DATA_MASK) << DESC_BUFF_LEN_OFF);
 698         }
 699
 700         cmd |= (skb->len & DESC_DATA_MASK) << DESC_DATA_LEN_OFF;
 701         cmd |= DESC_VLD_BUSY;
 702
 703         return cmd;
 704 }
 705
 706 static int hix5hd2_fill_sg_desc(struct hix5hd2_priv *priv,
 707                                 struct sk_buff *skb, u32 pos)
 708 {
 709         struct sg_desc *desc;
 710         dma_addr_t addr;
 711         int ret;
 712         int i;
 713
 714         desc = priv->tx_ring.desc + pos;
 715
 716         desc->total_len = cpu_to_le32(skb->len);
 717         addr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
 718                               DMA_TO_DEVICE);
 719         if (unlikely(dma_mapping_error(priv->dev, addr)))
 720                 return -EINVAL;
 721         desc->linear_addr = cpu_to_le32(addr);
 722         desc->linear_len = cpu_to_le32(skb_headlen(skb));
 723
 724         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 725                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 726                 int len = frag->size;
 727
 728                 addr = skb_frag_dma_map(priv->dev, frag, 0, len, DMA_TO_DEVICE);
 729                 ret = dma_mapping_error(priv->dev, addr);
 730                 if (unlikely(ret))
 731                         return -EINVAL;
 732                 desc->frags[i].addr = cpu_to_le32(addr);
 733                 desc->frags[i].size = cpu_to_le32(len);
 734         }
 735
 736         return 0;
 737 }
 738
 739 static netdev_tx_t hix5hd2_net_xmit(struct sk_buff *skb, struct net_device *dev)
 740 {
 741         struct hix5hd2_priv *priv = netdev_priv(dev);
 742         struct hix5hd2_desc *desc;
 743         dma_addr_t addr;
 744         u32 pos;
 745         u32 cmd;
 746         int ret;
 747
 748         /* software write pointer */
 749         pos = dma_cnt(readl_relaxed(priv->base + TX_BQ_WR_ADDR));
 750         if (unlikely(priv->tx_skb[pos])) {
 751                 dev->stats.tx_dropped++;
 752                 dev->stats.tx_fifo_errors++;
 753                 netif_stop_queue(dev);
 754                 return NETDEV_TX_BUSY;
 755         }
 756
 757         desc = priv->tx_bq.desc + pos;
 758
 759         cmd = hix5hd2_get_desc_cmd(skb, priv->hw_cap);
 760         desc->cmd = cpu_to_le32(cmd);
 761
 762         if (skb_shinfo(skb)->nr_frags) {
 763                 ret = hix5hd2_fill_sg_desc(priv, skb, pos);
 764                 if (unlikely(ret)) {
 765                         dev_kfree_skb_any(skb);
 766                         dev->stats.tx_dropped++;
 767                         return NETDEV_TX_OK;
 768                 }
 769                 addr = priv->tx_ring.phys_addr + pos * sizeof(struct sg_desc);
 770         } else {
 771                 addr = dma_map_single(priv->dev, skb->data, skb->len,
 772                                       DMA_TO_DEVICE);
 773                 if (unlikely(dma_mapping_error(priv->dev, addr))) {
 774                         dev_kfree_skb_any(skb);
 775                         dev->stats.tx_dropped++;
 776                         return NETDEV_TX_OK;
 777                 }
 778         }
 779         desc->buff_addr = cpu_to_le32(addr);
 780
 781         priv->tx_skb[pos] = skb;
 782
 783         /* ensure desc updated */
 784         wmb();
 785
 786         pos = dma_ring_incr(pos, TX_DESC_NUM);
 787         writel_relaxed(dma_byte(pos), priv->base + TX_BQ_WR_ADDR);
 788
 789         netif_trans_update(dev);
 790         dev->stats.tx_packets++;
 791         dev->stats.tx_bytes += skb->len;
 792         netdev_sent_queue(dev, skb->len);
 793
 794         return NETDEV_TX_OK;
 795 }
 796
 797 static void hix5hd2_free_dma_desc_rings(struct hix5hd2_priv *priv)
 798 {
 799         struct hix5hd2_desc *desc;
 800         dma_addr_t addr;
 801         int i;
 802
 803         for (i = 0; i < RX_DESC_NUM; i++) {
 804                 struct sk_buff *skb = priv->rx_skb[i];
 805                 if (skb == NULL)
 806                         continue;
 807
 808                 desc = priv->rx_fq.desc + i;
 809                 addr = le32_to_cpu(desc->buff_addr);
 810                 dma_unmap_single(priv->dev, addr,
 811                                  MAC_MAX_FRAME_SIZE, DMA_FROM_DEVICE);
 812                 dev_kfree_skb_any(skb);
 813                 priv->rx_skb[i] = NULL;
 814         }
 815
 816         for (i = 0; i < TX_DESC_NUM; i++) {
 817                 struct sk_buff *skb = priv->tx_skb[i];
 818                 if (skb == NULL)
 819                         continue;
 820
 821                 desc = priv->tx_rq.desc + i;
 822                 addr = le32_to_cpu(desc->buff_addr);
 823                 dma_unmap_single(priv->dev, addr, skb->len, DMA_TO_DEVICE);
 824                 dev_kfree_skb_any(skb);
 825                 priv->tx_skb[i] = NULL;
 826         }
 827 }
 828
 829 static int hix5hd2_net_open(struct net_device *dev)
 830 {
 831         struct hix5hd2_priv *priv = netdev_priv(dev);
 832         struct phy_device *phy;
 833         int ret;
 834
 835         ret = clk_prepare_enable(priv->mac_core_clk);
 836         if (ret < 0) {
 837                 netdev_err(dev, "failed to enable mac core clk %d\n", ret);
 838                 return ret;
 839         }
 840
 841         ret = clk_prepare_enable(priv->mac_ifc_clk);
 842         if (ret < 0) {
 843                 clk_disable_unprepare(priv->mac_core_clk);
 844                 netdev_err(dev, "failed to enable mac ifc clk %d\n", ret);
 845                 return ret;
 846         }
 847
 848         phy = of_phy_connect(dev, priv->phy_node,
 849                              &hix5hd2_adjust_link, 0, priv->phy_mode);
 850         if (!phy) {
 851                 clk_disable_unprepare(priv->mac_ifc_clk);
 852                 clk_disable_unprepare(priv->mac_core_clk);
 853                 return -ENODEV;
 854         }
 855
 856         phy_start(phy);
 857         hix5hd2_hw_init(priv);
 858         hix5hd2_rx_refill(priv);
 859
 860         netdev_reset_queue(dev);
 861         netif_start_queue(dev);
 862         napi_enable(&priv->napi);
 863
 864         hix5hd2_port_enable(priv);
 865         hix5hd2_irq_enable(priv);
 866
 867         return 0;
 868 }
 869
 870 static int hix5hd2_net_close(struct net_device *dev)
 871 {
 872         struct hix5hd2_priv *priv = netdev_priv(dev);
 873
 874         hix5hd2_port_disable(priv);
 875         hix5hd2_irq_disable(priv);
 876         napi_disable(&priv->napi);
 877         netif_stop_queue(dev);
 878         hix5hd2_free_dma_desc_rings(priv);
 879
 880         if (dev->phydev) {
 881                 phy_stop(dev->phydev);
 882                 phy_disconnect(dev->phydev);
 883         }
 884
 885         clk_disable_unprepare(priv->mac_ifc_clk);
 886         clk_disable_unprepare(priv->mac_core_clk);
 887
 888         return 0;
 889 }
 890
 891 static void hix5hd2_tx_timeout_task(struct work_struct *work)
 892 {
 893         struct hix5hd2_priv *priv;
 894
 895         priv = container_of(work, struct hix5hd2_priv, tx_timeout_task);
 896         hix5hd2_net_close(priv->netdev);
 897         hix5hd2_net_open(priv->netdev);
 898 }
 899
 900 static void hix5hd2_net_timeout(struct net_device *dev)
 901 {
 902         struct hix5hd2_priv *priv = netdev_priv(dev);
 903
 904         schedule_work(&priv->tx_timeout_task);
 905 }
 906
 907 static const struct net_device_ops hix5hd2_netdev_ops = {
 908         .ndo_open               = hix5hd2_net_open,
 909         .ndo_stop               = hix5hd2_net_close,
 910         .ndo_start_xmit         = hix5hd2_net_xmit,
 911         .ndo_tx_timeout         = hix5hd2_net_timeout,
 912         .ndo_set_mac_address    = hix5hd2_net_set_mac_address,
 913 };
 914
 915 static const struct ethtool_ops hix5hd2_ethtools_ops = {
 916         .get_link               = ethtool_op_get_link,
 917         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
 918         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
 919 };
 920
 921 static int hix5hd2_mdio_wait_ready(struct mii_bus *bus)
 922 {
 923         struct hix5hd2_priv *priv = bus->priv;
 924         void __iomem *base = priv->base;
 925         int i, timeout = 10000;
 926
 927         for (i = 0; readl_relaxed(base + MDIO_SINGLE_CMD) & MDIO_START; i++) {
 928                 if (i == timeout)
 929                         return -ETIMEDOUT;
 930                 usleep_range(10, 20);
 931         }
 932
 933         return 0;
 934 }
 935
 936 static int hix5hd2_mdio_read(struct mii_bus *bus, int phy, int reg)
 937 {
 938         struct hix5hd2_priv *priv = bus->priv;
 939         void __iomem *base = priv->base;
 940         int val, ret;
 941
 942         ret = hix5hd2_mdio_wait_ready(bus);
 943         if (ret < 0)
 944                 goto out;
 945
 946         writel_relaxed(MDIO_READ | phy << 8 | reg, base + MDIO_SINGLE_CMD);
 947         ret = hix5hd2_mdio_wait_ready(bus);
 948         if (ret < 0)
 949                 goto out;
 950
 951         val = readl_relaxed(base + MDIO_RDATA_STATUS);
 952         if (val & MDIO_R_VALID) {
 953                 dev_err(bus->parent, "SMI bus read not valid\n");
 954                 ret = -ENODEV;
 955                 goto out;
 956         }
 957
 958         val = readl_relaxed(priv->base + MDIO_SINGLE_DATA);
 959         ret = (val >> 16) & 0xFFFF;
 960 out:
 961         return ret;
 962 }
 963
 964 static int hix5hd2_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
 965 {
 966         struct hix5hd2_priv *priv = bus->priv;
 967         void __iomem *base = priv->base;
 968         int ret;
 969
 970         ret = hix5hd2_mdio_wait_ready(bus);
 971         if (ret < 0)
 972                 goto out;
 973
 974         writel_relaxed(val, base + MDIO_SINGLE_DATA);
 975         writel_relaxed(MDIO_WRITE | phy << 8 | reg, base + MDIO_SINGLE_CMD);
 976         ret = hix5hd2_mdio_wait_ready(bus);
 977 out:
 978         return ret;
 979 }
 980
 981 static void hix5hd2_destroy_hw_desc_queue(struct hix5hd2_priv *priv)
 982 {
 983         int i;
 984
 985         for (i = 0; i < QUEUE_NUMS; i++) {
 986                 if (priv->pool[i].desc) {
 987                         dma_free_coherent(priv->dev, priv->pool[i].size,
 988                                           priv->pool[i].desc,
 989                                           priv->pool[i].phys_addr);
 990                         priv->pool[i].desc = NULL;
 991                 }
 992         }
 993 }
 994
 995 static int hix5hd2_init_hw_desc_queue(struct hix5hd2_priv *priv)
 996 {
 997         struct device *dev = priv->dev;
 998         struct hix5hd2_desc *virt_addr;
 999         dma_addr_t phys_addr;
1000         int size, i;
1001
1002         priv->rx_fq.count = RX_DESC_NUM;
1003         priv->rx_bq.count = RX_DESC_NUM;
1004         priv->tx_bq.count = TX_DESC_NUM;
1005         priv->tx_rq.count = TX_DESC_NUM;
1006
1007         for (i = 0; i < QUEUE_NUMS; i++) {
1008                 size = priv->pool[i].count * sizeof(struct hix5hd2_desc);
1009                 virt_addr = dma_alloc_coherent(dev, size, &phys_addr,
1010                                                GFP_KERNEL);
1011                 if (virt_addr == NULL)
1012                         goto error_free_pool;
1013
1014                 priv->pool[i].size = size;
1015                 priv->pool[i].desc = virt_addr;
1016                 priv->pool[i].phys_addr = phys_addr;
1017         }
1018         return 0;
1019
1020 error_free_pool:
1021         hix5hd2_destroy_hw_desc_queue(priv);
1022
1023         return -ENOMEM;
1024 }
1025
1026 static int hix5hd2_init_sg_desc_queue(struct hix5hd2_priv *priv)
1027 {
1028         struct sg_desc *desc;
1029         dma_addr_t phys_addr;
1030
1031         desc = (struct sg_desc *)dma_alloc_coherent(priv->dev,
1032                                 TX_DESC_NUM * sizeof(struct sg_desc),
1033                                 &phys_addr, GFP_KERNEL);
1034         if (!desc)
1035                 return -ENOMEM;
1036
1037         priv->tx_ring.desc = desc;
1038         priv->tx_ring.phys_addr = phys_addr;
1039
1040         return 0;
1041 }
1042
1043 static void hix5hd2_destroy_sg_desc_queue(struct hix5hd2_priv *priv)
1044 {
1045         if (priv->tx_ring.desc) {
1046                 dma_free_coherent(priv->dev,
1047                                   TX_DESC_NUM * sizeof(struct sg_desc),
1048                                   priv->tx_ring.desc, priv->tx_ring.phys_addr);
1049                 priv->tx_ring.desc = NULL;
1050         }
1051 }
1052
1053 static inline void hix5hd2_mac_core_reset(struct hix5hd2_priv *priv)
1054 {
1055         if (!priv->mac_core_rst)
1056                 return;
1057
1058         reset_control_assert(priv->mac_core_rst);
1059         reset_control_deassert(priv->mac_core_rst);
1060 }
1061
1062 static void hix5hd2_sleep_us(u32 time_us)
1063 {
1064         u32 time_ms;
1065
1066         if (!time_us)
1067                 return;
1068
1069         time_ms = DIV_ROUND_UP(time_us, 1000);
1070         if (time_ms < 20)
1071                 usleep_range(time_us, time_us + 500);
1072         else
1073                 msleep(time_ms);
1074 }
1075
1076 static void hix5hd2_phy_reset(struct hix5hd2_priv *priv)
1077 {
1078         /* To make sure PHY hardware reset success,
1079          * we must keep PHY in deassert state first and
1080          * then complete the hardware reset operation
1081          */
1082         reset_control_deassert(priv->phy_rst);
1083         hix5hd2_sleep_us(priv->phy_reset_delays[PRE_DELAY]);
1084
1085         reset_control_assert(priv->phy_rst);
1086         /* delay some time to ensure reset ok,
1087          * this depends on PHY hardware feature
1088          */
1089         hix5hd2_sleep_us(priv->phy_reset_delays[PULSE]);
1090         reset_control_deassert(priv->phy_rst);
1091         /* delay some time to ensure later MDIO access */
1092         hix5hd2_sleep_us(priv->phy_reset_delays[POST_DELAY]);
1093 }
1094
1095 static const struct of_device_id hix5hd2_of_match[];
1096
1097 static int hix5hd2_dev_probe(struct platform_device *pdev)
1098 {
1099         struct device *dev = &pdev->dev;
1100         struct device_node *node = dev->of_node;
1101         const struct of_device_id *of_id = NULL;
1102         struct net_device *ndev;
1103         struct hix5hd2_priv *priv;
1104         struct resource *res;
1105         struct mii_bus *bus;
1106         const char *mac_addr;
1107         int ret;
1108
1109         ndev = alloc_etherdev(sizeof(struct hix5hd2_priv));
1110         if (!ndev)
1111                 return -ENOMEM;
1112
1113         platform_set_drvdata(pdev, ndev);
1114
1115         priv = netdev_priv(ndev);
1116         priv->dev = dev;
1117         priv->netdev = ndev;
1118
1119         of_id = of_match_device(hix5hd2_of_match, dev);
1120         if (!of_id) {
1121                 ret = -EINVAL;
1122                 goto out_free_netdev;
1123         }
1124         priv->hw_cap = (unsigned long)of_id->data;
1125
1126         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1127         priv->base = devm_ioremap_resource(dev, res);
1128         if (IS_ERR(priv->base)) {
1129                 ret = PTR_ERR(priv->base);
1130                 goto out_free_netdev;
1131         }
1132
1133         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1134         priv->ctrl_base = devm_ioremap_resource(dev, res);
1135         if (IS_ERR(priv->ctrl_base)) {
1136                 ret = PTR_ERR(priv->ctrl_base);
1137                 goto out_free_netdev;
1138         }
1139
1140         priv->mac_core_clk = devm_clk_get(&pdev->dev, "mac_core");
1141         if (IS_ERR(priv->mac_core_clk)) {
1142                 netdev_err(ndev, "failed to get mac core clk\n");
1143                 ret = -ENODEV;
1144                 goto out_free_netdev;
1145         }
1146
1147         ret = clk_prepare_enable(priv->mac_core_clk);
1148         if (ret < 0) {
1149                 netdev_err(ndev, "failed to enable mac core clk %d\n", ret);
1150                 goto out_free_netdev;
1151         }
1152
1153         priv->mac_ifc_clk = devm_clk_get(&pdev->dev, "mac_ifc");
1154         if (IS_ERR(priv->mac_ifc_clk))
1155                 priv->mac_ifc_clk = NULL;
1156
1157         ret = clk_prepare_enable(priv->mac_ifc_clk);
1158         if (ret < 0) {
1159                 netdev_err(ndev, "failed to enable mac ifc clk %d\n", ret);
1160                 goto out_disable_mac_core_clk;
1161         }
1162
1163         priv->mac_core_rst = devm_reset_control_get(dev, "mac_core");
1164         if (IS_ERR(priv->mac_core_rst))
1165                 priv->mac_core_rst = NULL;
1166         hix5hd2_mac_core_reset(priv);
1167
1168         priv->mac_ifc_rst = devm_reset_control_get(dev, "mac_ifc");
1169         if (IS_ERR(priv->mac_ifc_rst))
1170                 priv->mac_ifc_rst = NULL;
1171
1172         priv->phy_rst = devm_reset_control_get(dev, "phy");
1173         if (IS_ERR(priv->phy_rst)) {
1174                 priv->phy_rst = NULL;
1175         } else {
1176                 ret = of_property_read_u32_array(node,
1177                                                  PHY_RESET_DELAYS_PROPERTY,
1178                                                  priv->phy_reset_delays,
1179                                                  DELAYS_NUM);
1180                 if (ret)
1181                         goto out_disable_clk;
1182                 hix5hd2_phy_reset(priv);
1183         }
1184
1185         bus = mdiobus_alloc();
1186         if (bus == NULL) {
1187                 ret = -ENOMEM;
1188                 goto out_disable_clk;
1189         }
1190
1191         bus->priv = priv;
1192         bus->name = "hix5hd2_mii_bus";
1193         bus->read = hix5hd2_mdio_read;
1194         bus->write = hix5hd2_mdio_write;
1195         bus->parent = &pdev->dev;
1196         snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
1197         priv->bus = bus;
1198
1199         ret = of_mdiobus_register(bus, node);
1200         if (ret)
1201                 goto err_free_mdio;
1202
1203         priv->phy_mode = of_get_phy_mode(node);
1204         if (priv->phy_mode < 0) {
1205                 netdev_err(ndev, "not find phy-mode\n");
1206                 ret = -EINVAL;
1207                 goto err_mdiobus;
1208         }
1209
1210         priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
1211         if (!priv->phy_node) {
1212                 netdev_err(ndev, "not find phy-handle\n");
1213                 ret = -EINVAL;
1214                 goto err_mdiobus;
1215         }
1216
1217         ndev->irq = platform_get_irq(pdev, 0);
1218         if (ndev->irq <= 0) {
1219                 netdev_err(ndev, "No irq resource\n");
1220                 ret = -EINVAL;
1221                 goto out_phy_node;
1222         }
1223
1224         ret = devm_request_irq(dev, ndev->irq, hix5hd2_interrupt,
1225                                0, pdev->name, ndev);
1226         if (ret) {
1227                 netdev_err(ndev, "devm_request_irq failed\n");
1228                 goto out_phy_node;
1229         }
1230
1231         mac_addr = of_get_mac_address(node);
1232         if (mac_addr)
1233                 ether_addr_copy(ndev->dev_addr, mac_addr);
1234         if (!is_valid_ether_addr(ndev->dev_addr)) {
1235                 eth_hw_addr_random(ndev);
1236                 netdev_warn(ndev, "using random MAC address %pM\n",
1237                             ndev->dev_addr);
1238         }
1239
1240         INIT_WORK(&priv->tx_timeout_task, hix5hd2_tx_timeout_task);
1241         ndev->watchdog_timeo = 6 * HZ;
1242         ndev->priv_flags |= IFF_UNICAST_FLT;
1243         ndev->netdev_ops = &hix5hd2_netdev_ops;
1244         ndev->ethtool_ops = &hix5hd2_ethtools_ops;
1245         SET_NETDEV_DEV(ndev, dev);
1246
1247         if (HAS_CAP_TSO(priv->hw_cap))
1248                 ndev->hw_features |= NETIF_F_SG;
1249
1250         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1251         ndev->vlan_features |= ndev->features;
1252
1253         ret = hix5hd2_init_hw_desc_queue(priv);
1254         if (ret)
1255                 goto out_phy_node;
1256
1257         netif_napi_add(ndev, &priv->napi, hix5hd2_poll, NAPI_POLL_WEIGHT);
1258
1259         if (HAS_CAP_TSO(priv->hw_cap)) {
1260                 ret = hix5hd2_init_sg_desc_queue(priv);
1261                 if (ret)
1262                         goto out_destroy_queue;
1263         }
1264
1265         ret = register_netdev(priv->netdev);
1266         if (ret) {
1267                 netdev_err(ndev, "register_netdev failed!");
1268                 goto out_destroy_queue;
1269         }
1270
1271         clk_disable_unprepare(priv->mac_ifc_clk);
1272         clk_disable_unprepare(priv->mac_core_clk);
1273
1274         return ret;
1275
1276 out_destroy_queue:
1277         if (HAS_CAP_TSO(priv->hw_cap))
1278                 hix5hd2_destroy_sg_desc_queue(priv);
1279         netif_napi_del(&priv->napi);
1280         hix5hd2_destroy_hw_desc_queue(priv);
1281 out_phy_node:
1282         of_node_put(priv->phy_node);
1283 err_mdiobus:
1284         mdiobus_unregister(bus);
1285 err_free_mdio:
1286         mdiobus_free(bus);
1287 out_disable_clk:
1288         clk_disable_unprepare(priv->mac_ifc_clk);
1289 out_disable_mac_core_clk:
1290         clk_disable_unprepare(priv->mac_core_clk);
1291 out_free_netdev:
1292         free_netdev(ndev);
1293
1294         return ret;
1295 }
1296
1297 static int hix5hd2_dev_remove(struct platform_device *pdev)
1298 {
1299         struct net_device *ndev = platform_get_drvdata(pdev);
1300         struct hix5hd2_priv *priv = netdev_priv(ndev);
1301
1302         netif_napi_del(&priv->napi);
1303         unregister_netdev(ndev);
1304         mdiobus_unregister(priv->bus);
1305         mdiobus_free(priv->bus);
1306
1307         if (HAS_CAP_TSO(priv->hw_cap))
1308                 hix5hd2_destroy_sg_desc_queue(priv);
1309         hix5hd2_destroy_hw_desc_queue(priv);
1310         of_node_put(priv->phy_node);
1311         cancel_work_sync(&priv->tx_timeout_task);
1312         free_netdev(ndev);
1313
1314         return 0;
1315 }
1316
1317 static const struct of_device_id hix5hd2_of_match[] = {
1318         { .compatible = "hisilicon,hisi-gmac-v1", .data = (void *)GEMAC_V1 },
1319         { .compatible = "hisilicon,hisi-gmac-v2", .data = (void *)GEMAC_V2 },
1320         { .compatible = "hisilicon,hix5hd2-gmac", .data = (void *)GEMAC_V1 },
1321         { .compatible = "hisilicon,hi3798cv200-gmac", .data = (void *)GEMAC_V2 },
1322         { .compatible = "hisilicon,hi3516a-gmac", .data = (void *)GEMAC_V2 },
1323         {},
1324 };
1325
1326 MODULE_DEVICE_TABLE(of, hix5hd2_of_match);
1327
1328 static struct platform_driver hix5hd2_dev_driver = {
1329         .driver = {
1330                 .name = "hisi-gmac",
1331                 .of_match_table = hix5hd2_of_match,
1332         },
1333         .probe = hix5hd2_dev_probe,
1334         .remove = hix5hd2_dev_remove,
1335 };
1336
1337 module_platform_driver(hix5hd2_dev_driver);
1338
1339 MODULE_DESCRIPTION("HISILICON Gigabit Ethernet MAC driver");
1340 MODULE_LICENSE("GPL v2");
1341 MODULE_ALIAS("platform:hisi-gmac");