1 /* drivers/net/ethernet/freescale/gianfar.c
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/delay.h>
74 #include <linux/netdevice.h>
75 #include <linux/etherdevice.h>
76 #include <linux/skbuff.h>
77 #include <linux/if_vlan.h>
78 #include <linux/spinlock.h>
80 #include <linux/of_address.h>
81 #include <linux/of_irq.h>
82 #include <linux/of_mdio.h>
83 #include <linux/of_platform.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
88 #include <linux/net_tstamp.h>
93 #include <asm/mpc85xx.h>
96 #include <linux/uaccess.h>
97 #include <linux/module.h>
98 #include <linux/dma-mapping.h>
99 #include <linux/crc32.h>
100 #include <linux/mii.h>
101 #include <linux/phy.h>
102 #include <linux/phy_fixed.h>
103 #include <linux/of.h>
104 #include <linux/of_net.h>
105 #include <linux/of_address.h>
106 #include <linux/of_irq.h>
110 #define TX_TIMEOUT (5*HZ)
112 const char gfar_driver_version[] = "2.0";
114 static int gfar_enet_open(struct net_device *dev);
115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
116 static void gfar_reset_task(struct work_struct *work);
117 static void gfar_timeout(struct net_device *dev);
118 static int gfar_close(struct net_device *dev);
119 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
121 static int gfar_set_mac_address(struct net_device *dev);
122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
123 static irqreturn_t gfar_error(int irq, void *dev_id);
124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
126 static void adjust_link(struct net_device *dev);
127 static noinline void gfar_update_link_state(struct gfar_private *priv);
128 static int init_phy(struct net_device *dev);
129 static int gfar_probe(struct platform_device *ofdev);
130 static int gfar_remove(struct platform_device *ofdev);
131 static void free_skb_resources(struct gfar_private *priv);
132 static void gfar_set_multi(struct net_device *dev);
133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
134 static void gfar_configure_serdes(struct net_device *dev);
135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
139 #ifdef CONFIG_NET_POLL_CONTROLLER
140 static void gfar_netpoll(struct net_device *dev);
142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
144 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb);
145 static void gfar_halt_nodisable(struct gfar_private *priv);
146 static void gfar_clear_exact_match(struct net_device *dev);
147 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
153 MODULE_LICENSE("GPL");
155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
160 bdp->bufPtr = cpu_to_be32(buf);
162 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
163 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
164 lstatus |= BD_LFLAG(RXBD_WRAP);
168 bdp->lstatus = cpu_to_be32(lstatus);
171 static void gfar_init_bds(struct net_device *ndev)
173 struct gfar_private *priv = netdev_priv(ndev);
174 struct gfar __iomem *regs = priv->gfargrp[0].regs;
175 struct gfar_priv_tx_q *tx_queue = NULL;
176 struct gfar_priv_rx_q *rx_queue = NULL;
181 for (i = 0; i < priv->num_tx_queues; i++) {
182 tx_queue = priv->tx_queue[i];
183 /* Initialize some variables in our dev structure */
184 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
185 tx_queue->dirty_tx = tx_queue->tx_bd_base;
186 tx_queue->cur_tx = tx_queue->tx_bd_base;
187 tx_queue->skb_curtx = 0;
188 tx_queue->skb_dirtytx = 0;
190 /* Initialize Transmit Descriptor Ring */
191 txbdp = tx_queue->tx_bd_base;
192 for (j = 0; j < tx_queue->tx_ring_size; j++) {
198 /* Set the last descriptor in the ring to indicate wrap */
200 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
204 rfbptr = ®s->rfbptr0;
205 for (i = 0; i < priv->num_rx_queues; i++) {
206 rx_queue = priv->rx_queue[i];
208 rx_queue->next_to_clean = 0;
209 rx_queue->next_to_use = 0;
210 rx_queue->next_to_alloc = 0;
212 /* make sure next_to_clean != next_to_use after this
213 * by leaving at least 1 unused descriptor
215 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
217 rx_queue->rfbptr = rfbptr;
222 static int gfar_alloc_skb_resources(struct net_device *ndev)
227 struct gfar_private *priv = netdev_priv(ndev);
228 struct device *dev = priv->dev;
229 struct gfar_priv_tx_q *tx_queue = NULL;
230 struct gfar_priv_rx_q *rx_queue = NULL;
232 priv->total_tx_ring_size = 0;
233 for (i = 0; i < priv->num_tx_queues; i++)
234 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
236 priv->total_rx_ring_size = 0;
237 for (i = 0; i < priv->num_rx_queues; i++)
238 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
240 /* Allocate memory for the buffer descriptors */
241 vaddr = dma_alloc_coherent(dev,
242 (priv->total_tx_ring_size *
243 sizeof(struct txbd8)) +
244 (priv->total_rx_ring_size *
245 sizeof(struct rxbd8)),
250 for (i = 0; i < priv->num_tx_queues; i++) {
251 tx_queue = priv->tx_queue[i];
252 tx_queue->tx_bd_base = vaddr;
253 tx_queue->tx_bd_dma_base = addr;
254 tx_queue->dev = ndev;
255 /* enet DMA only understands physical addresses */
256 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
257 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
260 /* Start the rx descriptor ring where the tx ring leaves off */
261 for (i = 0; i < priv->num_rx_queues; i++) {
262 rx_queue = priv->rx_queue[i];
263 rx_queue->rx_bd_base = vaddr;
264 rx_queue->rx_bd_dma_base = addr;
265 rx_queue->ndev = ndev;
267 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
268 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
271 /* Setup the skbuff rings */
272 for (i = 0; i < priv->num_tx_queues; i++) {
273 tx_queue = priv->tx_queue[i];
274 tx_queue->tx_skbuff =
275 kmalloc_array(tx_queue->tx_ring_size,
276 sizeof(*tx_queue->tx_skbuff),
278 if (!tx_queue->tx_skbuff)
281 for (j = 0; j < tx_queue->tx_ring_size; j++)
282 tx_queue->tx_skbuff[j] = NULL;
285 for (i = 0; i < priv->num_rx_queues; i++) {
286 rx_queue = priv->rx_queue[i];
287 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
288 sizeof(*rx_queue->rx_buff),
290 if (!rx_queue->rx_buff)
299 free_skb_resources(priv);
303 static void gfar_init_tx_rx_base(struct gfar_private *priv)
305 struct gfar __iomem *regs = priv->gfargrp[0].regs;
309 baddr = ®s->tbase0;
310 for (i = 0; i < priv->num_tx_queues; i++) {
311 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
315 baddr = ®s->rbase0;
316 for (i = 0; i < priv->num_rx_queues; i++) {
317 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
322 static void gfar_init_rqprm(struct gfar_private *priv)
324 struct gfar __iomem *regs = priv->gfargrp[0].regs;
328 baddr = ®s->rqprm0;
329 for (i = 0; i < priv->num_rx_queues; i++) {
330 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
331 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
336 static void gfar_rx_offload_en(struct gfar_private *priv)
338 /* set this when rx hw offload (TOE) functions are being used */
339 priv->uses_rxfcb = 0;
341 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
342 priv->uses_rxfcb = 1;
344 if (priv->hwts_rx_en || priv->rx_filer_enable)
345 priv->uses_rxfcb = 1;
348 static void gfar_mac_rx_config(struct gfar_private *priv)
350 struct gfar __iomem *regs = priv->gfargrp[0].regs;
353 if (priv->rx_filer_enable) {
354 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
355 /* Program the RIR0 reg with the required distribution */
356 if (priv->poll_mode == GFAR_SQ_POLLING)
357 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0);
358 else /* GFAR_MQ_POLLING */
359 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0);
362 /* Restore PROMISC mode */
363 if (priv->ndev->flags & IFF_PROMISC)
366 if (priv->ndev->features & NETIF_F_RXCSUM)
367 rctrl |= RCTRL_CHECKSUMMING;
369 if (priv->extended_hash)
370 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
373 rctrl &= ~RCTRL_PAL_MASK;
374 rctrl |= RCTRL_PADDING(priv->padding);
377 /* Enable HW time stamping if requested from user space */
378 if (priv->hwts_rx_en)
379 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
381 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
382 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
384 /* Clear the LFC bit */
385 gfar_write(®s->rctrl, rctrl);
386 /* Init flow control threshold values */
387 gfar_init_rqprm(priv);
388 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL);
391 /* Init rctrl based on our settings */
392 gfar_write(®s->rctrl, rctrl);
395 static void gfar_mac_tx_config(struct gfar_private *priv)
397 struct gfar __iomem *regs = priv->gfargrp[0].regs;
400 if (priv->ndev->features & NETIF_F_IP_CSUM)
401 tctrl |= TCTRL_INIT_CSUM;
403 if (priv->prio_sched_en)
404 tctrl |= TCTRL_TXSCHED_PRIO;
406 tctrl |= TCTRL_TXSCHED_WRRS;
407 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
408 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
411 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
412 tctrl |= TCTRL_VLINS;
414 gfar_write(®s->tctrl, tctrl);
417 static void gfar_configure_coalescing(struct gfar_private *priv,
418 unsigned long tx_mask, unsigned long rx_mask)
420 struct gfar __iomem *regs = priv->gfargrp[0].regs;
423 if (priv->mode == MQ_MG_MODE) {
426 baddr = ®s->txic0;
427 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
428 gfar_write(baddr + i, 0);
429 if (likely(priv->tx_queue[i]->txcoalescing))
430 gfar_write(baddr + i, priv->tx_queue[i]->txic);
433 baddr = ®s->rxic0;
434 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
435 gfar_write(baddr + i, 0);
436 if (likely(priv->rx_queue[i]->rxcoalescing))
437 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
440 /* Backward compatible case -- even if we enable
441 * multiple queues, there's only single reg to program
443 gfar_write(®s->txic, 0);
444 if (likely(priv->tx_queue[0]->txcoalescing))
445 gfar_write(®s->txic, priv->tx_queue[0]->txic);
447 gfar_write(®s->rxic, 0);
448 if (unlikely(priv->rx_queue[0]->rxcoalescing))
449 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
453 void gfar_configure_coalescing_all(struct gfar_private *priv)
455 gfar_configure_coalescing(priv, 0xFF, 0xFF);
458 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
460 struct gfar_private *priv = netdev_priv(dev);
461 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
462 unsigned long tx_packets = 0, tx_bytes = 0;
465 for (i = 0; i < priv->num_rx_queues; i++) {
466 rx_packets += priv->rx_queue[i]->stats.rx_packets;
467 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
468 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
471 dev->stats.rx_packets = rx_packets;
472 dev->stats.rx_bytes = rx_bytes;
473 dev->stats.rx_dropped = rx_dropped;
475 for (i = 0; i < priv->num_tx_queues; i++) {
476 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
477 tx_packets += priv->tx_queue[i]->stats.tx_packets;
480 dev->stats.tx_bytes = tx_bytes;
481 dev->stats.tx_packets = tx_packets;
486 static int gfar_set_mac_addr(struct net_device *dev, void *p)
488 eth_mac_addr(dev, p);
490 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
495 static const struct net_device_ops gfar_netdev_ops = {
496 .ndo_open = gfar_enet_open,
497 .ndo_start_xmit = gfar_start_xmit,
498 .ndo_stop = gfar_close,
499 .ndo_change_mtu = gfar_change_mtu,
500 .ndo_set_features = gfar_set_features,
501 .ndo_set_rx_mode = gfar_set_multi,
502 .ndo_tx_timeout = gfar_timeout,
503 .ndo_do_ioctl = gfar_ioctl,
504 .ndo_get_stats = gfar_get_stats,
505 .ndo_set_mac_address = gfar_set_mac_addr,
506 .ndo_validate_addr = eth_validate_addr,
507 #ifdef CONFIG_NET_POLL_CONTROLLER
508 .ndo_poll_controller = gfar_netpoll,
512 static void gfar_ints_disable(struct gfar_private *priv)
515 for (i = 0; i < priv->num_grps; i++) {
516 struct gfar __iomem *regs = priv->gfargrp[i].regs;
518 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
520 /* Initialize IMASK */
521 gfar_write(®s->imask, IMASK_INIT_CLEAR);
525 static void gfar_ints_enable(struct gfar_private *priv)
528 for (i = 0; i < priv->num_grps; i++) {
529 struct gfar __iomem *regs = priv->gfargrp[i].regs;
530 /* Unmask the interrupts we look for */
531 gfar_write(®s->imask, IMASK_DEFAULT);
535 static int gfar_alloc_tx_queues(struct gfar_private *priv)
539 for (i = 0; i < priv->num_tx_queues; i++) {
540 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
542 if (!priv->tx_queue[i])
545 priv->tx_queue[i]->tx_skbuff = NULL;
546 priv->tx_queue[i]->qindex = i;
547 priv->tx_queue[i]->dev = priv->ndev;
548 spin_lock_init(&(priv->tx_queue[i]->txlock));
553 static int gfar_alloc_rx_queues(struct gfar_private *priv)
557 for (i = 0; i < priv->num_rx_queues; i++) {
558 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
560 if (!priv->rx_queue[i])
563 priv->rx_queue[i]->qindex = i;
564 priv->rx_queue[i]->ndev = priv->ndev;
569 static void gfar_free_tx_queues(struct gfar_private *priv)
573 for (i = 0; i < priv->num_tx_queues; i++)
574 kfree(priv->tx_queue[i]);
577 static void gfar_free_rx_queues(struct gfar_private *priv)
581 for (i = 0; i < priv->num_rx_queues; i++)
582 kfree(priv->rx_queue[i]);
585 static void unmap_group_regs(struct gfar_private *priv)
589 for (i = 0; i < MAXGROUPS; i++)
590 if (priv->gfargrp[i].regs)
591 iounmap(priv->gfargrp[i].regs);
594 static void free_gfar_dev(struct gfar_private *priv)
598 for (i = 0; i < priv->num_grps; i++)
599 for (j = 0; j < GFAR_NUM_IRQS; j++) {
600 kfree(priv->gfargrp[i].irqinfo[j]);
601 priv->gfargrp[i].irqinfo[j] = NULL;
604 free_netdev(priv->ndev);
607 static void disable_napi(struct gfar_private *priv)
611 for (i = 0; i < priv->num_grps; i++) {
612 napi_disable(&priv->gfargrp[i].napi_rx);
613 napi_disable(&priv->gfargrp[i].napi_tx);
617 static void enable_napi(struct gfar_private *priv)
621 for (i = 0; i < priv->num_grps; i++) {
622 napi_enable(&priv->gfargrp[i].napi_rx);
623 napi_enable(&priv->gfargrp[i].napi_tx);
627 static int gfar_parse_group(struct device_node *np,
628 struct gfar_private *priv, const char *model)
630 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
633 for (i = 0; i < GFAR_NUM_IRQS; i++) {
634 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
636 if (!grp->irqinfo[i])
640 grp->regs = of_iomap(np, 0);
644 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
646 /* If we aren't the FEC we have multiple interrupts */
647 if (model && strcasecmp(model, "FEC")) {
648 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
649 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
650 if (!gfar_irq(grp, TX)->irq ||
651 !gfar_irq(grp, RX)->irq ||
652 !gfar_irq(grp, ER)->irq)
657 spin_lock_init(&grp->grplock);
658 if (priv->mode == MQ_MG_MODE) {
659 u32 rxq_mask, txq_mask;
662 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
663 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
665 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
667 grp->rx_bit_map = rxq_mask ?
668 rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
671 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
673 grp->tx_bit_map = txq_mask ?
674 txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
677 if (priv->poll_mode == GFAR_SQ_POLLING) {
678 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
679 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
680 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
683 grp->rx_bit_map = 0xFF;
684 grp->tx_bit_map = 0xFF;
687 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
688 * right to left, so we need to revert the 8 bits to get the q index
690 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
691 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
693 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
694 * also assign queues to groups
696 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
698 grp->rx_queue = priv->rx_queue[i];
699 grp->num_rx_queues++;
700 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
701 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
702 priv->rx_queue[i]->grp = grp;
705 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
707 grp->tx_queue = priv->tx_queue[i];
708 grp->num_tx_queues++;
709 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
710 priv->tqueue |= (TQUEUE_EN0 >> i);
711 priv->tx_queue[i]->grp = grp;
719 static int gfar_of_group_count(struct device_node *np)
721 struct device_node *child;
724 for_each_available_child_of_node(np, child)
725 if (!of_node_cmp(child->name, "queue-group"))
731 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
735 const void *mac_addr;
737 struct net_device *dev = NULL;
738 struct gfar_private *priv = NULL;
739 struct device_node *np = ofdev->dev.of_node;
740 struct device_node *child = NULL;
743 unsigned int num_tx_qs, num_rx_qs;
744 unsigned short mode, poll_mode;
749 if (of_device_is_compatible(np, "fsl,etsec2")) {
751 poll_mode = GFAR_SQ_POLLING;
754 poll_mode = GFAR_SQ_POLLING;
757 if (mode == SQ_SG_MODE) {
760 } else { /* MQ_MG_MODE */
761 /* get the actual number of supported groups */
762 unsigned int num_grps = gfar_of_group_count(np);
764 if (num_grps == 0 || num_grps > MAXGROUPS) {
765 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
767 pr_err("Cannot do alloc_etherdev, aborting\n");
771 if (poll_mode == GFAR_SQ_POLLING) {
772 num_tx_qs = num_grps; /* one txq per int group */
773 num_rx_qs = num_grps; /* one rxq per int group */
774 } else { /* GFAR_MQ_POLLING */
775 u32 tx_queues, rx_queues;
778 /* parse the num of HW tx and rx queues */
779 ret = of_property_read_u32(np, "fsl,num_tx_queues",
781 num_tx_qs = ret ? 1 : tx_queues;
783 ret = of_property_read_u32(np, "fsl,num_rx_queues",
785 num_rx_qs = ret ? 1 : rx_queues;
789 if (num_tx_qs > MAX_TX_QS) {
790 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
791 num_tx_qs, MAX_TX_QS);
792 pr_err("Cannot do alloc_etherdev, aborting\n");
796 if (num_rx_qs > MAX_RX_QS) {
797 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
798 num_rx_qs, MAX_RX_QS);
799 pr_err("Cannot do alloc_etherdev, aborting\n");
803 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
808 priv = netdev_priv(dev);
812 priv->poll_mode = poll_mode;
814 priv->num_tx_queues = num_tx_qs;
815 netif_set_real_num_rx_queues(dev, num_rx_qs);
816 priv->num_rx_queues = num_rx_qs;
818 err = gfar_alloc_tx_queues(priv);
820 goto tx_alloc_failed;
822 err = gfar_alloc_rx_queues(priv);
824 goto rx_alloc_failed;
826 err = of_property_read_string(np, "model", &model);
828 pr_err("Device model property missing, aborting\n");
829 goto rx_alloc_failed;
832 /* Init Rx queue filer rule set linked list */
833 INIT_LIST_HEAD(&priv->rx_list.list);
834 priv->rx_list.count = 0;
835 mutex_init(&priv->rx_queue_access);
837 for (i = 0; i < MAXGROUPS; i++)
838 priv->gfargrp[i].regs = NULL;
840 /* Parse and initialize group specific information */
841 if (priv->mode == MQ_MG_MODE) {
842 for_each_available_child_of_node(np, child) {
843 if (of_node_cmp(child->name, "queue-group"))
846 err = gfar_parse_group(child, priv, model);
850 } else { /* SQ_SG_MODE */
851 err = gfar_parse_group(np, priv, model);
856 if (of_property_read_bool(np, "bd-stash")) {
857 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
858 priv->bd_stash_en = 1;
861 err = of_property_read_u32(np, "rx-stash-len", &stash_len);
864 priv->rx_stash_size = stash_len;
866 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
869 priv->rx_stash_index = stash_idx;
871 if (stash_len || stash_idx)
872 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
874 mac_addr = of_get_mac_address(np);
877 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
879 if (model && !strcasecmp(model, "TSEC"))
880 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
881 FSL_GIANFAR_DEV_HAS_COALESCE |
882 FSL_GIANFAR_DEV_HAS_RMON |
883 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
885 if (model && !strcasecmp(model, "eTSEC"))
886 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
887 FSL_GIANFAR_DEV_HAS_COALESCE |
888 FSL_GIANFAR_DEV_HAS_RMON |
889 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
890 FSL_GIANFAR_DEV_HAS_CSUM |
891 FSL_GIANFAR_DEV_HAS_VLAN |
892 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
893 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
894 FSL_GIANFAR_DEV_HAS_TIMER |
895 FSL_GIANFAR_DEV_HAS_RX_FILER;
897 err = of_property_read_string(np, "phy-connection-type", &ctype);
899 /* We only care about rgmii-id. The rest are autodetected */
900 if (err == 0 && !strcmp(ctype, "rgmii-id"))
901 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
903 priv->interface = PHY_INTERFACE_MODE_MII;
905 if (of_find_property(np, "fsl,magic-packet", NULL))
906 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
908 if (of_get_property(np, "fsl,wake-on-filer", NULL))
909 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
911 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
913 /* In the case of a fixed PHY, the DT node associated
914 * to the PHY is the Ethernet MAC DT node.
916 if (!priv->phy_node && of_phy_is_fixed_link(np)) {
917 err = of_phy_register_fixed_link(np);
921 priv->phy_node = of_node_get(np);
924 /* Find the TBI PHY. If it's not there, we don't support SGMII */
925 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
930 unmap_group_regs(priv);
932 gfar_free_rx_queues(priv);
934 gfar_free_tx_queues(priv);
939 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
941 struct hwtstamp_config config;
942 struct gfar_private *priv = netdev_priv(netdev);
944 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
947 /* reserved for future extensions */
951 switch (config.tx_type) {
952 case HWTSTAMP_TX_OFF:
953 priv->hwts_tx_en = 0;
956 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
958 priv->hwts_tx_en = 1;
964 switch (config.rx_filter) {
965 case HWTSTAMP_FILTER_NONE:
966 if (priv->hwts_rx_en) {
967 priv->hwts_rx_en = 0;
972 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
974 if (!priv->hwts_rx_en) {
975 priv->hwts_rx_en = 1;
978 config.rx_filter = HWTSTAMP_FILTER_ALL;
982 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
986 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
988 struct hwtstamp_config config;
989 struct gfar_private *priv = netdev_priv(netdev);
992 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
993 config.rx_filter = (priv->hwts_rx_en ?
994 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
996 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1000 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1002 struct phy_device *phydev = dev->phydev;
1004 if (!netif_running(dev))
1007 if (cmd == SIOCSHWTSTAMP)
1008 return gfar_hwtstamp_set(dev, rq);
1009 if (cmd == SIOCGHWTSTAMP)
1010 return gfar_hwtstamp_get(dev, rq);
1015 return phy_mii_ioctl(phydev, rq, cmd);
1018 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1021 u32 rqfpr = FPR_FILER_MASK;
1025 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1026 priv->ftp_rqfpr[rqfar] = rqfpr;
1027 priv->ftp_rqfcr[rqfar] = rqfcr;
1028 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1031 rqfcr = RQFCR_CMP_NOMATCH;
1032 priv->ftp_rqfpr[rqfar] = rqfpr;
1033 priv->ftp_rqfcr[rqfar] = rqfcr;
1034 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1037 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1039 priv->ftp_rqfcr[rqfar] = rqfcr;
1040 priv->ftp_rqfpr[rqfar] = rqfpr;
1041 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1044 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1046 priv->ftp_rqfcr[rqfar] = rqfcr;
1047 priv->ftp_rqfpr[rqfar] = rqfpr;
1048 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1053 static void gfar_init_filer_table(struct gfar_private *priv)
1056 u32 rqfar = MAX_FILER_IDX;
1058 u32 rqfpr = FPR_FILER_MASK;
1061 rqfcr = RQFCR_CMP_MATCH;
1062 priv->ftp_rqfcr[rqfar] = rqfcr;
1063 priv->ftp_rqfpr[rqfar] = rqfpr;
1064 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1066 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1067 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1068 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1069 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1070 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1071 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1073 /* cur_filer_idx indicated the first non-masked rule */
1074 priv->cur_filer_idx = rqfar;
1076 /* Rest are masked rules */
1077 rqfcr = RQFCR_CMP_NOMATCH;
1078 for (i = 0; i < rqfar; i++) {
1079 priv->ftp_rqfcr[i] = rqfcr;
1080 priv->ftp_rqfpr[i] = rqfpr;
1081 gfar_write_filer(priv, i, rqfcr, rqfpr);
1086 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1088 unsigned int pvr = mfspr(SPRN_PVR);
1089 unsigned int svr = mfspr(SPRN_SVR);
1090 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1091 unsigned int rev = svr & 0xffff;
1093 /* MPC8313 Rev 2.0 and higher; All MPC837x */
1094 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1095 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1096 priv->errata |= GFAR_ERRATA_74;
1098 /* MPC8313 and MPC837x all rev */
1099 if ((pvr == 0x80850010 && mod == 0x80b0) ||
1100 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1101 priv->errata |= GFAR_ERRATA_76;
1103 /* MPC8313 Rev < 2.0 */
1104 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1105 priv->errata |= GFAR_ERRATA_12;
1108 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1110 unsigned int svr = mfspr(SPRN_SVR);
1112 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1113 priv->errata |= GFAR_ERRATA_12;
1114 /* P2020/P1010 Rev 1; MPC8548 Rev 2 */
1115 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1116 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) ||
1117 ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31)))
1118 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1122 static void gfar_detect_errata(struct gfar_private *priv)
1124 struct device *dev = &priv->ofdev->dev;
1126 /* no plans to fix */
1127 priv->errata |= GFAR_ERRATA_A002;
1130 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1131 __gfar_detect_errata_85xx(priv);
1132 else /* non-mpc85xx parts, i.e. e300 core based */
1133 __gfar_detect_errata_83xx(priv);
1137 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1141 void gfar_mac_reset(struct gfar_private *priv)
1143 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1146 /* Reset MAC layer */
1147 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
1149 /* We need to delay at least 3 TX clocks */
1152 /* the soft reset bit is not self-resetting, so we need to
1153 * clear it before resuming normal operation
1155 gfar_write(®s->maccfg1, 0);
1159 gfar_rx_offload_en(priv);
1161 /* Initialize the max receive frame/buffer lengths */
1162 gfar_write(®s->maxfrm, GFAR_JUMBO_FRAME_SIZE);
1163 gfar_write(®s->mrblr, GFAR_RXB_SIZE);
1165 /* Initialize the Minimum Frame Length Register */
1166 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
1168 /* Initialize MACCFG2. */
1169 tempval = MACCFG2_INIT_SETTINGS;
1171 /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
1172 * are marked as truncated. Avoid this by MACCFG2[Huge Frame]=1,
1173 * and by checking RxBD[LG] and discarding larger than MAXFRM.
1175 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1176 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1178 gfar_write(®s->maccfg2, tempval);
1180 /* Clear mac addr hash registers */
1181 gfar_write(®s->igaddr0, 0);
1182 gfar_write(®s->igaddr1, 0);
1183 gfar_write(®s->igaddr2, 0);
1184 gfar_write(®s->igaddr3, 0);
1185 gfar_write(®s->igaddr4, 0);
1186 gfar_write(®s->igaddr5, 0);
1187 gfar_write(®s->igaddr6, 0);
1188 gfar_write(®s->igaddr7, 0);
1190 gfar_write(®s->gaddr0, 0);
1191 gfar_write(®s->gaddr1, 0);
1192 gfar_write(®s->gaddr2, 0);
1193 gfar_write(®s->gaddr3, 0);
1194 gfar_write(®s->gaddr4, 0);
1195 gfar_write(®s->gaddr5, 0);
1196 gfar_write(®s->gaddr6, 0);
1197 gfar_write(®s->gaddr7, 0);
1199 if (priv->extended_hash)
1200 gfar_clear_exact_match(priv->ndev);
1202 gfar_mac_rx_config(priv);
1204 gfar_mac_tx_config(priv);
1206 gfar_set_mac_address(priv->ndev);
1208 gfar_set_multi(priv->ndev);
1210 /* clear ievent and imask before configuring coalescing */
1211 gfar_ints_disable(priv);
1213 /* Configure the coalescing support */
1214 gfar_configure_coalescing_all(priv);
1217 static void gfar_hw_init(struct gfar_private *priv)
1219 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1222 /* Stop the DMA engine now, in case it was running before
1223 * (The firmware could have used it, and left it running).
1227 gfar_mac_reset(priv);
1229 /* Zero out the rmon mib registers if it has them */
1230 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1231 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1233 /* Mask off the CAM interrupts */
1234 gfar_write(®s->rmon.cam1, 0xffffffff);
1235 gfar_write(®s->rmon.cam2, 0xffffffff);
1238 /* Initialize ECNTRL */
1239 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
1241 /* Set the extraction length and index */
1242 attrs = ATTRELI_EL(priv->rx_stash_size) |
1243 ATTRELI_EI(priv->rx_stash_index);
1245 gfar_write(®s->attreli, attrs);
1247 /* Start with defaults, and add stashing
1248 * depending on driver parameters
1250 attrs = ATTR_INIT_SETTINGS;
1252 if (priv->bd_stash_en)
1253 attrs |= ATTR_BDSTASH;
1255 if (priv->rx_stash_size != 0)
1256 attrs |= ATTR_BUFSTASH;
1258 gfar_write(®s->attr, attrs);
1261 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1262 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1263 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1265 /* Program the interrupt steering regs, only for MG devices */
1266 if (priv->num_grps > 1)
1267 gfar_write_isrg(priv);
1270 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1272 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1274 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1275 priv->extended_hash = 1;
1276 priv->hash_width = 9;
1278 priv->hash_regs[0] = ®s->igaddr0;
1279 priv->hash_regs[1] = ®s->igaddr1;
1280 priv->hash_regs[2] = ®s->igaddr2;
1281 priv->hash_regs[3] = ®s->igaddr3;
1282 priv->hash_regs[4] = ®s->igaddr4;
1283 priv->hash_regs[5] = ®s->igaddr5;
1284 priv->hash_regs[6] = ®s->igaddr6;
1285 priv->hash_regs[7] = ®s->igaddr7;
1286 priv->hash_regs[8] = ®s->gaddr0;
1287 priv->hash_regs[9] = ®s->gaddr1;
1288 priv->hash_regs[10] = ®s->gaddr2;
1289 priv->hash_regs[11] = ®s->gaddr3;
1290 priv->hash_regs[12] = ®s->gaddr4;
1291 priv->hash_regs[13] = ®s->gaddr5;
1292 priv->hash_regs[14] = ®s->gaddr6;
1293 priv->hash_regs[15] = ®s->gaddr7;
1296 priv->extended_hash = 0;
1297 priv->hash_width = 8;
1299 priv->hash_regs[0] = ®s->gaddr0;
1300 priv->hash_regs[1] = ®s->gaddr1;
1301 priv->hash_regs[2] = ®s->gaddr2;
1302 priv->hash_regs[3] = ®s->gaddr3;
1303 priv->hash_regs[4] = ®s->gaddr4;
1304 priv->hash_regs[5] = ®s->gaddr5;
1305 priv->hash_regs[6] = ®s->gaddr6;
1306 priv->hash_regs[7] = ®s->gaddr7;
1310 /* Set up the ethernet device structure, private data,
1311 * and anything else we need before we start
1313 static int gfar_probe(struct platform_device *ofdev)
1315 struct device_node *np = ofdev->dev.of_node;
1316 struct net_device *dev = NULL;
1317 struct gfar_private *priv = NULL;
1320 err = gfar_of_init(ofdev, &dev);
1325 priv = netdev_priv(dev);
1327 priv->ofdev = ofdev;
1328 priv->dev = &ofdev->dev;
1329 SET_NETDEV_DEV(dev, &ofdev->dev);
1331 INIT_WORK(&priv->reset_task, gfar_reset_task);
1333 platform_set_drvdata(ofdev, priv);
1335 gfar_detect_errata(priv);
1337 /* Set the dev->base_addr to the gfar reg region */
1338 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1340 /* Fill in the dev structure */
1341 dev->watchdog_timeo = TX_TIMEOUT;
1342 /* MTU range: 50 - 9586 */
1345 dev->max_mtu = GFAR_JUMBO_FRAME_SIZE - ETH_HLEN;
1346 dev->netdev_ops = &gfar_netdev_ops;
1347 dev->ethtool_ops = &gfar_ethtool_ops;
1349 /* Register for napi ...We are registering NAPI for each grp */
1350 for (i = 0; i < priv->num_grps; i++) {
1351 if (priv->poll_mode == GFAR_SQ_POLLING) {
1352 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1353 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1354 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1355 gfar_poll_tx_sq, 2);
1357 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1358 gfar_poll_rx, GFAR_DEV_WEIGHT);
1359 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1364 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1365 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1367 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1368 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1371 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1372 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1373 NETIF_F_HW_VLAN_CTAG_RX;
1374 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1377 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1379 gfar_init_addr_hash_table(priv);
1381 /* Insert receive time stamps into padding alignment bytes, and
1382 * plus 2 bytes padding to ensure the cpu alignment.
1384 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1385 priv->padding = 8 + DEFAULT_PADDING;
1387 if (dev->features & NETIF_F_IP_CSUM ||
1388 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1389 dev->needed_headroom = GMAC_FCB_LEN;
1391 /* Initializing some of the rx/tx queue level parameters */
1392 for (i = 0; i < priv->num_tx_queues; i++) {
1393 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1394 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1395 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1396 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1399 for (i = 0; i < priv->num_rx_queues; i++) {
1400 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1401 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1402 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1405 /* Always enable rx filer if available */
1406 priv->rx_filer_enable =
1407 (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
1408 /* Enable most messages by default */
1409 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1410 /* use pritority h/w tx queue scheduling for single queue devices */
1411 if (priv->num_tx_queues == 1)
1412 priv->prio_sched_en = 1;
1414 set_bit(GFAR_DOWN, &priv->state);
1418 /* Carrier starts down, phylib will bring it up */
1419 netif_carrier_off(dev);
1421 err = register_netdev(dev);
1424 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1428 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
1429 priv->wol_supported |= GFAR_WOL_MAGIC;
1431 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
1432 priv->rx_filer_enable)
1433 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
1435 device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
1437 /* fill out IRQ number and name fields */
1438 for (i = 0; i < priv->num_grps; i++) {
1439 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1440 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1441 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1442 dev->name, "_g", '0' + i, "_tx");
1443 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1444 dev->name, "_g", '0' + i, "_rx");
1445 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1446 dev->name, "_g", '0' + i, "_er");
1448 strcpy(gfar_irq(grp, TX)->name, dev->name);
1451 /* Initialize the filer table */
1452 gfar_init_filer_table(priv);
1454 /* Print out the device info */
1455 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1457 /* Even more device info helps when determining which kernel
1458 * provided which set of benchmarks.
1460 netdev_info(dev, "Running with NAPI enabled\n");
1461 for (i = 0; i < priv->num_rx_queues; i++)
1462 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1463 i, priv->rx_queue[i]->rx_ring_size);
1464 for (i = 0; i < priv->num_tx_queues; i++)
1465 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1466 i, priv->tx_queue[i]->tx_ring_size);
1471 if (of_phy_is_fixed_link(np))
1472 of_phy_deregister_fixed_link(np);
1473 unmap_group_regs(priv);
1474 gfar_free_rx_queues(priv);
1475 gfar_free_tx_queues(priv);
1476 of_node_put(priv->phy_node);
1477 of_node_put(priv->tbi_node);
1478 free_gfar_dev(priv);
1482 static int gfar_remove(struct platform_device *ofdev)
1484 struct gfar_private *priv = platform_get_drvdata(ofdev);
1485 struct device_node *np = ofdev->dev.of_node;
1487 of_node_put(priv->phy_node);
1488 of_node_put(priv->tbi_node);
1490 unregister_netdev(priv->ndev);
1492 if (of_phy_is_fixed_link(np))
1493 of_phy_deregister_fixed_link(np);
1495 unmap_group_regs(priv);
1496 gfar_free_rx_queues(priv);
1497 gfar_free_tx_queues(priv);
1498 free_gfar_dev(priv);
1505 static void __gfar_filer_disable(struct gfar_private *priv)
1507 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1510 temp = gfar_read(®s->rctrl);
1511 temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
1512 gfar_write(®s->rctrl, temp);
1515 static void __gfar_filer_enable(struct gfar_private *priv)
1517 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1520 temp = gfar_read(®s->rctrl);
1521 temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
1522 gfar_write(®s->rctrl, temp);
1525 /* Filer rules implementing wol capabilities */
1526 static void gfar_filer_config_wol(struct gfar_private *priv)
1531 __gfar_filer_disable(priv);
1533 /* clear the filer table, reject any packet by default */
1534 rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
1535 for (i = 0; i <= MAX_FILER_IDX; i++)
1536 gfar_write_filer(priv, i, rqfcr, 0);
1539 if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
1540 /* unicast packet, accept it */
1541 struct net_device *ndev = priv->ndev;
1542 /* get the default rx queue index */
1543 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
1544 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
1545 (ndev->dev_addr[1] << 8) |
1548 rqfcr = (qindex << 10) | RQFCR_AND |
1549 RQFCR_CMP_EXACT | RQFCR_PID_DAH;
1551 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1553 dest_mac_addr = (ndev->dev_addr[3] << 16) |
1554 (ndev->dev_addr[4] << 8) |
1556 rqfcr = (qindex << 10) | RQFCR_GPI |
1557 RQFCR_CMP_EXACT | RQFCR_PID_DAL;
1558 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1561 __gfar_filer_enable(priv);
1564 static void gfar_filer_restore_table(struct gfar_private *priv)
1569 __gfar_filer_disable(priv);
1571 for (i = 0; i <= MAX_FILER_IDX; i++) {
1572 rqfcr = priv->ftp_rqfcr[i];
1573 rqfpr = priv->ftp_rqfpr[i];
1574 gfar_write_filer(priv, i, rqfcr, rqfpr);
1577 __gfar_filer_enable(priv);
1580 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
1581 static void gfar_start_wol_filer(struct gfar_private *priv)
1583 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1587 /* Enable Rx hw queues */
1588 gfar_write(®s->rqueue, priv->rqueue);
1590 /* Initialize DMACTRL to have WWR and WOP */
1591 tempval = gfar_read(®s->dmactrl);
1592 tempval |= DMACTRL_INIT_SETTINGS;
1593 gfar_write(®s->dmactrl, tempval);
1595 /* Make sure we aren't stopped */
1596 tempval = gfar_read(®s->dmactrl);
1597 tempval &= ~DMACTRL_GRS;
1598 gfar_write(®s->dmactrl, tempval);
1600 for (i = 0; i < priv->num_grps; i++) {
1601 regs = priv->gfargrp[i].regs;
1602 /* Clear RHLT, so that the DMA starts polling now */
1603 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1604 /* enable the Filer General Purpose Interrupt */
1605 gfar_write(®s->imask, IMASK_FGPI);
1609 tempval = gfar_read(®s->maccfg1);
1610 tempval |= MACCFG1_RX_EN;
1611 gfar_write(®s->maccfg1, tempval);
1614 static int gfar_suspend(struct device *dev)
1616 struct gfar_private *priv = dev_get_drvdata(dev);
1617 struct net_device *ndev = priv->ndev;
1618 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1620 u16 wol = priv->wol_opts;
1622 if (!netif_running(ndev))
1626 netif_tx_lock(ndev);
1627 netif_device_detach(ndev);
1628 netif_tx_unlock(ndev);
1632 if (wol & GFAR_WOL_MAGIC) {
1633 /* Enable interrupt on Magic Packet */
1634 gfar_write(®s->imask, IMASK_MAG);
1636 /* Enable Magic Packet mode */
1637 tempval = gfar_read(®s->maccfg2);
1638 tempval |= MACCFG2_MPEN;
1639 gfar_write(®s->maccfg2, tempval);
1641 /* re-enable the Rx block */
1642 tempval = gfar_read(®s->maccfg1);
1643 tempval |= MACCFG1_RX_EN;
1644 gfar_write(®s->maccfg1, tempval);
1646 } else if (wol & GFAR_WOL_FILER_UCAST) {
1647 gfar_filer_config_wol(priv);
1648 gfar_start_wol_filer(priv);
1651 phy_stop(ndev->phydev);
1657 static int gfar_resume(struct device *dev)
1659 struct gfar_private *priv = dev_get_drvdata(dev);
1660 struct net_device *ndev = priv->ndev;
1661 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1663 u16 wol = priv->wol_opts;
1665 if (!netif_running(ndev))
1668 if (wol & GFAR_WOL_MAGIC) {
1669 /* Disable Magic Packet mode */
1670 tempval = gfar_read(®s->maccfg2);
1671 tempval &= ~MACCFG2_MPEN;
1672 gfar_write(®s->maccfg2, tempval);
1674 } else if (wol & GFAR_WOL_FILER_UCAST) {
1675 /* need to stop rx only, tx is already down */
1677 gfar_filer_restore_table(priv);
1680 phy_start(ndev->phydev);
1685 netif_device_attach(ndev);
1691 static int gfar_restore(struct device *dev)
1693 struct gfar_private *priv = dev_get_drvdata(dev);
1694 struct net_device *ndev = priv->ndev;
1696 if (!netif_running(ndev)) {
1697 netif_device_attach(ndev);
1702 gfar_init_bds(ndev);
1704 gfar_mac_reset(priv);
1706 gfar_init_tx_rx_base(priv);
1712 priv->oldduplex = -1;
1715 phy_start(ndev->phydev);
1717 netif_device_attach(ndev);
1723 static const struct dev_pm_ops gfar_pm_ops = {
1724 .suspend = gfar_suspend,
1725 .resume = gfar_resume,
1726 .freeze = gfar_suspend,
1727 .thaw = gfar_resume,
1728 .restore = gfar_restore,
1731 #define GFAR_PM_OPS (&gfar_pm_ops)
1735 #define GFAR_PM_OPS NULL
1739 /* Reads the controller's registers to determine what interface
1740 * connects it to the PHY.
1742 static phy_interface_t gfar_get_interface(struct net_device *dev)
1744 struct gfar_private *priv = netdev_priv(dev);
1745 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1748 ecntrl = gfar_read(®s->ecntrl);
1750 if (ecntrl & ECNTRL_SGMII_MODE)
1751 return PHY_INTERFACE_MODE_SGMII;
1753 if (ecntrl & ECNTRL_TBI_MODE) {
1754 if (ecntrl & ECNTRL_REDUCED_MODE)
1755 return PHY_INTERFACE_MODE_RTBI;
1757 return PHY_INTERFACE_MODE_TBI;
1760 if (ecntrl & ECNTRL_REDUCED_MODE) {
1761 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1762 return PHY_INTERFACE_MODE_RMII;
1765 phy_interface_t interface = priv->interface;
1767 /* This isn't autodetected right now, so it must
1768 * be set by the device tree or platform code.
1770 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1771 return PHY_INTERFACE_MODE_RGMII_ID;
1773 return PHY_INTERFACE_MODE_RGMII;
1777 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1778 return PHY_INTERFACE_MODE_GMII;
1780 return PHY_INTERFACE_MODE_MII;
1784 /* Initializes driver's PHY state, and attaches to the PHY.
1785 * Returns 0 on success.
1787 static int init_phy(struct net_device *dev)
1789 struct gfar_private *priv = netdev_priv(dev);
1790 uint gigabit_support =
1791 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1792 GFAR_SUPPORTED_GBIT : 0;
1793 phy_interface_t interface;
1794 struct phy_device *phydev;
1795 struct ethtool_eee edata;
1799 priv->oldduplex = -1;
1801 interface = gfar_get_interface(dev);
1803 phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1806 dev_err(&dev->dev, "could not attach to PHY\n");
1810 if (interface == PHY_INTERFACE_MODE_SGMII)
1811 gfar_configure_serdes(dev);
1813 /* Remove any features not supported by the controller */
1814 phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1815 phydev->advertising = phydev->supported;
1817 /* Add support for flow control, but don't advertise it by default */
1818 phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1820 /* disable EEE autoneg, EEE not supported by eTSEC */
1821 memset(&edata, 0, sizeof(struct ethtool_eee));
1822 phy_ethtool_set_eee(phydev, &edata);
1827 /* Initialize TBI PHY interface for communicating with the
1828 * SERDES lynx PHY on the chip. We communicate with this PHY
1829 * through the MDIO bus on each controller, treating it as a
1830 * "normal" PHY at the address found in the TBIPA register. We assume
1831 * that the TBIPA register is valid. Either the MDIO bus code will set
1832 * it to a value that doesn't conflict with other PHYs on the bus, or the
1833 * value doesn't matter, as there are no other PHYs on the bus.
1835 static void gfar_configure_serdes(struct net_device *dev)
1837 struct gfar_private *priv = netdev_priv(dev);
1838 struct phy_device *tbiphy;
1840 if (!priv->tbi_node) {
1841 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1842 "device tree specify a tbi-handle\n");
1846 tbiphy = of_phy_find_device(priv->tbi_node);
1848 dev_err(&dev->dev, "error: Could not get TBI device\n");
1852 /* If the link is already up, we must already be ok, and don't need to
1853 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1854 * everything for us? Resetting it takes the link down and requires
1855 * several seconds for it to come back.
1857 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1858 put_device(&tbiphy->mdio.dev);
1862 /* Single clk mode, mii mode off(for serdes communication) */
1863 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1865 phy_write(tbiphy, MII_ADVERTISE,
1866 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1867 ADVERTISE_1000XPSE_ASYM);
1869 phy_write(tbiphy, MII_BMCR,
1870 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1873 put_device(&tbiphy->mdio.dev);
1876 static int __gfar_is_rx_idle(struct gfar_private *priv)
1880 /* Normaly TSEC should not hang on GRS commands, so we should
1881 * actually wait for IEVENT_GRSC flag.
1883 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1886 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1887 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1888 * and the Rx can be safely reset.
1890 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1892 if ((res & 0xffff) == (res >> 16))
1898 /* Halt the receive and transmit queues */
1899 static void gfar_halt_nodisable(struct gfar_private *priv)
1901 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1903 unsigned int timeout;
1906 gfar_ints_disable(priv);
1908 if (gfar_is_dma_stopped(priv))
1911 /* Stop the DMA, and wait for it to stop */
1912 tempval = gfar_read(®s->dmactrl);
1913 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1914 gfar_write(®s->dmactrl, tempval);
1918 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1924 stopped = gfar_is_dma_stopped(priv);
1926 if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1927 !__gfar_is_rx_idle(priv))
1931 /* Halt the receive and transmit queues */
1932 void gfar_halt(struct gfar_private *priv)
1934 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1937 /* Dissable the Rx/Tx hw queues */
1938 gfar_write(®s->rqueue, 0);
1939 gfar_write(®s->tqueue, 0);
1943 gfar_halt_nodisable(priv);
1945 /* Disable Rx/Tx DMA */
1946 tempval = gfar_read(®s->maccfg1);
1947 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1948 gfar_write(®s->maccfg1, tempval);
1951 void stop_gfar(struct net_device *dev)
1953 struct gfar_private *priv = netdev_priv(dev);
1955 netif_tx_stop_all_queues(dev);
1957 smp_mb__before_atomic();
1958 set_bit(GFAR_DOWN, &priv->state);
1959 smp_mb__after_atomic();
1963 /* disable ints and gracefully shut down Rx/Tx DMA */
1966 phy_stop(dev->phydev);
1968 free_skb_resources(priv);
1971 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1973 struct txbd8 *txbdp;
1974 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1977 txbdp = tx_queue->tx_bd_base;
1979 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1980 if (!tx_queue->tx_skbuff[i])
1983 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1984 be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1986 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1989 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1990 be16_to_cpu(txbdp->length),
1994 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1995 tx_queue->tx_skbuff[i] = NULL;
1997 kfree(tx_queue->tx_skbuff);
1998 tx_queue->tx_skbuff = NULL;
2001 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
2005 struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
2008 dev_kfree_skb(rx_queue->skb);
2010 for (i = 0; i < rx_queue->rx_ring_size; i++) {
2011 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
2020 dma_unmap_page(rx_queue->dev, rxb->dma,
2021 PAGE_SIZE, DMA_FROM_DEVICE);
2022 __free_page(rxb->page);
2027 kfree(rx_queue->rx_buff);
2028 rx_queue->rx_buff = NULL;
2031 /* If there are any tx skbs or rx skbs still around, free them.
2032 * Then free tx_skbuff and rx_skbuff
2034 static void free_skb_resources(struct gfar_private *priv)
2036 struct gfar_priv_tx_q *tx_queue = NULL;
2037 struct gfar_priv_rx_q *rx_queue = NULL;
2040 /* Go through all the buffer descriptors and free their data buffers */
2041 for (i = 0; i < priv->num_tx_queues; i++) {
2042 struct netdev_queue *txq;
2044 tx_queue = priv->tx_queue[i];
2045 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
2046 if (tx_queue->tx_skbuff)
2047 free_skb_tx_queue(tx_queue);
2048 netdev_tx_reset_queue(txq);
2051 for (i = 0; i < priv->num_rx_queues; i++) {
2052 rx_queue = priv->rx_queue[i];
2053 if (rx_queue->rx_buff)
2054 free_skb_rx_queue(rx_queue);
2057 dma_free_coherent(priv->dev,
2058 sizeof(struct txbd8) * priv->total_tx_ring_size +
2059 sizeof(struct rxbd8) * priv->total_rx_ring_size,
2060 priv->tx_queue[0]->tx_bd_base,
2061 priv->tx_queue[0]->tx_bd_dma_base);
2064 void gfar_start(struct gfar_private *priv)
2066 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2070 /* Enable Rx/Tx hw queues */
2071 gfar_write(®s->rqueue, priv->rqueue);
2072 gfar_write(®s->tqueue, priv->tqueue);
2074 /* Initialize DMACTRL to have WWR and WOP */
2075 tempval = gfar_read(®s->dmactrl);
2076 tempval |= DMACTRL_INIT_SETTINGS;
2077 gfar_write(®s->dmactrl, tempval);
2079 /* Make sure we aren't stopped */
2080 tempval = gfar_read(®s->dmactrl);
2081 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
2082 gfar_write(®s->dmactrl, tempval);
2084 for (i = 0; i < priv->num_grps; i++) {
2085 regs = priv->gfargrp[i].regs;
2086 /* Clear THLT/RHLT, so that the DMA starts polling now */
2087 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
2088 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
2091 /* Enable Rx/Tx DMA */
2092 tempval = gfar_read(®s->maccfg1);
2093 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2094 gfar_write(®s->maccfg1, tempval);
2096 gfar_ints_enable(priv);
2098 netif_trans_update(priv->ndev); /* prevent tx timeout */
2101 static void free_grp_irqs(struct gfar_priv_grp *grp)
2103 free_irq(gfar_irq(grp, TX)->irq, grp);
2104 free_irq(gfar_irq(grp, RX)->irq, grp);
2105 free_irq(gfar_irq(grp, ER)->irq, grp);
2108 static int register_grp_irqs(struct gfar_priv_grp *grp)
2110 struct gfar_private *priv = grp->priv;
2111 struct net_device *dev = priv->ndev;
2114 /* If the device has multiple interrupts, register for
2115 * them. Otherwise, only register for the one
2117 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2118 /* Install our interrupt handlers for Error,
2119 * Transmit, and Receive
2121 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2122 gfar_irq(grp, ER)->name, grp);
2124 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2125 gfar_irq(grp, ER)->irq);
2129 enable_irq_wake(gfar_irq(grp, ER)->irq);
2131 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2132 gfar_irq(grp, TX)->name, grp);
2134 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2135 gfar_irq(grp, TX)->irq);
2138 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2139 gfar_irq(grp, RX)->name, grp);
2141 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2142 gfar_irq(grp, RX)->irq);
2145 enable_irq_wake(gfar_irq(grp, RX)->irq);
2148 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2149 gfar_irq(grp, TX)->name, grp);
2151 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2152 gfar_irq(grp, TX)->irq);
2155 enable_irq_wake(gfar_irq(grp, TX)->irq);
2161 free_irq(gfar_irq(grp, TX)->irq, grp);
2163 free_irq(gfar_irq(grp, ER)->irq, grp);
2169 static void gfar_free_irq(struct gfar_private *priv)
2174 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2175 for (i = 0; i < priv->num_grps; i++)
2176 free_grp_irqs(&priv->gfargrp[i]);
2178 for (i = 0; i < priv->num_grps; i++)
2179 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2184 static int gfar_request_irq(struct gfar_private *priv)
2188 for (i = 0; i < priv->num_grps; i++) {
2189 err = register_grp_irqs(&priv->gfargrp[i]);
2191 for (j = 0; j < i; j++)
2192 free_grp_irqs(&priv->gfargrp[j]);
2200 /* Bring the controller up and running */
2201 int startup_gfar(struct net_device *ndev)
2203 struct gfar_private *priv = netdev_priv(ndev);
2206 gfar_mac_reset(priv);
2208 err = gfar_alloc_skb_resources(ndev);
2212 gfar_init_tx_rx_base(priv);
2214 smp_mb__before_atomic();
2215 clear_bit(GFAR_DOWN, &priv->state);
2216 smp_mb__after_atomic();
2218 /* Start Rx/Tx DMA and enable the interrupts */
2221 /* force link state update after mac reset */
2224 priv->oldduplex = -1;
2226 phy_start(ndev->phydev);
2230 netif_tx_wake_all_queues(ndev);
2235 /* Called when something needs to use the ethernet device
2236 * Returns 0 for success.
2238 static int gfar_enet_open(struct net_device *dev)
2240 struct gfar_private *priv = netdev_priv(dev);
2243 err = init_phy(dev);
2247 err = gfar_request_irq(priv);
2251 err = startup_gfar(dev);
2258 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2260 struct txfcb *fcb = skb_push(skb, GMAC_FCB_LEN);
2262 memset(fcb, 0, GMAC_FCB_LEN);
2267 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2270 /* If we're here, it's a IP packet with a TCP or UDP
2271 * payload. We set it to checksum, using a pseudo-header
2274 u8 flags = TXFCB_DEFAULT;
2276 /* Tell the controller what the protocol is
2277 * And provide the already calculated phcs
2279 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2281 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2283 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2285 /* l3os is the distance between the start of the
2286 * frame (skb->data) and the start of the IP hdr.
2287 * l4os is the distance between the start of the
2288 * l3 hdr and the l4 hdr
2290 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2291 fcb->l4os = skb_network_header_len(skb);
2296 static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2298 fcb->flags |= TXFCB_VLN;
2299 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2302 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2303 struct txbd8 *base, int ring_size)
2305 struct txbd8 *new_bd = bdp + stride;
2307 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2310 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2313 return skip_txbd(bdp, 1, base, ring_size);
2316 /* eTSEC12: csum generation not supported for some fcb offsets */
2317 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2318 unsigned long fcb_addr)
2320 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2321 (fcb_addr % 0x20) > 0x18);
2324 /* eTSEC76: csum generation for frames larger than 2500 may
2325 * cause excess delays before start of transmission
2327 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2330 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2334 /* This is called by the kernel when a frame is ready for transmission.
2335 * It is pointed to by the dev->hard_start_xmit function pointer
2337 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2339 struct gfar_private *priv = netdev_priv(dev);
2340 struct gfar_priv_tx_q *tx_queue = NULL;
2341 struct netdev_queue *txq;
2342 struct gfar __iomem *regs = NULL;
2343 struct txfcb *fcb = NULL;
2344 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2348 int do_tstamp, do_csum, do_vlan;
2350 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2352 rq = skb->queue_mapping;
2353 tx_queue = priv->tx_queue[rq];
2354 txq = netdev_get_tx_queue(dev, rq);
2355 base = tx_queue->tx_bd_base;
2356 regs = tx_queue->grp->regs;
2358 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2359 do_vlan = skb_vlan_tag_present(skb);
2360 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2363 if (do_csum || do_vlan)
2364 fcb_len = GMAC_FCB_LEN;
2366 /* check if time stamp should be generated */
2367 if (unlikely(do_tstamp))
2368 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2370 /* make space for additional header when fcb is needed */
2371 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2372 struct sk_buff *skb_new;
2374 skb_new = skb_realloc_headroom(skb, fcb_len);
2376 dev->stats.tx_errors++;
2377 dev_kfree_skb_any(skb);
2378 return NETDEV_TX_OK;
2382 skb_set_owner_w(skb_new, skb->sk);
2383 dev_consume_skb_any(skb);
2387 /* total number of fragments in the SKB */
2388 nr_frags = skb_shinfo(skb)->nr_frags;
2390 /* calculate the required number of TxBDs for this skb */
2391 if (unlikely(do_tstamp))
2392 nr_txbds = nr_frags + 2;
2394 nr_txbds = nr_frags + 1;
2396 /* check if there is space to queue this packet */
2397 if (nr_txbds > tx_queue->num_txbdfree) {
2398 /* no space, stop the queue */
2399 netif_tx_stop_queue(txq);
2400 dev->stats.tx_fifo_errors++;
2401 return NETDEV_TX_BUSY;
2404 /* Update transmit stats */
2405 bytes_sent = skb->len;
2406 tx_queue->stats.tx_bytes += bytes_sent;
2407 /* keep Tx bytes on wire for BQL accounting */
2408 GFAR_CB(skb)->bytes_sent = bytes_sent;
2409 tx_queue->stats.tx_packets++;
2411 txbdp = txbdp_start = tx_queue->cur_tx;
2412 lstatus = be32_to_cpu(txbdp->lstatus);
2414 /* Add TxPAL between FCB and frame if required */
2415 if (unlikely(do_tstamp)) {
2416 skb_push(skb, GMAC_TXPAL_LEN);
2417 memset(skb->data, 0, GMAC_TXPAL_LEN);
2420 /* Add TxFCB if required */
2422 fcb = gfar_add_fcb(skb);
2423 lstatus |= BD_LFLAG(TXBD_TOE);
2426 /* Set up checksumming */
2428 gfar_tx_checksum(skb, fcb, fcb_len);
2430 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2431 unlikely(gfar_csum_errata_76(priv, skb->len))) {
2432 __skb_pull(skb, GMAC_FCB_LEN);
2433 skb_checksum_help(skb);
2434 if (do_vlan || do_tstamp) {
2435 /* put back a new fcb for vlan/tstamp TOE */
2436 fcb = gfar_add_fcb(skb);
2438 /* Tx TOE not used */
2439 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2446 gfar_tx_vlan(skb, fcb);
2448 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2450 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2453 txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2455 /* Time stamp insertion requires one additional TxBD */
2456 if (unlikely(do_tstamp))
2457 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2458 tx_queue->tx_ring_size);
2460 if (likely(!nr_frags)) {
2461 if (likely(!do_tstamp))
2462 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2464 u32 lstatus_start = lstatus;
2466 /* Place the fragment addresses and lengths into the TxBDs */
2467 frag = &skb_shinfo(skb)->frags[0];
2468 for (i = 0; i < nr_frags; i++, frag++) {
2471 /* Point at the next BD, wrapping as needed */
2472 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2474 size = skb_frag_size(frag);
2476 lstatus = be32_to_cpu(txbdp->lstatus) | size |
2477 BD_LFLAG(TXBD_READY);
2479 /* Handle the last BD specially */
2480 if (i == nr_frags - 1)
2481 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2483 bufaddr = skb_frag_dma_map(priv->dev, frag, 0,
2484 size, DMA_TO_DEVICE);
2485 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2488 /* set the TxBD length and buffer pointer */
2489 txbdp->bufPtr = cpu_to_be32(bufaddr);
2490 txbdp->lstatus = cpu_to_be32(lstatus);
2493 lstatus = lstatus_start;
2496 /* If time stamping is requested one additional TxBD must be set up. The
2497 * first TxBD points to the FCB and must have a data length of
2498 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2499 * the full frame length.
2501 if (unlikely(do_tstamp)) {
2502 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2504 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2507 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2508 (skb_headlen(skb) - fcb_len);
2510 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2512 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2513 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2514 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2516 /* Setup tx hardware time stamping */
2517 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2520 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2523 netdev_tx_sent_queue(txq, bytes_sent);
2527 txbdp_start->lstatus = cpu_to_be32(lstatus);
2529 gfar_wmb(); /* force lstatus write before tx_skbuff */
2531 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2533 /* Update the current skb pointer to the next entry we will use
2534 * (wrapping if necessary)
2536 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2537 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2539 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2541 /* We can work in parallel with gfar_clean_tx_ring(), except
2542 * when modifying num_txbdfree. Note that we didn't grab the lock
2543 * when we were reading the num_txbdfree and checking for available
2544 * space, that's because outside of this function it can only grow.
2546 spin_lock_bh(&tx_queue->txlock);
2547 /* reduce TxBD free count */
2548 tx_queue->num_txbdfree -= (nr_txbds);
2549 spin_unlock_bh(&tx_queue->txlock);
2551 /* If the next BD still needs to be cleaned up, then the bds
2552 * are full. We need to tell the kernel to stop sending us stuff.
2554 if (!tx_queue->num_txbdfree) {
2555 netif_tx_stop_queue(txq);
2557 dev->stats.tx_fifo_errors++;
2560 /* Tell the DMA to go go go */
2561 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2563 return NETDEV_TX_OK;
2566 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2568 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2569 for (i = 0; i < nr_frags; i++) {
2570 lstatus = be32_to_cpu(txbdp->lstatus);
2571 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2574 lstatus &= ~BD_LFLAG(TXBD_READY);
2575 txbdp->lstatus = cpu_to_be32(lstatus);
2576 bufaddr = be32_to_cpu(txbdp->bufPtr);
2577 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2579 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2582 dev_kfree_skb_any(skb);
2583 return NETDEV_TX_OK;
2586 /* Stops the kernel queue, and halts the controller */
2587 static int gfar_close(struct net_device *dev)
2589 struct gfar_private *priv = netdev_priv(dev);
2591 cancel_work_sync(&priv->reset_task);
2594 /* Disconnect from the PHY */
2595 phy_disconnect(dev->phydev);
2597 gfar_free_irq(priv);
2602 /* Changes the mac address if the controller is not running. */
2603 static int gfar_set_mac_address(struct net_device *dev)
2605 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2610 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2612 struct gfar_private *priv = netdev_priv(dev);
2614 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2617 if (dev->flags & IFF_UP)
2622 if (dev->flags & IFF_UP)
2625 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2630 void reset_gfar(struct net_device *ndev)
2632 struct gfar_private *priv = netdev_priv(ndev);
2634 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2640 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2643 /* gfar_reset_task gets scheduled when a packet has not been
2644 * transmitted after a set amount of time.
2645 * For now, assume that clearing out all the structures, and
2646 * starting over will fix the problem.
2648 static void gfar_reset_task(struct work_struct *work)
2650 struct gfar_private *priv = container_of(work, struct gfar_private,
2652 reset_gfar(priv->ndev);
2655 static void gfar_timeout(struct net_device *dev)
2657 struct gfar_private *priv = netdev_priv(dev);
2659 dev->stats.tx_errors++;
2660 schedule_work(&priv->reset_task);
2663 /* Interrupt Handler for Transmit complete */
2664 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2666 struct net_device *dev = tx_queue->dev;
2667 struct netdev_queue *txq;
2668 struct gfar_private *priv = netdev_priv(dev);
2669 struct txbd8 *bdp, *next = NULL;
2670 struct txbd8 *lbdp = NULL;
2671 struct txbd8 *base = tx_queue->tx_bd_base;
2672 struct sk_buff *skb;
2674 int tx_ring_size = tx_queue->tx_ring_size;
2675 int frags = 0, nr_txbds = 0;
2678 int tqi = tx_queue->qindex;
2679 unsigned int bytes_sent = 0;
2683 txq = netdev_get_tx_queue(dev, tqi);
2684 bdp = tx_queue->dirty_tx;
2685 skb_dirtytx = tx_queue->skb_dirtytx;
2687 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2689 frags = skb_shinfo(skb)->nr_frags;
2691 /* When time stamping, one additional TxBD must be freed.
2692 * Also, we need to dma_unmap_single() the TxPAL.
2694 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2695 nr_txbds = frags + 2;
2697 nr_txbds = frags + 1;
2699 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2701 lstatus = be32_to_cpu(lbdp->lstatus);
2703 /* Only clean completed frames */
2704 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2705 (lstatus & BD_LENGTH_MASK))
2708 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2709 next = next_txbd(bdp, base, tx_ring_size);
2710 buflen = be16_to_cpu(next->length) +
2711 GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2713 buflen = be16_to_cpu(bdp->length);
2715 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2716 buflen, DMA_TO_DEVICE);
2718 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2719 struct skb_shared_hwtstamps shhwtstamps;
2720 u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2723 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2724 shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2725 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2726 skb_tstamp_tx(skb, &shhwtstamps);
2727 gfar_clear_txbd_status(bdp);
2731 gfar_clear_txbd_status(bdp);
2732 bdp = next_txbd(bdp, base, tx_ring_size);
2734 for (i = 0; i < frags; i++) {
2735 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2736 be16_to_cpu(bdp->length),
2738 gfar_clear_txbd_status(bdp);
2739 bdp = next_txbd(bdp, base, tx_ring_size);
2742 bytes_sent += GFAR_CB(skb)->bytes_sent;
2744 dev_kfree_skb_any(skb);
2746 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2748 skb_dirtytx = (skb_dirtytx + 1) &
2749 TX_RING_MOD_MASK(tx_ring_size);
2752 spin_lock(&tx_queue->txlock);
2753 tx_queue->num_txbdfree += nr_txbds;
2754 spin_unlock(&tx_queue->txlock);
2757 /* If we freed a buffer, we can restart transmission, if necessary */
2758 if (tx_queue->num_txbdfree &&
2759 netif_tx_queue_stopped(txq) &&
2760 !(test_bit(GFAR_DOWN, &priv->state)))
2761 netif_wake_subqueue(priv->ndev, tqi);
2763 /* Update dirty indicators */
2764 tx_queue->skb_dirtytx = skb_dirtytx;
2765 tx_queue->dirty_tx = bdp;
2767 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2770 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
2775 page = dev_alloc_page();
2776 if (unlikely(!page))
2779 addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
2780 if (unlikely(dma_mapping_error(rxq->dev, addr))) {
2788 rxb->page_offset = 0;
2793 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2795 struct gfar_private *priv = netdev_priv(rx_queue->ndev);
2796 struct gfar_extra_stats *estats = &priv->extra_stats;
2798 netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
2799 atomic64_inc(&estats->rx_alloc_err);
2802 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2806 struct gfar_rx_buff *rxb;
2809 i = rx_queue->next_to_use;
2810 bdp = &rx_queue->rx_bd_base[i];
2811 rxb = &rx_queue->rx_buff[i];
2813 while (alloc_cnt--) {
2814 /* try reuse page */
2815 if (unlikely(!rxb->page)) {
2816 if (unlikely(!gfar_new_page(rx_queue, rxb))) {
2817 gfar_rx_alloc_err(rx_queue);
2822 /* Setup the new RxBD */
2823 gfar_init_rxbdp(rx_queue, bdp,
2824 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
2826 /* Update to the next pointer */
2830 if (unlikely(++i == rx_queue->rx_ring_size)) {
2832 bdp = rx_queue->rx_bd_base;
2833 rxb = rx_queue->rx_buff;
2837 rx_queue->next_to_use = i;
2838 rx_queue->next_to_alloc = i;
2841 static void count_errors(u32 lstatus, struct net_device *ndev)
2843 struct gfar_private *priv = netdev_priv(ndev);
2844 struct net_device_stats *stats = &ndev->stats;
2845 struct gfar_extra_stats *estats = &priv->extra_stats;
2847 /* If the packet was truncated, none of the other errors matter */
2848 if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2849 stats->rx_length_errors++;
2851 atomic64_inc(&estats->rx_trunc);
2855 /* Count the errors, if there were any */
2856 if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2857 stats->rx_length_errors++;
2859 if (lstatus & BD_LFLAG(RXBD_LARGE))
2860 atomic64_inc(&estats->rx_large);
2862 atomic64_inc(&estats->rx_short);
2864 if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2865 stats->rx_frame_errors++;
2866 atomic64_inc(&estats->rx_nonoctet);
2868 if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2869 atomic64_inc(&estats->rx_crcerr);
2870 stats->rx_crc_errors++;
2872 if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2873 atomic64_inc(&estats->rx_overrun);
2874 stats->rx_over_errors++;
2878 irqreturn_t gfar_receive(int irq, void *grp_id)
2880 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2881 unsigned long flags;
2884 ievent = gfar_read(&grp->regs->ievent);
2886 if (unlikely(ievent & IEVENT_FGPI)) {
2887 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2891 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2892 spin_lock_irqsave(&grp->grplock, flags);
2893 imask = gfar_read(&grp->regs->imask);
2894 imask &= IMASK_RX_DISABLED;
2895 gfar_write(&grp->regs->imask, imask);
2896 spin_unlock_irqrestore(&grp->grplock, flags);
2897 __napi_schedule(&grp->napi_rx);
2899 /* Clear IEVENT, so interrupts aren't called again
2900 * because of the packets that have already arrived.
2902 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2908 /* Interrupt Handler for Transmit complete */
2909 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2911 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2912 unsigned long flags;
2915 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2916 spin_lock_irqsave(&grp->grplock, flags);
2917 imask = gfar_read(&grp->regs->imask);
2918 imask &= IMASK_TX_DISABLED;
2919 gfar_write(&grp->regs->imask, imask);
2920 spin_unlock_irqrestore(&grp->grplock, flags);
2921 __napi_schedule(&grp->napi_tx);
2923 /* Clear IEVENT, so interrupts aren't called again
2924 * because of the packets that have already arrived.
2926 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2932 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2933 struct sk_buff *skb, bool first)
2935 unsigned int size = lstatus & BD_LENGTH_MASK;
2936 struct page *page = rxb->page;
2937 bool last = !!(lstatus & BD_LFLAG(RXBD_LAST));
2939 /* Remove the FCS from the packet length */
2941 size -= ETH_FCS_LEN;
2943 if (likely(first)) {
2946 /* the last fragments' length contains the full frame length */
2950 /* in case the last fragment consisted only of the FCS */
2952 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2953 rxb->page_offset + RXBUF_ALIGNMENT,
2954 size, GFAR_RXB_TRUESIZE);
2957 /* try reuse page */
2958 if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page)))
2961 /* change offset to the other half */
2962 rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2969 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2970 struct gfar_rx_buff *old_rxb)
2972 struct gfar_rx_buff *new_rxb;
2973 u16 nta = rxq->next_to_alloc;
2975 new_rxb = &rxq->rx_buff[nta];
2977 /* find next buf that can reuse a page */
2979 rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2981 /* copy page reference */
2982 *new_rxb = *old_rxb;
2984 /* sync for use by the device */
2985 dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2986 old_rxb->page_offset,
2987 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2990 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2991 u32 lstatus, struct sk_buff *skb)
2993 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2994 struct page *page = rxb->page;
2998 void *buff_addr = page_address(page) + rxb->page_offset;
3000 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
3001 if (unlikely(!skb)) {
3002 gfar_rx_alloc_err(rx_queue);
3005 skb_reserve(skb, RXBUF_ALIGNMENT);
3009 dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
3010 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
3012 if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
3013 /* reuse the free half of the page */
3014 gfar_reuse_rx_page(rx_queue, rxb);
3016 /* page cannot be reused, unmap it */
3017 dma_unmap_page(rx_queue->dev, rxb->dma,
3018 PAGE_SIZE, DMA_FROM_DEVICE);
3021 /* clear rxb content */
3027 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
3029 /* If valid headers were found, and valid sums
3030 * were verified, then we tell the kernel that no
3031 * checksumming is necessary. Otherwise, it is [FIXME]
3033 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
3034 (RXFCB_CIP | RXFCB_CTU))
3035 skb->ip_summed = CHECKSUM_UNNECESSARY;
3037 skb_checksum_none_assert(skb);
3040 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
3041 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
3043 struct gfar_private *priv = netdev_priv(ndev);
3044 struct rxfcb *fcb = NULL;
3046 /* fcb is at the beginning if exists */
3047 fcb = (struct rxfcb *)skb->data;
3049 /* Remove the FCB from the skb
3050 * Remove the padded bytes, if there are any
3052 if (priv->uses_rxfcb)
3053 skb_pull(skb, GMAC_FCB_LEN);
3055 /* Get receive timestamp from the skb */
3056 if (priv->hwts_rx_en) {
3057 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
3058 u64 *ns = (u64 *) skb->data;
3060 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3061 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
3065 skb_pull(skb, priv->padding);
3067 if (ndev->features & NETIF_F_RXCSUM)
3068 gfar_rx_checksum(skb, fcb);
3070 /* Tell the skb what kind of packet this is */
3071 skb->protocol = eth_type_trans(skb, ndev);
3073 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
3074 * Even if vlan rx accel is disabled, on some chips
3075 * RXFCB_VLN is pseudo randomly set.
3077 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
3078 be16_to_cpu(fcb->flags) & RXFCB_VLN)
3079 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3080 be16_to_cpu(fcb->vlctl));
3083 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
3084 * until the budget/quota has been reached. Returns the number
3087 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
3089 struct net_device *ndev = rx_queue->ndev;
3090 struct gfar_private *priv = netdev_priv(ndev);
3093 struct sk_buff *skb = rx_queue->skb;
3094 int cleaned_cnt = gfar_rxbd_unused(rx_queue);
3095 unsigned int total_bytes = 0, total_pkts = 0;
3097 /* Get the first full descriptor */
3098 i = rx_queue->next_to_clean;
3100 while (rx_work_limit--) {
3103 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
3104 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3108 bdp = &rx_queue->rx_bd_base[i];
3109 lstatus = be32_to_cpu(bdp->lstatus);
3110 if (lstatus & BD_LFLAG(RXBD_EMPTY))
3113 /* order rx buffer descriptor reads */
3116 /* fetch next to clean buffer from the ring */
3117 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
3124 if (unlikely(++i == rx_queue->rx_ring_size))
3127 rx_queue->next_to_clean = i;
3129 /* fetch next buffer if not the last in frame */
3130 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
3133 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
3134 count_errors(lstatus, ndev);
3136 /* discard faulty buffer */
3139 rx_queue->stats.rx_dropped++;
3143 /* Increment the number of packets */
3145 total_bytes += skb->len;
3147 skb_record_rx_queue(skb, rx_queue->qindex);
3149 gfar_process_frame(ndev, skb);
3151 /* Send the packet up the stack */
3152 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
3157 /* Store incomplete frames for completion */
3158 rx_queue->skb = skb;
3160 rx_queue->stats.rx_packets += total_pkts;
3161 rx_queue->stats.rx_bytes += total_bytes;
3164 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3166 /* Update Last Free RxBD pointer for LFC */
3167 if (unlikely(priv->tx_actual_en)) {
3168 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3170 gfar_write(rx_queue->rfbptr, bdp_dma);
3176 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
3178 struct gfar_priv_grp *gfargrp =
3179 container_of(napi, struct gfar_priv_grp, napi_rx);
3180 struct gfar __iomem *regs = gfargrp->regs;
3181 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
3184 /* Clear IEVENT, so interrupts aren't called again
3185 * because of the packets that have already arrived
3187 gfar_write(®s->ievent, IEVENT_RX_MASK);
3189 work_done = gfar_clean_rx_ring(rx_queue, budget);
3191 if (work_done < budget) {
3193 napi_complete_done(napi, work_done);
3194 /* Clear the halt bit in RSTAT */
3195 gfar_write(®s->rstat, gfargrp->rstat);
3197 spin_lock_irq(&gfargrp->grplock);
3198 imask = gfar_read(®s->imask);
3199 imask |= IMASK_RX_DEFAULT;
3200 gfar_write(®s->imask, imask);
3201 spin_unlock_irq(&gfargrp->grplock);
3207 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3209 struct gfar_priv_grp *gfargrp =
3210 container_of(napi, struct gfar_priv_grp, napi_tx);
3211 struct gfar __iomem *regs = gfargrp->regs;
3212 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3215 /* Clear IEVENT, so interrupts aren't called again
3216 * because of the packets that have already arrived
3218 gfar_write(®s->ievent, IEVENT_TX_MASK);
3220 /* run Tx cleanup to completion */
3221 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3222 gfar_clean_tx_ring(tx_queue);
3224 napi_complete(napi);
3226 spin_lock_irq(&gfargrp->grplock);
3227 imask = gfar_read(®s->imask);
3228 imask |= IMASK_TX_DEFAULT;
3229 gfar_write(®s->imask, imask);
3230 spin_unlock_irq(&gfargrp->grplock);
3235 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3237 struct gfar_priv_grp *gfargrp =
3238 container_of(napi, struct gfar_priv_grp, napi_rx);
3239 struct gfar_private *priv = gfargrp->priv;
3240 struct gfar __iomem *regs = gfargrp->regs;
3241 struct gfar_priv_rx_q *rx_queue = NULL;
3242 int work_done = 0, work_done_per_q = 0;
3243 int i, budget_per_q = 0;
3244 unsigned long rstat_rxf;
3247 /* Clear IEVENT, so interrupts aren't called again
3248 * because of the packets that have already arrived
3250 gfar_write(®s->ievent, IEVENT_RX_MASK);
3252 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK;
3254 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3256 budget_per_q = budget/num_act_queues;
3258 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3259 /* skip queue if not active */
3260 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3263 rx_queue = priv->rx_queue[i];
3265 gfar_clean_rx_ring(rx_queue, budget_per_q);
3266 work_done += work_done_per_q;
3268 /* finished processing this queue */
3269 if (work_done_per_q < budget_per_q) {
3270 /* clear active queue hw indication */
3271 gfar_write(®s->rstat,
3272 RSTAT_CLEAR_RXF0 >> i);
3275 if (!num_act_queues)
3280 if (!num_act_queues) {
3282 napi_complete_done(napi, work_done);
3284 /* Clear the halt bit in RSTAT */
3285 gfar_write(®s->rstat, gfargrp->rstat);
3287 spin_lock_irq(&gfargrp->grplock);
3288 imask = gfar_read(®s->imask);
3289 imask |= IMASK_RX_DEFAULT;
3290 gfar_write(®s->imask, imask);
3291 spin_unlock_irq(&gfargrp->grplock);
3297 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3299 struct gfar_priv_grp *gfargrp =
3300 container_of(napi, struct gfar_priv_grp, napi_tx);
3301 struct gfar_private *priv = gfargrp->priv;
3302 struct gfar __iomem *regs = gfargrp->regs;
3303 struct gfar_priv_tx_q *tx_queue = NULL;
3304 int has_tx_work = 0;
3307 /* Clear IEVENT, so interrupts aren't called again
3308 * because of the packets that have already arrived
3310 gfar_write(®s->ievent, IEVENT_TX_MASK);
3312 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3313 tx_queue = priv->tx_queue[i];
3314 /* run Tx cleanup to completion */
3315 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3316 gfar_clean_tx_ring(tx_queue);
3323 napi_complete(napi);
3325 spin_lock_irq(&gfargrp->grplock);
3326 imask = gfar_read(®s->imask);
3327 imask |= IMASK_TX_DEFAULT;
3328 gfar_write(®s->imask, imask);
3329 spin_unlock_irq(&gfargrp->grplock);
3336 #ifdef CONFIG_NET_POLL_CONTROLLER
3337 /* Polling 'interrupt' - used by things like netconsole to send skbs
3338 * without having to re-enable interrupts. It's not called while
3339 * the interrupt routine is executing.
3341 static void gfar_netpoll(struct net_device *dev)
3343 struct gfar_private *priv = netdev_priv(dev);
3346 /* If the device has multiple interrupts, run tx/rx */
3347 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3348 for (i = 0; i < priv->num_grps; i++) {
3349 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3351 disable_irq(gfar_irq(grp, TX)->irq);
3352 disable_irq(gfar_irq(grp, RX)->irq);
3353 disable_irq(gfar_irq(grp, ER)->irq);
3354 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3355 enable_irq(gfar_irq(grp, ER)->irq);
3356 enable_irq(gfar_irq(grp, RX)->irq);
3357 enable_irq(gfar_irq(grp, TX)->irq);
3360 for (i = 0; i < priv->num_grps; i++) {
3361 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3363 disable_irq(gfar_irq(grp, TX)->irq);
3364 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3365 enable_irq(gfar_irq(grp, TX)->irq);
3371 /* The interrupt handler for devices with one interrupt */
3372 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3374 struct gfar_priv_grp *gfargrp = grp_id;
3376 /* Save ievent for future reference */
3377 u32 events = gfar_read(&gfargrp->regs->ievent);
3379 /* Check for reception */
3380 if (events & IEVENT_RX_MASK)
3381 gfar_receive(irq, grp_id);
3383 /* Check for transmit completion */
3384 if (events & IEVENT_TX_MASK)
3385 gfar_transmit(irq, grp_id);
3387 /* Check for errors */
3388 if (events & IEVENT_ERR_MASK)
3389 gfar_error(irq, grp_id);
3394 /* Called every time the controller might need to be made
3395 * aware of new link state. The PHY code conveys this
3396 * information through variables in the phydev structure, and this
3397 * function converts those variables into the appropriate
3398 * register values, and can bring down the device if needed.
3400 static void adjust_link(struct net_device *dev)
3402 struct gfar_private *priv = netdev_priv(dev);
3403 struct phy_device *phydev = dev->phydev;
3405 if (unlikely(phydev->link != priv->oldlink ||
3406 (phydev->link && (phydev->duplex != priv->oldduplex ||
3407 phydev->speed != priv->oldspeed))))
3408 gfar_update_link_state(priv);
3411 /* Update the hash table based on the current list of multicast
3412 * addresses we subscribe to. Also, change the promiscuity of
3413 * the device based on the flags (this function is called
3414 * whenever dev->flags is changed
3416 static void gfar_set_multi(struct net_device *dev)
3418 struct netdev_hw_addr *ha;
3419 struct gfar_private *priv = netdev_priv(dev);
3420 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3423 if (dev->flags & IFF_PROMISC) {
3424 /* Set RCTRL to PROM */
3425 tempval = gfar_read(®s->rctrl);
3426 tempval |= RCTRL_PROM;
3427 gfar_write(®s->rctrl, tempval);
3429 /* Set RCTRL to not PROM */
3430 tempval = gfar_read(®s->rctrl);
3431 tempval &= ~(RCTRL_PROM);
3432 gfar_write(®s->rctrl, tempval);
3435 if (dev->flags & IFF_ALLMULTI) {
3436 /* Set the hash to rx all multicast frames */
3437 gfar_write(®s->igaddr0, 0xffffffff);
3438 gfar_write(®s->igaddr1, 0xffffffff);
3439 gfar_write(®s->igaddr2, 0xffffffff);
3440 gfar_write(®s->igaddr3, 0xffffffff);
3441 gfar_write(®s->igaddr4, 0xffffffff);
3442 gfar_write(®s->igaddr5, 0xffffffff);
3443 gfar_write(®s->igaddr6, 0xffffffff);
3444 gfar_write(®s->igaddr7, 0xffffffff);
3445 gfar_write(®s->gaddr0, 0xffffffff);
3446 gfar_write(®s->gaddr1, 0xffffffff);
3447 gfar_write(®s->gaddr2, 0xffffffff);
3448 gfar_write(®s->gaddr3, 0xffffffff);
3449 gfar_write(®s->gaddr4, 0xffffffff);
3450 gfar_write(®s->gaddr5, 0xffffffff);
3451 gfar_write(®s->gaddr6, 0xffffffff);
3452 gfar_write(®s->gaddr7, 0xffffffff);
3457 /* zero out the hash */
3458 gfar_write(®s->igaddr0, 0x0);
3459 gfar_write(®s->igaddr1, 0x0);
3460 gfar_write(®s->igaddr2, 0x0);
3461 gfar_write(®s->igaddr3, 0x0);
3462 gfar_write(®s->igaddr4, 0x0);
3463 gfar_write(®s->igaddr5, 0x0);
3464 gfar_write(®s->igaddr6, 0x0);
3465 gfar_write(®s->igaddr7, 0x0);
3466 gfar_write(®s->gaddr0, 0x0);
3467 gfar_write(®s->gaddr1, 0x0);
3468 gfar_write(®s->gaddr2, 0x0);
3469 gfar_write(®s->gaddr3, 0x0);
3470 gfar_write(®s->gaddr4, 0x0);
3471 gfar_write(®s->gaddr5, 0x0);
3472 gfar_write(®s->gaddr6, 0x0);
3473 gfar_write(®s->gaddr7, 0x0);
3475 /* If we have extended hash tables, we need to
3476 * clear the exact match registers to prepare for
3479 if (priv->extended_hash) {
3480 em_num = GFAR_EM_NUM + 1;
3481 gfar_clear_exact_match(dev);
3488 if (netdev_mc_empty(dev))
3491 /* Parse the list, and set the appropriate bits */
3492 netdev_for_each_mc_addr(ha, dev) {
3494 gfar_set_mac_for_addr(dev, idx, ha->addr);
3497 gfar_set_hash_for_addr(dev, ha->addr);
3503 /* Clears each of the exact match registers to zero, so they
3504 * don't interfere with normal reception
3506 static void gfar_clear_exact_match(struct net_device *dev)
3509 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3511 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3512 gfar_set_mac_for_addr(dev, idx, zero_arr);
3515 /* Set the appropriate hash bit for the given addr */
3516 /* The algorithm works like so:
3517 * 1) Take the Destination Address (ie the multicast address), and
3518 * do a CRC on it (little endian), and reverse the bits of the
3520 * 2) Use the 8 most significant bits as a hash into a 256-entry
3521 * table. The table is controlled through 8 32-bit registers:
3522 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3523 * gaddr7. This means that the 3 most significant bits in the
3524 * hash index which gaddr register to use, and the 5 other bits
3525 * indicate which bit (assuming an IBM numbering scheme, which
3526 * for PowerPC (tm) is usually the case) in the register holds
3529 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3532 struct gfar_private *priv = netdev_priv(dev);
3533 u32 result = ether_crc(ETH_ALEN, addr);
3534 int width = priv->hash_width;
3535 u8 whichbit = (result >> (32 - width)) & 0x1f;
3536 u8 whichreg = result >> (32 - width + 5);
3537 u32 value = (1 << (31-whichbit));
3539 tempval = gfar_read(priv->hash_regs[whichreg]);
3541 gfar_write(priv->hash_regs[whichreg], tempval);
3545 /* There are multiple MAC Address register pairs on some controllers
3546 * This function sets the numth pair to a given address
3548 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3551 struct gfar_private *priv = netdev_priv(dev);
3552 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3554 u32 __iomem *macptr = ®s->macstnaddr1;
3558 /* For a station address of 0x12345678ABCD in transmission
3559 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3560 * MACnADDR2 is set to 0x34120000.
3562 tempval = (addr[5] << 24) | (addr[4] << 16) |
3563 (addr[3] << 8) | addr[2];
3565 gfar_write(macptr, tempval);
3567 tempval = (addr[1] << 24) | (addr[0] << 16);
3569 gfar_write(macptr+1, tempval);
3572 /* GFAR error interrupt handler */
3573 static irqreturn_t gfar_error(int irq, void *grp_id)
3575 struct gfar_priv_grp *gfargrp = grp_id;
3576 struct gfar __iomem *regs = gfargrp->regs;
3577 struct gfar_private *priv= gfargrp->priv;
3578 struct net_device *dev = priv->ndev;
3580 /* Save ievent for future reference */
3581 u32 events = gfar_read(®s->ievent);
3584 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
3586 /* Magic Packet is not an error. */
3587 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3588 (events & IEVENT_MAG))
3589 events &= ~IEVENT_MAG;
3592 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3594 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3595 events, gfar_read(®s->imask));
3597 /* Update the error counters */
3598 if (events & IEVENT_TXE) {
3599 dev->stats.tx_errors++;
3601 if (events & IEVENT_LC)
3602 dev->stats.tx_window_errors++;
3603 if (events & IEVENT_CRL)
3604 dev->stats.tx_aborted_errors++;
3605 if (events & IEVENT_XFUN) {
3606 netif_dbg(priv, tx_err, dev,
3607 "TX FIFO underrun, packet dropped\n");
3608 dev->stats.tx_dropped++;
3609 atomic64_inc(&priv->extra_stats.tx_underrun);
3611 schedule_work(&priv->reset_task);
3613 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3615 if (events & IEVENT_BSY) {
3616 dev->stats.rx_over_errors++;
3617 atomic64_inc(&priv->extra_stats.rx_bsy);
3619 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3620 gfar_read(®s->rstat));
3622 if (events & IEVENT_BABR) {
3623 dev->stats.rx_errors++;
3624 atomic64_inc(&priv->extra_stats.rx_babr);
3626 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3628 if (events & IEVENT_EBERR) {
3629 atomic64_inc(&priv->extra_stats.eberr);
3630 netif_dbg(priv, rx_err, dev, "bus error\n");
3632 if (events & IEVENT_RXC)
3633 netif_dbg(priv, rx_status, dev, "control frame\n");
3635 if (events & IEVENT_BABT) {
3636 atomic64_inc(&priv->extra_stats.tx_babt);
3637 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3642 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3644 struct net_device *ndev = priv->ndev;
3645 struct phy_device *phydev = ndev->phydev;
3648 if (!phydev->duplex)
3651 if (!priv->pause_aneg_en) {
3652 if (priv->tx_pause_en)
3653 val |= MACCFG1_TX_FLOW;
3654 if (priv->rx_pause_en)
3655 val |= MACCFG1_RX_FLOW;
3657 u16 lcl_adv, rmt_adv;
3659 /* get link partner capabilities */
3662 rmt_adv = LPA_PAUSE_CAP;
3663 if (phydev->asym_pause)
3664 rmt_adv |= LPA_PAUSE_ASYM;
3667 if (phydev->advertising & ADVERTISED_Pause)
3668 lcl_adv |= ADVERTISE_PAUSE_CAP;
3669 if (phydev->advertising & ADVERTISED_Asym_Pause)
3670 lcl_adv |= ADVERTISE_PAUSE_ASYM;
3672 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3673 if (flowctrl & FLOW_CTRL_TX)
3674 val |= MACCFG1_TX_FLOW;
3675 if (flowctrl & FLOW_CTRL_RX)
3676 val |= MACCFG1_RX_FLOW;
3682 static noinline void gfar_update_link_state(struct gfar_private *priv)
3684 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3685 struct net_device *ndev = priv->ndev;
3686 struct phy_device *phydev = ndev->phydev;
3687 struct gfar_priv_rx_q *rx_queue = NULL;
3690 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3694 u32 tempval1 = gfar_read(®s->maccfg1);
3695 u32 tempval = gfar_read(®s->maccfg2);
3696 u32 ecntrl = gfar_read(®s->ecntrl);
3697 u32 tx_flow_oldval = (tempval1 & MACCFG1_TX_FLOW);
3699 if (phydev->duplex != priv->oldduplex) {
3700 if (!(phydev->duplex))
3701 tempval &= ~(MACCFG2_FULL_DUPLEX);
3703 tempval |= MACCFG2_FULL_DUPLEX;
3705 priv->oldduplex = phydev->duplex;
3708 if (phydev->speed != priv->oldspeed) {
3709 switch (phydev->speed) {
3712 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3714 ecntrl &= ~(ECNTRL_R100);
3719 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3721 /* Reduced mode distinguishes
3722 * between 10 and 100
3724 if (phydev->speed == SPEED_100)
3725 ecntrl |= ECNTRL_R100;
3727 ecntrl &= ~(ECNTRL_R100);
3730 netif_warn(priv, link, priv->ndev,
3731 "Ack! Speed (%d) is not 10/100/1000!\n",
3736 priv->oldspeed = phydev->speed;
3739 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3740 tempval1 |= gfar_get_flowctrl_cfg(priv);
3742 /* Turn last free buffer recording on */
3743 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3744 for (i = 0; i < priv->num_rx_queues; i++) {
3747 rx_queue = priv->rx_queue[i];
3748 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3749 gfar_write(rx_queue->rfbptr, bdp_dma);
3752 priv->tx_actual_en = 1;
3755 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3756 priv->tx_actual_en = 0;
3758 gfar_write(®s->maccfg1, tempval1);
3759 gfar_write(®s->maccfg2, tempval);
3760 gfar_write(®s->ecntrl, ecntrl);
3765 } else if (priv->oldlink) {
3768 priv->oldduplex = -1;
3771 if (netif_msg_link(priv))
3772 phy_print_status(phydev);
3775 static const struct of_device_id gfar_match[] =
3779 .compatible = "gianfar",
3782 .compatible = "fsl,etsec2",
3786 MODULE_DEVICE_TABLE(of, gfar_match);
3788 /* Structure for a device driver */
3789 static struct platform_driver gfar_driver = {
3791 .name = "fsl-gianfar",
3793 .of_match_table = gfar_match,
3795 .probe = gfar_probe,
3796 .remove = gfar_remove,
3799 module_platform_driver(gfar_driver);