ade6b3e4ed1326a42aa39d52b2465f1b271c02f8
[sfrench/cifs-2.6.git] / drivers / net / ethernet / faraday / ftgmac100.c
1 /*
2  * Faraday FTGMAC100 Gigabit Ethernet
3  *
4  * (C) Copyright 2009-2011 Faraday Technology
5  * Po-Yu Chuang <ratbert@faraday-tech.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20  */
21
22 #define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
23
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/ethtool.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/of.h>
32 #include <linux/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/property.h>
35 #include <net/ip.h>
36 #include <net/ncsi.h>
37
38 #include "ftgmac100.h"
39
40 #define DRV_NAME        "ftgmac100"
41 #define DRV_VERSION     "0.7"
42
43 #define RX_QUEUE_ENTRIES        256     /* must be power of 2 */
44 #define TX_QUEUE_ENTRIES        512     /* must be power of 2 */
45
46 #define MAX_PKT_SIZE            1518
47 #define RX_BUF_SIZE             PAGE_SIZE       /* must be smaller than 0x3fff */
48
49 /******************************************************************************
50  * private data
51  *****************************************************************************/
52 struct ftgmac100_descs {
53         struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
54         struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES];
55 };
56
57 struct ftgmac100 {
58         struct resource *res;
59         void __iomem *base;
60         int irq;
61
62         struct ftgmac100_descs *descs;
63         dma_addr_t descs_dma_addr;
64
65         struct page *rx_pages[RX_QUEUE_ENTRIES];
66
67         unsigned int rx_pointer;
68         unsigned int tx_clean_pointer;
69         unsigned int tx_pointer;
70         unsigned int tx_pending;
71
72         spinlock_t tx_lock;
73
74         struct net_device *netdev;
75         struct device *dev;
76         struct ncsi_dev *ndev;
77         struct napi_struct napi;
78
79         struct mii_bus *mii_bus;
80         int old_speed;
81         int int_mask_all;
82         bool use_ncsi;
83         bool enabled;
84
85         u32 rxdes0_edorr_mask;
86         u32 txdes0_edotr_mask;
87 };
88
89 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
90                                    struct ftgmac100_rxdes *rxdes, gfp_t gfp);
91
92 /******************************************************************************
93  * internal functions (hardware register access)
94  *****************************************************************************/
95 static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr)
96 {
97         iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR);
98 }
99
100 static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv,
101                 unsigned int size)
102 {
103         size = FTGMAC100_RBSR_SIZE(size);
104         iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR);
105 }
106
107 static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv,
108                                                    dma_addr_t addr)
109 {
110         iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
111 }
112
113 static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv)
114 {
115         iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
116 }
117
118 static int ftgmac100_reset_hw(struct ftgmac100 *priv)
119 {
120         struct net_device *netdev = priv->netdev;
121         int i;
122
123         /* NOTE: reset clears all registers */
124         iowrite32(FTGMAC100_MACCR_SW_RST, priv->base + FTGMAC100_OFFSET_MACCR);
125         for (i = 0; i < 5; i++) {
126                 unsigned int maccr;
127
128                 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
129                 if (!(maccr & FTGMAC100_MACCR_SW_RST))
130                         return 0;
131
132                 udelay(1000);
133         }
134
135         netdev_err(netdev, "software reset failed\n");
136         return -EIO;
137 }
138
139 static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac)
140 {
141         unsigned int maddr = mac[0] << 8 | mac[1];
142         unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
143
144         iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
145         iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
146 }
147
148 static void ftgmac100_setup_mac(struct ftgmac100 *priv)
149 {
150         u8 mac[ETH_ALEN];
151         unsigned int m;
152         unsigned int l;
153         void *addr;
154
155         addr = device_get_mac_address(priv->dev, mac, ETH_ALEN);
156         if (addr) {
157                 ether_addr_copy(priv->netdev->dev_addr, mac);
158                 dev_info(priv->dev, "Read MAC address %pM from device tree\n",
159                          mac);
160                 return;
161         }
162
163         m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
164         l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
165
166         mac[0] = (m >> 8) & 0xff;
167         mac[1] = m & 0xff;
168         mac[2] = (l >> 24) & 0xff;
169         mac[3] = (l >> 16) & 0xff;
170         mac[4] = (l >> 8) & 0xff;
171         mac[5] = l & 0xff;
172
173         if (is_valid_ether_addr(mac)) {
174                 ether_addr_copy(priv->netdev->dev_addr, mac);
175                 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
176         } else {
177                 eth_hw_addr_random(priv->netdev);
178                 dev_info(priv->dev, "Generated random MAC address %pM\n",
179                          priv->netdev->dev_addr);
180         }
181 }
182
183 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
184 {
185         int ret;
186
187         ret = eth_prepare_mac_addr_change(dev, p);
188         if (ret < 0)
189                 return ret;
190
191         eth_commit_mac_addr_change(dev, p);
192         ftgmac100_set_mac(netdev_priv(dev), dev->dev_addr);
193
194         return 0;
195 }
196
197 static void ftgmac100_init_hw(struct ftgmac100 *priv)
198 {
199         /* setup ring buffer base registers */
200         ftgmac100_set_rx_ring_base(priv,
201                                    priv->descs_dma_addr +
202                                    offsetof(struct ftgmac100_descs, rxdes));
203         ftgmac100_set_normal_prio_tx_ring_base(priv,
204                                                priv->descs_dma_addr +
205                                                offsetof(struct ftgmac100_descs, txdes));
206
207         ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE);
208
209         iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC);
210
211         ftgmac100_set_mac(priv, priv->netdev->dev_addr);
212 }
213
214 #define MACCR_ENABLE_ALL        (FTGMAC100_MACCR_TXDMA_EN       | \
215                                  FTGMAC100_MACCR_RXDMA_EN       | \
216                                  FTGMAC100_MACCR_TXMAC_EN       | \
217                                  FTGMAC100_MACCR_RXMAC_EN       | \
218                                  FTGMAC100_MACCR_FULLDUP        | \
219                                  FTGMAC100_MACCR_CRC_APD        | \
220                                  FTGMAC100_MACCR_RX_RUNT        | \
221                                  FTGMAC100_MACCR_RX_BROADPKT)
222
223 static void ftgmac100_start_hw(struct ftgmac100 *priv, int speed)
224 {
225         int maccr = MACCR_ENABLE_ALL;
226
227         switch (speed) {
228         default:
229         case 10:
230                 break;
231
232         case 100:
233                 maccr |= FTGMAC100_MACCR_FAST_MODE;
234                 break;
235
236         case 1000:
237                 maccr |= FTGMAC100_MACCR_GIGA_MODE;
238                 break;
239         }
240
241         iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
242 }
243
244 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
245 {
246         iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
247 }
248
249 /******************************************************************************
250  * internal functions (receive descriptor)
251  *****************************************************************************/
252 static bool ftgmac100_rxdes_first_segment(struct ftgmac100_rxdes *rxdes)
253 {
254         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FRS);
255 }
256
257 static bool ftgmac100_rxdes_last_segment(struct ftgmac100_rxdes *rxdes)
258 {
259         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_LRS);
260 }
261
262 static bool ftgmac100_rxdes_packet_ready(struct ftgmac100_rxdes *rxdes)
263 {
264         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY);
265 }
266
267 static void ftgmac100_rxdes_set_dma_own(const struct ftgmac100 *priv,
268                                         struct ftgmac100_rxdes *rxdes)
269 {
270         /* clear status bits */
271         rxdes->rxdes0 &= cpu_to_le32(priv->rxdes0_edorr_mask);
272 }
273
274 static bool ftgmac100_rxdes_rx_error(struct ftgmac100_rxdes *rxdes)
275 {
276         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ERR);
277 }
278
279 static bool ftgmac100_rxdes_crc_error(struct ftgmac100_rxdes *rxdes)
280 {
281         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_CRC_ERR);
282 }
283
284 static bool ftgmac100_rxdes_frame_too_long(struct ftgmac100_rxdes *rxdes)
285 {
286         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FTL);
287 }
288
289 static bool ftgmac100_rxdes_runt(struct ftgmac100_rxdes *rxdes)
290 {
291         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RUNT);
292 }
293
294 static bool ftgmac100_rxdes_odd_nibble(struct ftgmac100_rxdes *rxdes)
295 {
296         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ODD_NB);
297 }
298
299 static unsigned int ftgmac100_rxdes_data_length(struct ftgmac100_rxdes *rxdes)
300 {
301         return le32_to_cpu(rxdes->rxdes0) & FTGMAC100_RXDES0_VDBC;
302 }
303
304 static bool ftgmac100_rxdes_multicast(struct ftgmac100_rxdes *rxdes)
305 {
306         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_MULTICAST);
307 }
308
309 static void ftgmac100_rxdes_set_end_of_ring(const struct ftgmac100 *priv,
310                                             struct ftgmac100_rxdes *rxdes)
311 {
312         rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
313 }
314
315 static void ftgmac100_rxdes_set_dma_addr(struct ftgmac100_rxdes *rxdes,
316                                          dma_addr_t addr)
317 {
318         rxdes->rxdes3 = cpu_to_le32(addr);
319 }
320
321 static dma_addr_t ftgmac100_rxdes_get_dma_addr(struct ftgmac100_rxdes *rxdes)
322 {
323         return le32_to_cpu(rxdes->rxdes3);
324 }
325
326 static bool ftgmac100_rxdes_is_tcp(struct ftgmac100_rxdes *rxdes)
327 {
328         return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) ==
329                cpu_to_le32(FTGMAC100_RXDES1_PROT_TCPIP);
330 }
331
332 static bool ftgmac100_rxdes_is_udp(struct ftgmac100_rxdes *rxdes)
333 {
334         return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) ==
335                cpu_to_le32(FTGMAC100_RXDES1_PROT_UDPIP);
336 }
337
338 static bool ftgmac100_rxdes_tcpcs_err(struct ftgmac100_rxdes *rxdes)
339 {
340         return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_TCP_CHKSUM_ERR);
341 }
342
343 static bool ftgmac100_rxdes_udpcs_err(struct ftgmac100_rxdes *rxdes)
344 {
345         return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_UDP_CHKSUM_ERR);
346 }
347
348 static bool ftgmac100_rxdes_ipcs_err(struct ftgmac100_rxdes *rxdes)
349 {
350         return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_IP_CHKSUM_ERR);
351 }
352
353 static inline struct page **ftgmac100_rxdes_page_slot(struct ftgmac100 *priv,
354                                                       struct ftgmac100_rxdes *rxdes)
355 {
356         return &priv->rx_pages[rxdes - priv->descs->rxdes];
357 }
358
359 /*
360  * rxdes2 is not used by hardware. We use it to keep track of page.
361  * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
362  */
363 static void ftgmac100_rxdes_set_page(struct ftgmac100 *priv,
364                                      struct ftgmac100_rxdes *rxdes,
365                                      struct page *page)
366 {
367         *ftgmac100_rxdes_page_slot(priv, rxdes) = page;
368 }
369
370 static struct page *ftgmac100_rxdes_get_page(struct ftgmac100 *priv,
371                                              struct ftgmac100_rxdes *rxdes)
372 {
373         return *ftgmac100_rxdes_page_slot(priv, rxdes);
374 }
375
376 /******************************************************************************
377  * internal functions (receive)
378  *****************************************************************************/
379 static int ftgmac100_next_rx_pointer(int pointer)
380 {
381         return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
382 }
383
384 static void ftgmac100_rx_pointer_advance(struct ftgmac100 *priv)
385 {
386         priv->rx_pointer = ftgmac100_next_rx_pointer(priv->rx_pointer);
387 }
388
389 static struct ftgmac100_rxdes *ftgmac100_current_rxdes(struct ftgmac100 *priv)
390 {
391         return &priv->descs->rxdes[priv->rx_pointer];
392 }
393
394 static struct ftgmac100_rxdes *
395 ftgmac100_rx_locate_first_segment(struct ftgmac100 *priv)
396 {
397         struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv);
398
399         while (ftgmac100_rxdes_packet_ready(rxdes)) {
400                 if (ftgmac100_rxdes_first_segment(rxdes))
401                         return rxdes;
402
403                 ftgmac100_rxdes_set_dma_own(priv, rxdes);
404                 ftgmac100_rx_pointer_advance(priv);
405                 rxdes = ftgmac100_current_rxdes(priv);
406         }
407
408         return NULL;
409 }
410
411 static bool ftgmac100_rx_packet_error(struct ftgmac100 *priv,
412                                       struct ftgmac100_rxdes *rxdes)
413 {
414         struct net_device *netdev = priv->netdev;
415         bool error = false;
416
417         if (unlikely(ftgmac100_rxdes_rx_error(rxdes))) {
418                 if (net_ratelimit())
419                         netdev_info(netdev, "rx err\n");
420
421                 netdev->stats.rx_errors++;
422                 error = true;
423         }
424
425         if (unlikely(ftgmac100_rxdes_crc_error(rxdes))) {
426                 if (net_ratelimit())
427                         netdev_info(netdev, "rx crc err\n");
428
429                 netdev->stats.rx_crc_errors++;
430                 error = true;
431         } else if (unlikely(ftgmac100_rxdes_ipcs_err(rxdes))) {
432                 if (net_ratelimit())
433                         netdev_info(netdev, "rx IP checksum err\n");
434
435                 error = true;
436         }
437
438         if (unlikely(ftgmac100_rxdes_frame_too_long(rxdes))) {
439                 if (net_ratelimit())
440                         netdev_info(netdev, "rx frame too long\n");
441
442                 netdev->stats.rx_length_errors++;
443                 error = true;
444         } else if (unlikely(ftgmac100_rxdes_runt(rxdes))) {
445                 if (net_ratelimit())
446                         netdev_info(netdev, "rx runt\n");
447
448                 netdev->stats.rx_length_errors++;
449                 error = true;
450         } else if (unlikely(ftgmac100_rxdes_odd_nibble(rxdes))) {
451                 if (net_ratelimit())
452                         netdev_info(netdev, "rx odd nibble\n");
453
454                 netdev->stats.rx_length_errors++;
455                 error = true;
456         }
457
458         return error;
459 }
460
461 static void ftgmac100_rx_drop_packet(struct ftgmac100 *priv)
462 {
463         struct net_device *netdev = priv->netdev;
464         struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv);
465         bool done = false;
466
467         if (net_ratelimit())
468                 netdev_dbg(netdev, "drop packet %p\n", rxdes);
469
470         do {
471                 if (ftgmac100_rxdes_last_segment(rxdes))
472                         done = true;
473
474                 ftgmac100_rxdes_set_dma_own(priv, rxdes);
475                 ftgmac100_rx_pointer_advance(priv);
476                 rxdes = ftgmac100_current_rxdes(priv);
477         } while (!done && ftgmac100_rxdes_packet_ready(rxdes));
478
479         netdev->stats.rx_dropped++;
480 }
481
482 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
483 {
484         struct net_device *netdev = priv->netdev;
485         struct ftgmac100_rxdes *rxdes;
486         struct sk_buff *skb;
487         bool done = false;
488
489         rxdes = ftgmac100_rx_locate_first_segment(priv);
490         if (!rxdes)
491                 return false;
492
493         if (unlikely(ftgmac100_rx_packet_error(priv, rxdes))) {
494                 ftgmac100_rx_drop_packet(priv);
495                 return true;
496         }
497
498         /* start processing */
499         skb = netdev_alloc_skb_ip_align(netdev, 128);
500         if (unlikely(!skb)) {
501                 if (net_ratelimit())
502                         netdev_err(netdev, "rx skb alloc failed\n");
503
504                 ftgmac100_rx_drop_packet(priv);
505                 return true;
506         }
507
508         if (unlikely(ftgmac100_rxdes_multicast(rxdes)))
509                 netdev->stats.multicast++;
510
511         /*
512          * It seems that HW does checksum incorrectly with fragmented packets,
513          * so we are conservative here - if HW checksum error, let software do
514          * the checksum again.
515          */
516         if ((ftgmac100_rxdes_is_tcp(rxdes) && !ftgmac100_rxdes_tcpcs_err(rxdes)) ||
517             (ftgmac100_rxdes_is_udp(rxdes) && !ftgmac100_rxdes_udpcs_err(rxdes)))
518                 skb->ip_summed = CHECKSUM_UNNECESSARY;
519
520         do {
521                 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes);
522                 struct page *page = ftgmac100_rxdes_get_page(priv, rxdes);
523                 unsigned int size;
524
525                 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
526
527                 size = ftgmac100_rxdes_data_length(rxdes);
528                 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, 0, size);
529
530                 skb->len += size;
531                 skb->data_len += size;
532                 skb->truesize += PAGE_SIZE;
533
534                 if (ftgmac100_rxdes_last_segment(rxdes))
535                         done = true;
536
537                 ftgmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC);
538
539                 ftgmac100_rx_pointer_advance(priv);
540                 rxdes = ftgmac100_current_rxdes(priv);
541         } while (!done);
542
543         /* Small frames are copied into linear part of skb to free one page */
544         if (skb->len <= 128) {
545                 skb->truesize -= PAGE_SIZE;
546                 __pskb_pull_tail(skb, skb->len);
547         } else {
548                 /* We pull the minimum amount into linear part */
549                 __pskb_pull_tail(skb, ETH_HLEN);
550         }
551         skb->protocol = eth_type_trans(skb, netdev);
552
553         netdev->stats.rx_packets++;
554         netdev->stats.rx_bytes += skb->len;
555
556         /* push packet to protocol stack */
557         napi_gro_receive(&priv->napi, skb);
558
559         (*processed)++;
560         return true;
561 }
562
563 /******************************************************************************
564  * internal functions (transmit descriptor)
565  *****************************************************************************/
566 static void ftgmac100_txdes_reset(const struct ftgmac100 *priv,
567                                   struct ftgmac100_txdes *txdes)
568 {
569         /* clear all except end of ring bit */
570         txdes->txdes0 &= cpu_to_le32(priv->txdes0_edotr_mask);
571         txdes->txdes1 = 0;
572         txdes->txdes2 = 0;
573         txdes->txdes3 = 0;
574 }
575
576 static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes *txdes)
577 {
578         return txdes->txdes0 & cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
579 }
580
581 static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes *txdes)
582 {
583         /*
584          * Make sure dma own bit will not be set before any other
585          * descriptor fields.
586          */
587         wmb();
588         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
589 }
590
591 static void ftgmac100_txdes_set_end_of_ring(const struct ftgmac100 *priv,
592                                             struct ftgmac100_txdes *txdes)
593 {
594         txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
595 }
596
597 static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes *txdes)
598 {
599         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_FTS);
600 }
601
602 static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes *txdes)
603 {
604         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_LTS);
605 }
606
607 static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes *txdes,
608                                             unsigned int len)
609 {
610         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len));
611 }
612
613 static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes *txdes)
614 {
615         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TXIC);
616 }
617
618 static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes *txdes)
619 {
620         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM);
621 }
622
623 static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes *txdes)
624 {
625         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM);
626 }
627
628 static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes *txdes)
629 {
630         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM);
631 }
632
633 static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes *txdes,
634                                          dma_addr_t addr)
635 {
636         txdes->txdes3 = cpu_to_le32(addr);
637 }
638
639 static dma_addr_t ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes *txdes)
640 {
641         return le32_to_cpu(txdes->txdes3);
642 }
643
644 /*
645  * txdes2 is not used by hardware. We use it to keep track of socket buffer.
646  * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
647  */
648 static void ftgmac100_txdes_set_skb(struct ftgmac100_txdes *txdes,
649                                     struct sk_buff *skb)
650 {
651         txdes->txdes2 = (unsigned int)skb;
652 }
653
654 static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes)
655 {
656         return (struct sk_buff *)txdes->txdes2;
657 }
658
659 /******************************************************************************
660  * internal functions (transmit)
661  *****************************************************************************/
662 static int ftgmac100_next_tx_pointer(int pointer)
663 {
664         return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
665 }
666
667 static void ftgmac100_tx_pointer_advance(struct ftgmac100 *priv)
668 {
669         priv->tx_pointer = ftgmac100_next_tx_pointer(priv->tx_pointer);
670 }
671
672 static void ftgmac100_tx_clean_pointer_advance(struct ftgmac100 *priv)
673 {
674         priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv->tx_clean_pointer);
675 }
676
677 static struct ftgmac100_txdes *ftgmac100_current_txdes(struct ftgmac100 *priv)
678 {
679         return &priv->descs->txdes[priv->tx_pointer];
680 }
681
682 static struct ftgmac100_txdes *
683 ftgmac100_current_clean_txdes(struct ftgmac100 *priv)
684 {
685         return &priv->descs->txdes[priv->tx_clean_pointer];
686 }
687
688 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
689 {
690         struct net_device *netdev = priv->netdev;
691         struct ftgmac100_txdes *txdes;
692         struct sk_buff *skb;
693         dma_addr_t map;
694
695         if (priv->tx_pending == 0)
696                 return false;
697
698         txdes = ftgmac100_current_clean_txdes(priv);
699
700         if (ftgmac100_txdes_owned_by_dma(txdes))
701                 return false;
702
703         skb = ftgmac100_txdes_get_skb(txdes);
704         map = ftgmac100_txdes_get_dma_addr(txdes);
705
706         netdev->stats.tx_packets++;
707         netdev->stats.tx_bytes += skb->len;
708
709         dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
710
711         dev_kfree_skb(skb);
712
713         ftgmac100_txdes_reset(priv, txdes);
714
715         ftgmac100_tx_clean_pointer_advance(priv);
716
717         spin_lock(&priv->tx_lock);
718         priv->tx_pending--;
719         spin_unlock(&priv->tx_lock);
720         netif_wake_queue(netdev);
721
722         return true;
723 }
724
725 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
726 {
727         while (ftgmac100_tx_complete_packet(priv))
728                 ;
729 }
730
731 static int ftgmac100_xmit(struct ftgmac100 *priv, struct sk_buff *skb,
732                           dma_addr_t map)
733 {
734         struct net_device *netdev = priv->netdev;
735         struct ftgmac100_txdes *txdes;
736         unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
737
738         txdes = ftgmac100_current_txdes(priv);
739         ftgmac100_tx_pointer_advance(priv);
740
741         /* setup TX descriptor */
742         ftgmac100_txdes_set_skb(txdes, skb);
743         ftgmac100_txdes_set_dma_addr(txdes, map);
744         ftgmac100_txdes_set_buffer_size(txdes, len);
745
746         ftgmac100_txdes_set_first_segment(txdes);
747         ftgmac100_txdes_set_last_segment(txdes);
748         ftgmac100_txdes_set_txint(txdes);
749         if (skb->ip_summed == CHECKSUM_PARTIAL) {
750                 __be16 protocol = skb->protocol;
751
752                 if (protocol == cpu_to_be16(ETH_P_IP)) {
753                         u8 ip_proto = ip_hdr(skb)->protocol;
754
755                         ftgmac100_txdes_set_ipcs(txdes);
756                         if (ip_proto == IPPROTO_TCP)
757                                 ftgmac100_txdes_set_tcpcs(txdes);
758                         else if (ip_proto == IPPROTO_UDP)
759                                 ftgmac100_txdes_set_udpcs(txdes);
760                 }
761         }
762
763         spin_lock(&priv->tx_lock);
764         priv->tx_pending++;
765         if (priv->tx_pending == TX_QUEUE_ENTRIES)
766                 netif_stop_queue(netdev);
767
768         /* start transmit */
769         ftgmac100_txdes_set_dma_own(txdes);
770         spin_unlock(&priv->tx_lock);
771
772         ftgmac100_txdma_normal_prio_start_polling(priv);
773
774         return NETDEV_TX_OK;
775 }
776
777 /******************************************************************************
778  * internal functions (buffer)
779  *****************************************************************************/
780 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
781                                    struct ftgmac100_rxdes *rxdes, gfp_t gfp)
782 {
783         struct net_device *netdev = priv->netdev;
784         struct page *page;
785         dma_addr_t map;
786
787         page = alloc_page(gfp);
788         if (!page) {
789                 if (net_ratelimit())
790                         netdev_err(netdev, "failed to allocate rx page\n");
791                 return -ENOMEM;
792         }
793
794         map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE);
795         if (unlikely(dma_mapping_error(priv->dev, map))) {
796                 if (net_ratelimit())
797                         netdev_err(netdev, "failed to map rx page\n");
798                 __free_page(page);
799                 return -ENOMEM;
800         }
801
802         ftgmac100_rxdes_set_page(priv, rxdes, page);
803         ftgmac100_rxdes_set_dma_addr(rxdes, map);
804         ftgmac100_rxdes_set_dma_own(priv, rxdes);
805         return 0;
806 }
807
808 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
809 {
810         int i;
811
812         for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
813                 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
814                 struct page *page = ftgmac100_rxdes_get_page(priv, rxdes);
815                 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes);
816
817                 if (!page)
818                         continue;
819
820                 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
821                 __free_page(page);
822         }
823
824         for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
825                 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i];
826                 struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes);
827                 dma_addr_t map = ftgmac100_txdes_get_dma_addr(txdes);
828
829                 if (!skb)
830                         continue;
831
832                 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
833                 kfree_skb(skb);
834         }
835
836         dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs),
837                           priv->descs, priv->descs_dma_addr);
838 }
839
840 static int ftgmac100_alloc_buffers(struct ftgmac100 *priv)
841 {
842         int i;
843
844         priv->descs = dma_zalloc_coherent(priv->dev,
845                                           sizeof(struct ftgmac100_descs),
846                                           &priv->descs_dma_addr, GFP_KERNEL);
847         if (!priv->descs)
848                 return -ENOMEM;
849
850         /* initialize RX ring */
851         ftgmac100_rxdes_set_end_of_ring(priv,
852                                         &priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]);
853
854         for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
855                 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
856
857                 if (ftgmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL))
858                         goto err;
859         }
860
861         /* initialize TX ring */
862         ftgmac100_txdes_set_end_of_ring(priv,
863                                         &priv->descs->txdes[TX_QUEUE_ENTRIES - 1]);
864         return 0;
865
866 err:
867         ftgmac100_free_buffers(priv);
868         return -ENOMEM;
869 }
870
871 /******************************************************************************
872  * internal functions (mdio)
873  *****************************************************************************/
874 static void ftgmac100_adjust_link(struct net_device *netdev)
875 {
876         struct ftgmac100 *priv = netdev_priv(netdev);
877         struct phy_device *phydev = netdev->phydev;
878         int ier;
879
880         if (phydev->speed == priv->old_speed)
881                 return;
882
883         priv->old_speed = phydev->speed;
884
885         ier = ioread32(priv->base + FTGMAC100_OFFSET_IER);
886
887         /* disable all interrupts */
888         iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
889
890         netif_stop_queue(netdev);
891         ftgmac100_stop_hw(priv);
892
893         netif_start_queue(netdev);
894         ftgmac100_init_hw(priv);
895         ftgmac100_start_hw(priv, phydev->speed);
896
897         /* re-enable interrupts */
898         iowrite32(ier, priv->base + FTGMAC100_OFFSET_IER);
899 }
900
901 static int ftgmac100_mii_probe(struct ftgmac100 *priv)
902 {
903         struct net_device *netdev = priv->netdev;
904         struct phy_device *phydev;
905
906         phydev = phy_find_first(priv->mii_bus);
907         if (!phydev) {
908                 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
909                 return -ENODEV;
910         }
911
912         phydev = phy_connect(netdev, phydev_name(phydev),
913                              &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII);
914
915         if (IS_ERR(phydev)) {
916                 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
917                 return PTR_ERR(phydev);
918         }
919
920         return 0;
921 }
922
923 /******************************************************************************
924  * struct mii_bus functions
925  *****************************************************************************/
926 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
927 {
928         struct net_device *netdev = bus->priv;
929         struct ftgmac100 *priv = netdev_priv(netdev);
930         unsigned int phycr;
931         int i;
932
933         phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
934
935         /* preserve MDC cycle threshold */
936         phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
937
938         phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
939                  FTGMAC100_PHYCR_REGAD(regnum) |
940                  FTGMAC100_PHYCR_MIIRD;
941
942         iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
943
944         for (i = 0; i < 10; i++) {
945                 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
946
947                 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
948                         int data;
949
950                         data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
951                         return FTGMAC100_PHYDATA_MIIRDATA(data);
952                 }
953
954                 udelay(100);
955         }
956
957         netdev_err(netdev, "mdio read timed out\n");
958         return -EIO;
959 }
960
961 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
962                                    int regnum, u16 value)
963 {
964         struct net_device *netdev = bus->priv;
965         struct ftgmac100 *priv = netdev_priv(netdev);
966         unsigned int phycr;
967         int data;
968         int i;
969
970         phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
971
972         /* preserve MDC cycle threshold */
973         phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
974
975         phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
976                  FTGMAC100_PHYCR_REGAD(regnum) |
977                  FTGMAC100_PHYCR_MIIWR;
978
979         data = FTGMAC100_PHYDATA_MIIWDATA(value);
980
981         iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
982         iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
983
984         for (i = 0; i < 10; i++) {
985                 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
986
987                 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
988                         return 0;
989
990                 udelay(100);
991         }
992
993         netdev_err(netdev, "mdio write timed out\n");
994         return -EIO;
995 }
996
997 /******************************************************************************
998  * struct ethtool_ops functions
999  *****************************************************************************/
1000 static void ftgmac100_get_drvinfo(struct net_device *netdev,
1001                                   struct ethtool_drvinfo *info)
1002 {
1003         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1004         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1005         strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
1006 }
1007
1008 static const struct ethtool_ops ftgmac100_ethtool_ops = {
1009         .get_drvinfo            = ftgmac100_get_drvinfo,
1010         .get_link               = ethtool_op_get_link,
1011         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1012         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1013 };
1014
1015 /******************************************************************************
1016  * interrupt handler
1017  *****************************************************************************/
1018 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
1019 {
1020         struct net_device *netdev = dev_id;
1021         struct ftgmac100 *priv = netdev_priv(netdev);
1022
1023         /* When running in NCSI mode, the interface should be ready for
1024          * receiving or transmitting NCSI packets before it's opened.
1025          */
1026         if (likely(priv->use_ncsi || netif_running(netdev))) {
1027                 /* Disable interrupts for polling */
1028                 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1029                 napi_schedule(&priv->napi);
1030         }
1031
1032         return IRQ_HANDLED;
1033 }
1034
1035 /******************************************************************************
1036  * struct napi_struct functions
1037  *****************************************************************************/
1038 static int ftgmac100_poll(struct napi_struct *napi, int budget)
1039 {
1040         struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1041         struct net_device *netdev = priv->netdev;
1042         unsigned int status;
1043         bool completed = true;
1044         int rx = 0;
1045
1046         status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1047         iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1048
1049         if (status & (FTGMAC100_INT_RPKT_BUF | FTGMAC100_INT_NO_RXBUF)) {
1050                 /*
1051                  * FTGMAC100_INT_RPKT_BUF:
1052                  *      RX DMA has received packets into RX buffer successfully
1053                  *
1054                  * FTGMAC100_INT_NO_RXBUF:
1055                  *      RX buffer unavailable
1056                  */
1057                 bool retry;
1058
1059                 do {
1060                         retry = ftgmac100_rx_packet(priv, &rx);
1061                 } while (retry && rx < budget);
1062
1063                 if (retry && rx == budget)
1064                         completed = false;
1065         }
1066
1067         if (status & (FTGMAC100_INT_XPKT_ETH | FTGMAC100_INT_XPKT_LOST)) {
1068                 /*
1069                  * FTGMAC100_INT_XPKT_ETH:
1070                  *      packet transmitted to ethernet successfully
1071                  *
1072                  * FTGMAC100_INT_XPKT_LOST:
1073                  *      packet transmitted to ethernet lost due to late
1074                  *      collision or excessive collision
1075                  */
1076                 ftgmac100_tx_complete(priv);
1077         }
1078
1079         if (status & priv->int_mask_all & (FTGMAC100_INT_NO_RXBUF |
1080                         FTGMAC100_INT_RPKT_LOST | FTGMAC100_INT_AHB_ERR)) {
1081                 if (net_ratelimit())
1082                         netdev_info(netdev, "[ISR] = 0x%x: %s%s%s\n", status,
1083                                     status & FTGMAC100_INT_NO_RXBUF ? "NO_RXBUF " : "",
1084                                     status & FTGMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "",
1085                                     status & FTGMAC100_INT_AHB_ERR ? "AHB_ERR " : "");
1086
1087                 if (status & FTGMAC100_INT_NO_RXBUF) {
1088                         /* RX buffer unavailable */
1089                         netdev->stats.rx_over_errors++;
1090                 }
1091
1092                 if (status & FTGMAC100_INT_RPKT_LOST) {
1093                         /* received packet lost due to RX FIFO full */
1094                         netdev->stats.rx_fifo_errors++;
1095                 }
1096         }
1097
1098         if (completed) {
1099                 napi_complete(napi);
1100
1101                 /* enable all interrupts */
1102                 iowrite32(priv->int_mask_all,
1103                           priv->base + FTGMAC100_OFFSET_IER);
1104         }
1105
1106         return rx;
1107 }
1108
1109 /******************************************************************************
1110  * struct net_device_ops functions
1111  *****************************************************************************/
1112 static int ftgmac100_open(struct net_device *netdev)
1113 {
1114         struct ftgmac100 *priv = netdev_priv(netdev);
1115         unsigned int status;
1116         int err;
1117
1118         err = ftgmac100_alloc_buffers(priv);
1119         if (err) {
1120                 netdev_err(netdev, "failed to allocate buffers\n");
1121                 goto err_alloc;
1122         }
1123
1124         err = request_irq(priv->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1125         if (err) {
1126                 netdev_err(netdev, "failed to request irq %d\n", priv->irq);
1127                 goto err_irq;
1128         }
1129
1130         priv->rx_pointer = 0;
1131         priv->tx_clean_pointer = 0;
1132         priv->tx_pointer = 0;
1133         priv->tx_pending = 0;
1134
1135         err = ftgmac100_reset_hw(priv);
1136         if (err)
1137                 goto err_hw;
1138
1139         ftgmac100_init_hw(priv);
1140         ftgmac100_start_hw(priv, priv->use_ncsi ? 100 : 10);
1141
1142         /* Clear stale interrupts */
1143         status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1144         iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1145
1146         if (netdev->phydev)
1147                 phy_start(netdev->phydev);
1148         else if (priv->use_ncsi)
1149                 netif_carrier_on(netdev);
1150
1151         napi_enable(&priv->napi);
1152         netif_start_queue(netdev);
1153
1154         /* enable all interrupts */
1155         iowrite32(priv->int_mask_all, priv->base + FTGMAC100_OFFSET_IER);
1156
1157         /* Start the NCSI device */
1158         if (priv->use_ncsi) {
1159                 err = ncsi_start_dev(priv->ndev);
1160                 if (err)
1161                         goto err_ncsi;
1162         }
1163
1164         priv->enabled = true;
1165
1166         return 0;
1167
1168 err_ncsi:
1169         napi_disable(&priv->napi);
1170         netif_stop_queue(netdev);
1171         iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1172 err_hw:
1173         free_irq(priv->irq, netdev);
1174 err_irq:
1175         ftgmac100_free_buffers(priv);
1176 err_alloc:
1177         return err;
1178 }
1179
1180 static int ftgmac100_stop(struct net_device *netdev)
1181 {
1182         struct ftgmac100 *priv = netdev_priv(netdev);
1183
1184         if (!priv->enabled)
1185                 return 0;
1186
1187         /* disable all interrupts */
1188         priv->enabled = false;
1189         iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1190
1191         netif_stop_queue(netdev);
1192         napi_disable(&priv->napi);
1193         if (netdev->phydev)
1194                 phy_stop(netdev->phydev);
1195         else if (priv->use_ncsi)
1196                 ncsi_stop_dev(priv->ndev);
1197
1198         ftgmac100_stop_hw(priv);
1199         free_irq(priv->irq, netdev);
1200         ftgmac100_free_buffers(priv);
1201
1202         return 0;
1203 }
1204
1205 static int ftgmac100_hard_start_xmit(struct sk_buff *skb,
1206                                      struct net_device *netdev)
1207 {
1208         struct ftgmac100 *priv = netdev_priv(netdev);
1209         dma_addr_t map;
1210
1211         if (unlikely(skb->len > MAX_PKT_SIZE)) {
1212                 if (net_ratelimit())
1213                         netdev_dbg(netdev, "tx packet too big\n");
1214
1215                 netdev->stats.tx_dropped++;
1216                 kfree_skb(skb);
1217                 return NETDEV_TX_OK;
1218         }
1219
1220         map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
1221         if (unlikely(dma_mapping_error(priv->dev, map))) {
1222                 /* drop packet */
1223                 if (net_ratelimit())
1224                         netdev_err(netdev, "map socket buffer failed\n");
1225
1226                 netdev->stats.tx_dropped++;
1227                 kfree_skb(skb);
1228                 return NETDEV_TX_OK;
1229         }
1230
1231         return ftgmac100_xmit(priv, skb, map);
1232 }
1233
1234 /* optional */
1235 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1236 {
1237         if (!netdev->phydev)
1238                 return -ENXIO;
1239
1240         return phy_mii_ioctl(netdev->phydev, ifr, cmd);
1241 }
1242
1243 static const struct net_device_ops ftgmac100_netdev_ops = {
1244         .ndo_open               = ftgmac100_open,
1245         .ndo_stop               = ftgmac100_stop,
1246         .ndo_start_xmit         = ftgmac100_hard_start_xmit,
1247         .ndo_set_mac_address    = ftgmac100_set_mac_addr,
1248         .ndo_validate_addr      = eth_validate_addr,
1249         .ndo_do_ioctl           = ftgmac100_do_ioctl,
1250 };
1251
1252 static int ftgmac100_setup_mdio(struct net_device *netdev)
1253 {
1254         struct ftgmac100 *priv = netdev_priv(netdev);
1255         struct platform_device *pdev = to_platform_device(priv->dev);
1256         int i, err = 0;
1257         u32 reg;
1258
1259         /* initialize mdio bus */
1260         priv->mii_bus = mdiobus_alloc();
1261         if (!priv->mii_bus)
1262                 return -EIO;
1263
1264         if (of_machine_is_compatible("aspeed,ast2400") ||
1265             of_machine_is_compatible("aspeed,ast2500")) {
1266                 /* This driver supports the old MDIO interface */
1267                 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1268                 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1269                 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1270         };
1271
1272         priv->mii_bus->name = "ftgmac100_mdio";
1273         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1274                  pdev->name, pdev->id);
1275         priv->mii_bus->priv = priv->netdev;
1276         priv->mii_bus->read = ftgmac100_mdiobus_read;
1277         priv->mii_bus->write = ftgmac100_mdiobus_write;
1278
1279         for (i = 0; i < PHY_MAX_ADDR; i++)
1280                 priv->mii_bus->irq[i] = PHY_POLL;
1281
1282         err = mdiobus_register(priv->mii_bus);
1283         if (err) {
1284                 dev_err(priv->dev, "Cannot register MDIO bus!\n");
1285                 goto err_register_mdiobus;
1286         }
1287
1288         err = ftgmac100_mii_probe(priv);
1289         if (err) {
1290                 dev_err(priv->dev, "MII Probe failed!\n");
1291                 goto err_mii_probe;
1292         }
1293
1294         return 0;
1295
1296 err_mii_probe:
1297         mdiobus_unregister(priv->mii_bus);
1298 err_register_mdiobus:
1299         mdiobus_free(priv->mii_bus);
1300         return err;
1301 }
1302
1303 static void ftgmac100_destroy_mdio(struct net_device *netdev)
1304 {
1305         struct ftgmac100 *priv = netdev_priv(netdev);
1306
1307         if (!netdev->phydev)
1308                 return;
1309
1310         phy_disconnect(netdev->phydev);
1311         mdiobus_unregister(priv->mii_bus);
1312         mdiobus_free(priv->mii_bus);
1313 }
1314
1315 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1316 {
1317         if (unlikely(nd->state != ncsi_dev_state_functional))
1318                 return;
1319
1320         netdev_info(nd->dev, "NCSI interface %s\n",
1321                     nd->link_up ? "up" : "down");
1322 }
1323
1324 /******************************************************************************
1325  * struct platform_driver functions
1326  *****************************************************************************/
1327 static int ftgmac100_probe(struct platform_device *pdev)
1328 {
1329         struct resource *res;
1330         int irq;
1331         struct net_device *netdev;
1332         struct ftgmac100 *priv;
1333         int err = 0;
1334
1335         if (!pdev)
1336                 return -ENODEV;
1337
1338         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1339         if (!res)
1340                 return -ENXIO;
1341
1342         irq = platform_get_irq(pdev, 0);
1343         if (irq < 0)
1344                 return irq;
1345
1346         /* setup net_device */
1347         netdev = alloc_etherdev(sizeof(*priv));
1348         if (!netdev) {
1349                 err = -ENOMEM;
1350                 goto err_alloc_etherdev;
1351         }
1352
1353         SET_NETDEV_DEV(netdev, &pdev->dev);
1354
1355         netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1356         netdev->netdev_ops = &ftgmac100_netdev_ops;
1357
1358         platform_set_drvdata(pdev, netdev);
1359
1360         /* setup private data */
1361         priv = netdev_priv(netdev);
1362         priv->netdev = netdev;
1363         priv->dev = &pdev->dev;
1364
1365         spin_lock_init(&priv->tx_lock);
1366
1367         /* initialize NAPI */
1368         netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1369
1370         /* map io memory */
1371         priv->res = request_mem_region(res->start, resource_size(res),
1372                                        dev_name(&pdev->dev));
1373         if (!priv->res) {
1374                 dev_err(&pdev->dev, "Could not reserve memory region\n");
1375                 err = -ENOMEM;
1376                 goto err_req_mem;
1377         }
1378
1379         priv->base = ioremap(res->start, resource_size(res));
1380         if (!priv->base) {
1381                 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1382                 err = -EIO;
1383                 goto err_ioremap;
1384         }
1385
1386         priv->irq = irq;
1387
1388         /* MAC address from chip or random one */
1389         ftgmac100_setup_mac(priv);
1390
1391         priv->int_mask_all = (FTGMAC100_INT_RPKT_LOST |
1392                               FTGMAC100_INT_XPKT_ETH |
1393                               FTGMAC100_INT_XPKT_LOST |
1394                               FTGMAC100_INT_AHB_ERR |
1395                               FTGMAC100_INT_RPKT_BUF |
1396                               FTGMAC100_INT_NO_RXBUF);
1397
1398         if (of_machine_is_compatible("aspeed,ast2400") ||
1399             of_machine_is_compatible("aspeed,ast2500")) {
1400                 priv->rxdes0_edorr_mask = BIT(30);
1401                 priv->txdes0_edotr_mask = BIT(30);
1402         } else {
1403                 priv->rxdes0_edorr_mask = BIT(15);
1404                 priv->txdes0_edotr_mask = BIT(15);
1405         }
1406
1407         if (pdev->dev.of_node &&
1408             of_get_property(pdev->dev.of_node, "use-ncsi", NULL)) {
1409                 if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1410                         dev_err(&pdev->dev, "NCSI stack not enabled\n");
1411                         goto err_ncsi_dev;
1412                 }
1413
1414                 dev_info(&pdev->dev, "Using NCSI interface\n");
1415                 priv->use_ncsi = true;
1416                 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1417                 if (!priv->ndev)
1418                         goto err_ncsi_dev;
1419         } else {
1420                 priv->use_ncsi = false;
1421                 err = ftgmac100_setup_mdio(netdev);
1422                 if (err)
1423                         goto err_setup_mdio;
1424         }
1425
1426         /* We have to disable on-chip IP checksum functionality
1427          * when NCSI is enabled on the interface. It doesn't work
1428          * in that case.
1429          */
1430         netdev->features = NETIF_F_IP_CSUM | NETIF_F_GRO;
1431         if (priv->use_ncsi &&
1432             of_get_property(pdev->dev.of_node, "no-hw-checksum", NULL))
1433                 netdev->features &= ~NETIF_F_IP_CSUM;
1434
1435
1436         /* register network device */
1437         err = register_netdev(netdev);
1438         if (err) {
1439                 dev_err(&pdev->dev, "Failed to register netdev\n");
1440                 goto err_register_netdev;
1441         }
1442
1443         netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base);
1444
1445         return 0;
1446
1447 err_ncsi_dev:
1448 err_register_netdev:
1449         ftgmac100_destroy_mdio(netdev);
1450 err_setup_mdio:
1451         iounmap(priv->base);
1452 err_ioremap:
1453         release_resource(priv->res);
1454 err_req_mem:
1455         netif_napi_del(&priv->napi);
1456         free_netdev(netdev);
1457 err_alloc_etherdev:
1458         return err;
1459 }
1460
1461 static int ftgmac100_remove(struct platform_device *pdev)
1462 {
1463         struct net_device *netdev;
1464         struct ftgmac100 *priv;
1465
1466         netdev = platform_get_drvdata(pdev);
1467         priv = netdev_priv(netdev);
1468
1469         unregister_netdev(netdev);
1470         ftgmac100_destroy_mdio(netdev);
1471
1472         iounmap(priv->base);
1473         release_resource(priv->res);
1474
1475         netif_napi_del(&priv->napi);
1476         free_netdev(netdev);
1477         return 0;
1478 }
1479
1480 static const struct of_device_id ftgmac100_of_match[] = {
1481         { .compatible = "faraday,ftgmac100" },
1482         { }
1483 };
1484 MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
1485
1486 static struct platform_driver ftgmac100_driver = {
1487         .probe  = ftgmac100_probe,
1488         .remove = ftgmac100_remove,
1489         .driver = {
1490                 .name           = DRV_NAME,
1491                 .of_match_table = ftgmac100_of_match,
1492         },
1493 };
1494 module_platform_driver(ftgmac100_driver);
1495
1496 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1497 MODULE_DESCRIPTION("FTGMAC100 driver");
1498 MODULE_LICENSE("GPL");