2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2010 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 #define MYPF_BASE 0x1b000
39 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
41 #define PF0_BASE 0x1e000
42 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
44 #define PF_STRIDE 0x400
45 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
46 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
48 #define MYPORT_BASE 0x1c000
49 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
51 #define PORT0_BASE 0x20000
52 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
54 #define PORT_STRIDE 0x2000
55 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
56 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
58 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
59 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
61 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
62 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
63 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
64 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
66 #define SGE_PF_KDOORBELL 0x0
67 #define QID_MASK 0xffff8000U
69 #define QID(x) ((x) << QID_SHIFT)
70 #define DBPRIO(x) ((x) << 14)
71 #define DBTYPE(x) ((x) << 13)
72 #define PIDX_MASK 0x00003fffU
74 #define PIDX(x) ((x) << PIDX_SHIFT)
76 #define M_PIDX_T5 0x1fffU
77 #define PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
80 #define SGE_PF_GTS 0x4
81 #define INGRESSQID_MASK 0xffff0000U
82 #define INGRESSQID_SHIFT 16
83 #define INGRESSQID(x) ((x) << INGRESSQID_SHIFT)
84 #define TIMERREG_MASK 0x0000e000U
85 #define TIMERREG_SHIFT 13
86 #define TIMERREG(x) ((x) << TIMERREG_SHIFT)
87 #define SEINTARM_MASK 0x00001000U
88 #define SEINTARM_SHIFT 12
89 #define SEINTARM(x) ((x) << SEINTARM_SHIFT)
90 #define CIDXINC_MASK 0x00000fffU
91 #define CIDXINC_SHIFT 0
92 #define CIDXINC(x) ((x) << CIDXINC_SHIFT)
94 #define X_RXPKTCPLMODE_SPLIT 1
95 #define X_INGPADBOUNDARY_SHIFT 5
97 #define SGE_CONTROL 0x1008
98 #define DCASYSTYPE 0x00080000U
99 #define RXPKTCPLMODE_MASK 0x00040000U
100 #define RXPKTCPLMODE_SHIFT 18
101 #define RXPKTCPLMODE(x) ((x) << RXPKTCPLMODE_SHIFT)
102 #define EGRSTATUSPAGESIZE_MASK 0x00020000U
103 #define EGRSTATUSPAGESIZE_SHIFT 17
104 #define EGRSTATUSPAGESIZE(x) ((x) << EGRSTATUSPAGESIZE_SHIFT)
105 #define PKTSHIFT_MASK 0x00001c00U
106 #define PKTSHIFT_SHIFT 10
107 #define PKTSHIFT(x) ((x) << PKTSHIFT_SHIFT)
108 #define PKTSHIFT_GET(x) (((x) & PKTSHIFT_MASK) >> PKTSHIFT_SHIFT)
109 #define INGPCIEBOUNDARY_MASK 0x00000380U
110 #define INGPCIEBOUNDARY_SHIFT 7
111 #define INGPCIEBOUNDARY(x) ((x) << INGPCIEBOUNDARY_SHIFT)
112 #define INGPADBOUNDARY_MASK 0x00000070U
113 #define INGPADBOUNDARY_SHIFT 4
114 #define INGPADBOUNDARY(x) ((x) << INGPADBOUNDARY_SHIFT)
115 #define INGPADBOUNDARY_GET(x) (((x) & INGPADBOUNDARY_MASK) \
116 >> INGPADBOUNDARY_SHIFT)
117 #define EGRPCIEBOUNDARY_MASK 0x0000000eU
118 #define EGRPCIEBOUNDARY_SHIFT 1
119 #define EGRPCIEBOUNDARY(x) ((x) << EGRPCIEBOUNDARY_SHIFT)
120 #define GLOBALENABLE 0x00000001U
122 #define SGE_HOST_PAGE_SIZE 0x100c
124 #define HOSTPAGESIZEPF7_MASK 0x0000000fU
125 #define HOSTPAGESIZEPF7_SHIFT 28
126 #define HOSTPAGESIZEPF7(x) ((x) << HOSTPAGESIZEPF7_SHIFT)
128 #define HOSTPAGESIZEPF6_MASK 0x0000000fU
129 #define HOSTPAGESIZEPF6_SHIFT 24
130 #define HOSTPAGESIZEPF6(x) ((x) << HOSTPAGESIZEPF6_SHIFT)
132 #define HOSTPAGESIZEPF5_MASK 0x0000000fU
133 #define HOSTPAGESIZEPF5_SHIFT 20
134 #define HOSTPAGESIZEPF5(x) ((x) << HOSTPAGESIZEPF5_SHIFT)
136 #define HOSTPAGESIZEPF4_MASK 0x0000000fU
137 #define HOSTPAGESIZEPF4_SHIFT 16
138 #define HOSTPAGESIZEPF4(x) ((x) << HOSTPAGESIZEPF4_SHIFT)
140 #define HOSTPAGESIZEPF3_MASK 0x0000000fU
141 #define HOSTPAGESIZEPF3_SHIFT 12
142 #define HOSTPAGESIZEPF3(x) ((x) << HOSTPAGESIZEPF3_SHIFT)
144 #define HOSTPAGESIZEPF2_MASK 0x0000000fU
145 #define HOSTPAGESIZEPF2_SHIFT 8
146 #define HOSTPAGESIZEPF2(x) ((x) << HOSTPAGESIZEPF2_SHIFT)
148 #define HOSTPAGESIZEPF1_MASK 0x0000000fU
149 #define HOSTPAGESIZEPF1_SHIFT 4
150 #define HOSTPAGESIZEPF1(x) ((x) << HOSTPAGESIZEPF1_SHIFT)
152 #define HOSTPAGESIZEPF0_MASK 0x0000000fU
153 #define HOSTPAGESIZEPF0_SHIFT 0
154 #define HOSTPAGESIZEPF0(x) ((x) << HOSTPAGESIZEPF0_SHIFT)
156 #define SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
157 #define QUEUESPERPAGEPF0_MASK 0x0000000fU
158 #define QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK)
160 #define QUEUESPERPAGEPF1 4
162 #define SGE_INT_CAUSE1 0x1024
163 #define SGE_INT_CAUSE2 0x1030
164 #define SGE_INT_CAUSE3 0x103c
165 #define ERR_FLM_DBP 0x80000000U
166 #define ERR_FLM_IDMA1 0x40000000U
167 #define ERR_FLM_IDMA0 0x20000000U
168 #define ERR_FLM_HINT 0x10000000U
169 #define ERR_PCIE_ERROR3 0x08000000U
170 #define ERR_PCIE_ERROR2 0x04000000U
171 #define ERR_PCIE_ERROR1 0x02000000U
172 #define ERR_PCIE_ERROR0 0x01000000U
173 #define ERR_TIMER_ABOVE_MAX_QID 0x00800000U
174 #define ERR_CPL_EXCEED_IQE_SIZE 0x00400000U
175 #define ERR_INVALID_CIDX_INC 0x00200000U
176 #define ERR_ITP_TIME_PAUSED 0x00100000U
177 #define ERR_CPL_OPCODE_0 0x00080000U
178 #define ERR_DROPPED_DB 0x00040000U
179 #define ERR_DATA_CPL_ON_HIGH_QID1 0x00020000U
180 #define ERR_DATA_CPL_ON_HIGH_QID0 0x00010000U
181 #define ERR_BAD_DB_PIDX3 0x00008000U
182 #define ERR_BAD_DB_PIDX2 0x00004000U
183 #define ERR_BAD_DB_PIDX1 0x00002000U
184 #define ERR_BAD_DB_PIDX0 0x00001000U
185 #define ERR_ING_PCIE_CHAN 0x00000800U
186 #define ERR_ING_CTXT_PRIO 0x00000400U
187 #define ERR_EGR_CTXT_PRIO 0x00000200U
188 #define DBFIFO_HP_INT 0x00000100U
189 #define DBFIFO_LP_INT 0x00000080U
190 #define REG_ADDRESS_ERR 0x00000040U
191 #define INGRESS_SIZE_ERR 0x00000020U
192 #define EGRESS_SIZE_ERR 0x00000010U
193 #define ERR_INV_CTXT3 0x00000008U
194 #define ERR_INV_CTXT2 0x00000004U
195 #define ERR_INV_CTXT1 0x00000002U
196 #define ERR_INV_CTXT0 0x00000001U
198 #define SGE_INT_ENABLE3 0x1040
199 #define SGE_FL_BUFFER_SIZE0 0x1044
200 #define SGE_FL_BUFFER_SIZE1 0x1048
201 #define SGE_FL_BUFFER_SIZE2 0x104c
202 #define SGE_FL_BUFFER_SIZE3 0x1050
203 #define SGE_FL_BUFFER_SIZE4 0x1054
204 #define SGE_FL_BUFFER_SIZE5 0x1058
205 #define SGE_FL_BUFFER_SIZE6 0x105c
206 #define SGE_FL_BUFFER_SIZE7 0x1060
207 #define SGE_FL_BUFFER_SIZE8 0x1064
209 #define SGE_INGRESS_RX_THRESHOLD 0x10a0
210 #define THRESHOLD_0_MASK 0x3f000000U
211 #define THRESHOLD_0_SHIFT 24
212 #define THRESHOLD_0(x) ((x) << THRESHOLD_0_SHIFT)
213 #define THRESHOLD_0_GET(x) (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT)
214 #define THRESHOLD_1_MASK 0x003f0000U
215 #define THRESHOLD_1_SHIFT 16
216 #define THRESHOLD_1(x) ((x) << THRESHOLD_1_SHIFT)
217 #define THRESHOLD_1_GET(x) (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT)
218 #define THRESHOLD_2_MASK 0x00003f00U
219 #define THRESHOLD_2_SHIFT 8
220 #define THRESHOLD_2(x) ((x) << THRESHOLD_2_SHIFT)
221 #define THRESHOLD_2_GET(x) (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT)
222 #define THRESHOLD_3_MASK 0x0000003fU
223 #define THRESHOLD_3_SHIFT 0
224 #define THRESHOLD_3(x) ((x) << THRESHOLD_3_SHIFT)
225 #define THRESHOLD_3_GET(x) (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT)
227 #define SGE_CONM_CTRL 0x1094
228 #define EGRTHRESHOLD_MASK 0x00003f00U
229 #define EGRTHRESHOLDshift 8
230 #define EGRTHRESHOLD(x) ((x) << EGRTHRESHOLDshift)
231 #define EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift)
233 #define EGRTHRESHOLDPACKING_MASK 0x3fU
234 #define EGRTHRESHOLDPACKING_SHIFT 14
235 #define EGRTHRESHOLDPACKING(x) ((x) << EGRTHRESHOLDPACKING_SHIFT)
236 #define EGRTHRESHOLDPACKING_GET(x) (((x) >> EGRTHRESHOLDPACKING_SHIFT) & \
237 EGRTHRESHOLDPACKING_MASK)
239 #define SGE_DBFIFO_STATUS 0x10a4
240 #define HP_INT_THRESH_SHIFT 28
241 #define HP_INT_THRESH_MASK 0xfU
242 #define HP_INT_THRESH(x) ((x) << HP_INT_THRESH_SHIFT)
243 #define LP_INT_THRESH_SHIFT 12
244 #define LP_INT_THRESH_MASK 0xfU
245 #define LP_INT_THRESH(x) ((x) << LP_INT_THRESH_SHIFT)
247 #define SGE_DOORBELL_CONTROL 0x10a8
248 #define ENABLE_DROP (1 << 13)
250 #define S_NOCOALESCE 26
251 #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE)
252 #define F_NOCOALESCE V_NOCOALESCE(1U)
254 #define SGE_TIMER_VALUE_0_AND_1 0x10b8
255 #define TIMERVALUE0_MASK 0xffff0000U
256 #define TIMERVALUE0_SHIFT 16
257 #define TIMERVALUE0(x) ((x) << TIMERVALUE0_SHIFT)
258 #define TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT)
259 #define TIMERVALUE1_MASK 0x0000ffffU
260 #define TIMERVALUE1_SHIFT 0
261 #define TIMERVALUE1(x) ((x) << TIMERVALUE1_SHIFT)
262 #define TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT)
264 #define SGE_TIMER_VALUE_2_AND_3 0x10bc
265 #define TIMERVALUE2_MASK 0xffff0000U
266 #define TIMERVALUE2_SHIFT 16
267 #define TIMERVALUE2(x) ((x) << TIMERVALUE2_SHIFT)
268 #define TIMERVALUE2_GET(x) (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT)
269 #define TIMERVALUE3_MASK 0x0000ffffU
270 #define TIMERVALUE3_SHIFT 0
271 #define TIMERVALUE3(x) ((x) << TIMERVALUE3_SHIFT)
272 #define TIMERVALUE3_GET(x) (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT)
274 #define SGE_TIMER_VALUE_4_AND_5 0x10c0
275 #define TIMERVALUE4_MASK 0xffff0000U
276 #define TIMERVALUE4_SHIFT 16
277 #define TIMERVALUE4(x) ((x) << TIMERVALUE4_SHIFT)
278 #define TIMERVALUE4_GET(x) (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT)
279 #define TIMERVALUE5_MASK 0x0000ffffU
280 #define TIMERVALUE5_SHIFT 0
281 #define TIMERVALUE5(x) ((x) << TIMERVALUE5_SHIFT)
282 #define TIMERVALUE5_GET(x) (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT)
284 #define SGE_DEBUG_INDEX 0x10cc
285 #define SGE_DEBUG_DATA_HIGH 0x10d0
286 #define SGE_DEBUG_DATA_LOW 0x10d4
287 #define SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
288 #define SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
289 #define SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
290 #define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
292 #define S_HP_INT_THRESH 28
293 #define M_HP_INT_THRESH 0xfU
294 #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
295 #define S_LP_INT_THRESH_T5 18
296 #define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
297 #define M_LP_COUNT_T5 0x3ffffU
298 #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT) & M_LP_COUNT_T5)
299 #define M_HP_COUNT 0x7ffU
300 #define S_HP_COUNT 16
301 #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
302 #define S_LP_INT_THRESH 12
303 #define M_LP_INT_THRESH 0xfU
304 #define M_LP_INT_THRESH_T5 0xfffU
305 #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
306 #define M_LP_COUNT 0x7ffU
308 #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
309 #define A_SGE_DBFIFO_STATUS 0x10a4
311 #define SGE_STAT_TOTAL 0x10e4
312 #define SGE_STAT_MATCH 0x10e8
314 #define SGE_STAT_CFG 0x10ec
315 #define S_STATSOURCE_T5 9
316 #define STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
318 #define SGE_DBFIFO_STATUS2 0x1118
319 #define M_HP_COUNT_T5 0x3ffU
320 #define G_HP_COUNT_T5(x) ((x) & M_HP_COUNT_T5)
321 #define S_HP_INT_THRESH_T5 10
322 #define M_HP_INT_THRESH_T5 0xfU
323 #define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
325 #define S_ENABLE_DROP 13
326 #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
327 #define F_ENABLE_DROP V_ENABLE_DROP(1U)
328 #define S_DROPPED_DB 0
329 #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
330 #define F_DROPPED_DB V_DROPPED_DB(1U)
331 #define A_SGE_DOORBELL_CONTROL 0x10a8
333 #define A_SGE_CTXT_CMD 0x11fc
334 #define A_SGE_DBQ_CTXT_BADDR 0x1084
336 #define PCIE_PF_CFG 0x40
337 #define AIVEC(x) ((x) << 4)
338 #define AIVEC_MASK 0x3ffU
340 #define PCIE_PF_CLI 0x44
341 #define PCIE_INT_CAUSE 0x3004
342 #define UNXSPLCPLERR 0x20000000U
343 #define PCIEPINT 0x10000000U
344 #define PCIESINT 0x08000000U
345 #define RPLPERR 0x04000000U
346 #define RXWRPERR 0x02000000U
347 #define RXCPLPERR 0x01000000U
348 #define PIOTAGPERR 0x00800000U
349 #define MATAGPERR 0x00400000U
350 #define INTXCLRPERR 0x00200000U
351 #define FIDPERR 0x00100000U
352 #define CFGSNPPERR 0x00080000U
353 #define HRSPPERR 0x00040000U
354 #define HREQPERR 0x00020000U
355 #define HCNTPERR 0x00010000U
356 #define DRSPPERR 0x00008000U
357 #define DREQPERR 0x00004000U
358 #define DCNTPERR 0x00002000U
359 #define CRSPPERR 0x00001000U
360 #define CREQPERR 0x00000800U
361 #define CCNTPERR 0x00000400U
362 #define TARTAGPERR 0x00000200U
363 #define PIOREQPERR 0x00000100U
364 #define PIOCPLPERR 0x00000080U
365 #define MSIXDIPERR 0x00000040U
366 #define MSIXDATAPERR 0x00000020U
367 #define MSIXADDRHPERR 0x00000010U
368 #define MSIXADDRLPERR 0x00000008U
369 #define MSIDATAPERR 0x00000004U
370 #define MSIADDRHPERR 0x00000002U
371 #define MSIADDRLPERR 0x00000001U
373 #define READRSPERR 0x20000000U
374 #define TRGT1GRPPERR 0x10000000U
375 #define IPSOTPERR 0x08000000U
376 #define IPRXDATAGRPPERR 0x02000000U
377 #define IPRXHDRGRPPERR 0x01000000U
378 #define MAGRPPERR 0x00400000U
379 #define VFIDPERR 0x00200000U
380 #define HREQWRPERR 0x00010000U
381 #define DREQWRPERR 0x00002000U
382 #define MSTTAGQPERR 0x00000400U
383 #define PIOREQGRPPERR 0x00000100U
384 #define PIOCPLGRPPERR 0x00000080U
385 #define MSIXSTIPERR 0x00000004U
386 #define MSTTIMEOUTPERR 0x00000002U
387 #define MSTGRPPERR 0x00000001U
389 #define PCIE_NONFAT_ERR 0x3010
390 #define PCIE_MEM_ACCESS_BASE_WIN 0x3068
391 #define S_PCIEOFST 10
392 #define M_PCIEOFST 0x3fffffU
393 #define GET_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
394 #define PCIEOFST_MASK 0xfffffc00U
395 #define BIR_MASK 0x00000300U
397 #define BIR(x) ((x) << BIR_SHIFT)
398 #define WINDOW_MASK 0x000000ffU
399 #define WINDOW_SHIFT 0
400 #define WINDOW(x) ((x) << WINDOW_SHIFT)
401 #define PCIE_MEM_ACCESS_OFFSET 0x306c
404 #define V_PFNUM(x) ((x) << S_PFNUM)
406 #define PCIE_FW 0x30b8
407 #define PCIE_FW_ERR 0x80000000U
408 #define PCIE_FW_INIT 0x40000000U
409 #define PCIE_FW_HALT 0x20000000U
410 #define PCIE_FW_MASTER_VLD 0x00008000U
411 #define PCIE_FW_MASTER(x) ((x) << 12)
412 #define PCIE_FW_MASTER_MASK 0x7
413 #define PCIE_FW_MASTER_GET(x) (((x) >> 12) & PCIE_FW_MASTER_MASK)
415 #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
416 #define RNPP 0x80000000U
417 #define RPCP 0x20000000U
418 #define RCIP 0x08000000U
419 #define RCCP 0x04000000U
420 #define RFTP 0x00800000U
421 #define PTRP 0x00100000U
423 #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
424 #define TPCP 0x40000000U
425 #define TNPP 0x20000000U
426 #define TFTP 0x10000000U
427 #define TCAP 0x08000000U
428 #define TCIP 0x04000000U
429 #define RCAP 0x02000000U
430 #define PLUP 0x00800000U
431 #define PLDN 0x00400000U
432 #define OTDD 0x00200000U
433 #define GTRP 0x00100000U
434 #define RDPE 0x00040000U
435 #define TDCE 0x00020000U
436 #define TDUE 0x00010000U
438 #define MC_INT_CAUSE 0x7518
439 #define ECC_UE_INT_CAUSE 0x00000004U
440 #define ECC_CE_INT_CAUSE 0x00000002U
441 #define PERR_INT_CAUSE 0x00000001U
443 #define MC_ECC_STATUS 0x751c
444 #define ECC_CECNT_MASK 0xffff0000U
445 #define ECC_CECNT_SHIFT 16
446 #define ECC_CECNT(x) ((x) << ECC_CECNT_SHIFT)
447 #define ECC_CECNT_GET(x) (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT)
448 #define ECC_UECNT_MASK 0x0000ffffU
449 #define ECC_UECNT_SHIFT 0
450 #define ECC_UECNT(x) ((x) << ECC_UECNT_SHIFT)
451 #define ECC_UECNT_GET(x) (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT)
453 #define MC_BIST_CMD 0x7600
454 #define START_BIST 0x80000000U
455 #define BIST_CMD_GAP_MASK 0x0000ff00U
456 #define BIST_CMD_GAP_SHIFT 8
457 #define BIST_CMD_GAP(x) ((x) << BIST_CMD_GAP_SHIFT)
458 #define BIST_OPCODE_MASK 0x00000003U
459 #define BIST_OPCODE_SHIFT 0
460 #define BIST_OPCODE(x) ((x) << BIST_OPCODE_SHIFT)
462 #define MC_BIST_CMD_ADDR 0x7604
463 #define MC_BIST_CMD_LEN 0x7608
464 #define MC_BIST_DATA_PATTERN 0x760c
465 #define BIST_DATA_TYPE_MASK 0x0000000fU
466 #define BIST_DATA_TYPE_SHIFT 0
467 #define BIST_DATA_TYPE(x) ((x) << BIST_DATA_TYPE_SHIFT)
469 #define MC_BIST_STATUS_RDATA 0x7688
471 #define MA_EDRAM0_BAR 0x77c0
472 #define MA_EDRAM1_BAR 0x77c4
473 #define EDRAM_SIZE_MASK 0xfffU
474 #define EDRAM_SIZE_GET(x) ((x) & EDRAM_SIZE_MASK)
476 #define MA_EXT_MEMORY_BAR 0x77c8
477 #define EXT_MEM_SIZE_MASK 0x00000fffU
478 #define EXT_MEM_SIZE_SHIFT 0
479 #define EXT_MEM_SIZE_GET(x) (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT)
481 #define MA_TARGET_MEM_ENABLE 0x77d8
482 #define EXT_MEM1_ENABLE 0x00000010U
483 #define EXT_MEM_ENABLE 0x00000004U
484 #define EDRAM1_ENABLE 0x00000002U
485 #define EDRAM0_ENABLE 0x00000001U
487 #define MA_INT_CAUSE 0x77e0
488 #define MEM_PERR_INT_CAUSE 0x00000002U
489 #define MEM_WRAP_INT_CAUSE 0x00000001U
491 #define MA_INT_WRAP_STATUS 0x77e4
492 #define MEM_WRAP_ADDRESS_MASK 0xfffffff0U
493 #define MEM_WRAP_ADDRESS_SHIFT 4
494 #define MEM_WRAP_ADDRESS_GET(x) (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT)
495 #define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU
496 #define MEM_WRAP_CLIENT_NUM_SHIFT 0
497 #define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT)
498 #define MA_PCIE_FW 0x30b8
499 #define MA_PARITY_ERROR_STATUS 0x77f4
501 #define MA_EXT_MEMORY1_BAR 0x7808
502 #define EDC_0_BASE_ADDR 0x7900
504 #define EDC_BIST_CMD 0x7904
505 #define EDC_BIST_CMD_ADDR 0x7908
506 #define EDC_BIST_CMD_LEN 0x790c
507 #define EDC_BIST_DATA_PATTERN 0x7910
508 #define EDC_BIST_STATUS_RDATA 0x7928
509 #define EDC_INT_CAUSE 0x7978
510 #define ECC_UE_PAR 0x00000020U
511 #define ECC_CE_PAR 0x00000010U
512 #define PERR_PAR_CAUSE 0x00000008U
514 #define EDC_ECC_STATUS 0x797c
516 #define EDC_1_BASE_ADDR 0x7980
518 #define CIM_BOOT_CFG 0x7b00
519 #define BOOTADDR_MASK 0xffffff00U
522 #define CIM_PF_MAILBOX_DATA 0x240
523 #define CIM_PF_MAILBOX_CTRL 0x280
524 #define MBMSGVALID 0x00000008U
525 #define MBINTREQ 0x00000004U
526 #define MBOWNER_MASK 0x00000003U
527 #define MBOWNER_SHIFT 0
528 #define MBOWNER(x) ((x) << MBOWNER_SHIFT)
529 #define MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT)
531 #define CIM_PF_HOST_INT_ENABLE 0x288
532 #define MBMSGRDYINTEN(x) ((x) << 19)
534 #define CIM_PF_HOST_INT_CAUSE 0x28c
535 #define MBMSGRDYINT 0x00080000U
537 #define CIM_HOST_INT_CAUSE 0x7b2c
538 #define TIEQOUTPARERRINT 0x00100000U
539 #define TIEQINPARERRINT 0x00080000U
540 #define MBHOSTPARERR 0x00040000U
541 #define MBUPPARERR 0x00020000U
542 #define IBQPARERR 0x0001f800U
543 #define IBQTP0PARERR 0x00010000U
544 #define IBQTP1PARERR 0x00008000U
545 #define IBQULPPARERR 0x00004000U
546 #define IBQSGELOPARERR 0x00002000U
547 #define IBQSGEHIPARERR 0x00001000U
548 #define IBQNCSIPARERR 0x00000800U
549 #define OBQPARERR 0x000007e0U
550 #define OBQULP0PARERR 0x00000400U
551 #define OBQULP1PARERR 0x00000200U
552 #define OBQULP2PARERR 0x00000100U
553 #define OBQULP3PARERR 0x00000080U
554 #define OBQSGEPARERR 0x00000040U
555 #define OBQNCSIPARERR 0x00000020U
556 #define PREFDROPINT 0x00000002U
557 #define UPACCNONZERO 0x00000001U
559 #define CIM_HOST_UPACC_INT_CAUSE 0x7b34
560 #define EEPROMWRINT 0x40000000U
561 #define TIMEOUTMAINT 0x20000000U
562 #define TIMEOUTINT 0x10000000U
563 #define RSPOVRLOOKUPINT 0x08000000U
564 #define REQOVRLOOKUPINT 0x04000000U
565 #define BLKWRPLINT 0x02000000U
566 #define BLKRDPLINT 0x01000000U
567 #define SGLWRPLINT 0x00800000U
568 #define SGLRDPLINT 0x00400000U
569 #define BLKWRCTLINT 0x00200000U
570 #define BLKRDCTLINT 0x00100000U
571 #define SGLWRCTLINT 0x00080000U
572 #define SGLRDCTLINT 0x00040000U
573 #define BLKWREEPROMINT 0x00020000U
574 #define BLKRDEEPROMINT 0x00010000U
575 #define SGLWREEPROMINT 0x00008000U
576 #define SGLRDEEPROMINT 0x00004000U
577 #define BLKWRFLASHINT 0x00002000U
578 #define BLKRDFLASHINT 0x00001000U
579 #define SGLWRFLASHINT 0x00000800U
580 #define SGLRDFLASHINT 0x00000400U
581 #define BLKWRBOOTINT 0x00000200U
582 #define BLKRDBOOTINT 0x00000100U
583 #define SGLWRBOOTINT 0x00000080U
584 #define SGLRDBOOTINT 0x00000040U
585 #define ILLWRBEINT 0x00000020U
586 #define ILLRDBEINT 0x00000010U
587 #define ILLRDINT 0x00000008U
588 #define ILLWRINT 0x00000004U
589 #define ILLTRANSINT 0x00000002U
590 #define RSVDSPACEINT 0x00000001U
592 #define TP_OUT_CONFIG 0x7d04
593 #define VLANEXTENABLE_MASK 0x0000f000U
594 #define VLANEXTENABLE_SHIFT 12
596 #define TP_GLOBAL_CONFIG 0x7d08
597 #define FIVETUPLELOOKUP_SHIFT 17
598 #define FIVETUPLELOOKUP_MASK 0x00060000U
599 #define FIVETUPLELOOKUP(x) ((x) << FIVETUPLELOOKUP_SHIFT)
600 #define FIVETUPLELOOKUP_GET(x) (((x) & FIVETUPLELOOKUP_MASK) >> \
601 FIVETUPLELOOKUP_SHIFT)
603 #define TP_PARA_REG2 0x7d68
604 #define MAXRXDATA_MASK 0xffff0000U
605 #define MAXRXDATA_SHIFT 16
606 #define MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT)
608 #define TP_TIMER_RESOLUTION 0x7d90
609 #define TIMERRESOLUTION_MASK 0x00ff0000U
610 #define TIMERRESOLUTION_SHIFT 16
611 #define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT)
612 #define DELAYEDACKRESOLUTION_MASK 0x000000ffU
613 #define DELAYEDACKRESOLUTION_SHIFT 0
614 #define DELAYEDACKRESOLUTION_GET(x) \
615 (((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT)
617 #define TP_SHIFT_CNT 0x7dc0
618 #define SYNSHIFTMAX_SHIFT 24
619 #define SYNSHIFTMAX_MASK 0xff000000U
620 #define SYNSHIFTMAX(x) ((x) << SYNSHIFTMAX_SHIFT)
621 #define SYNSHIFTMAX_GET(x) (((x) & SYNSHIFTMAX_MASK) >> \
623 #define RXTSHIFTMAXR1_SHIFT 20
624 #define RXTSHIFTMAXR1_MASK 0x00f00000U
625 #define RXTSHIFTMAXR1(x) ((x) << RXTSHIFTMAXR1_SHIFT)
626 #define RXTSHIFTMAXR1_GET(x) (((x) & RXTSHIFTMAXR1_MASK) >> \
628 #define RXTSHIFTMAXR2_SHIFT 16
629 #define RXTSHIFTMAXR2_MASK 0x000f0000U
630 #define RXTSHIFTMAXR2(x) ((x) << RXTSHIFTMAXR2_SHIFT)
631 #define RXTSHIFTMAXR2_GET(x) (((x) & RXTSHIFTMAXR2_MASK) >> \
633 #define PERSHIFTBACKOFFMAX_SHIFT 12
634 #define PERSHIFTBACKOFFMAX_MASK 0x0000f000U
635 #define PERSHIFTBACKOFFMAX(x) ((x) << PERSHIFTBACKOFFMAX_SHIFT)
636 #define PERSHIFTBACKOFFMAX_GET(x) (((x) & PERSHIFTBACKOFFMAX_MASK) >> \
637 PERSHIFTBACKOFFMAX_SHIFT)
638 #define PERSHIFTMAX_SHIFT 8
639 #define PERSHIFTMAX_MASK 0x00000f00U
640 #define PERSHIFTMAX(x) ((x) << PERSHIFTMAX_SHIFT)
641 #define PERSHIFTMAX_GET(x) (((x) & PERSHIFTMAX_MASK) >> \
643 #define KEEPALIVEMAXR1_SHIFT 4
644 #define KEEPALIVEMAXR1_MASK 0x000000f0U
645 #define KEEPALIVEMAXR1(x) ((x) << KEEPALIVEMAXR1_SHIFT)
646 #define KEEPALIVEMAXR1_GET(x) (((x) & KEEPALIVEMAXR1_MASK) >> \
647 KEEPALIVEMAXR1_SHIFT)
648 #define KEEPALIVEMAXR2_SHIFT 0
649 #define KEEPALIVEMAXR2_MASK 0x0000000fU
650 #define KEEPALIVEMAXR2(x) ((x) << KEEPALIVEMAXR2_SHIFT)
651 #define KEEPALIVEMAXR2_GET(x) (((x) & KEEPALIVEMAXR2_MASK) >> \
652 KEEPALIVEMAXR2_SHIFT)
654 #define TP_CCTRL_TABLE 0x7ddc
655 #define TP_MTU_TABLE 0x7de4
656 #define MTUINDEX_MASK 0xff000000U
657 #define MTUINDEX_SHIFT 24
658 #define MTUINDEX(x) ((x) << MTUINDEX_SHIFT)
659 #define MTUWIDTH_MASK 0x000f0000U
660 #define MTUWIDTH_SHIFT 16
661 #define MTUWIDTH(x) ((x) << MTUWIDTH_SHIFT)
662 #define MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT)
663 #define MTUVALUE_MASK 0x00003fffU
664 #define MTUVALUE_SHIFT 0
665 #define MTUVALUE(x) ((x) << MTUVALUE_SHIFT)
666 #define MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT)
668 #define TP_RSS_LKP_TABLE 0x7dec
669 #define LKPTBLROWVLD 0x80000000U
670 #define LKPTBLQUEUE1_MASK 0x000ffc00U
671 #define LKPTBLQUEUE1_SHIFT 10
672 #define LKPTBLQUEUE1(x) ((x) << LKPTBLQUEUE1_SHIFT)
673 #define LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT)
674 #define LKPTBLQUEUE0_MASK 0x000003ffU
675 #define LKPTBLQUEUE0_SHIFT 0
676 #define LKPTBLQUEUE0(x) ((x) << LKPTBLQUEUE0_SHIFT)
677 #define LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT)
679 #define TP_PIO_ADDR 0x7e40
680 #define TP_PIO_DATA 0x7e44
681 #define TP_MIB_INDEX 0x7e50
682 #define TP_MIB_DATA 0x7e54
683 #define TP_INT_CAUSE 0x7e74
684 #define FLMTXFLSTEMPTY 0x40000000U
686 #define TP_VLAN_PRI_MAP 0x140
687 #define FRAGMENTATION_SHIFT 9
688 #define FRAGMENTATION_MASK 0x00000200U
689 #define MPSHITTYPE_MASK 0x00000100U
690 #define MACMATCH_MASK 0x00000080U
691 #define ETHERTYPE_MASK 0x00000040U
692 #define PROTOCOL_MASK 0x00000020U
693 #define TOS_MASK 0x00000010U
694 #define VLAN_MASK 0x00000008U
695 #define VNIC_ID_MASK 0x00000004U
696 #define PORT_MASK 0x00000002U
698 #define FCOE_MASK 0x00000001U
700 #define TP_INGRESS_CONFIG 0x141
701 #define VNIC 0x00000800U
702 #define CSUM_HAS_PSEUDO_HDR 0x00000400U
703 #define RM_OVLAN 0x00000200U
704 #define LOOKUPEVERYPKT 0x00000100U
706 #define TP_MIB_MAC_IN_ERR_0 0x0
707 #define TP_MIB_TCP_OUT_RST 0xc
708 #define TP_MIB_TCP_IN_SEG_HI 0x10
709 #define TP_MIB_TCP_IN_SEG_LO 0x11
710 #define TP_MIB_TCP_OUT_SEG_HI 0x12
711 #define TP_MIB_TCP_OUT_SEG_LO 0x13
712 #define TP_MIB_TCP_RXT_SEG_HI 0x14
713 #define TP_MIB_TCP_RXT_SEG_LO 0x15
714 #define TP_MIB_TNL_CNG_DROP_0 0x18
715 #define TP_MIB_TCP_V6IN_ERR_0 0x28
716 #define TP_MIB_TCP_V6OUT_RST 0x2c
717 #define TP_MIB_OFD_ARP_DROP 0x36
718 #define TP_MIB_TNL_DROP_0 0x44
719 #define TP_MIB_OFD_VLN_DROP_0 0x58
721 #define ULP_TX_INT_CAUSE 0x8dcc
722 #define PBL_BOUND_ERR_CH3 0x80000000U
723 #define PBL_BOUND_ERR_CH2 0x40000000U
724 #define PBL_BOUND_ERR_CH1 0x20000000U
725 #define PBL_BOUND_ERR_CH0 0x10000000U
727 #define PM_RX_INT_CAUSE 0x8fdc
728 #define ZERO_E_CMD_ERROR 0x00400000U
729 #define PMRX_FRAMING_ERROR 0x003ffff0U
730 #define OCSPI_PAR_ERROR 0x00000008U
731 #define DB_OPTIONS_PAR_ERROR 0x00000004U
732 #define IESPI_PAR_ERROR 0x00000002U
733 #define E_PCMD_PAR_ERROR 0x00000001U
735 #define PM_TX_INT_CAUSE 0x8ffc
736 #define PCMD_LEN_OVFL0 0x80000000U
737 #define PCMD_LEN_OVFL1 0x40000000U
738 #define PCMD_LEN_OVFL2 0x20000000U
739 #define ZERO_C_CMD_ERROR 0x10000000U
740 #define PMTX_FRAMING_ERROR 0x0ffffff0U
741 #define OESPI_PAR_ERROR 0x00000008U
742 #define ICSPI_PAR_ERROR 0x00000002U
743 #define C_PCMD_PAR_ERROR 0x00000001U
745 #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
746 #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
747 #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
748 #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
749 #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
750 #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
751 #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
752 #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
753 #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
754 #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
755 #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
756 #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
757 #define MPS_PORT_STAT_TX_PORT_64B_L 0x430
758 #define MPS_PORT_STAT_TX_PORT_64B_H 0x434
759 #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
760 #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
761 #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
762 #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
763 #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
764 #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
765 #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
766 #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
767 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
768 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
769 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
770 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
771 #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
772 #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
773 #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
774 #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
775 #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
776 #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
777 #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
778 #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
779 #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
780 #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
781 #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
782 #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
783 #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
784 #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
785 #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
786 #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
787 #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
788 #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
789 #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
790 #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
791 #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
792 #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
793 #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
794 #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
795 #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
796 #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
797 #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
798 #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
799 #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
800 #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
801 #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
802 #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
803 #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
804 #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
805 #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
806 #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
807 #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
808 #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
809 #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
810 #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
811 #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
812 #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
813 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
814 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
815 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
816 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
817 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
818 #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
819 #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
820 #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
821 #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
822 #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
823 #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
824 #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
825 #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
826 #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
827 #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
828 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
829 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
830 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
831 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
832 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
833 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
834 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
835 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
836 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
837 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
838 #define MPS_PORT_STAT_RX_PORT_64B_L 0x590
839 #define MPS_PORT_STAT_RX_PORT_64B_H 0x594
840 #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
841 #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
842 #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
843 #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
844 #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
845 #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
846 #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
847 #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
848 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
849 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
850 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
851 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
852 #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
853 #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
854 #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
855 #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
856 #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
857 #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
858 #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
859 #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
860 #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
861 #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
862 #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
863 #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
864 #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
865 #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
866 #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
867 #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
868 #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
869 #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
870 #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
871 #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
872 #define MAC_PORT_CFG2 0x818
873 #define MAC_PORT_MAGIC_MACID_LO 0x824
874 #define MAC_PORT_MAGIC_MACID_HI 0x828
875 #define MAC_PORT_EPIO_DATA0 0x8c0
876 #define MAC_PORT_EPIO_DATA1 0x8c4
877 #define MAC_PORT_EPIO_DATA2 0x8c8
878 #define MAC_PORT_EPIO_DATA3 0x8cc
879 #define MAC_PORT_EPIO_OP 0x8d0
881 #define MPS_CMN_CTL 0x9000
882 #define NUMPORTS_MASK 0x00000003U
883 #define NUMPORTS_SHIFT 0
884 #define NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT)
886 #define MPS_INT_CAUSE 0x9008
887 #define STATINT 0x00000020U
888 #define TXINT 0x00000010U
889 #define RXINT 0x00000008U
890 #define TRCINT 0x00000004U
891 #define CLSINT 0x00000002U
892 #define PLINT 0x00000001U
894 #define MPS_TX_INT_CAUSE 0x9408
895 #define PORTERR 0x00010000U
896 #define FRMERR 0x00008000U
897 #define SECNTERR 0x00004000U
898 #define BUBBLE 0x00002000U
899 #define TXDESCFIFO 0x00001e00U
900 #define TXDATAFIFO 0x000001e0U
901 #define NCSIFIFO 0x00000010U
902 #define TPFIFO 0x0000000fU
904 #define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
905 #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
906 #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
908 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
909 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
910 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
911 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
912 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
913 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
914 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
915 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
916 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
917 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
918 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
919 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
920 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
921 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
922 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
923 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
924 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
925 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
926 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
927 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
928 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
929 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
930 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
931 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
932 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
933 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
934 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
935 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
936 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
937 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
938 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
939 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
940 #define MPS_TRC_CFG 0x9800
941 #define TRCFIFOEMPTY 0x00000010U
942 #define TRCIGNOREDROPINPUT 0x00000008U
943 #define TRCKEEPDUPLICATES 0x00000004U
944 #define TRCEN 0x00000002U
945 #define TRCMULTIFILTER 0x00000001U
947 #define MPS_TRC_RSS_CONTROL 0x9808
948 #define RSSCONTROL_MASK 0x00ff0000U
949 #define RSSCONTROL_SHIFT 16
950 #define RSSCONTROL(x) ((x) << RSSCONTROL_SHIFT)
951 #define QUEUENUMBER_MASK 0x0000ffffU
952 #define QUEUENUMBER_SHIFT 0
953 #define QUEUENUMBER(x) ((x) << QUEUENUMBER_SHIFT)
955 #define MPS_TRC_FILTER_MATCH_CTL_A 0x9810
956 #define TFINVERTMATCH 0x01000000U
957 #define TFPKTTOOLARGE 0x00800000U
958 #define TFEN 0x00400000U
959 #define TFPORT_MASK 0x003c0000U
960 #define TFPORT_SHIFT 18
961 #define TFPORT(x) ((x) << TFPORT_SHIFT)
962 #define TFPORT_GET(x) (((x) & TFPORT_MASK) >> TFPORT_SHIFT)
963 #define TFDROP 0x00020000U
964 #define TFSOPEOPERR 0x00010000U
965 #define TFLENGTH_MASK 0x00001f00U
966 #define TFLENGTH_SHIFT 8
967 #define TFLENGTH(x) ((x) << TFLENGTH_SHIFT)
968 #define TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT)
969 #define TFOFFSET_MASK 0x0000001fU
970 #define TFOFFSET_SHIFT 0
971 #define TFOFFSET(x) ((x) << TFOFFSET_SHIFT)
972 #define TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT)
974 #define MPS_TRC_FILTER_MATCH_CTL_B 0x9820
975 #define TFMINPKTSIZE_MASK 0x01ff0000U
976 #define TFMINPKTSIZE_SHIFT 16
977 #define TFMINPKTSIZE(x) ((x) << TFMINPKTSIZE_SHIFT)
978 #define TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT)
979 #define TFCAPTUREMAX_MASK 0x00003fffU
980 #define TFCAPTUREMAX_SHIFT 0
981 #define TFCAPTUREMAX(x) ((x) << TFCAPTUREMAX_SHIFT)
982 #define TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT)
984 #define MPS_TRC_INT_CAUSE 0x985c
985 #define MISCPERR 0x00000100U
986 #define PKTFIFO 0x000000f0U
987 #define FILTMEM 0x0000000fU
989 #define MPS_TRC_FILTER0_MATCH 0x9c00
990 #define MPS_TRC_FILTER0_DONT_CARE 0x9c80
991 #define MPS_TRC_FILTER1_MATCH 0x9d00
992 #define MPS_CLS_INT_CAUSE 0xd028
993 #define PLERRENB 0x00000008U
994 #define HASHSRAM 0x00000004U
995 #define MATCHTCAM 0x00000002U
996 #define MATCHSRAM 0x00000001U
998 #define MPS_RX_PERR_INT_CAUSE 0x11074
1000 #define CPL_INTR_CAUSE 0x19054
1001 #define CIM_OP_MAP_PERR 0x00000020U
1002 #define CIM_OVFL_ERROR 0x00000010U
1003 #define TP_FRAMING_ERROR 0x00000008U
1004 #define SGE_FRAMING_ERROR 0x00000004U
1005 #define CIM_FRAMING_ERROR 0x00000002U
1006 #define ZERO_SWITCH_ERROR 0x00000001U
1008 #define SMB_INT_CAUSE 0x19090
1009 #define MSTTXFIFOPARINT 0x00200000U
1010 #define MSTRXFIFOPARINT 0x00100000U
1011 #define SLVFIFOPARINT 0x00080000U
1013 #define ULP_RX_INT_CAUSE 0x19158
1014 #define ULP_RX_ISCSI_TAGMASK 0x19164
1015 #define ULP_RX_ISCSI_PSZ 0x19168
1016 #define HPZ3_MASK 0x0f000000U
1017 #define HPZ3_SHIFT 24
1018 #define HPZ3(x) ((x) << HPZ3_SHIFT)
1019 #define HPZ2_MASK 0x000f0000U
1020 #define HPZ2_SHIFT 16
1021 #define HPZ2(x) ((x) << HPZ2_SHIFT)
1022 #define HPZ1_MASK 0x00000f00U
1023 #define HPZ1_SHIFT 8
1024 #define HPZ1(x) ((x) << HPZ1_SHIFT)
1025 #define HPZ0_MASK 0x0000000fU
1026 #define HPZ0_SHIFT 0
1027 #define HPZ0(x) ((x) << HPZ0_SHIFT)
1029 #define ULP_RX_TDDP_PSZ 0x19178
1031 #define SF_DATA 0x193f8
1032 #define SF_OP 0x193fc
1033 #define SF_BUSY 0x80000000U
1034 #define SF_LOCK 0x00000010U
1035 #define SF_CONT 0x00000008U
1036 #define BYTECNT_MASK 0x00000006U
1037 #define BYTECNT_SHIFT 1
1038 #define BYTECNT(x) ((x) << BYTECNT_SHIFT)
1039 #define OP_WR 0x00000001U
1041 #define PL_PF_INT_CAUSE 0x3c0
1042 #define PFSW 0x00000008U
1043 #define PFSGE 0x00000004U
1044 #define PFCIM 0x00000002U
1045 #define PFMPS 0x00000001U
1047 #define PL_PF_INT_ENABLE 0x3c4
1048 #define PL_PF_CTL 0x3c8
1049 #define SWINT 0x00000001U
1051 #define PL_WHOAMI 0x19400
1052 #define SOURCEPF_MASK 0x00000700U
1053 #define SOURCEPF_SHIFT 8
1054 #define SOURCEPF(x) ((x) << SOURCEPF_SHIFT)
1055 #define SOURCEPF_GET(x) (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT)
1056 #define ISVF 0x00000080U
1057 #define VFID_MASK 0x0000007fU
1058 #define VFID_SHIFT 0
1059 #define VFID(x) ((x) << VFID_SHIFT)
1060 #define VFID_GET(x) (((x) & VFID_MASK) >> VFID_SHIFT)
1062 #define PL_INT_CAUSE 0x1940c
1063 #define ULP_TX 0x08000000U
1064 #define SGE 0x04000000U
1065 #define HMA 0x02000000U
1066 #define CPL_SWITCH 0x01000000U
1067 #define ULP_RX 0x00800000U
1068 #define PM_RX 0x00400000U
1069 #define PM_TX 0x00200000U
1070 #define MA 0x00100000U
1071 #define TP 0x00080000U
1072 #define LE 0x00040000U
1073 #define EDC1 0x00020000U
1074 #define EDC0 0x00010000U
1075 #define MC 0x00008000U
1076 #define PCIE 0x00004000U
1077 #define PMU 0x00002000U
1078 #define XGMAC_KR1 0x00001000U
1079 #define XGMAC_KR0 0x00000800U
1080 #define XGMAC1 0x00000400U
1081 #define XGMAC0 0x00000200U
1082 #define SMB 0x00000100U
1083 #define SF 0x00000080U
1084 #define PL 0x00000040U
1085 #define NCSI 0x00000020U
1086 #define MPS 0x00000010U
1087 #define MI 0x00000008U
1088 #define DBG 0x00000004U
1089 #define I2CM 0x00000002U
1090 #define CIM 0x00000001U
1092 #define PL_INT_ENABLE 0x19410
1093 #define PL_INT_MAP0 0x19414
1094 #define PL_RST 0x19428
1095 #define PIORST 0x00000002U
1096 #define PIORSTMODE 0x00000001U
1098 #define PL_PL_INT_CAUSE 0x19430
1099 #define FATALPERR 0x00000010U
1100 #define PERRVFID 0x00000001U
1102 #define PL_REV 0x1943c
1106 #define V_REV(x) ((x) << S_REV)
1107 #define G_REV(x) (((x) >> S_REV) & M_REV)
1109 #define LE_DB_CONFIG 0x19c04
1110 #define HASHEN 0x00100000U
1112 #define LE_DB_SERVER_INDEX 0x19c18
1113 #define LE_DB_ACT_CNT_IPV4 0x19c20
1114 #define LE_DB_ACT_CNT_IPV6 0x19c24
1116 #define LE_DB_INT_CAUSE 0x19c3c
1117 #define REQQPARERR 0x00010000U
1118 #define UNKNOWNCMD 0x00008000U
1119 #define PARITYERR 0x00000040U
1120 #define LIPMISS 0x00000020U
1121 #define LIP0 0x00000010U
1123 #define LE_DB_TID_HASHBASE 0x19df8
1125 #define NCSI_INT_CAUSE 0x1a0d8
1126 #define CIM_DM_PRTY_ERR 0x00000100U
1127 #define MPS_DM_PRTY_ERR 0x00000080U
1128 #define TXFIFO_PRTY_ERR 0x00000002U
1129 #define RXFIFO_PRTY_ERR 0x00000001U
1131 #define XGMAC_PORT_CFG2 0x1018
1132 #define PATEN 0x00040000U
1133 #define MAGICEN 0x00020000U
1135 #define XGMAC_PORT_MAGIC_MACID_LO 0x1024
1136 #define XGMAC_PORT_MAGIC_MACID_HI 0x1028
1138 #define XGMAC_PORT_EPIO_DATA0 0x10c0
1139 #define XGMAC_PORT_EPIO_DATA1 0x10c4
1140 #define XGMAC_PORT_EPIO_DATA2 0x10c8
1141 #define XGMAC_PORT_EPIO_DATA3 0x10cc
1142 #define XGMAC_PORT_EPIO_OP 0x10d0
1143 #define EPIOWR 0x00000100U
1144 #define ADDRESS_MASK 0x000000ffU
1145 #define ADDRESS_SHIFT 0
1146 #define ADDRESS(x) ((x) << ADDRESS_SHIFT)
1148 #define MAC_PORT_INT_CAUSE 0x8dc
1149 #define XGMAC_PORT_INT_CAUSE 0x10dc
1151 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
1153 #define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34
1155 #define S_TX_MOD_QUEUE_REQ_MAP 0
1156 #define M_TX_MOD_QUEUE_REQ_MAP 0xffffU
1157 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
1159 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30
1161 #define S_TX_MODQ_WEIGHT3 24
1162 #define M_TX_MODQ_WEIGHT3 0xffU
1163 #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3)
1165 #define S_TX_MODQ_WEIGHT2 16
1166 #define M_TX_MODQ_WEIGHT2 0xffU
1167 #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2)
1169 #define S_TX_MODQ_WEIGHT1 8
1170 #define M_TX_MODQ_WEIGHT1 0xffU
1171 #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1)
1173 #define S_TX_MODQ_WEIGHT0 0
1174 #define M_TX_MODQ_WEIGHT0 0xffU
1175 #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0)
1177 #define A_TP_TX_SCHED_HDR 0x23
1179 #define A_TP_TX_SCHED_FIFO 0x24
1181 #define A_TP_TX_SCHED_PCMD 0x25
1184 #define V_VNIC(x) ((x) << S_VNIC)
1185 #define F_VNIC V_VNIC(1U)
1187 #define S_FRAGMENTATION 9
1188 #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
1189 #define F_FRAGMENTATION V_FRAGMENTATION(1U)
1191 #define S_MPSHITTYPE 8
1192 #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
1193 #define F_MPSHITTYPE V_MPSHITTYPE(1U)
1195 #define S_MACMATCH 7
1196 #define V_MACMATCH(x) ((x) << S_MACMATCH)
1197 #define F_MACMATCH V_MACMATCH(1U)
1199 #define S_ETHERTYPE 6
1200 #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
1201 #define F_ETHERTYPE V_ETHERTYPE(1U)
1203 #define S_PROTOCOL 5
1204 #define V_PROTOCOL(x) ((x) << S_PROTOCOL)
1205 #define F_PROTOCOL V_PROTOCOL(1U)
1208 #define V_TOS(x) ((x) << S_TOS)
1209 #define F_TOS V_TOS(1U)
1212 #define V_VLAN(x) ((x) << S_VLAN)
1213 #define F_VLAN V_VLAN(1U)
1216 #define V_VNIC_ID(x) ((x) << S_VNIC_ID)
1217 #define F_VNIC_ID V_VNIC_ID(1U)
1220 #define V_PORT(x) ((x) << S_PORT)
1221 #define F_PORT V_PORT(1U)
1224 #define V_FCOE(x) ((x) << S_FCOE)
1225 #define F_FCOE V_FCOE(1U)
1227 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
1228 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
1230 #define T5_PORT0_BASE 0x30000
1231 #define T5_PORT_STRIDE 0x4000
1232 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
1233 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
1235 #define MC_0_BASE_ADDR 0x40000
1236 #define MC_1_BASE_ADDR 0x48000
1237 #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
1238 #define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
1240 #define MC_P_BIST_CMD 0x41400
1241 #define MC_P_BIST_CMD_ADDR 0x41404
1242 #define MC_P_BIST_CMD_LEN 0x41408
1243 #define MC_P_BIST_DATA_PATTERN 0x4140c
1244 #define MC_P_BIST_STATUS_RDATA 0x41488
1245 #define EDC_T50_BASE_ADDR 0x50000
1246 #define EDC_H_BIST_CMD 0x50004
1247 #define EDC_H_BIST_CMD_ADDR 0x50008
1248 #define EDC_H_BIST_CMD_LEN 0x5000c
1249 #define EDC_H_BIST_DATA_PATTERN 0x50010
1250 #define EDC_H_BIST_STATUS_RDATA 0x50028
1252 #define EDC_T51_BASE_ADDR 0x50800
1253 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
1254 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
1256 #define A_PL_VF_REV 0x4
1257 #define A_PL_VF_WHOAMI 0x0
1258 #define A_PL_VF_REVISION 0x8
1261 #define M_CHIPID 0xfU
1262 #define V_CHIPID(x) ((x) << S_CHIPID)
1263 #define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
1265 /* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
1266 * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP
1267 * selects for a particular field being present. These fields, when present
1268 * in the Compressed Filter Tuple, have the following widths in bits.
1272 #define W_FT_VNIC_ID 17
1273 #define W_FT_VLAN 17
1275 #define W_FT_PROTOCOL 8
1276 #define W_FT_ETHERTYPE 16
1277 #define W_FT_MACMATCH 9
1278 #define W_FT_MPSHITTYPE 3
1279 #define W_FT_FRAGMENTATION 1
1281 /* Some of the Compressed Filter Tuple fields have internal structure. These
1282 * bit shifts/masks describe those structures. All shifts are relative to the
1283 * base position of the fields within the Compressed Filter Tuple
1285 #define S_FT_VLAN_VLD 16
1286 #define V_FT_VLAN_VLD(x) ((x) << S_FT_VLAN_VLD)
1287 #define F_FT_VLAN_VLD V_FT_VLAN_VLD(1U)
1289 #define S_FT_VNID_ID_VF 0
1290 #define V_FT_VNID_ID_VF(x) ((x) << S_FT_VNID_ID_VF)
1292 #define S_FT_VNID_ID_PF 7
1293 #define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF)
1295 #define S_FT_VNID_ID_VLD 16
1296 #define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD)
1298 #endif /* __T4_REGS_H */