drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/delay.h>
  36 #include "cxgb4.h"
  37 #include "t4_regs.h"
  38 #include "t4_values.h"
  39 #include "t4fw_api.h"
  40 #include "t4fw_version.h"
  41
  42 /**
  43  *      t4_wait_op_done_val - wait until an operation is completed
  44  *      @adapter: the adapter performing the operation
  45  *      @reg: the register to check for completion
  46  *      @mask: a single-bit field within @reg that indicates completion
  47  *      @polarity: the value of the field when the operation is completed
  48  *      @attempts: number of check iterations
  49  *      @delay: delay in usecs between iterations
  50  *      @valp: where to store the value of the register at completion time
  51  *
  52  *      Wait until an operation is completed by checking a bit in a register
  53  *      up to @attempts times.  If @valp is not NULL the value of the register
  54  *      at the time it indicated completion is stored there.  Returns 0 if the
  55  *      operation completes and -EAGAIN otherwise.
  56  */
  57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  58                                int polarity, int attempts, int delay, u32 *valp)
  59 {
  60         while (1) {
  61                 u32 val = t4_read_reg(adapter, reg);
  62
  63                 if (!!(val & mask) == polarity) {
  64                         if (valp)
  65                                 *valp = val;
  66                         return 0;
  67                 }
  68                 if (--attempts == 0)
  69                         return -EAGAIN;
  70                 if (delay)
  71                         udelay(delay);
  72         }
  73 }
  74
  75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  76                                   int polarity, int attempts, int delay)
  77 {
  78         return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  79                                    delay, NULL);
  80 }
  81
  82 /**
  83  *      t4_set_reg_field - set a register field to a value
  84  *      @adapter: the adapter to program
  85  *      @addr: the register address
  86  *      @mask: specifies the portion of the register to modify
  87  *      @val: the new value for the register field
  88  *
  89  *      Sets a register field specified by the supplied mask to the
  90  *      given value.
  91  */
  92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  93                       u32 val)
  94 {
  95         u32 v = t4_read_reg(adapter, addr) & ~mask;
  96
  97         t4_write_reg(adapter, addr, v | val);
  98         (void) t4_read_reg(adapter, addr);      /* flush */
  99 }
 100
 101 /**
 102  *      t4_read_indirect - read indirectly addressed registers
 103  *      @adap: the adapter
 104  *      @addr_reg: register holding the indirect address
 105  *      @data_reg: register holding the value of the indirect register
 106  *      @vals: where the read register values are stored
 107  *      @nregs: how many indirect registers to read
 108  *      @start_idx: index of first indirect register to read
 109  *
 110  *      Reads registers that are accessed indirectly through an address/data
 111  *      register pair.
 112  */
 113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 114                              unsigned int data_reg, u32 *vals,
 115                              unsigned int nregs, unsigned int start_idx)
 116 {
 117         while (nregs--) {
 118                 t4_write_reg(adap, addr_reg, start_idx);
 119                 *vals++ = t4_read_reg(adap, data_reg);
 120                 start_idx++;
 121         }
 122 }
 123
 124 /**
 125  *      t4_write_indirect - write indirectly addressed registers
 126  *      @adap: the adapter
 127  *      @addr_reg: register holding the indirect addresses
 128  *      @data_reg: register holding the value for the indirect registers
 129  *      @vals: values to write
 130  *      @nregs: how many indirect registers to write
 131  *      @start_idx: address of first indirect register to write
 132  *
 133  *      Writes a sequential block of registers that are accessed indirectly
 134  *      through an address/data register pair.
 135  */
 136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 137                        unsigned int data_reg, const u32 *vals,
 138                        unsigned int nregs, unsigned int start_idx)
 139 {
 140         while (nregs--) {
 141                 t4_write_reg(adap, addr_reg, start_idx++);
 142                 t4_write_reg(adap, data_reg, *vals++);
 143         }
 144 }
 145
 146 /*
 147  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
 148  * mechanism.  This guarantees that we get the real value even if we're
 149  * operating within a Virtual Machine and the Hypervisor is trapping our
 150  * Configuration Space accesses.
 151  */
 152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
 153 {
 154         u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
 155
 156         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
 157                 req |= ENABLE_F;
 158         else
 159                 req |= T6_ENABLE_F;
 160
 161         if (is_t4(adap->params.chip))
 162                 req |= LOCALCFG_F;
 163
 164         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
 165         *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
 166
 167         /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
 168          * Configuration Space read.  (None of the other fields matter when
 169          * ENABLE is 0 so a simple register write is easier than a
 170          * read-modify-write via t4_set_reg_field().)
 171          */
 172         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
 173 }
 174
 175 /*
 176  * t4_report_fw_error - report firmware error
 177  * @adap: the adapter
 178  *
 179  * The adapter firmware can indicate error conditions to the host.
 180  * If the firmware has indicated an error, print out the reason for
 181  * the firmware error.
 182  */
 183 static void t4_report_fw_error(struct adapter *adap)
 184 {
 185         static const char *const reason[] = {
 186                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 187                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 188                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 189                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 190                 "Unexpected Event",             /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 191                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 192                 "Device Shutdown",              /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 193                 "Reserved",                     /* reserved */
 194         };
 195         u32 pcie_fw;
 196
 197         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 198         if (pcie_fw & PCIE_FW_ERR_F)
 199                 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
 200                         reason[PCIE_FW_EVAL_G(pcie_fw)]);
 201 }
 202
 203 /*
 204  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 205  */
 206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 207                          u32 mbox_addr)
 208 {
 209         for ( ; nflit; nflit--, mbox_addr += 8)
 210                 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 211 }
 212
 213 /*
 214  * Handle a FW assertion reported in a mailbox.
 215  */
 216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 217 {
 218         struct fw_debug_cmd asrt;
 219
 220         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 221         dev_alert(adap->pdev_dev,
 222                   "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 223                   asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 224                   be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 225 }
 226
 227 /**
 228  *      t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
 229  *      @adapter: the adapter
 230  *      @cmd: the Firmware Mailbox Command or Reply
 231  *      @size: command length in bytes
 232  *      @access: the time (ms) needed to access the Firmware Mailbox
 233  *      @execute: the time (ms) the command spent being executed
 234  */
 235 static void t4_record_mbox(struct adapter *adapter,
 236                            const __be64 *cmd, unsigned int size,
 237                            int access, int execute)
 238 {
 239         struct mbox_cmd_log *log = adapter->mbox_log;
 240         struct mbox_cmd *entry;
 241         int i;
 242
 243         entry = mbox_cmd_log_entry(log, log->cursor++);
 244         if (log->cursor == log->size)
 245                 log->cursor = 0;
 246
 247         for (i = 0; i < size / 8; i++)
 248                 entry->cmd[i] = be64_to_cpu(cmd[i]);
 249         while (i < MBOX_LEN / 8)
 250                 entry->cmd[i++] = 0;
 251         entry->timestamp = jiffies;
 252         entry->seqno = log->seqno++;
 253         entry->access = access;
 254         entry->execute = execute;
 255 }
 256
 257 /**
 258  *      t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 259  *      @adap: the adapter
 260  *      @mbox: index of the mailbox to use
 261  *      @cmd: the command to write
 262  *      @size: command length in bytes
 263  *      @rpl: where to optionally store the reply
 264  *      @sleep_ok: if true we may sleep while awaiting command completion
 265  *      @timeout: time to wait for command to finish before timing out
 266  *
 267  *      Sends the given command to FW through the selected mailbox and waits
 268  *      for the FW to execute the command.  If @rpl is not %NULL it is used to
 269  *      store the FW's reply to the command.  The command and its optional
 270  *      reply are of the same length.  FW can take up to %FW_CMD_MAX_TIMEOUT ms
 271  *      to respond.  @sleep_ok determines whether we may sleep while awaiting
 272  *      the response.  If sleeping is allowed we use progressive backoff
 273  *      otherwise we spin.
 274  *
 275  *      The return value is 0 on success or a negative errno on failure.  A
 276  *      failure can happen either because we are not able to execute the
 277  *      command or FW executes it but signals an error.  In the latter case
 278  *      the return value is the error code indicated by FW (negated).
 279  */
 280 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 281                             int size, void *rpl, bool sleep_ok, int timeout)
 282 {
 283         static const int delay[] = {
 284                 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
 285         };
 286
 287         struct mbox_list entry;
 288         u16 access = 0;
 289         u16 execute = 0;
 290         u32 v;
 291         u64 res;
 292         int i, ms, delay_idx, ret;
 293         const __be64 *p = cmd;
 294         u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
 295         u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
 296         __be64 cmd_rpl[MBOX_LEN / 8];
 297         u32 pcie_fw;
 298
 299         if ((size & 15) || size > MBOX_LEN)
 300                 return -EINVAL;
 301
 302         /*
 303          * If the device is off-line, as in EEH, commands will time out.
 304          * Fail them early so we don't waste time waiting.
 305          */
 306         if (adap->pdev->error_state != pci_channel_io_normal)
 307                 return -EIO;
 308
 309         /* If we have a negative timeout, that implies that we can't sleep. */
 310         if (timeout < 0) {
 311                 sleep_ok = false;
 312                 timeout = -timeout;
 313         }
 314
 315         /* Queue ourselves onto the mailbox access list.  When our entry is at
 316          * the front of the list, we have rights to access the mailbox.  So we
 317          * wait [for a while] till we're at the front [or bail out with an
 318          * EBUSY] ...
 319          */
 320         spin_lock(&adap->mbox_lock);
 321         list_add_tail(&entry.list, &adap->mlist.list);
 322         spin_unlock(&adap->mbox_lock);
 323
 324         delay_idx = 0;
 325         ms = delay[0];
 326
 327         for (i = 0; ; i += ms) {
 328                 /* If we've waited too long, return a busy indication.  This
 329                  * really ought to be based on our initial position in the
 330                  * mailbox access list but this is a start.  We very rearely
 331                  * contend on access to the mailbox ...
 332                  */
 333                 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 334                 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
 335                         spin_lock(&adap->mbox_lock);
 336                         list_del(&entry.list);
 337                         spin_unlock(&adap->mbox_lock);
 338                         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
 339                         t4_record_mbox(adap, cmd, size, access, ret);
 340                         return ret;
 341                 }
 342
 343                 /* If we're at the head, break out and start the mailbox
 344                  * protocol.
 345                  */
 346                 if (list_first_entry(&adap->mlist.list, struct mbox_list,
 347                                      list) == &entry)
 348                         break;
 349
 350                 /* Delay for a bit before checking again ... */
 351                 if (sleep_ok) {
 352                         ms = delay[delay_idx];  /* last element may repeat */
 353                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 354                                 delay_idx++;
 355                         msleep(ms);
 356                 } else {
 357                         mdelay(ms);
 358                 }
 359         }
 360
 361         /* Loop trying to get ownership of the mailbox.  Return an error
 362          * if we can't gain ownership.
 363          */
 364         v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 365         for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
 366                 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 367         if (v != MBOX_OWNER_DRV) {
 368                 spin_lock(&adap->mbox_lock);
 369                 list_del(&entry.list);
 370                 spin_unlock(&adap->mbox_lock);
 371                 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
 372                 t4_record_mbox(adap, cmd, size, access, ret);
 373                 return ret;
 374         }
 375
 376         /* Copy in the new mailbox command and send it on its way ... */
 377         t4_record_mbox(adap, cmd, size, access, 0);
 378         for (i = 0; i < size; i += 8)
 379                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
 380
 381         t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
 382         t4_read_reg(adap, ctl_reg);          /* flush write */
 383
 384         delay_idx = 0;
 385         ms = delay[0];
 386
 387         for (i = 0;
 388              !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
 389              i < timeout;
 390              i += ms) {
 391                 if (sleep_ok) {
 392                         ms = delay[delay_idx];  /* last element may repeat */
 393                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 394                                 delay_idx++;
 395                         msleep(ms);
 396                 } else
 397                         mdelay(ms);
 398
 399                 v = t4_read_reg(adap, ctl_reg);
 400                 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
 401                         if (!(v & MBMSGVALID_F)) {
 402                                 t4_write_reg(adap, ctl_reg, 0);
 403                                 continue;
 404                         }
 405
 406                         get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
 407                         res = be64_to_cpu(cmd_rpl[0]);
 408
 409                         if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
 410                                 fw_asrt(adap, data_reg);
 411                                 res = FW_CMD_RETVAL_V(EIO);
 412                         } else if (rpl) {
 413                                 memcpy(rpl, cmd_rpl, size);
 414                         }
 415
 416                         t4_write_reg(adap, ctl_reg, 0);
 417
 418                         execute = i + ms;
 419                         t4_record_mbox(adap, cmd_rpl,
 420                                        MBOX_LEN, access, execute);
 421                         spin_lock(&adap->mbox_lock);
 422                         list_del(&entry.list);
 423                         spin_unlock(&adap->mbox_lock);
 424                         return -FW_CMD_RETVAL_G((int)res);
 425                 }
 426         }
 427
 428         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
 429         t4_record_mbox(adap, cmd, size, access, ret);
 430         dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
 431                 *(const u8 *)cmd, mbox);
 432         t4_report_fw_error(adap);
 433         spin_lock(&adap->mbox_lock);
 434         list_del(&entry.list);
 435         spin_unlock(&adap->mbox_lock);
 436         t4_fatal_err(adap);
 437         return ret;
 438 }
 439
 440 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 441                     void *rpl, bool sleep_ok)
 442 {
 443         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 444                                        FW_CMD_MAX_TIMEOUT);
 445 }
 446
 447 static int t4_edc_err_read(struct adapter *adap, int idx)
 448 {
 449         u32 edc_ecc_err_addr_reg;
 450         u32 rdata_reg;
 451
 452         if (is_t4(adap->params.chip)) {
 453                 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
 454                 return 0;
 455         }
 456         if (idx != 0 && idx != 1) {
 457                 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
 458                 return 0;
 459         }
 460
 461         edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
 462         rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
 463
 464         CH_WARN(adap,
 465                 "edc%d err addr 0x%x: 0x%x.\n",
 466                 idx, edc_ecc_err_addr_reg,
 467                 t4_read_reg(adap, edc_ecc_err_addr_reg));
 468         CH_WARN(adap,
 469                 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
 470                 rdata_reg,
 471                 (unsigned long long)t4_read_reg64(adap, rdata_reg),
 472                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
 473                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
 474                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
 475                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
 476                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
 477                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
 478                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
 479                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
 480
 481         return 0;
 482 }
 483
 484 /**
 485  *      t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
 486  *      @adap: the adapter
 487  *      @win: PCI-E Memory Window to use
 488  *      @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
 489  *      @addr: address within indicated memory type
 490  *      @len: amount of memory to transfer
 491  *      @hbuf: host memory buffer
 492  *      @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 493  *
 494  *      Reads/writes an [almost] arbitrary memory region in the firmware: the
 495  *      firmware memory address and host buffer must be aligned on 32-bit
 496  *      boudaries; the length may be arbitrary.  The memory is transferred as
 497  *      a raw byte sequence from/to the firmware's memory.  If this memory
 498  *      contains data structures which contain multi-byte integers, it's the
 499  *      caller's responsibility to perform appropriate byte order conversions.
 500  */
 501 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
 502                  u32 len, void *hbuf, int dir)
 503 {
 504         u32 pos, offset, resid, memoffset;
 505         u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
 506         u32 *buf;
 507
 508         /* Argument sanity checks ...
 509          */
 510         if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
 511                 return -EINVAL;
 512         buf = (u32 *)hbuf;
 513
 514         /* It's convenient to be able to handle lengths which aren't a
 515          * multiple of 32-bits because we often end up transferring files to
 516          * the firmware.  So we'll handle that by normalizing the length here
 517          * and then handling any residual transfer at the end.
 518          */
 519         resid = len & 0x3;
 520         len -= resid;
 521
 522         /* Offset into the region of memory which is being accessed
 523          * MEM_EDC0 = 0
 524          * MEM_EDC1 = 1
 525          * MEM_MC   = 2 -- MEM_MC for chips with only 1 memory controller
 526          * MEM_MC1  = 3 -- for chips with 2 memory controllers (e.g. T5)
 527          */
 528         edc_size  = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
 529         if (mtype != MEM_MC1)
 530                 memoffset = (mtype * (edc_size * 1024 * 1024));
 531         else {
 532                 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
 533                                                       MA_EXT_MEMORY0_BAR_A));
 534                 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
 535         }
 536
 537         /* Determine the PCIE_MEM_ACCESS_OFFSET */
 538         addr = addr + memoffset;
 539
 540         /* Each PCI-E Memory Window is programmed with a window size -- or
 541          * "aperture" -- which controls the granularity of its mapping onto
 542          * adapter memory.  We need to grab that aperture in order to know
 543          * how to use the specified window.  The window is also programmed
 544          * with the base address of the Memory Window in BAR0's address
 545          * space.  For T4 this is an absolute PCI-E Bus Address.  For T5
 546          * the address is relative to BAR0.
 547          */
 548         mem_reg = t4_read_reg(adap,
 549                               PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
 550                                                   win));
 551         mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
 552         mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
 553         if (is_t4(adap->params.chip))
 554                 mem_base -= adap->t4_bar0;
 555         win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 556
 557         /* Calculate our initial PCI-E Memory Window Position and Offset into
 558          * that Window.
 559          */
 560         pos = addr & ~(mem_aperture-1);
 561         offset = addr - pos;
 562
 563         /* Set up initial PCI-E Memory Window to cover the start of our
 564          * transfer.  (Read it back to ensure that changes propagate before we
 565          * attempt to use the new value.)
 566          */
 567         t4_write_reg(adap,
 568                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
 569                      pos | win_pf);
 570         t4_read_reg(adap,
 571                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
 572
 573         /* Transfer data to/from the adapter as long as there's an integral
 574          * number of 32-bit transfers to complete.
 575          *
 576          * A note on Endianness issues:
 577          *
 578          * The "register" reads and writes below from/to the PCI-E Memory
 579          * Window invoke the standard adapter Big-Endian to PCI-E Link
 580          * Little-Endian "swizzel."  As a result, if we have the following
 581          * data in adapter memory:
 582          *
 583          *     Memory:  ... | b0 | b1 | b2 | b3 | ...
 584          *     Address:      i+0  i+1  i+2  i+3
 585          *
 586          * Then a read of the adapter memory via the PCI-E Memory Window
 587          * will yield:
 588          *
 589          *     x = readl(i)
 590          *         31                  0
 591          *         [ b3 | b2 | b1 | b0 ]
 592          *
 593          * If this value is stored into local memory on a Little-Endian system
 594          * it will show up correctly in local memory as:
 595          *
 596          *     ( ..., b0, b1, b2, b3, ... )
 597          *
 598          * But on a Big-Endian system, the store will show up in memory
 599          * incorrectly swizzled as:
 600          *
 601          *     ( ..., b3, b2, b1, b0, ... )
 602          *
 603          * So we need to account for this in the reads and writes to the
 604          * PCI-E Memory Window below by undoing the register read/write
 605          * swizzels.
 606          */
 607         while (len > 0) {
 608                 if (dir == T4_MEMORY_READ)
 609                         *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
 610                                                 mem_base + offset));
 611                 else
 612                         t4_write_reg(adap, mem_base + offset,
 613                                      (__force u32)cpu_to_le32(*buf++));
 614                 offset += sizeof(__be32);
 615                 len -= sizeof(__be32);
 616
 617                 /* If we've reached the end of our current window aperture,
 618                  * move the PCI-E Memory Window on to the next.  Note that
 619                  * doing this here after "len" may be 0 allows us to set up
 620                  * the PCI-E Memory Window for a possible final residual
 621                  * transfer below ...
 622                  */
 623                 if (offset == mem_aperture) {
 624                         pos += mem_aperture;
 625                         offset = 0;
 626                         t4_write_reg(adap,
 627                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 628                                                     win), pos | win_pf);
 629                         t4_read_reg(adap,
 630                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 631                                                     win));
 632                 }
 633         }
 634
 635         /* If the original transfer had a length which wasn't a multiple of
 636          * 32-bits, now's where we need to finish off the transfer of the
 637          * residual amount.  The PCI-E Memory Window has already been moved
 638          * above (if necessary) to cover this final transfer.
 639          */
 640         if (resid) {
 641                 union {
 642                         u32 word;
 643                         char byte[4];
 644                 } last;
 645                 unsigned char *bp;
 646                 int i;
 647
 648                 if (dir == T4_MEMORY_READ) {
 649                         last.word = le32_to_cpu(
 650                                         (__force __le32)t4_read_reg(adap,
 651                                                 mem_base + offset));
 652                         for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
 653                                 bp[i] = last.byte[i];
 654                 } else {
 655                         last.word = *buf;
 656                         for (i = resid; i < 4; i++)
 657                                 last.byte[i] = 0;
 658                         t4_write_reg(adap, mem_base + offset,
 659                                      (__force u32)cpu_to_le32(last.word));
 660                 }
 661         }
 662
 663         return 0;
 664 }
 665
 666 /* Return the specified PCI-E Configuration Space register from our Physical
 667  * Function.  We try first via a Firmware LDST Command since we prefer to let
 668  * the firmware own all of these registers, but if that fails we go for it
 669  * directly ourselves.
 670  */
 671 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
 672 {
 673         u32 val, ldst_addrspace;
 674
 675         /* If fw_attach != 0, construct and send the Firmware LDST Command to
 676          * retrieve the specified PCI-E Configuration Space register.
 677          */
 678         struct fw_ldst_cmd ldst_cmd;
 679         int ret;
 680
 681         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
 682         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
 683         ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
 684                                                FW_CMD_REQUEST_F |
 685                                                FW_CMD_READ_F |
 686                                                ldst_addrspace);
 687         ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
 688         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
 689         ldst_cmd.u.pcie.ctrl_to_fn =
 690                 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
 691         ldst_cmd.u.pcie.r = reg;
 692
 693         /* If the LDST Command succeeds, return the result, otherwise
 694          * fall through to reading it directly ourselves ...
 695          */
 696         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
 697                          &ldst_cmd);
 698         if (ret == 0)
 699                 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
 700         else
 701                 /* Read the desired Configuration Space register via the PCI-E
 702                  * Backdoor mechanism.
 703                  */
 704                 t4_hw_pci_read_cfg4(adap, reg, &val);
 705         return val;
 706 }
 707
 708 /* Get the window based on base passed to it.
 709  * Window aperture is currently unhandled, but there is no use case for it
 710  * right now
 711  */
 712 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
 713                          u32 memwin_base)
 714 {
 715         u32 ret;
 716
 717         if (is_t4(adap->params.chip)) {
 718                 u32 bar0;
 719
 720                 /* Truncation intentional: we only read the bottom 32-bits of
 721                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
 722                  * mechanism to read BAR0 instead of using
 723                  * pci_resource_start() because we could be operating from
 724                  * within a Virtual Machine which is trapping our accesses to
 725                  * our Configuration Space and we need to set up the PCI-E
 726                  * Memory Window decoders with the actual addresses which will
 727                  * be coming across the PCI-E link.
 728                  */
 729                 bar0 = t4_read_pcie_cfg4(adap, pci_base);
 730                 bar0 &= pci_mask;
 731                 adap->t4_bar0 = bar0;
 732
 733                 ret = bar0 + memwin_base;
 734         } else {
 735                 /* For T5, only relative offset inside the PCIe BAR is passed */
 736                 ret = memwin_base;
 737         }
 738         return ret;
 739 }
 740
 741 /* Get the default utility window (win0) used by everyone */
 742 u32 t4_get_util_window(struct adapter *adap)
 743 {
 744         return t4_get_window(adap, PCI_BASE_ADDRESS_0,
 745                              PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
 746 }
 747
 748 /* Set up memory window for accessing adapter memory ranges.  (Read
 749  * back MA register to ensure that changes propagate before we attempt
 750  * to use the new values.)
 751  */
 752 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
 753 {
 754         t4_write_reg(adap,
 755                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
 756                      memwin_base | BIR_V(0) |
 757                      WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
 758         t4_read_reg(adap,
 759                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
 760 }
 761
 762 /**
 763  *      t4_get_regs_len - return the size of the chips register set
 764  *      @adapter: the adapter
 765  *
 766  *      Returns the size of the chip's BAR0 register space.
 767  */
 768 unsigned int t4_get_regs_len(struct adapter *adapter)
 769 {
 770         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 771
 772         switch (chip_version) {
 773         case CHELSIO_T4:
 774                 return T4_REGMAP_SIZE;
 775
 776         case CHELSIO_T5:
 777         case CHELSIO_T6:
 778                 return T5_REGMAP_SIZE;
 779         }
 780
 781         dev_err(adapter->pdev_dev,
 782                 "Unsupported chip version %d\n", chip_version);
 783         return 0;
 784 }
 785
 786 /**
 787  *      t4_get_regs - read chip registers into provided buffer
 788  *      @adap: the adapter
 789  *      @buf: register buffer
 790  *      @buf_size: size (in bytes) of register buffer
 791  *
 792  *      If the provided register buffer isn't large enough for the chip's
 793  *      full register range, the register dump will be truncated to the
 794  *      register buffer's size.
 795  */
 796 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 797 {
 798         static const unsigned int t4_reg_ranges[] = {
 799                 0x1008, 0x1108,
 800                 0x1180, 0x1184,
 801                 0x1190, 0x1194,
 802                 0x11a0, 0x11a4,
 803                 0x11b0, 0x11b4,
 804                 0x11fc, 0x123c,
 805                 0x1300, 0x173c,
 806                 0x1800, 0x18fc,
 807                 0x3000, 0x30d8,
 808                 0x30e0, 0x30e4,
 809                 0x30ec, 0x5910,
 810                 0x5920, 0x5924,
 811                 0x5960, 0x5960,
 812                 0x5968, 0x5968,
 813                 0x5970, 0x5970,
 814                 0x5978, 0x5978,
 815                 0x5980, 0x5980,
 816                 0x5988, 0x5988,
 817                 0x5990, 0x5990,
 818                 0x5998, 0x5998,
 819                 0x59a0, 0x59d4,
 820                 0x5a00, 0x5ae0,
 821                 0x5ae8, 0x5ae8,
 822                 0x5af0, 0x5af0,
 823                 0x5af8, 0x5af8,
 824                 0x6000, 0x6098,
 825                 0x6100, 0x6150,
 826                 0x6200, 0x6208,
 827                 0x6240, 0x6248,
 828                 0x6280, 0x62b0,
 829                 0x62c0, 0x6338,
 830                 0x6370, 0x638c,
 831                 0x6400, 0x643c,
 832                 0x6500, 0x6524,
 833                 0x6a00, 0x6a04,
 834                 0x6a14, 0x6a38,
 835                 0x6a60, 0x6a70,
 836                 0x6a78, 0x6a78,
 837                 0x6b00, 0x6b0c,
 838                 0x6b1c, 0x6b84,
 839                 0x6bf0, 0x6bf8,
 840                 0x6c00, 0x6c0c,
 841                 0x6c1c, 0x6c84,
 842                 0x6cf0, 0x6cf8,
 843                 0x6d00, 0x6d0c,
 844                 0x6d1c, 0x6d84,
 845                 0x6df0, 0x6df8,
 846                 0x6e00, 0x6e0c,
 847                 0x6e1c, 0x6e84,
 848                 0x6ef0, 0x6ef8,
 849                 0x6f00, 0x6f0c,
 850                 0x6f1c, 0x6f84,
 851                 0x6ff0, 0x6ff8,
 852                 0x7000, 0x700c,
 853                 0x701c, 0x7084,
 854                 0x70f0, 0x70f8,
 855                 0x7100, 0x710c,
 856                 0x711c, 0x7184,
 857                 0x71f0, 0x71f8,
 858                 0x7200, 0x720c,
 859                 0x721c, 0x7284,
 860                 0x72f0, 0x72f8,
 861                 0x7300, 0x730c,
 862                 0x731c, 0x7384,
 863                 0x73f0, 0x73f8,
 864                 0x7400, 0x7450,
 865                 0x7500, 0x7530,
 866                 0x7600, 0x760c,
 867                 0x7614, 0x761c,
 868                 0x7680, 0x76cc,
 869                 0x7700, 0x7798,
 870                 0x77c0, 0x77fc,
 871                 0x7900, 0x79fc,
 872                 0x7b00, 0x7b58,
 873                 0x7b60, 0x7b84,
 874                 0x7b8c, 0x7c38,
 875                 0x7d00, 0x7d38,
 876                 0x7d40, 0x7d80,
 877                 0x7d8c, 0x7ddc,
 878                 0x7de4, 0x7e04,
 879                 0x7e10, 0x7e1c,
 880                 0x7e24, 0x7e38,
 881                 0x7e40, 0x7e44,
 882                 0x7e4c, 0x7e78,
 883                 0x7e80, 0x7ea4,
 884                 0x7eac, 0x7edc,
 885                 0x7ee8, 0x7efc,
 886                 0x8dc0, 0x8e04,
 887                 0x8e10, 0x8e1c,
 888                 0x8e30, 0x8e78,
 889                 0x8ea0, 0x8eb8,
 890                 0x8ec0, 0x8f6c,
 891                 0x8fc0, 0x9008,
 892                 0x9010, 0x9058,
 893                 0x9060, 0x9060,
 894                 0x9068, 0x9074,
 895                 0x90fc, 0x90fc,
 896                 0x9400, 0x9408,
 897                 0x9410, 0x9458,
 898                 0x9600, 0x9600,
 899                 0x9608, 0x9638,
 900                 0x9640, 0x96bc,
 901                 0x9800, 0x9808,
 902                 0x9820, 0x983c,
 903                 0x9850, 0x9864,
 904                 0x9c00, 0x9c6c,
 905                 0x9c80, 0x9cec,
 906                 0x9d00, 0x9d6c,
 907                 0x9d80, 0x9dec,
 908                 0x9e00, 0x9e6c,
 909                 0x9e80, 0x9eec,
 910                 0x9f00, 0x9f6c,
 911                 0x9f80, 0x9fec,
 912                 0xd004, 0xd004,
 913                 0xd010, 0xd03c,
 914                 0xdfc0, 0xdfe0,
 915                 0xe000, 0xea7c,
 916                 0xf000, 0x11110,
 917                 0x11118, 0x11190,
 918                 0x19040, 0x1906c,
 919                 0x19078, 0x19080,
 920                 0x1908c, 0x190e4,
 921                 0x190f0, 0x190f8,
 922                 0x19100, 0x19110,
 923                 0x19120, 0x19124,
 924                 0x19150, 0x19194,
 925                 0x1919c, 0x191b0,
 926                 0x191d0, 0x191e8,
 927                 0x19238, 0x1924c,
 928                 0x193f8, 0x1943c,
 929                 0x1944c, 0x19474,
 930                 0x19490, 0x194e0,
 931                 0x194f0, 0x194f8,
 932                 0x19800, 0x19c08,
 933                 0x19c10, 0x19c90,
 934                 0x19ca0, 0x19ce4,
 935                 0x19cf0, 0x19d40,
 936                 0x19d50, 0x19d94,
 937                 0x19da0, 0x19de8,
 938                 0x19df0, 0x19e40,
 939                 0x19e50, 0x19e90,
 940                 0x19ea0, 0x19f4c,
 941                 0x1a000, 0x1a004,
 942                 0x1a010, 0x1a06c,
 943                 0x1a0b0, 0x1a0e4,
 944                 0x1a0ec, 0x1a0f4,
 945                 0x1a100, 0x1a108,
 946                 0x1a114, 0x1a120,
 947                 0x1a128, 0x1a130,
 948                 0x1a138, 0x1a138,
 949                 0x1a190, 0x1a1c4,
 950                 0x1a1fc, 0x1a1fc,
 951                 0x1e040, 0x1e04c,
 952                 0x1e284, 0x1e28c,
 953                 0x1e2c0, 0x1e2c0,
 954                 0x1e2e0, 0x1e2e0,
 955                 0x1e300, 0x1e384,
 956                 0x1e3c0, 0x1e3c8,
 957                 0x1e440, 0x1e44c,
 958                 0x1e684, 0x1e68c,
 959                 0x1e6c0, 0x1e6c0,
 960                 0x1e6e0, 0x1e6e0,
 961                 0x1e700, 0x1e784,
 962                 0x1e7c0, 0x1e7c8,
 963                 0x1e840, 0x1e84c,
 964                 0x1ea84, 0x1ea8c,
 965                 0x1eac0, 0x1eac0,
 966                 0x1eae0, 0x1eae0,
 967                 0x1eb00, 0x1eb84,
 968                 0x1ebc0, 0x1ebc8,
 969                 0x1ec40, 0x1ec4c,
 970                 0x1ee84, 0x1ee8c,
 971                 0x1eec0, 0x1eec0,
 972                 0x1eee0, 0x1eee0,
 973                 0x1ef00, 0x1ef84,
 974                 0x1efc0, 0x1efc8,
 975                 0x1f040, 0x1f04c,
 976                 0x1f284, 0x1f28c,
 977                 0x1f2c0, 0x1f2c0,
 978                 0x1f2e0, 0x1f2e0,
 979                 0x1f300, 0x1f384,
 980                 0x1f3c0, 0x1f3c8,
 981                 0x1f440, 0x1f44c,
 982                 0x1f684, 0x1f68c,
 983                 0x1f6c0, 0x1f6c0,
 984                 0x1f6e0, 0x1f6e0,
 985                 0x1f700, 0x1f784,
 986                 0x1f7c0, 0x1f7c8,
 987                 0x1f840, 0x1f84c,
 988                 0x1fa84, 0x1fa8c,
 989                 0x1fac0, 0x1fac0,
 990                 0x1fae0, 0x1fae0,
 991                 0x1fb00, 0x1fb84,
 992                 0x1fbc0, 0x1fbc8,
 993                 0x1fc40, 0x1fc4c,
 994                 0x1fe84, 0x1fe8c,
 995                 0x1fec0, 0x1fec0,
 996                 0x1fee0, 0x1fee0,
 997                 0x1ff00, 0x1ff84,
 998                 0x1ffc0, 0x1ffc8,
 999                 0x20000, 0x2002c,
1000                 0x20100, 0x2013c,
1001                 0x20190, 0x201a0,
1002                 0x201a8, 0x201b8,
1003                 0x201c4, 0x201c8,
1004                 0x20200, 0x20318,
1005                 0x20400, 0x204b4,
1006                 0x204c0, 0x20528,
1007                 0x20540, 0x20614,
1008                 0x21000, 0x21040,
1009                 0x2104c, 0x21060,
1010                 0x210c0, 0x210ec,
1011                 0x21200, 0x21268,
1012                 0x21270, 0x21284,
1013                 0x212fc, 0x21388,
1014                 0x21400, 0x21404,
1015                 0x21500, 0x21500,
1016                 0x21510, 0x21518,
1017                 0x2152c, 0x21530,
1018                 0x2153c, 0x2153c,
1019                 0x21550, 0x21554,
1020                 0x21600, 0x21600,
1021                 0x21608, 0x2161c,
1022                 0x21624, 0x21628,
1023                 0x21630, 0x21634,
1024                 0x2163c, 0x2163c,
1025                 0x21700, 0x2171c,
1026                 0x21780, 0x2178c,
1027                 0x21800, 0x21818,
1028                 0x21820, 0x21828,
1029                 0x21830, 0x21848,
1030                 0x21850, 0x21854,
1031                 0x21860, 0x21868,
1032                 0x21870, 0x21870,
1033                 0x21878, 0x21898,
1034                 0x218a0, 0x218a8,
1035                 0x218b0, 0x218c8,
1036                 0x218d0, 0x218d4,
1037                 0x218e0, 0x218e8,
1038                 0x218f0, 0x218f0,
1039                 0x218f8, 0x21a18,
1040                 0x21a20, 0x21a28,
1041                 0x21a30, 0x21a48,
1042                 0x21a50, 0x21a54,
1043                 0x21a60, 0x21a68,
1044                 0x21a70, 0x21a70,
1045                 0x21a78, 0x21a98,
1046                 0x21aa0, 0x21aa8,
1047                 0x21ab0, 0x21ac8,
1048                 0x21ad0, 0x21ad4,
1049                 0x21ae0, 0x21ae8,
1050                 0x21af0, 0x21af0,
1051                 0x21af8, 0x21c18,
1052                 0x21c20, 0x21c20,
1053                 0x21c28, 0x21c30,
1054                 0x21c38, 0x21c38,
1055                 0x21c80, 0x21c98,
1056                 0x21ca0, 0x21ca8,
1057                 0x21cb0, 0x21cc8,
1058                 0x21cd0, 0x21cd4,
1059                 0x21ce0, 0x21ce8,
1060                 0x21cf0, 0x21cf0,
1061                 0x21cf8, 0x21d7c,
1062                 0x21e00, 0x21e04,
1063                 0x22000, 0x2202c,
1064                 0x22100, 0x2213c,
1065                 0x22190, 0x221a0,
1066                 0x221a8, 0x221b8,
1067                 0x221c4, 0x221c8,
1068                 0x22200, 0x22318,
1069                 0x22400, 0x224b4,
1070                 0x224c0, 0x22528,
1071                 0x22540, 0x22614,
1072                 0x23000, 0x23040,
1073                 0x2304c, 0x23060,
1074                 0x230c0, 0x230ec,
1075                 0x23200, 0x23268,
1076                 0x23270, 0x23284,
1077                 0x232fc, 0x23388,
1078                 0x23400, 0x23404,
1079                 0x23500, 0x23500,
1080                 0x23510, 0x23518,
1081                 0x2352c, 0x23530,
1082                 0x2353c, 0x2353c,
1083                 0x23550, 0x23554,
1084                 0x23600, 0x23600,
1085                 0x23608, 0x2361c,
1086                 0x23624, 0x23628,
1087                 0x23630, 0x23634,
1088                 0x2363c, 0x2363c,
1089                 0x23700, 0x2371c,
1090                 0x23780, 0x2378c,
1091                 0x23800, 0x23818,
1092                 0x23820, 0x23828,
1093                 0x23830, 0x23848,
1094                 0x23850, 0x23854,
1095                 0x23860, 0x23868,
1096                 0x23870, 0x23870,
1097                 0x23878, 0x23898,
1098                 0x238a0, 0x238a8,
1099                 0x238b0, 0x238c8,
1100                 0x238d0, 0x238d4,
1101                 0x238e0, 0x238e8,
1102                 0x238f0, 0x238f0,
1103                 0x238f8, 0x23a18,
1104                 0x23a20, 0x23a28,
1105                 0x23a30, 0x23a48,
1106                 0x23a50, 0x23a54,
1107                 0x23a60, 0x23a68,
1108                 0x23a70, 0x23a70,
1109                 0x23a78, 0x23a98,
1110                 0x23aa0, 0x23aa8,
1111                 0x23ab0, 0x23ac8,
1112                 0x23ad0, 0x23ad4,
1113                 0x23ae0, 0x23ae8,
1114                 0x23af0, 0x23af0,
1115                 0x23af8, 0x23c18,
1116                 0x23c20, 0x23c20,
1117                 0x23c28, 0x23c30,
1118                 0x23c38, 0x23c38,
1119                 0x23c80, 0x23c98,
1120                 0x23ca0, 0x23ca8,
1121                 0x23cb0, 0x23cc8,
1122                 0x23cd0, 0x23cd4,
1123                 0x23ce0, 0x23ce8,
1124                 0x23cf0, 0x23cf0,
1125                 0x23cf8, 0x23d7c,
1126                 0x23e00, 0x23e04,
1127                 0x24000, 0x2402c,
1128                 0x24100, 0x2413c,
1129                 0x24190, 0x241a0,
1130                 0x241a8, 0x241b8,
1131                 0x241c4, 0x241c8,
1132                 0x24200, 0x24318,
1133                 0x24400, 0x244b4,
1134                 0x244c0, 0x24528,
1135                 0x24540, 0x24614,
1136                 0x25000, 0x25040,
1137                 0x2504c, 0x25060,
1138                 0x250c0, 0x250ec,
1139                 0x25200, 0x25268,
1140                 0x25270, 0x25284,
1141                 0x252fc, 0x25388,
1142                 0x25400, 0x25404,
1143                 0x25500, 0x25500,
1144                 0x25510, 0x25518,
1145                 0x2552c, 0x25530,
1146                 0x2553c, 0x2553c,
1147                 0x25550, 0x25554,
1148                 0x25600, 0x25600,
1149                 0x25608, 0x2561c,
1150                 0x25624, 0x25628,
1151                 0x25630, 0x25634,
1152                 0x2563c, 0x2563c,
1153                 0x25700, 0x2571c,
1154                 0x25780, 0x2578c,
1155                 0x25800, 0x25818,
1156                 0x25820, 0x25828,
1157                 0x25830, 0x25848,
1158                 0x25850, 0x25854,
1159                 0x25860, 0x25868,
1160                 0x25870, 0x25870,
1161                 0x25878, 0x25898,
1162                 0x258a0, 0x258a8,
1163                 0x258b0, 0x258c8,
1164                 0x258d0, 0x258d4,
1165                 0x258e0, 0x258e8,
1166                 0x258f0, 0x258f0,
1167                 0x258f8, 0x25a18,
1168                 0x25a20, 0x25a28,
1169                 0x25a30, 0x25a48,
1170                 0x25a50, 0x25a54,
1171                 0x25a60, 0x25a68,
1172                 0x25a70, 0x25a70,
1173                 0x25a78, 0x25a98,
1174                 0x25aa0, 0x25aa8,
1175                 0x25ab0, 0x25ac8,
1176                 0x25ad0, 0x25ad4,
1177                 0x25ae0, 0x25ae8,
1178                 0x25af0, 0x25af0,
1179                 0x25af8, 0x25c18,
1180                 0x25c20, 0x25c20,
1181                 0x25c28, 0x25c30,
1182                 0x25c38, 0x25c38,
1183                 0x25c80, 0x25c98,
1184                 0x25ca0, 0x25ca8,
1185                 0x25cb0, 0x25cc8,
1186                 0x25cd0, 0x25cd4,
1187                 0x25ce0, 0x25ce8,
1188                 0x25cf0, 0x25cf0,
1189                 0x25cf8, 0x25d7c,
1190                 0x25e00, 0x25e04,
1191                 0x26000, 0x2602c,
1192                 0x26100, 0x2613c,
1193                 0x26190, 0x261a0,
1194                 0x261a8, 0x261b8,
1195                 0x261c4, 0x261c8,
1196                 0x26200, 0x26318,
1197                 0x26400, 0x264b4,
1198                 0x264c0, 0x26528,
1199                 0x26540, 0x26614,
1200                 0x27000, 0x27040,
1201                 0x2704c, 0x27060,
1202                 0x270c0, 0x270ec,
1203                 0x27200, 0x27268,
1204                 0x27270, 0x27284,
1205                 0x272fc, 0x27388,
1206                 0x27400, 0x27404,
1207                 0x27500, 0x27500,
1208                 0x27510, 0x27518,
1209                 0x2752c, 0x27530,
1210                 0x2753c, 0x2753c,
1211                 0x27550, 0x27554,
1212                 0x27600, 0x27600,
1213                 0x27608, 0x2761c,
1214                 0x27624, 0x27628,
1215                 0x27630, 0x27634,
1216                 0x2763c, 0x2763c,
1217                 0x27700, 0x2771c,
1218                 0x27780, 0x2778c,
1219                 0x27800, 0x27818,
1220                 0x27820, 0x27828,
1221                 0x27830, 0x27848,
1222                 0x27850, 0x27854,
1223                 0x27860, 0x27868,
1224                 0x27870, 0x27870,
1225                 0x27878, 0x27898,
1226                 0x278a0, 0x278a8,
1227                 0x278b0, 0x278c8,
1228                 0x278d0, 0x278d4,
1229                 0x278e0, 0x278e8,
1230                 0x278f0, 0x278f0,
1231                 0x278f8, 0x27a18,
1232                 0x27a20, 0x27a28,
1233                 0x27a30, 0x27a48,
1234                 0x27a50, 0x27a54,
1235                 0x27a60, 0x27a68,
1236                 0x27a70, 0x27a70,
1237                 0x27a78, 0x27a98,
1238                 0x27aa0, 0x27aa8,
1239                 0x27ab0, 0x27ac8,
1240                 0x27ad0, 0x27ad4,
1241                 0x27ae0, 0x27ae8,
1242                 0x27af0, 0x27af0,
1243                 0x27af8, 0x27c18,
1244                 0x27c20, 0x27c20,
1245                 0x27c28, 0x27c30,
1246                 0x27c38, 0x27c38,
1247                 0x27c80, 0x27c98,
1248                 0x27ca0, 0x27ca8,
1249                 0x27cb0, 0x27cc8,
1250                 0x27cd0, 0x27cd4,
1251                 0x27ce0, 0x27ce8,
1252                 0x27cf0, 0x27cf0,
1253                 0x27cf8, 0x27d7c,
1254                 0x27e00, 0x27e04,
1255         };
1256
1257         static const unsigned int t5_reg_ranges[] = {
1258                 0x1008, 0x10c0,
1259                 0x10cc, 0x10f8,
1260                 0x1100, 0x1100,
1261                 0x110c, 0x1148,
1262                 0x1180, 0x1184,
1263                 0x1190, 0x1194,
1264                 0x11a0, 0x11a4,
1265                 0x11b0, 0x11b4,
1266                 0x11fc, 0x123c,
1267                 0x1280, 0x173c,
1268                 0x1800, 0x18fc,
1269                 0x3000, 0x3028,
1270                 0x3060, 0x30b0,
1271                 0x30b8, 0x30d8,
1272                 0x30e0, 0x30fc,
1273                 0x3140, 0x357c,
1274                 0x35a8, 0x35cc,
1275                 0x35ec, 0x35ec,
1276                 0x3600, 0x5624,
1277                 0x56cc, 0x56ec,
1278                 0x56f4, 0x5720,
1279                 0x5728, 0x575c,
1280                 0x580c, 0x5814,
1281                 0x5890, 0x589c,
1282                 0x58a4, 0x58ac,
1283                 0x58b8, 0x58bc,
1284                 0x5940, 0x59c8,
1285                 0x59d0, 0x59dc,
1286                 0x59fc, 0x5a18,
1287                 0x5a60, 0x5a70,
1288                 0x5a80, 0x5a9c,
1289                 0x5b94, 0x5bfc,
1290                 0x6000, 0x6020,
1291                 0x6028, 0x6040,
1292                 0x6058, 0x609c,
1293                 0x60a8, 0x614c,
1294                 0x7700, 0x7798,
1295                 0x77c0, 0x78fc,
1296                 0x7b00, 0x7b58,
1297                 0x7b60, 0x7b84,
1298                 0x7b8c, 0x7c54,
1299                 0x7d00, 0x7d38,
1300                 0x7d40, 0x7d80,
1301                 0x7d8c, 0x7ddc,
1302                 0x7de4, 0x7e04,
1303                 0x7e10, 0x7e1c,
1304                 0x7e24, 0x7e38,
1305                 0x7e40, 0x7e44,
1306                 0x7e4c, 0x7e78,
1307                 0x7e80, 0x7edc,
1308                 0x7ee8, 0x7efc,
1309                 0x8dc0, 0x8de0,
1310                 0x8df8, 0x8e04,
1311                 0x8e10, 0x8e84,
1312                 0x8ea0, 0x8f84,
1313                 0x8fc0, 0x9058,
1314                 0x9060, 0x9060,
1315                 0x9068, 0x90f8,
1316                 0x9400, 0x9408,
1317                 0x9410, 0x9470,
1318                 0x9600, 0x9600,
1319                 0x9608, 0x9638,
1320                 0x9640, 0x96f4,
1321                 0x9800, 0x9808,
1322                 0x9820, 0x983c,
1323                 0x9850, 0x9864,
1324                 0x9c00, 0x9c6c,
1325                 0x9c80, 0x9cec,
1326                 0x9d00, 0x9d6c,
1327                 0x9d80, 0x9dec,
1328                 0x9e00, 0x9e6c,
1329                 0x9e80, 0x9eec,
1330                 0x9f00, 0x9f6c,
1331                 0x9f80, 0xa020,
1332                 0xd004, 0xd004,
1333                 0xd010, 0xd03c,
1334                 0xdfc0, 0xdfe0,
1335                 0xe000, 0x1106c,
1336                 0x11074, 0x11088,
1337                 0x1109c, 0x1117c,
1338                 0x11190, 0x11204,
1339                 0x19040, 0x1906c,
1340                 0x19078, 0x19080,
1341                 0x1908c, 0x190e8,
1342                 0x190f0, 0x190f8,
1343                 0x19100, 0x19110,
1344                 0x19120, 0x19124,
1345                 0x19150, 0x19194,
1346                 0x1919c, 0x191b0,
1347                 0x191d0, 0x191e8,
1348                 0x19238, 0x19290,
1349                 0x193f8, 0x19428,
1350                 0x19430, 0x19444,
1351                 0x1944c, 0x1946c,
1352                 0x19474, 0x19474,
1353                 0x19490, 0x194cc,
1354                 0x194f0, 0x194f8,
1355                 0x19c00, 0x19c08,
1356                 0x19c10, 0x19c60,
1357                 0x19c94, 0x19ce4,
1358                 0x19cf0, 0x19d40,
1359                 0x19d50, 0x19d94,
1360                 0x19da0, 0x19de8,
1361                 0x19df0, 0x19e10,
1362                 0x19e50, 0x19e90,
1363                 0x19ea0, 0x19f24,
1364                 0x19f34, 0x19f34,
1365                 0x19f40, 0x19f50,
1366                 0x19f90, 0x19fb4,
1367                 0x19fc4, 0x19fe4,
1368                 0x1a000, 0x1a004,
1369                 0x1a010, 0x1a06c,
1370                 0x1a0b0, 0x1a0e4,
1371                 0x1a0ec, 0x1a0f8,
1372                 0x1a100, 0x1a108,
1373                 0x1a114, 0x1a120,
1374                 0x1a128, 0x1a130,
1375                 0x1a138, 0x1a138,
1376                 0x1a190, 0x1a1c4,
1377                 0x1a1fc, 0x1a1fc,
1378                 0x1e008, 0x1e00c,
1379                 0x1e040, 0x1e044,
1380                 0x1e04c, 0x1e04c,
1381                 0x1e284, 0x1e290,
1382                 0x1e2c0, 0x1e2c0,
1383                 0x1e2e0, 0x1e2e0,
1384                 0x1e300, 0x1e384,
1385                 0x1e3c0, 0x1e3c8,
1386                 0x1e408, 0x1e40c,
1387                 0x1e440, 0x1e444,
1388                 0x1e44c, 0x1e44c,
1389                 0x1e684, 0x1e690,
1390                 0x1e6c0, 0x1e6c0,
1391                 0x1e6e0, 0x1e6e0,
1392                 0x1e700, 0x1e784,
1393                 0x1e7c0, 0x1e7c8,
1394                 0x1e808, 0x1e80c,
1395                 0x1e840, 0x1e844,
1396                 0x1e84c, 0x1e84c,
1397                 0x1ea84, 0x1ea90,
1398                 0x1eac0, 0x1eac0,
1399                 0x1eae0, 0x1eae0,
1400                 0x1eb00, 0x1eb84,
1401                 0x1ebc0, 0x1ebc8,
1402                 0x1ec08, 0x1ec0c,
1403                 0x1ec40, 0x1ec44,
1404                 0x1ec4c, 0x1ec4c,
1405                 0x1ee84, 0x1ee90,
1406                 0x1eec0, 0x1eec0,
1407                 0x1eee0, 0x1eee0,
1408                 0x1ef00, 0x1ef84,
1409                 0x1efc0, 0x1efc8,
1410                 0x1f008, 0x1f00c,
1411                 0x1f040, 0x1f044,
1412                 0x1f04c, 0x1f04c,
1413                 0x1f284, 0x1f290,
1414                 0x1f2c0, 0x1f2c0,
1415                 0x1f2e0, 0x1f2e0,
1416                 0x1f300, 0x1f384,
1417                 0x1f3c0, 0x1f3c8,
1418                 0x1f408, 0x1f40c,
1419                 0x1f440, 0x1f444,
1420                 0x1f44c, 0x1f44c,
1421                 0x1f684, 0x1f690,
1422                 0x1f6c0, 0x1f6c0,
1423                 0x1f6e0, 0x1f6e0,
1424                 0x1f700, 0x1f784,
1425                 0x1f7c0, 0x1f7c8,
1426                 0x1f808, 0x1f80c,
1427                 0x1f840, 0x1f844,
1428                 0x1f84c, 0x1f84c,
1429                 0x1fa84, 0x1fa90,
1430                 0x1fac0, 0x1fac0,
1431                 0x1fae0, 0x1fae0,
1432                 0x1fb00, 0x1fb84,
1433                 0x1fbc0, 0x1fbc8,
1434                 0x1fc08, 0x1fc0c,
1435                 0x1fc40, 0x1fc44,
1436                 0x1fc4c, 0x1fc4c,
1437                 0x1fe84, 0x1fe90,
1438                 0x1fec0, 0x1fec0,
1439                 0x1fee0, 0x1fee0,
1440                 0x1ff00, 0x1ff84,
1441                 0x1ffc0, 0x1ffc8,
1442                 0x30000, 0x30030,
1443                 0x30100, 0x30144,
1444                 0x30190, 0x301a0,
1445                 0x301a8, 0x301b8,
1446                 0x301c4, 0x301c8,
1447                 0x301d0, 0x301d0,
1448                 0x30200, 0x30318,
1449                 0x30400, 0x304b4,
1450                 0x304c0, 0x3052c,
1451                 0x30540, 0x3061c,
1452                 0x30800, 0x30828,
1453                 0x30834, 0x30834,
1454                 0x308c0, 0x30908,
1455                 0x30910, 0x309ac,
1456                 0x30a00, 0x30a14,
1457                 0x30a1c, 0x30a2c,
1458                 0x30a44, 0x30a50,
1459                 0x30a74, 0x30a74,
1460                 0x30a7c, 0x30afc,
1461                 0x30b08, 0x30c24,
1462                 0x30d00, 0x30d00,
1463                 0x30d08, 0x30d14,
1464                 0x30d1c, 0x30d20,
1465                 0x30d3c, 0x30d3c,
1466                 0x30d48, 0x30d50,
1467                 0x31200, 0x3120c,
1468                 0x31220, 0x31220,
1469                 0x31240, 0x31240,
1470                 0x31600, 0x3160c,
1471                 0x31a00, 0x31a1c,
1472                 0x31e00, 0x31e20,
1473                 0x31e38, 0x31e3c,
1474                 0x31e80, 0x31e80,
1475                 0x31e88, 0x31ea8,
1476                 0x31eb0, 0x31eb4,
1477                 0x31ec8, 0x31ed4,
1478                 0x31fb8, 0x32004,
1479                 0x32200, 0x32200,
1480                 0x32208, 0x32240,
1481                 0x32248, 0x32280,
1482                 0x32288, 0x322c0,
1483                 0x322c8, 0x322fc,
1484                 0x32600, 0x32630,
1485                 0x32a00, 0x32abc,
1486                 0x32b00, 0x32b10,
1487                 0x32b20, 0x32b30,
1488                 0x32b40, 0x32b50,
1489                 0x32b60, 0x32b70,
1490                 0x33000, 0x33028,
1491                 0x33030, 0x33048,
1492                 0x33060, 0x33068,
1493                 0x33070, 0x3309c,
1494                 0x330f0, 0x33128,
1495                 0x33130, 0x33148,
1496                 0x33160, 0x33168,
1497                 0x33170, 0x3319c,
1498                 0x331f0, 0x33238,
1499                 0x33240, 0x33240,
1500                 0x33248, 0x33250,
1501                 0x3325c, 0x33264,
1502                 0x33270, 0x332b8,
1503                 0x332c0, 0x332e4,
1504                 0x332f8, 0x33338,
1505                 0x33340, 0x33340,
1506                 0x33348, 0x33350,
1507                 0x3335c, 0x33364,
1508                 0x33370, 0x333b8,
1509                 0x333c0, 0x333e4,
1510                 0x333f8, 0x33428,
1511                 0x33430, 0x33448,
1512                 0x33460, 0x33468,
1513                 0x33470, 0x3349c,
1514                 0x334f0, 0x33528,
1515                 0x33530, 0x33548,
1516                 0x33560, 0x33568,
1517                 0x33570, 0x3359c,
1518                 0x335f0, 0x33638,
1519                 0x33640, 0x33640,
1520                 0x33648, 0x33650,
1521                 0x3365c, 0x33664,
1522                 0x33670, 0x336b8,
1523                 0x336c0, 0x336e4,
1524                 0x336f8, 0x33738,
1525                 0x33740, 0x33740,
1526                 0x33748, 0x33750,
1527                 0x3375c, 0x33764,
1528                 0x33770, 0x337b8,
1529                 0x337c0, 0x337e4,
1530                 0x337f8, 0x337fc,
1531                 0x33814, 0x33814,
1532                 0x3382c, 0x3382c,
1533                 0x33880, 0x3388c,
1534                 0x338e8, 0x338ec,
1535                 0x33900, 0x33928,
1536                 0x33930, 0x33948,
1537                 0x33960, 0x33968,
1538                 0x33970, 0x3399c,
1539                 0x339f0, 0x33a38,
1540                 0x33a40, 0x33a40,
1541                 0x33a48, 0x33a50,
1542                 0x33a5c, 0x33a64,
1543                 0x33a70, 0x33ab8,
1544                 0x33ac0, 0x33ae4,
1545                 0x33af8, 0x33b10,
1546                 0x33b28, 0x33b28,
1547                 0x33b3c, 0x33b50,
1548                 0x33bf0, 0x33c10,
1549                 0x33c28, 0x33c28,
1550                 0x33c3c, 0x33c50,
1551                 0x33cf0, 0x33cfc,
1552                 0x34000, 0x34030,
1553                 0x34100, 0x34144,
1554                 0x34190, 0x341a0,
1555                 0x341a8, 0x341b8,
1556                 0x341c4, 0x341c8,
1557                 0x341d0, 0x341d0,
1558                 0x34200, 0x34318,
1559                 0x34400, 0x344b4,
1560                 0x344c0, 0x3452c,
1561                 0x34540, 0x3461c,
1562                 0x34800, 0x34828,
1563                 0x34834, 0x34834,
1564                 0x348c0, 0x34908,
1565                 0x34910, 0x349ac,
1566                 0x34a00, 0x34a14,
1567                 0x34a1c, 0x34a2c,
1568                 0x34a44, 0x34a50,
1569                 0x34a74, 0x34a74,
1570                 0x34a7c, 0x34afc,
1571                 0x34b08, 0x34c24,
1572                 0x34d00, 0x34d00,
1573                 0x34d08, 0x34d14,
1574                 0x34d1c, 0x34d20,
1575                 0x34d3c, 0x34d3c,
1576                 0x34d48, 0x34d50,
1577                 0x35200, 0x3520c,
1578                 0x35220, 0x35220,
1579                 0x35240, 0x35240,
1580                 0x35600, 0x3560c,
1581                 0x35a00, 0x35a1c,
1582                 0x35e00, 0x35e20,
1583                 0x35e38, 0x35e3c,
1584                 0x35e80, 0x35e80,
1585                 0x35e88, 0x35ea8,
1586                 0x35eb0, 0x35eb4,
1587                 0x35ec8, 0x35ed4,
1588                 0x35fb8, 0x36004,
1589                 0x36200, 0x36200,
1590                 0x36208, 0x36240,
1591                 0x36248, 0x36280,
1592                 0x36288, 0x362c0,
1593                 0x362c8, 0x362fc,
1594                 0x36600, 0x36630,
1595                 0x36a00, 0x36abc,
1596                 0x36b00, 0x36b10,
1597                 0x36b20, 0x36b30,
1598                 0x36b40, 0x36b50,
1599                 0x36b60, 0x36b70,
1600                 0x37000, 0x37028,
1601                 0x37030, 0x37048,
1602                 0x37060, 0x37068,
1603                 0x37070, 0x3709c,
1604                 0x370f0, 0x37128,
1605                 0x37130, 0x37148,
1606                 0x37160, 0x37168,
1607                 0x37170, 0x3719c,
1608                 0x371f0, 0x37238,
1609                 0x37240, 0x37240,
1610                 0x37248, 0x37250,
1611                 0x3725c, 0x37264,
1612                 0x37270, 0x372b8,
1613                 0x372c0, 0x372e4,
1614                 0x372f8, 0x37338,
1615                 0x37340, 0x37340,
1616                 0x37348, 0x37350,
1617                 0x3735c, 0x37364,
1618                 0x37370, 0x373b8,
1619                 0x373c0, 0x373e4,
1620                 0x373f8, 0x37428,
1621                 0x37430, 0x37448,
1622                 0x37460, 0x37468,
1623                 0x37470, 0x3749c,
1624                 0x374f0, 0x37528,
1625                 0x37530, 0x37548,
1626                 0x37560, 0x37568,
1627                 0x37570, 0x3759c,
1628                 0x375f0, 0x37638,
1629                 0x37640, 0x37640,
1630                 0x37648, 0x37650,
1631                 0x3765c, 0x37664,
1632                 0x37670, 0x376b8,
1633                 0x376c0, 0x376e4,
1634                 0x376f8, 0x37738,
1635                 0x37740, 0x37740,
1636                 0x37748, 0x37750,
1637                 0x3775c, 0x37764,
1638                 0x37770, 0x377b8,
1639                 0x377c0, 0x377e4,
1640                 0x377f8, 0x377fc,
1641                 0x37814, 0x37814,
1642                 0x3782c, 0x3782c,
1643                 0x37880, 0x3788c,
1644                 0x378e8, 0x378ec,
1645                 0x37900, 0x37928,
1646                 0x37930, 0x37948,
1647                 0x37960, 0x37968,
1648                 0x37970, 0x3799c,
1649                 0x379f0, 0x37a38,
1650                 0x37a40, 0x37a40,
1651                 0x37a48, 0x37a50,
1652                 0x37a5c, 0x37a64,
1653                 0x37a70, 0x37ab8,
1654                 0x37ac0, 0x37ae4,
1655                 0x37af8, 0x37b10,
1656                 0x37b28, 0x37b28,
1657                 0x37b3c, 0x37b50,
1658                 0x37bf0, 0x37c10,
1659                 0x37c28, 0x37c28,
1660                 0x37c3c, 0x37c50,
1661                 0x37cf0, 0x37cfc,
1662                 0x38000, 0x38030,
1663                 0x38100, 0x38144,
1664                 0x38190, 0x381a0,
1665                 0x381a8, 0x381b8,
1666                 0x381c4, 0x381c8,
1667                 0x381d0, 0x381d0,
1668                 0x38200, 0x38318,
1669                 0x38400, 0x384b4,
1670                 0x384c0, 0x3852c,
1671                 0x38540, 0x3861c,
1672                 0x38800, 0x38828,
1673                 0x38834, 0x38834,
1674                 0x388c0, 0x38908,
1675                 0x38910, 0x389ac,
1676                 0x38a00, 0x38a14,
1677                 0x38a1c, 0x38a2c,
1678                 0x38a44, 0x38a50,
1679                 0x38a74, 0x38a74,
1680                 0x38a7c, 0x38afc,
1681                 0x38b08, 0x38c24,
1682                 0x38d00, 0x38d00,
1683                 0x38d08, 0x38d14,
1684                 0x38d1c, 0x38d20,
1685                 0x38d3c, 0x38d3c,
1686                 0x38d48, 0x38d50,
1687                 0x39200, 0x3920c,
1688                 0x39220, 0x39220,
1689                 0x39240, 0x39240,
1690                 0x39600, 0x3960c,
1691                 0x39a00, 0x39a1c,
1692                 0x39e00, 0x39e20,
1693                 0x39e38, 0x39e3c,
1694                 0x39e80, 0x39e80,
1695                 0x39e88, 0x39ea8,
1696                 0x39eb0, 0x39eb4,
1697                 0x39ec8, 0x39ed4,
1698                 0x39fb8, 0x3a004,
1699                 0x3a200, 0x3a200,
1700                 0x3a208, 0x3a240,
1701                 0x3a248, 0x3a280,
1702                 0x3a288, 0x3a2c0,
1703                 0x3a2c8, 0x3a2fc,
1704                 0x3a600, 0x3a630,
1705                 0x3aa00, 0x3aabc,
1706                 0x3ab00, 0x3ab10,
1707                 0x3ab20, 0x3ab30,
1708                 0x3ab40, 0x3ab50,
1709                 0x3ab60, 0x3ab70,
1710                 0x3b000, 0x3b028,
1711                 0x3b030, 0x3b048,
1712                 0x3b060, 0x3b068,
1713                 0x3b070, 0x3b09c,
1714                 0x3b0f0, 0x3b128,
1715                 0x3b130, 0x3b148,
1716                 0x3b160, 0x3b168,
1717                 0x3b170, 0x3b19c,
1718                 0x3b1f0, 0x3b238,
1719                 0x3b240, 0x3b240,
1720                 0x3b248, 0x3b250,
1721                 0x3b25c, 0x3b264,
1722                 0x3b270, 0x3b2b8,
1723                 0x3b2c0, 0x3b2e4,
1724                 0x3b2f8, 0x3b338,
1725                 0x3b340, 0x3b340,
1726                 0x3b348, 0x3b350,
1727                 0x3b35c, 0x3b364,
1728                 0x3b370, 0x3b3b8,
1729                 0x3b3c0, 0x3b3e4,
1730                 0x3b3f8, 0x3b428,
1731                 0x3b430, 0x3b448,
1732                 0x3b460, 0x3b468,
1733                 0x3b470, 0x3b49c,
1734                 0x3b4f0, 0x3b528,
1735                 0x3b530, 0x3b548,
1736                 0x3b560, 0x3b568,
1737                 0x3b570, 0x3b59c,
1738                 0x3b5f0, 0x3b638,
1739                 0x3b640, 0x3b640,
1740                 0x3b648, 0x3b650,
1741                 0x3b65c, 0x3b664,
1742                 0x3b670, 0x3b6b8,
1743                 0x3b6c0, 0x3b6e4,
1744                 0x3b6f8, 0x3b738,
1745                 0x3b740, 0x3b740,
1746                 0x3b748, 0x3b750,
1747                 0x3b75c, 0x3b764,
1748                 0x3b770, 0x3b7b8,
1749                 0x3b7c0, 0x3b7e4,
1750                 0x3b7f8, 0x3b7fc,
1751                 0x3b814, 0x3b814,
1752                 0x3b82c, 0x3b82c,
1753                 0x3b880, 0x3b88c,
1754                 0x3b8e8, 0x3b8ec,
1755                 0x3b900, 0x3b928,
1756                 0x3b930, 0x3b948,
1757                 0x3b960, 0x3b968,
1758                 0x3b970, 0x3b99c,
1759                 0x3b9f0, 0x3ba38,
1760                 0x3ba40, 0x3ba40,
1761                 0x3ba48, 0x3ba50,
1762                 0x3ba5c, 0x3ba64,
1763                 0x3ba70, 0x3bab8,
1764                 0x3bac0, 0x3bae4,
1765                 0x3baf8, 0x3bb10,
1766                 0x3bb28, 0x3bb28,
1767                 0x3bb3c, 0x3bb50,
1768                 0x3bbf0, 0x3bc10,
1769                 0x3bc28, 0x3bc28,
1770                 0x3bc3c, 0x3bc50,
1771                 0x3bcf0, 0x3bcfc,
1772                 0x3c000, 0x3c030,
1773                 0x3c100, 0x3c144,
1774                 0x3c190, 0x3c1a0,
1775                 0x3c1a8, 0x3c1b8,
1776                 0x3c1c4, 0x3c1c8,
1777                 0x3c1d0, 0x3c1d0,
1778                 0x3c200, 0x3c318,
1779                 0x3c400, 0x3c4b4,
1780                 0x3c4c0, 0x3c52c,
1781                 0x3c540, 0x3c61c,
1782                 0x3c800, 0x3c828,
1783                 0x3c834, 0x3c834,
1784                 0x3c8c0, 0x3c908,
1785                 0x3c910, 0x3c9ac,
1786                 0x3ca00, 0x3ca14,
1787                 0x3ca1c, 0x3ca2c,
1788                 0x3ca44, 0x3ca50,
1789                 0x3ca74, 0x3ca74,
1790                 0x3ca7c, 0x3cafc,
1791                 0x3cb08, 0x3cc24,
1792                 0x3cd00, 0x3cd00,
1793                 0x3cd08, 0x3cd14,
1794                 0x3cd1c, 0x3cd20,
1795                 0x3cd3c, 0x3cd3c,
1796                 0x3cd48, 0x3cd50,
1797                 0x3d200, 0x3d20c,
1798                 0x3d220, 0x3d220,
1799                 0x3d240, 0x3d240,
1800                 0x3d600, 0x3d60c,
1801                 0x3da00, 0x3da1c,
1802                 0x3de00, 0x3de20,
1803                 0x3de38, 0x3de3c,
1804                 0x3de80, 0x3de80,
1805                 0x3de88, 0x3dea8,
1806                 0x3deb0, 0x3deb4,
1807                 0x3dec8, 0x3ded4,
1808                 0x3dfb8, 0x3e004,
1809                 0x3e200, 0x3e200,
1810                 0x3e208, 0x3e240,
1811                 0x3e248, 0x3e280,
1812                 0x3e288, 0x3e2c0,
1813                 0x3e2c8, 0x3e2fc,
1814                 0x3e600, 0x3e630,
1815                 0x3ea00, 0x3eabc,
1816                 0x3eb00, 0x3eb10,
1817                 0x3eb20, 0x3eb30,
1818                 0x3eb40, 0x3eb50,
1819                 0x3eb60, 0x3eb70,
1820                 0x3f000, 0x3f028,
1821                 0x3f030, 0x3f048,
1822                 0x3f060, 0x3f068,
1823                 0x3f070, 0x3f09c,
1824                 0x3f0f0, 0x3f128,
1825                 0x3f130, 0x3f148,
1826                 0x3f160, 0x3f168,
1827                 0x3f170, 0x3f19c,
1828                 0x3f1f0, 0x3f238,
1829                 0x3f240, 0x3f240,
1830                 0x3f248, 0x3f250,
1831                 0x3f25c, 0x3f264,
1832                 0x3f270, 0x3f2b8,
1833                 0x3f2c0, 0x3f2e4,
1834                 0x3f2f8, 0x3f338,
1835                 0x3f340, 0x3f340,
1836                 0x3f348, 0x3f350,
1837                 0x3f35c, 0x3f364,
1838                 0x3f370, 0x3f3b8,
1839                 0x3f3c0, 0x3f3e4,
1840                 0x3f3f8, 0x3f428,
1841                 0x3f430, 0x3f448,
1842                 0x3f460, 0x3f468,
1843                 0x3f470, 0x3f49c,
1844                 0x3f4f0, 0x3f528,
1845                 0x3f530, 0x3f548,
1846                 0x3f560, 0x3f568,
1847                 0x3f570, 0x3f59c,
1848                 0x3f5f0, 0x3f638,
1849                 0x3f640, 0x3f640,
1850                 0x3f648, 0x3f650,
1851                 0x3f65c, 0x3f664,
1852                 0x3f670, 0x3f6b8,
1853                 0x3f6c0, 0x3f6e4,
1854                 0x3f6f8, 0x3f738,
1855                 0x3f740, 0x3f740,
1856                 0x3f748, 0x3f750,
1857                 0x3f75c, 0x3f764,
1858                 0x3f770, 0x3f7b8,
1859                 0x3f7c0, 0x3f7e4,
1860                 0x3f7f8, 0x3f7fc,
1861                 0x3f814, 0x3f814,
1862                 0x3f82c, 0x3f82c,
1863                 0x3f880, 0x3f88c,
1864                 0x3f8e8, 0x3f8ec,
1865                 0x3f900, 0x3f928,
1866                 0x3f930, 0x3f948,
1867                 0x3f960, 0x3f968,
1868                 0x3f970, 0x3f99c,
1869                 0x3f9f0, 0x3fa38,
1870                 0x3fa40, 0x3fa40,
1871                 0x3fa48, 0x3fa50,
1872                 0x3fa5c, 0x3fa64,
1873                 0x3fa70, 0x3fab8,
1874                 0x3fac0, 0x3fae4,
1875                 0x3faf8, 0x3fb10,
1876                 0x3fb28, 0x3fb28,
1877                 0x3fb3c, 0x3fb50,
1878                 0x3fbf0, 0x3fc10,
1879                 0x3fc28, 0x3fc28,
1880                 0x3fc3c, 0x3fc50,
1881                 0x3fcf0, 0x3fcfc,
1882                 0x40000, 0x4000c,
1883                 0x40040, 0x40050,
1884                 0x40060, 0x40068,
1885                 0x4007c, 0x4008c,
1886                 0x40094, 0x400b0,
1887                 0x400c0, 0x40144,
1888                 0x40180, 0x4018c,
1889                 0x40200, 0x40254,
1890                 0x40260, 0x40264,
1891                 0x40270, 0x40288,
1892                 0x40290, 0x40298,
1893                 0x402ac, 0x402c8,
1894                 0x402d0, 0x402e0,
1895                 0x402f0, 0x402f0,
1896                 0x40300, 0x4033c,
1897                 0x403f8, 0x403fc,
1898                 0x41304, 0x413c4,
1899                 0x41400, 0x4140c,
1900                 0x41414, 0x4141c,
1901                 0x41480, 0x414d0,
1902                 0x44000, 0x44054,
1903                 0x4405c, 0x44078,
1904                 0x440c0, 0x44174,
1905                 0x44180, 0x441ac,
1906                 0x441b4, 0x441b8,
1907                 0x441c0, 0x44254,
1908                 0x4425c, 0x44278,
1909                 0x442c0, 0x44374,
1910                 0x44380, 0x443ac,
1911                 0x443b4, 0x443b8,
1912                 0x443c0, 0x44454,
1913                 0x4445c, 0x44478,
1914                 0x444c0, 0x44574,
1915                 0x44580, 0x445ac,
1916                 0x445b4, 0x445b8,
1917                 0x445c0, 0x44654,
1918                 0x4465c, 0x44678,
1919                 0x446c0, 0x44774,
1920                 0x44780, 0x447ac,
1921                 0x447b4, 0x447b8,
1922                 0x447c0, 0x44854,
1923                 0x4485c, 0x44878,
1924                 0x448c0, 0x44974,
1925                 0x44980, 0x449ac,
1926                 0x449b4, 0x449b8,
1927                 0x449c0, 0x449fc,
1928                 0x45000, 0x45004,
1929                 0x45010, 0x45030,
1930                 0x45040, 0x45060,
1931                 0x45068, 0x45068,
1932                 0x45080, 0x45084,
1933                 0x450a0, 0x450b0,
1934                 0x45200, 0x45204,
1935                 0x45210, 0x45230,
1936                 0x45240, 0x45260,
1937                 0x45268, 0x45268,
1938                 0x45280, 0x45284,
1939                 0x452a0, 0x452b0,
1940                 0x460c0, 0x460e4,
1941                 0x47000, 0x4703c,
1942                 0x47044, 0x4708c,
1943                 0x47200, 0x47250,
1944                 0x47400, 0x47408,
1945                 0x47414, 0x47420,
1946                 0x47600, 0x47618,
1947                 0x47800, 0x47814,
1948                 0x48000, 0x4800c,
1949                 0x48040, 0x48050,
1950                 0x48060, 0x48068,
1951                 0x4807c, 0x4808c,
1952                 0x48094, 0x480b0,
1953                 0x480c0, 0x48144,
1954                 0x48180, 0x4818c,
1955                 0x48200, 0x48254,
1956                 0x48260, 0x48264,
1957                 0x48270, 0x48288,
1958                 0x48290, 0x48298,
1959                 0x482ac, 0x482c8,
1960                 0x482d0, 0x482e0,
1961                 0x482f0, 0x482f0,
1962                 0x48300, 0x4833c,
1963                 0x483f8, 0x483fc,
1964                 0x49304, 0x493c4,
1965                 0x49400, 0x4940c,
1966                 0x49414, 0x4941c,
1967                 0x49480, 0x494d0,
1968                 0x4c000, 0x4c054,
1969                 0x4c05c, 0x4c078,
1970                 0x4c0c0, 0x4c174,
1971                 0x4c180, 0x4c1ac,
1972                 0x4c1b4, 0x4c1b8,
1973                 0x4c1c0, 0x4c254,
1974                 0x4c25c, 0x4c278,
1975                 0x4c2c0, 0x4c374,
1976                 0x4c380, 0x4c3ac,
1977                 0x4c3b4, 0x4c3b8,
1978                 0x4c3c0, 0x4c454,
1979                 0x4c45c, 0x4c478,
1980                 0x4c4c0, 0x4c574,
1981                 0x4c580, 0x4c5ac,
1982                 0x4c5b4, 0x4c5b8,
1983                 0x4c5c0, 0x4c654,
1984                 0x4c65c, 0x4c678,
1985                 0x4c6c0, 0x4c774,
1986                 0x4c780, 0x4c7ac,
1987                 0x4c7b4, 0x4c7b8,
1988                 0x4c7c0, 0x4c854,
1989                 0x4c85c, 0x4c878,
1990                 0x4c8c0, 0x4c974,
1991                 0x4c980, 0x4c9ac,
1992                 0x4c9b4, 0x4c9b8,
1993                 0x4c9c0, 0x4c9fc,
1994                 0x4d000, 0x4d004,
1995                 0x4d010, 0x4d030,
1996                 0x4d040, 0x4d060,
1997                 0x4d068, 0x4d068,
1998                 0x4d080, 0x4d084,
1999                 0x4d0a0, 0x4d0b0,
2000                 0x4d200, 0x4d204,
2001                 0x4d210, 0x4d230,
2002                 0x4d240, 0x4d260,
2003                 0x4d268, 0x4d268,
2004                 0x4d280, 0x4d284,
2005                 0x4d2a0, 0x4d2b0,
2006                 0x4e0c0, 0x4e0e4,
2007                 0x4f000, 0x4f03c,
2008                 0x4f044, 0x4f08c,
2009                 0x4f200, 0x4f250,
2010                 0x4f400, 0x4f408,
2011                 0x4f414, 0x4f420,
2012                 0x4f600, 0x4f618,
2013                 0x4f800, 0x4f814,
2014                 0x50000, 0x50084,
2015                 0x50090, 0x500cc,
2016                 0x50400, 0x50400,
2017                 0x50800, 0x50884,
2018                 0x50890, 0x508cc,
2019                 0x50c00, 0x50c00,
2020                 0x51000, 0x5101c,
2021                 0x51300, 0x51308,
2022         };
2023
2024         static const unsigned int t6_reg_ranges[] = {
2025                 0x1008, 0x101c,
2026                 0x1024, 0x10a8,
2027                 0x10b4, 0x10f8,
2028                 0x1100, 0x1114,
2029                 0x111c, 0x112c,
2030                 0x1138, 0x113c,
2031                 0x1144, 0x114c,
2032                 0x1180, 0x1184,
2033                 0x1190, 0x1194,
2034                 0x11a0, 0x11a4,
2035                 0x11b0, 0x11b4,
2036                 0x11fc, 0x1274,
2037                 0x1280, 0x133c,
2038                 0x1800, 0x18fc,
2039                 0x3000, 0x302c,
2040                 0x3060, 0x30b0,
2041                 0x30b8, 0x30d8,
2042                 0x30e0, 0x30fc,
2043                 0x3140, 0x357c,
2044                 0x35a8, 0x35cc,
2045                 0x35ec, 0x35ec,
2046                 0x3600, 0x5624,
2047                 0x56cc, 0x56ec,
2048                 0x56f4, 0x5720,
2049                 0x5728, 0x575c,
2050                 0x580c, 0x5814,
2051                 0x5890, 0x589c,
2052                 0x58a4, 0x58ac,
2053                 0x58b8, 0x58bc,
2054                 0x5940, 0x595c,
2055                 0x5980, 0x598c,
2056                 0x59b0, 0x59c8,
2057                 0x59d0, 0x59dc,
2058                 0x59fc, 0x5a18,
2059                 0x5a60, 0x5a6c,
2060                 0x5a80, 0x5a8c,
2061                 0x5a94, 0x5a9c,
2062                 0x5b94, 0x5bfc,
2063                 0x5c10, 0x5e48,
2064                 0x5e50, 0x5e94,
2065                 0x5ea0, 0x5eb0,
2066                 0x5ec0, 0x5ec0,
2067                 0x5ec8, 0x5ed0,
2068                 0x5ee0, 0x5ee0,
2069                 0x5ef0, 0x5ef0,
2070                 0x5f00, 0x5f00,
2071                 0x6000, 0x6020,
2072                 0x6028, 0x6040,
2073                 0x6058, 0x609c,
2074                 0x60a8, 0x619c,
2075                 0x7700, 0x7798,
2076                 0x77c0, 0x7880,
2077                 0x78cc, 0x78fc,
2078                 0x7b00, 0x7b58,
2079                 0x7b60, 0x7b84,
2080                 0x7b8c, 0x7c54,
2081                 0x7d00, 0x7d38,
2082                 0x7d40, 0x7d84,
2083                 0x7d8c, 0x7ddc,
2084                 0x7de4, 0x7e04,
2085                 0x7e10, 0x7e1c,
2086                 0x7e24, 0x7e38,
2087                 0x7e40, 0x7e44,
2088                 0x7e4c, 0x7e78,
2089                 0x7e80, 0x7edc,
2090                 0x7ee8, 0x7efc,
2091                 0x8dc0, 0x8de4,
2092                 0x8df8, 0x8e04,
2093                 0x8e10, 0x8e84,
2094                 0x8ea0, 0x8f88,
2095                 0x8fb8, 0x9058,
2096                 0x9060, 0x9060,
2097                 0x9068, 0x90f8,
2098                 0x9100, 0x9124,
2099                 0x9400, 0x9470,
2100                 0x9600, 0x9600,
2101                 0x9608, 0x9638,
2102                 0x9640, 0x9704,
2103                 0x9710, 0x971c,
2104                 0x9800, 0x9808,
2105                 0x9820, 0x983c,
2106                 0x9850, 0x9864,
2107                 0x9c00, 0x9c6c,
2108                 0x9c80, 0x9cec,
2109                 0x9d00, 0x9d6c,
2110                 0x9d80, 0x9dec,
2111                 0x9e00, 0x9e6c,
2112                 0x9e80, 0x9eec,
2113                 0x9f00, 0x9f6c,
2114                 0x9f80, 0xa020,
2115                 0xd004, 0xd03c,
2116                 0xd100, 0xd118,
2117                 0xd200, 0xd214,
2118                 0xd220, 0xd234,
2119                 0xd240, 0xd254,
2120                 0xd260, 0xd274,
2121                 0xd280, 0xd294,
2122                 0xd2a0, 0xd2b4,
2123                 0xd2c0, 0xd2d4,
2124                 0xd2e0, 0xd2f4,
2125                 0xd300, 0xd31c,
2126                 0xdfc0, 0xdfe0,
2127                 0xe000, 0xf008,
2128                 0xf010, 0xf018,
2129                 0xf020, 0xf028,
2130                 0x11000, 0x11014,
2131                 0x11048, 0x1106c,
2132                 0x11074, 0x11088,
2133                 0x11098, 0x11120,
2134                 0x1112c, 0x1117c,
2135                 0x11190, 0x112e0,
2136                 0x11300, 0x1130c,
2137                 0x12000, 0x1206c,
2138                 0x19040, 0x1906c,
2139                 0x19078, 0x19080,
2140                 0x1908c, 0x190e8,
2141                 0x190f0, 0x190f8,
2142                 0x19100, 0x19110,
2143                 0x19120, 0x19124,
2144                 0x19150, 0x19194,
2145                 0x1919c, 0x191b0,
2146                 0x191d0, 0x191e8,
2147                 0x19238, 0x19290,
2148                 0x192a4, 0x192b0,
2149                 0x192bc, 0x192bc,
2150                 0x19348, 0x1934c,
2151                 0x193f8, 0x19418,
2152                 0x19420, 0x19428,
2153                 0x19430, 0x19444,
2154                 0x1944c, 0x1946c,
2155                 0x19474, 0x19474,
2156                 0x19490, 0x194cc,
2157                 0x194f0, 0x194f8,
2158                 0x19c00, 0x19c48,
2159                 0x19c50, 0x19c80,
2160                 0x19c94, 0x19c98,
2161                 0x19ca0, 0x19cbc,
2162                 0x19ce4, 0x19ce4,
2163                 0x19cf0, 0x19cf8,
2164                 0x19d00, 0x19d28,
2165                 0x19d50, 0x19d78,
2166                 0x19d94, 0x19d98,
2167                 0x19da0, 0x19dc8,
2168                 0x19df0, 0x19e10,
2169                 0x19e50, 0x19e6c,
2170                 0x19ea0, 0x19ebc,
2171                 0x19ec4, 0x19ef4,
2172                 0x19f04, 0x19f2c,
2173                 0x19f34, 0x19f34,
2174                 0x19f40, 0x19f50,
2175                 0x19f90, 0x19fac,
2176                 0x19fc4, 0x19fc8,
2177                 0x19fd0, 0x19fe4,
2178                 0x1a000, 0x1a004,
2179                 0x1a010, 0x1a06c,
2180                 0x1a0b0, 0x1a0e4,
2181                 0x1a0ec, 0x1a0f8,
2182                 0x1a100, 0x1a108,
2183                 0x1a114, 0x1a120,
2184                 0x1a128, 0x1a130,
2185                 0x1a138, 0x1a138,
2186                 0x1a190, 0x1a1c4,
2187                 0x1a1fc, 0x1a1fc,
2188                 0x1e008, 0x1e00c,
2189                 0x1e040, 0x1e044,
2190                 0x1e04c, 0x1e04c,
2191                 0x1e284, 0x1e290,
2192                 0x1e2c0, 0x1e2c0,
2193                 0x1e2e0, 0x1e2e0,
2194                 0x1e300, 0x1e384,
2195                 0x1e3c0, 0x1e3c8,
2196                 0x1e408, 0x1e40c,
2197                 0x1e440, 0x1e444,
2198                 0x1e44c, 0x1e44c,
2199                 0x1e684, 0x1e690,
2200                 0x1e6c0, 0x1e6c0,
2201                 0x1e6e0, 0x1e6e0,
2202                 0x1e700, 0x1e784,
2203                 0x1e7c0, 0x1e7c8,
2204                 0x1e808, 0x1e80c,
2205                 0x1e840, 0x1e844,
2206                 0x1e84c, 0x1e84c,
2207                 0x1ea84, 0x1ea90,
2208                 0x1eac0, 0x1eac0,
2209                 0x1eae0, 0x1eae0,
2210                 0x1eb00, 0x1eb84,
2211                 0x1ebc0, 0x1ebc8,
2212                 0x1ec08, 0x1ec0c,
2213                 0x1ec40, 0x1ec44,
2214                 0x1ec4c, 0x1ec4c,
2215                 0x1ee84, 0x1ee90,
2216                 0x1eec0, 0x1eec0,
2217                 0x1eee0, 0x1eee0,
2218                 0x1ef00, 0x1ef84,
2219                 0x1efc0, 0x1efc8,
2220                 0x1f008, 0x1f00c,
2221                 0x1f040, 0x1f044,
2222                 0x1f04c, 0x1f04c,
2223                 0x1f284, 0x1f290,
2224                 0x1f2c0, 0x1f2c0,
2225                 0x1f2e0, 0x1f2e0,
2226                 0x1f300, 0x1f384,
2227                 0x1f3c0, 0x1f3c8,
2228                 0x1f408, 0x1f40c,
2229                 0x1f440, 0x1f444,
2230                 0x1f44c, 0x1f44c,
2231                 0x1f684, 0x1f690,
2232                 0x1f6c0, 0x1f6c0,
2233                 0x1f6e0, 0x1f6e0,
2234                 0x1f700, 0x1f784,
2235                 0x1f7c0, 0x1f7c8,
2236                 0x1f808, 0x1f80c,
2237                 0x1f840, 0x1f844,
2238                 0x1f84c, 0x1f84c,
2239                 0x1fa84, 0x1fa90,
2240                 0x1fac0, 0x1fac0,
2241                 0x1fae0, 0x1fae0,
2242                 0x1fb00, 0x1fb84,
2243                 0x1fbc0, 0x1fbc8,
2244                 0x1fc08, 0x1fc0c,
2245                 0x1fc40, 0x1fc44,
2246                 0x1fc4c, 0x1fc4c,
2247                 0x1fe84, 0x1fe90,
2248                 0x1fec0, 0x1fec0,
2249                 0x1fee0, 0x1fee0,
2250                 0x1ff00, 0x1ff84,
2251                 0x1ffc0, 0x1ffc8,
2252                 0x30000, 0x30030,
2253                 0x30100, 0x30168,
2254                 0x30190, 0x301a0,
2255                 0x301a8, 0x301b8,
2256                 0x301c4, 0x301c8,
2257                 0x301d0, 0x301d0,
2258                 0x30200, 0x30320,
2259                 0x30400, 0x304b4,
2260                 0x304c0, 0x3052c,
2261                 0x30540, 0x3061c,
2262                 0x30800, 0x308a0,
2263                 0x308c0, 0x30908,
2264                 0x30910, 0x309b8,
2265                 0x30a00, 0x30a04,
2266                 0x30a0c, 0x30a14,
2267                 0x30a1c, 0x30a2c,
2268                 0x30a44, 0x30a50,
2269                 0x30a74, 0x30a74,
2270                 0x30a7c, 0x30afc,
2271                 0x30b08, 0x30c24,
2272                 0x30d00, 0x30d14,
2273                 0x30d1c, 0x30d3c,
2274                 0x30d44, 0x30d4c,
2275                 0x30d54, 0x30d74,
2276                 0x30d7c, 0x30d7c,
2277                 0x30de0, 0x30de0,
2278                 0x30e00, 0x30ed4,
2279                 0x30f00, 0x30fa4,
2280                 0x30fc0, 0x30fc4,
2281                 0x31000, 0x31004,
2282                 0x31080, 0x310fc,
2283                 0x31208, 0x31220,
2284                 0x3123c, 0x31254,
2285                 0x31300, 0x31300,
2286                 0x31308, 0x3131c,
2287                 0x31338, 0x3133c,
2288                 0x31380, 0x31380,
2289                 0x31388, 0x313a8,
2290                 0x313b4, 0x313b4,
2291                 0x31400, 0x31420,
2292                 0x31438, 0x3143c,
2293                 0x31480, 0x31480,
2294                 0x314a8, 0x314a8,
2295                 0x314b0, 0x314b4,
2296                 0x314c8, 0x314d4,
2297                 0x31a40, 0x31a4c,
2298                 0x31af0, 0x31b20,
2299                 0x31b38, 0x31b3c,
2300                 0x31b80, 0x31b80,
2301                 0x31ba8, 0x31ba8,
2302                 0x31bb0, 0x31bb4,
2303                 0x31bc8, 0x31bd4,
2304                 0x32140, 0x3218c,
2305                 0x321f0, 0x321f4,
2306                 0x32200, 0x32200,
2307                 0x32218, 0x32218,
2308                 0x32400, 0x32400,
2309                 0x32408, 0x3241c,
2310                 0x32618, 0x32620,
2311                 0x32664, 0x32664,
2312                 0x326a8, 0x326a8,
2313                 0x326ec, 0x326ec,
2314                 0x32a00, 0x32abc,
2315                 0x32b00, 0x32b18,
2316                 0x32b20, 0x32b38,
2317                 0x32b40, 0x32b58,
2318                 0x32b60, 0x32b78,
2319                 0x32c00, 0x32c00,
2320                 0x32c08, 0x32c3c,
2321                 0x33000, 0x3302c,
2322                 0x33034, 0x33050,
2323                 0x33058, 0x33058,
2324                 0x33060, 0x3308c,
2325                 0x3309c, 0x330ac,
2326                 0x330c0, 0x330c0,
2327                 0x330c8, 0x330d0,
2328                 0x330d8, 0x330e0,
2329                 0x330ec, 0x3312c,
2330                 0x33134, 0x33150,
2331                 0x33158, 0x33158,
2332                 0x33160, 0x3318c,
2333                 0x3319c, 0x331ac,
2334                 0x331c0, 0x331c0,
2335                 0x331c8, 0x331d0,
2336                 0x331d8, 0x331e0,
2337                 0x331ec, 0x33290,
2338                 0x33298, 0x332c4,
2339                 0x332e4, 0x33390,
2340                 0x33398, 0x333c4,
2341                 0x333e4, 0x3342c,
2342                 0x33434, 0x33450,
2343                 0x33458, 0x33458,
2344                 0x33460, 0x3348c,
2345                 0x3349c, 0x334ac,
2346                 0x334c0, 0x334c0,
2347                 0x334c8, 0x334d0,
2348                 0x334d8, 0x334e0,
2349                 0x334ec, 0x3352c,
2350                 0x33534, 0x33550,
2351                 0x33558, 0x33558,
2352                 0x33560, 0x3358c,
2353                 0x3359c, 0x335ac,
2354                 0x335c0, 0x335c0,
2355                 0x335c8, 0x335d0,
2356                 0x335d8, 0x335e0,
2357                 0x335ec, 0x33690,
2358                 0x33698, 0x336c4,
2359                 0x336e4, 0x33790,
2360                 0x33798, 0x337c4,
2361                 0x337e4, 0x337fc,
2362                 0x33814, 0x33814,
2363                 0x33854, 0x33868,
2364                 0x33880, 0x3388c,
2365                 0x338c0, 0x338d0,
2366                 0x338e8, 0x338ec,
2367                 0x33900, 0x3392c,
2368                 0x33934, 0x33950,
2369                 0x33958, 0x33958,
2370                 0x33960, 0x3398c,
2371                 0x3399c, 0x339ac,
2372                 0x339c0, 0x339c0,
2373                 0x339c8, 0x339d0,
2374                 0x339d8, 0x339e0,
2375                 0x339ec, 0x33a90,
2376                 0x33a98, 0x33ac4,
2377                 0x33ae4, 0x33b10,
2378                 0x33b24, 0x33b28,
2379                 0x33b38, 0x33b50,
2380                 0x33bf0, 0x33c10,
2381                 0x33c24, 0x33c28,
2382                 0x33c38, 0x33c50,
2383                 0x33cf0, 0x33cfc,
2384                 0x34000, 0x34030,
2385                 0x34100, 0x34168,
2386                 0x34190, 0x341a0,
2387                 0x341a8, 0x341b8,
2388                 0x341c4, 0x341c8,
2389                 0x341d0, 0x341d0,
2390                 0x34200, 0x34320,
2391                 0x34400, 0x344b4,
2392                 0x344c0, 0x3452c,
2393                 0x34540, 0x3461c,
2394                 0x34800, 0x348a0,
2395                 0x348c0, 0x34908,
2396                 0x34910, 0x349b8,
2397                 0x34a00, 0x34a04,
2398                 0x34a0c, 0x34a14,
2399                 0x34a1c, 0x34a2c,
2400                 0x34a44, 0x34a50,
2401                 0x34a74, 0x34a74,
2402                 0x34a7c, 0x34afc,
2403                 0x34b08, 0x34c24,
2404                 0x34d00, 0x34d14,
2405                 0x34d1c, 0x34d3c,
2406                 0x34d44, 0x34d4c,
2407                 0x34d54, 0x34d74,
2408                 0x34d7c, 0x34d7c,
2409                 0x34de0, 0x34de0,
2410                 0x34e00, 0x34ed4,
2411                 0x34f00, 0x34fa4,
2412                 0x34fc0, 0x34fc4,
2413                 0x35000, 0x35004,
2414                 0x35080, 0x350fc,
2415                 0x35208, 0x35220,
2416                 0x3523c, 0x35254,
2417                 0x35300, 0x35300,
2418                 0x35308, 0x3531c,
2419                 0x35338, 0x3533c,
2420                 0x35380, 0x35380,
2421                 0x35388, 0x353a8,
2422                 0x353b4, 0x353b4,
2423                 0x35400, 0x35420,
2424                 0x35438, 0x3543c,
2425                 0x35480, 0x35480,
2426                 0x354a8, 0x354a8,
2427                 0x354b0, 0x354b4,
2428                 0x354c8, 0x354d4,
2429                 0x35a40, 0x35a4c,
2430                 0x35af0, 0x35b20,
2431                 0x35b38, 0x35b3c,
2432                 0x35b80, 0x35b80,
2433                 0x35ba8, 0x35ba8,
2434                 0x35bb0, 0x35bb4,
2435                 0x35bc8, 0x35bd4,
2436                 0x36140, 0x3618c,
2437                 0x361f0, 0x361f4,
2438                 0x36200, 0x36200,
2439                 0x36218, 0x36218,
2440                 0x36400, 0x36400,
2441                 0x36408, 0x3641c,
2442                 0x36618, 0x36620,
2443                 0x36664, 0x36664,
2444                 0x366a8, 0x366a8,
2445                 0x366ec, 0x366ec,
2446                 0x36a00, 0x36abc,
2447                 0x36b00, 0x36b18,
2448                 0x36b20, 0x36b38,
2449                 0x36b40, 0x36b58,
2450                 0x36b60, 0x36b78,
2451                 0x36c00, 0x36c00,
2452                 0x36c08, 0x36c3c,
2453                 0x37000, 0x3702c,
2454                 0x37034, 0x37050,
2455                 0x37058, 0x37058,
2456                 0x37060, 0x3708c,
2457                 0x3709c, 0x370ac,
2458                 0x370c0, 0x370c0,
2459                 0x370c8, 0x370d0,
2460                 0x370d8, 0x370e0,
2461                 0x370ec, 0x3712c,
2462                 0x37134, 0x37150,
2463                 0x37158, 0x37158,
2464                 0x37160, 0x3718c,
2465                 0x3719c, 0x371ac,
2466                 0x371c0, 0x371c0,
2467                 0x371c8, 0x371d0,
2468                 0x371d8, 0x371e0,
2469                 0x371ec, 0x37290,
2470                 0x37298, 0x372c4,
2471                 0x372e4, 0x37390,
2472                 0x37398, 0x373c4,
2473                 0x373e4, 0x3742c,
2474                 0x37434, 0x37450,
2475                 0x37458, 0x37458,
2476                 0x37460, 0x3748c,
2477                 0x3749c, 0x374ac,
2478                 0x374c0, 0x374c0,
2479                 0x374c8, 0x374d0,
2480                 0x374d8, 0x374e0,
2481                 0x374ec, 0x3752c,
2482                 0x37534, 0x37550,
2483                 0x37558, 0x37558,
2484                 0x37560, 0x3758c,
2485                 0x3759c, 0x375ac,
2486                 0x375c0, 0x375c0,
2487                 0x375c8, 0x375d0,
2488                 0x375d8, 0x375e0,
2489                 0x375ec, 0x37690,
2490                 0x37698, 0x376c4,
2491                 0x376e4, 0x37790,
2492                 0x37798, 0x377c4,
2493                 0x377e4, 0x377fc,
2494                 0x37814, 0x37814,
2495                 0x37854, 0x37868,
2496                 0x37880, 0x3788c,
2497                 0x378c0, 0x378d0,
2498                 0x378e8, 0x378ec,
2499                 0x37900, 0x3792c,
2500                 0x37934, 0x37950,
2501                 0x37958, 0x37958,
2502                 0x37960, 0x3798c,
2503                 0x3799c, 0x379ac,
2504                 0x379c0, 0x379c0,
2505                 0x379c8, 0x379d0,
2506                 0x379d8, 0x379e0,
2507                 0x379ec, 0x37a90,
2508                 0x37a98, 0x37ac4,
2509                 0x37ae4, 0x37b10,
2510                 0x37b24, 0x37b28,
2511                 0x37b38, 0x37b50,
2512                 0x37bf0, 0x37c10,
2513                 0x37c24, 0x37c28,
2514                 0x37c38, 0x37c50,
2515                 0x37cf0, 0x37cfc,
2516                 0x40040, 0x40040,
2517                 0x40080, 0x40084,
2518                 0x40100, 0x40100,
2519                 0x40140, 0x401bc,
2520                 0x40200, 0x40214,
2521                 0x40228, 0x40228,
2522                 0x40240, 0x40258,
2523                 0x40280, 0x40280,
2524                 0x40304, 0x40304,
2525                 0x40330, 0x4033c,
2526                 0x41304, 0x413c8,
2527                 0x413d0, 0x413dc,
2528                 0x413f0, 0x413f0,
2529                 0x41400, 0x4140c,
2530                 0x41414, 0x4141c,
2531                 0x41480, 0x414d0,
2532                 0x44000, 0x4407c,
2533                 0x440c0, 0x441ac,
2534                 0x441b4, 0x4427c,
2535                 0x442c0, 0x443ac,
2536                 0x443b4, 0x4447c,
2537                 0x444c0, 0x445ac,
2538                 0x445b4, 0x4467c,
2539                 0x446c0, 0x447ac,
2540                 0x447b4, 0x4487c,
2541                 0x448c0, 0x449ac,
2542                 0x449b4, 0x44a7c,
2543                 0x44ac0, 0x44bac,
2544                 0x44bb4, 0x44c7c,
2545                 0x44cc0, 0x44dac,
2546                 0x44db4, 0x44e7c,
2547                 0x44ec0, 0x44fac,
2548                 0x44fb4, 0x4507c,
2549                 0x450c0, 0x451ac,
2550                 0x451b4, 0x451fc,
2551                 0x45800, 0x45804,
2552                 0x45810, 0x45830,
2553                 0x45840, 0x45860,
2554                 0x45868, 0x45868,
2555                 0x45880, 0x45884,
2556                 0x458a0, 0x458b0,
2557                 0x45a00, 0x45a04,
2558                 0x45a10, 0x45a30,
2559                 0x45a40, 0x45a60,
2560                 0x45a68, 0x45a68,
2561                 0x45a80, 0x45a84,
2562                 0x45aa0, 0x45ab0,
2563                 0x460c0, 0x460e4,
2564                 0x47000, 0x4703c,
2565                 0x47044, 0x4708c,
2566                 0x47200, 0x47250,
2567                 0x47400, 0x47408,
2568                 0x47414, 0x47420,
2569                 0x47600, 0x47618,
2570                 0x47800, 0x47814,
2571                 0x47820, 0x4782c,
2572                 0x50000, 0x50084,
2573                 0x50090, 0x500cc,
2574                 0x50300, 0x50384,
2575                 0x50400, 0x50400,
2576                 0x50800, 0x50884,
2577                 0x50890, 0x508cc,
2578                 0x50b00, 0x50b84,
2579                 0x50c00, 0x50c00,
2580                 0x51000, 0x51020,
2581                 0x51028, 0x510b0,
2582                 0x51300, 0x51324,
2583         };
2584
2585         u32 *buf_end = (u32 *)((char *)buf + buf_size);
2586         const unsigned int *reg_ranges;
2587         int reg_ranges_size, range;
2588         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2589
2590         /* Select the right set of register ranges to dump depending on the
2591          * adapter chip type.
2592          */
2593         switch (chip_version) {
2594         case CHELSIO_T4:
2595                 reg_ranges = t4_reg_ranges;
2596                 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2597                 break;
2598
2599         case CHELSIO_T5:
2600                 reg_ranges = t5_reg_ranges;
2601                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2602                 break;
2603
2604         case CHELSIO_T6:
2605                 reg_ranges = t6_reg_ranges;
2606                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2607                 break;
2608
2609         default:
2610                 dev_err(adap->pdev_dev,
2611                         "Unsupported chip version %d\n", chip_version);
2612                 return;
2613         }
2614
2615         /* Clear the register buffer and insert the appropriate register
2616          * values selected by the above register ranges.
2617          */
2618         memset(buf, 0, buf_size);
2619         for (range = 0; range < reg_ranges_size; range += 2) {
2620                 unsigned int reg = reg_ranges[range];
2621                 unsigned int last_reg = reg_ranges[range + 1];
2622                 u32 *bufp = (u32 *)((char *)buf + reg);
2623
2624                 /* Iterate across the register range filling in the register
2625                  * buffer but don't write past the end of the register buffer.
2626                  */
2627                 while (reg <= last_reg && bufp < buf_end) {
2628                         *bufp++ = t4_read_reg(adap, reg);
2629                         reg += sizeof(u32);
2630                 }
2631         }
2632 }
2633
2634 #define EEPROM_STAT_ADDR   0x7bfc
2635 #define VPD_SIZE           0x800
2636 #define VPD_BASE           0x400
2637 #define VPD_BASE_OLD       0
2638 #define VPD_LEN            1024
2639 #define CHELSIO_VPD_UNIQUE_ID 0x82
2640
2641 /**
2642  * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2643  * @phys_addr: the physical EEPROM address
2644  * @fn: the PCI function number
2645  * @sz: size of function-specific area
2646  *
2647  * Translate a physical EEPROM address to virtual.  The first 1K is
2648  * accessed through virtual addresses starting at 31K, the rest is
2649  * accessed through virtual addresses starting at 0.
2650  *
2651  * The mapping is as follows:
2652  * [0..1K) -> [31K..32K)
2653  * [1K..1K+A) -> [31K-A..31K)
2654  * [1K+A..ES) -> [0..ES-A-1K)
2655  *
2656  * where A = @fn * @sz, and ES = EEPROM size.
2657  */
2658 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2659 {
2660         fn *= sz;
2661         if (phys_addr < 1024)
2662                 return phys_addr + (31 << 10);
2663         if (phys_addr < 1024 + fn)
2664                 return 31744 - fn + phys_addr - 1024;
2665         if (phys_addr < EEPROMSIZE)
2666                 return phys_addr - 1024 - fn;
2667         return -EINVAL;
2668 }
2669
2670 /**
2671  *      t4_seeprom_wp - enable/disable EEPROM write protection
2672  *      @adapter: the adapter
2673  *      @enable: whether to enable or disable write protection
2674  *
2675  *      Enables or disables write protection on the serial EEPROM.
2676  */
2677 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2678 {
2679         unsigned int v = enable ? 0xc : 0;
2680         int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2681         return ret < 0 ? ret : 0;
2682 }
2683
2684 /**
2685  *      t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2686  *      @adapter: adapter to read
2687  *      @p: where to store the parameters
2688  *
2689  *      Reads card parameters stored in VPD EEPROM.
2690  */
2691 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2692 {
2693         int i, ret = 0, addr;
2694         int ec, sn, pn, na;
2695         u8 *vpd, csum;
2696         unsigned int vpdr_len, kw_offset, id_len;
2697
2698         vpd = vmalloc(VPD_LEN);
2699         if (!vpd)
2700                 return -ENOMEM;
2701
2702         /* We have two VPD data structures stored in the adapter VPD area.
2703          * By default, Linux calculates the size of the VPD area by traversing
2704          * the first VPD area at offset 0x0, so we need to tell the OS what
2705          * our real VPD size is.
2706          */
2707         ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2708         if (ret < 0)
2709                 goto out;
2710
2711         /* Card information normally starts at VPD_BASE but early cards had
2712          * it at 0.
2713          */
2714         ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2715         if (ret < 0)
2716                 goto out;
2717
2718         /* The VPD shall have a unique identifier specified by the PCI SIG.
2719          * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2720          * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2721          * is expected to automatically put this entry at the
2722          * beginning of the VPD.
2723          */
2724         addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2725
2726         ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2727         if (ret < 0)
2728                 goto out;
2729
2730         if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2731                 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2732                 ret = -EINVAL;
2733                 goto out;
2734         }
2735
2736         id_len = pci_vpd_lrdt_size(vpd);
2737         if (id_len > ID_LEN)
2738                 id_len = ID_LEN;
2739
2740         i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2741         if (i < 0) {
2742                 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2743                 ret = -EINVAL;
2744                 goto out;
2745         }
2746
2747         vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2748         kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2749         if (vpdr_len + kw_offset > VPD_LEN) {
2750                 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2751                 ret = -EINVAL;
2752                 goto out;
2753         }
2754
2755 #define FIND_VPD_KW(var, name) do { \
2756         var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2757         if (var < 0) { \
2758                 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2759                 ret = -EINVAL; \
2760                 goto out; \
2761         } \
2762         var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2763 } while (0)
2764
2765         FIND_VPD_KW(i, "RV");
2766         for (csum = 0; i >= 0; i--)
2767                 csum += vpd[i];
2768
2769         if (csum) {
2770                 dev_err(adapter->pdev_dev,
2771                         "corrupted VPD EEPROM, actual csum %u\n", csum);
2772                 ret = -EINVAL;
2773                 goto out;
2774         }
2775
2776         FIND_VPD_KW(ec, "EC");
2777         FIND_VPD_KW(sn, "SN");
2778         FIND_VPD_KW(pn, "PN");
2779         FIND_VPD_KW(na, "NA");
2780 #undef FIND_VPD_KW
2781
2782         memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2783         strim(p->id);
2784         memcpy(p->ec, vpd + ec, EC_LEN);
2785         strim(p->ec);
2786         i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2787         memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2788         strim(p->sn);
2789         i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2790         memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2791         strim(p->pn);
2792         memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2793         strim((char *)p->na);
2794
2795 out:
2796         vfree(vpd);
2797         return ret < 0 ? ret : 0;
2798 }
2799
2800 /**
2801  *      t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2802  *      @adapter: adapter to read
2803  *      @p: where to store the parameters
2804  *
2805  *      Reads card parameters stored in VPD EEPROM and retrieves the Core
2806  *      Clock.  This can only be called after a connection to the firmware
2807  *      is established.
2808  */
2809 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2810 {
2811         u32 cclk_param, cclk_val;
2812         int ret;
2813
2814         /* Grab the raw VPD parameters.
2815          */
2816         ret = t4_get_raw_vpd_params(adapter, p);
2817         if (ret)
2818                 return ret;
2819
2820         /* Ask firmware for the Core Clock since it knows how to translate the
2821          * Reference Clock ('V2') VPD field into a Core Clock value ...
2822          */
2823         cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2824                       FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2825         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2826                               1, &cclk_param, &cclk_val);
2827
2828         if (ret)
2829                 return ret;
2830         p->cclk = cclk_val;
2831
2832         return 0;
2833 }
2834
2835 /* serial flash and firmware constants */
2836 enum {
2837         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2838
2839         /* flash command opcodes */
2840         SF_PROG_PAGE    = 2,          /* program page */
2841         SF_WR_DISABLE   = 4,          /* disable writes */
2842         SF_RD_STATUS    = 5,          /* read status register */
2843         SF_WR_ENABLE    = 6,          /* enable writes */
2844         SF_RD_DATA_FAST = 0xb,        /* read flash */
2845         SF_RD_ID        = 0x9f,       /* read ID */
2846         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2847 };
2848
2849 /**
2850  *      sf1_read - read data from the serial flash
2851  *      @adapter: the adapter
2852  *      @byte_cnt: number of bytes to read
2853  *      @cont: whether another operation will be chained
2854  *      @lock: whether to lock SF for PL access only
2855  *      @valp: where to store the read data
2856  *
2857  *      Reads up to 4 bytes of data from the serial flash.  The location of
2858  *      the read needs to be specified prior to calling this by issuing the
2859  *      appropriate commands to the serial flash.
2860  */
2861 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2862                     int lock, u32 *valp)
2863 {
2864         int ret;
2865
2866         if (!byte_cnt || byte_cnt > 4)
2867                 return -EINVAL;
2868         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2869                 return -EBUSY;
2870         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2871                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2872         ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2873         if (!ret)
2874                 *valp = t4_read_reg(adapter, SF_DATA_A);
2875         return ret;
2876 }
2877
2878 /**
2879  *      sf1_write - write data to the serial flash
2880  *      @adapter: the adapter
2881  *      @byte_cnt: number of bytes to write
2882  *      @cont: whether another operation will be chained
2883  *      @lock: whether to lock SF for PL access only
2884  *      @val: value to write
2885  *
2886  *      Writes up to 4 bytes of data to the serial flash.  The location of
2887  *      the write needs to be specified prior to calling this by issuing the
2888  *      appropriate commands to the serial flash.
2889  */
2890 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2891                      int lock, u32 val)
2892 {
2893         if (!byte_cnt || byte_cnt > 4)
2894                 return -EINVAL;
2895         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2896                 return -EBUSY;
2897         t4_write_reg(adapter, SF_DATA_A, val);
2898         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2899                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2900         return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2901 }
2902
2903 /**
2904  *      flash_wait_op - wait for a flash operation to complete
2905  *      @adapter: the adapter
2906  *      @attempts: max number of polls of the status register
2907  *      @delay: delay between polls in ms
2908  *
2909  *      Wait for a flash operation to complete by polling the status register.
2910  */
2911 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2912 {
2913         int ret;
2914         u32 status;
2915
2916         while (1) {
2917                 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2918                     (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2919                         return ret;
2920                 if (!(status & 1))
2921                         return 0;
2922                 if (--attempts == 0)
2923                         return -EAGAIN;
2924                 if (delay)
2925                         msleep(delay);
2926         }
2927 }
2928
2929 /**
2930  *      t4_read_flash - read words from serial flash
2931  *      @adapter: the adapter
2932  *      @addr: the start address for the read
2933  *      @nwords: how many 32-bit words to read
2934  *      @data: where to store the read data
2935  *      @byte_oriented: whether to store data as bytes or as words
2936  *
2937  *      Read the specified number of 32-bit words from the serial flash.
2938  *      If @byte_oriented is set the read data is stored as a byte array
2939  *      (i.e., big-endian), otherwise as 32-bit words in the platform's
2940  *      natural endianness.
2941  */
2942 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2943                   unsigned int nwords, u32 *data, int byte_oriented)
2944 {
2945         int ret;
2946
2947         if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2948                 return -EINVAL;
2949
2950         addr = swab32(addr) | SF_RD_DATA_FAST;
2951
2952         if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2953             (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2954                 return ret;
2955
2956         for ( ; nwords; nwords--, data++) {
2957                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2958                 if (nwords == 1)
2959                         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2960                 if (ret)
2961                         return ret;
2962                 if (byte_oriented)
2963                         *data = (__force __u32)(cpu_to_be32(*data));
2964         }
2965         return 0;
2966 }
2967
2968 /**
2969  *      t4_write_flash - write up to a page of data to the serial flash
2970  *      @adapter: the adapter
2971  *      @addr: the start address to write
2972  *      @n: length of data to write in bytes
2973  *      @data: the data to write
2974  *
2975  *      Writes up to a page of data (256 bytes) to the serial flash starting
2976  *      at the given address.  All the data must be written to the same page.
2977  */
2978 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2979                           unsigned int n, const u8 *data)
2980 {
2981         int ret;
2982         u32 buf[64];
2983         unsigned int i, c, left, val, offset = addr & 0xff;
2984
2985         if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2986                 return -EINVAL;
2987
2988         val = swab32(addr) | SF_PROG_PAGE;
2989
2990         if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2991             (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2992                 goto unlock;
2993
2994         for (left = n; left; left -= c) {
2995                 c = min(left, 4U);
2996                 for (val = 0, i = 0; i < c; ++i)
2997                         val = (val << 8) + *data++;
2998
2999                 ret = sf1_write(adapter, c, c != left, 1, val);
3000                 if (ret)
3001                         goto unlock;
3002         }
3003         ret = flash_wait_op(adapter, 8, 1);
3004         if (ret)
3005                 goto unlock;
3006
3007         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3008
3009         /* Read the page to verify the write succeeded */
3010         ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
3011         if (ret)
3012                 return ret;
3013
3014         if (memcmp(data - n, (u8 *)buf + offset, n)) {
3015                 dev_err(adapter->pdev_dev,
3016                         "failed to correctly write the flash page at %#x\n",
3017                         addr);
3018                 return -EIO;
3019         }
3020         return 0;
3021
3022 unlock:
3023         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3024         return ret;
3025 }
3026
3027 /**
3028  *      t4_get_fw_version - read the firmware version
3029  *      @adapter: the adapter
3030  *      @vers: where to place the version
3031  *
3032  *      Reads the FW version from flash.
3033  */
3034 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3035 {
3036         return t4_read_flash(adapter, FLASH_FW_START +
3037                              offsetof(struct fw_hdr, fw_ver), 1,
3038                              vers, 0);
3039 }
3040
3041 /**
3042  *      t4_get_bs_version - read the firmware bootstrap version
3043  *      @adapter: the adapter
3044  *      @vers: where to place the version
3045  *
3046  *      Reads the FW Bootstrap version from flash.
3047  */
3048 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3049 {
3050         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3051                              offsetof(struct fw_hdr, fw_ver), 1,
3052                              vers, 0);
3053 }
3054
3055 /**
3056  *      t4_get_tp_version - read the TP microcode version
3057  *      @adapter: the adapter
3058  *      @vers: where to place the version
3059  *
3060  *      Reads the TP microcode version from flash.
3061  */
3062 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3063 {
3064         return t4_read_flash(adapter, FLASH_FW_START +
3065                              offsetof(struct fw_hdr, tp_microcode_ver),
3066                              1, vers, 0);
3067 }
3068
3069 /**
3070  *      t4_get_exprom_version - return the Expansion ROM version (if any)
3071  *      @adapter: the adapter
3072  *      @vers: where to place the version
3073  *
3074  *      Reads the Expansion ROM header from FLASH and returns the version
3075  *      number (if present) through the @vers return value pointer.  We return
3076  *      this in the Firmware Version Format since it's convenient.  Return
3077  *      0 on success, -ENOENT if no Expansion ROM is present.
3078  */
3079 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3080 {
3081         struct exprom_header {
3082                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
3083                 unsigned char hdr_ver[4];       /* Expansion ROM version */
3084         } *hdr;
3085         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3086                                            sizeof(u32))];
3087         int ret;
3088
3089         ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3090                             ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3091                             0);
3092         if (ret)
3093                 return ret;
3094
3095         hdr = (struct exprom_header *)exprom_header_buf;
3096         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3097                 return -ENOENT;
3098
3099         *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3100                  FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3101                  FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3102                  FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3103         return 0;
3104 }
3105
3106 /**
3107  *      t4_get_vpd_version - return the VPD version
3108  *      @adapter: the adapter
3109  *      @vers: where to place the version
3110  *
3111  *      Reads the VPD via the Firmware interface (thus this can only be called
3112  *      once we're ready to issue Firmware commands).  The format of the
3113  *      VPD version is adapter specific.  Returns 0 on success, an error on
3114  *      failure.
3115  *
3116  *      Note that early versions of the Firmware didn't include the ability
3117  *      to retrieve the VPD version, so we zero-out the return-value parameter
3118  *      in that case to avoid leaving it with garbage in it.
3119  *
3120  *      Also note that the Firmware will return its cached copy of the VPD
3121  *      Revision ID, not the actual Revision ID as written in the Serial
3122  *      EEPROM.  This is only an issue if a new VPD has been written and the
3123  *      Firmware/Chip haven't yet gone through a RESET sequence.  So it's best
3124  *      to defer calling this routine till after a FW_RESET_CMD has been issued
3125  *      if the Host Driver will be performing a full adapter initialization.
3126  */
3127 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3128 {
3129         u32 vpdrev_param;
3130         int ret;
3131
3132         vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3133                         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3134         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3135                               1, &vpdrev_param, vers);
3136         if (ret)
3137                 *vers = 0;
3138         return ret;
3139 }
3140
3141 /**
3142  *      t4_get_scfg_version - return the Serial Configuration version
3143  *      @adapter: the adapter
3144  *      @vers: where to place the version
3145  *
3146  *      Reads the Serial Configuration Version via the Firmware interface
3147  *      (thus this can only be called once we're ready to issue Firmware
3148  *      commands).  The format of the Serial Configuration version is
3149  *      adapter specific.  Returns 0 on success, an error on failure.
3150  *
3151  *      Note that early versions of the Firmware didn't include the ability
3152  *      to retrieve the Serial Configuration version, so we zero-out the
3153  *      return-value parameter in that case to avoid leaving it with
3154  *      garbage in it.
3155  *
3156  *      Also note that the Firmware will return its cached copy of the Serial
3157  *      Initialization Revision ID, not the actual Revision ID as written in
3158  *      the Serial EEPROM.  This is only an issue if a new VPD has been written
3159  *      and the Firmware/Chip haven't yet gone through a RESET sequence.  So
3160  *      it's best to defer calling this routine till after a FW_RESET_CMD has
3161  *      been issued if the Host Driver will be performing a full adapter
3162  *      initialization.
3163  */
3164 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3165 {
3166         u32 scfgrev_param;
3167         int ret;
3168
3169         scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3170                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3171         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3172                               1, &scfgrev_param, vers);
3173         if (ret)
3174                 *vers = 0;
3175         return ret;
3176 }
3177
3178 /**
3179  *      t4_get_version_info - extract various chip/firmware version information
3180  *      @adapter: the adapter
3181  *
3182  *      Reads various chip/firmware version numbers and stores them into the
3183  *      adapter Adapter Parameters structure.  If any of the efforts fails
3184  *      the first failure will be returned, but all of the version numbers
3185  *      will be read.
3186  */
3187 int t4_get_version_info(struct adapter *adapter)
3188 {
3189         int ret = 0;
3190
3191         #define FIRST_RET(__getvinfo) \
3192         do { \
3193                 int __ret = __getvinfo; \
3194                 if (__ret && !ret) \
3195                         ret = __ret; \
3196         } while (0)
3197
3198         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3199         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3200         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3201         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3202         FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3203         FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3204
3205         #undef FIRST_RET
3206         return ret;
3207 }
3208
3209 /**
3210  *      t4_dump_version_info - dump all of the adapter configuration IDs
3211  *      @adapter: the adapter
3212  *
3213  *      Dumps all of the various bits of adapter configuration version/revision
3214  *      IDs information.  This is typically called at some point after
3215  *      t4_get_version_info() has been called.
3216  */
3217 void t4_dump_version_info(struct adapter *adapter)
3218 {
3219         /* Device information */
3220         dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3221                  adapter->params.vpd.id,
3222                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
3223         dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3224                  adapter->params.vpd.sn, adapter->params.vpd.pn);
3225
3226         /* Firmware Version */
3227         if (!adapter->params.fw_vers)
3228                 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3229         else
3230                 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3231                          FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3232                          FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3233                          FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3234                          FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3235
3236         /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3237          * Firmware, so dev_info() is more appropriate here.)
3238          */
3239         if (!adapter->params.bs_vers)
3240                 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3241         else
3242                 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3243                          FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3244                          FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3245                          FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3246                          FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3247
3248         /* TP Microcode Version */
3249         if (!adapter->params.tp_vers)
3250                 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3251         else
3252                 dev_info(adapter->pdev_dev,
3253                          "TP Microcode version: %u.%u.%u.%u\n",
3254                          FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3255                          FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3256                          FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3257                          FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3258
3259         /* Expansion ROM version */
3260         if (!adapter->params.er_vers)
3261                 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3262         else
3263                 dev_info(adapter->pdev_dev,
3264                          "Expansion ROM version: %u.%u.%u.%u\n",
3265                          FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3266                          FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3267                          FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3268                          FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3269
3270         /* Serial Configuration version */
3271         dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3272                  adapter->params.scfg_vers);
3273
3274         /* VPD Version */
3275         dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3276                  adapter->params.vpd_vers);
3277 }
3278
3279 /**
3280  *      t4_check_fw_version - check if the FW is supported with this driver
3281  *      @adap: the adapter
3282  *
3283  *      Checks if an adapter's FW is compatible with the driver.  Returns 0
3284  *      if there's exact match, a negative error if the version could not be
3285  *      read or there's a major version mismatch
3286  */
3287 int t4_check_fw_version(struct adapter *adap)
3288 {
3289         int i, ret, major, minor, micro;
3290         int exp_major, exp_minor, exp_micro;
3291         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3292
3293         ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3294         /* Try multiple times before returning error */
3295         for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3296                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3297
3298         if (ret)
3299                 return ret;
3300
3301         major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3302         minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3303         micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3304
3305         switch (chip_version) {
3306         case CHELSIO_T4:
3307                 exp_major = T4FW_MIN_VERSION_MAJOR;
3308                 exp_minor = T4FW_MIN_VERSION_MINOR;
3309                 exp_micro = T4FW_MIN_VERSION_MICRO;
3310                 break;
3311         case CHELSIO_T5:
3312                 exp_major = T5FW_MIN_VERSION_MAJOR;
3313                 exp_minor = T5FW_MIN_VERSION_MINOR;
3314                 exp_micro = T5FW_MIN_VERSION_MICRO;
3315                 break;
3316         case CHELSIO_T6:
3317                 exp_major = T6FW_MIN_VERSION_MAJOR;
3318                 exp_minor = T6FW_MIN_VERSION_MINOR;
3319                 exp_micro = T6FW_MIN_VERSION_MICRO;
3320                 break;
3321         default:
3322                 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3323                         adap->chip);
3324                 return -EINVAL;
3325         }
3326
3327         if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3328             (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3329                 dev_err(adap->pdev_dev,
3330                         "Card has firmware version %u.%u.%u, minimum "
3331                         "supported firmware is %u.%u.%u.\n", major, minor,
3332                         micro, exp_major, exp_minor, exp_micro);
3333                 return -EFAULT;
3334         }
3335         return 0;
3336 }
3337
3338 /* Is the given firmware API compatible with the one the driver was compiled
3339  * with?
3340  */
3341 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3342 {
3343
3344         /* short circuit if it's the exact same firmware version */
3345         if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3346                 return 1;
3347
3348 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3349         if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3350             SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3351                 return 1;
3352 #undef SAME_INTF
3353
3354         return 0;
3355 }
3356
3357 /* The firmware in the filesystem is usable, but should it be installed?
3358  * This routine explains itself in detail if it indicates the filesystem
3359  * firmware should be installed.
3360  */
3361 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3362                                 int k, int c)
3363 {
3364         const char *reason;
3365
3366         if (!card_fw_usable) {
3367                 reason = "incompatible or unusable";
3368                 goto install;
3369         }
3370
3371         if (k > c) {
3372                 reason = "older than the version supported with this driver";
3373                 goto install;
3374         }
3375
3376         return 0;
3377
3378 install:
3379         dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3380                 "installing firmware %u.%u.%u.%u on card.\n",
3381                 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3382                 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3383                 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3384                 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3385
3386         return 1;
3387 }
3388
3389 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3390                const u8 *fw_data, unsigned int fw_size,
3391                struct fw_hdr *card_fw, enum dev_state state,
3392                int *reset)
3393 {
3394         int ret, card_fw_usable, fs_fw_usable;
3395         const struct fw_hdr *fs_fw;
3396         const struct fw_hdr *drv_fw;
3397
3398         drv_fw = &fw_info->fw_hdr;
3399
3400         /* Read the header of the firmware on the card */
3401         ret = -t4_read_flash(adap, FLASH_FW_START,
3402                             sizeof(*card_fw) / sizeof(uint32_t),
3403                             (uint32_t *)card_fw, 1);
3404         if (ret == 0) {
3405                 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3406         } else {
3407                 dev_err(adap->pdev_dev,
3408                         "Unable to read card's firmware header: %d\n", ret);
3409                 card_fw_usable = 0;
3410         }
3411
3412         if (fw_data != NULL) {
3413                 fs_fw = (const void *)fw_data;
3414                 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3415         } else {
3416                 fs_fw = NULL;
3417                 fs_fw_usable = 0;
3418         }
3419
3420         if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3421             (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3422                 /* Common case: the firmware on the card is an exact match and
3423                  * the filesystem one is an exact match too, or the filesystem
3424                  * one is absent/incompatible.
3425                  */
3426         } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3427                    should_install_fs_fw(adap, card_fw_usable,
3428                                         be32_to_cpu(fs_fw->fw_ver),
3429                                         be32_to_cpu(card_fw->fw_ver))) {
3430                 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3431                                      fw_size, 0);
3432                 if (ret != 0) {
3433                         dev_err(adap->pdev_dev,
3434                                 "failed to install firmware: %d\n", ret);
3435                         goto bye;
3436                 }
3437
3438                 /* Installed successfully, update the cached header too. */
3439                 *card_fw = *fs_fw;
3440                 card_fw_usable = 1;
3441                 *reset = 0;     /* already reset as part of load_fw */
3442         }
3443
3444         if (!card_fw_usable) {
3445                 uint32_t d, c, k;
3446
3447                 d = be32_to_cpu(drv_fw->fw_ver);
3448                 c = be32_to_cpu(card_fw->fw_ver);
3449                 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3450
3451                 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3452                         "chip state %d, "
3453                         "driver compiled with %d.%d.%d.%d, "
3454                         "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3455                         state,
3456                         FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3457                         FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3458                         FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3459                         FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3460                         FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3461                         FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3462                 ret = EINVAL;
3463                 goto bye;
3464         }
3465
3466         /* We're using whatever's on the card and it's known to be good. */
3467         adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3468         adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3469
3470 bye:
3471         return ret;
3472 }
3473
3474 /**
3475  *      t4_flash_erase_sectors - erase a range of flash sectors
3476  *      @adapter: the adapter
3477  *      @start: the first sector to erase
3478  *      @end: the last sector to erase
3479  *
3480  *      Erases the sectors in the given inclusive range.
3481  */
3482 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3483 {
3484         int ret = 0;
3485
3486         if (end >= adapter->params.sf_nsec)
3487                 return -EINVAL;
3488
3489         while (start <= end) {
3490                 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3491                     (ret = sf1_write(adapter, 4, 0, 1,
3492                                      SF_ERASE_SECTOR | (start << 8))) != 0 ||
3493                     (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3494                         dev_err(adapter->pdev_dev,
3495                                 "erase of flash sector %d failed, error %d\n",
3496                                 start, ret);
3497                         break;
3498                 }
3499                 start++;
3500         }
3501         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3502         return ret;
3503 }
3504
3505 /**
3506  *      t4_flash_cfg_addr - return the address of the flash configuration file
3507  *      @adapter: the adapter
3508  *
3509  *      Return the address within the flash where the Firmware Configuration
3510  *      File is stored.
3511  */
3512 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3513 {
3514         if (adapter->params.sf_size == 0x100000)
3515                 return FLASH_FPGA_CFG_START;
3516         else
3517                 return FLASH_CFG_START;
3518 }
3519
3520 /* Return TRUE if the specified firmware matches the adapter.  I.e. T4
3521  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3522  * and emit an error message for mismatched firmware to save our caller the
3523  * effort ...
3524  */
3525 static bool t4_fw_matches_chip(const struct adapter *adap,
3526                                const struct fw_hdr *hdr)
3527 {
3528         /* The expression below will return FALSE for any unsupported adapter
3529          * which will keep us "honest" in the future ...
3530          */
3531         if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3532             (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3533             (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3534                 return true;
3535
3536         dev_err(adap->pdev_dev,
3537                 "FW image (%d) is not suitable for this adapter (%d)\n",
3538                 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3539         return false;
3540 }
3541
3542 /**
3543  *      t4_load_fw - download firmware
3544  *      @adap: the adapter
3545  *      @fw_data: the firmware image to write
3546  *      @size: image size
3547  *
3548  *      Write the supplied firmware image to the card's serial flash.
3549  */
3550 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3551 {
3552         u32 csum;
3553         int ret, addr;
3554         unsigned int i;
3555         u8 first_page[SF_PAGE_SIZE];
3556         const __be32 *p = (const __be32 *)fw_data;
3557         const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3558         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3559         unsigned int fw_start_sec = FLASH_FW_START_SEC;
3560         unsigned int fw_size = FLASH_FW_MAX_SIZE;
3561         unsigned int fw_start = FLASH_FW_START;
3562
3563         if (!size) {
3564                 dev_err(adap->pdev_dev, "FW image has no data\n");
3565                 return -EINVAL;
3566         }
3567         if (size & 511) {
3568                 dev_err(adap->pdev_dev,
3569                         "FW image size not multiple of 512 bytes\n");
3570                 return -EINVAL;
3571         }
3572         if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3573                 dev_err(adap->pdev_dev,
3574                         "FW image size differs from size in FW header\n");
3575                 return -EINVAL;
3576         }
3577         if (size > fw_size) {
3578                 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3579                         fw_size);
3580                 return -EFBIG;
3581         }
3582         if (!t4_fw_matches_chip(adap, hdr))
3583                 return -EINVAL;
3584
3585         for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3586                 csum += be32_to_cpu(p[i]);
3587
3588         if (csum != 0xffffffff) {
3589                 dev_err(adap->pdev_dev,
3590                         "corrupted firmware image, checksum %#x\n", csum);
3591                 return -EINVAL;
3592         }
3593
3594         i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
3595         ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3596         if (ret)
3597                 goto out;
3598
3599         /*
3600          * We write the correct version at the end so the driver can see a bad
3601          * version if the FW write fails.  Start by writing a copy of the
3602          * first page with a bad version.
3603          */
3604         memcpy(first_page, fw_data, SF_PAGE_SIZE);
3605         ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3606         ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page);
3607         if (ret)
3608                 goto out;
3609
3610         addr = fw_start;
3611         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3612                 addr += SF_PAGE_SIZE;
3613                 fw_data += SF_PAGE_SIZE;
3614                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3615                 if (ret)
3616                         goto out;
3617         }
3618
3619         ret = t4_write_flash(adap,
3620                              fw_start + offsetof(struct fw_hdr, fw_ver),
3621                              sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3622 out:
3623         if (ret)
3624                 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3625                         ret);
3626         else
3627                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3628         return ret;
3629 }
3630
3631 /**
3632  *      t4_phy_fw_ver - return current PHY firmware version
3633  *      @adap: the adapter
3634  *      @phy_fw_ver: return value buffer for PHY firmware version
3635  *
3636  *      Returns the current version of external PHY firmware on the
3637  *      adapter.
3638  */
3639 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3640 {
3641         u32 param, val;
3642         int ret;
3643
3644         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3645                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3646                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3647                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3648         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3649                               &param, &val);
3650         if (ret < 0)
3651                 return ret;
3652         *phy_fw_ver = val;
3653         return 0;
3654 }
3655
3656 /**
3657  *      t4_load_phy_fw - download port PHY firmware
3658  *      @adap: the adapter
3659  *      @win: the PCI-E Memory Window index to use for t4_memory_rw()
3660  *      @win_lock: the lock to use to guard the memory copy
3661  *      @phy_fw_version: function to check PHY firmware versions
3662  *      @phy_fw_data: the PHY firmware image to write
3663  *      @phy_fw_size: image size
3664  *
3665  *      Transfer the specified PHY firmware to the adapter.  If a non-NULL
3666  *      @phy_fw_version is supplied, then it will be used to determine if
3667  *      it's necessary to perform the transfer by comparing the version
3668  *      of any existing adapter PHY firmware with that of the passed in
3669  *      PHY firmware image.  If @win_lock is non-NULL then it will be used
3670  *      around the call to t4_memory_rw() which transfers the PHY firmware
3671  *      to the adapter.
3672  *
3673  *      A negative error number will be returned if an error occurs.  If
3674  *      version number support is available and there's no need to upgrade
3675  *      the firmware, 0 will be returned.  If firmware is successfully
3676  *      transferred to the adapter, 1 will be retured.
3677  *
3678  *      NOTE: some adapters only have local RAM to store the PHY firmware.  As
3679  *      a result, a RESET of the adapter would cause that RAM to lose its
3680  *      contents.  Thus, loading PHY firmware on such adapters must happen
3681  *      after any FW_RESET_CMDs ...
3682  */
3683 int t4_load_phy_fw(struct adapter *adap,
3684                    int win, spinlock_t *win_lock,
3685                    int (*phy_fw_version)(const u8 *, size_t),
3686                    const u8 *phy_fw_data, size_t phy_fw_size)
3687 {
3688         unsigned long mtype = 0, maddr = 0;
3689         u32 param, val;
3690         int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3691         int ret;
3692
3693         /* If we have version number support, then check to see if the adapter
3694          * already has up-to-date PHY firmware loaded.
3695          */
3696          if (phy_fw_version) {
3697                 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3698                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3699                 if (ret < 0)
3700                         return ret;
3701
3702                 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3703                         CH_WARN(adap, "PHY Firmware already up-to-date, "
3704                                 "version %#x\n", cur_phy_fw_ver);
3705                         return 0;
3706                 }
3707         }
3708
3709         /* Ask the firmware where it wants us to copy the PHY firmware image.
3710          * The size of the file requires a special version of the READ coommand
3711          * which will pass the file size via the values field in PARAMS_CMD and
3712          * retrieve the return value from firmware and place it in the same
3713          * buffer values
3714          */
3715         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3716                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3717                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3718                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3719         val = phy_fw_size;
3720         ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3721                                  &param, &val, 1, true);
3722         if (ret < 0)
3723                 return ret;
3724         mtype = val >> 8;
3725         maddr = (val & 0xff) << 16;
3726
3727         /* Copy the supplied PHY Firmware image to the adapter memory location
3728          * allocated by the adapter firmware.
3729          */
3730         if (win_lock)
3731                 spin_lock_bh(win_lock);
3732         ret = t4_memory_rw(adap, win, mtype, maddr,
3733                            phy_fw_size, (__be32 *)phy_fw_data,
3734                            T4_MEMORY_WRITE);
3735         if (win_lock)
3736                 spin_unlock_bh(win_lock);
3737         if (ret)
3738                 return ret;
3739
3740         /* Tell the firmware that the PHY firmware image has been written to
3741          * RAM and it can now start copying it over to the PHYs.  The chip
3742          * firmware will RESET the affected PHYs as part of this operation
3743          * leaving them running the new PHY firmware image.
3744          */
3745         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3746                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3747                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3748                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3749         ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3750                                     &param, &val, 30000);
3751
3752         /* If we have version number support, then check to see that the new
3753          * firmware got loaded properly.
3754          */
3755         if (phy_fw_version) {
3756                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3757                 if (ret < 0)
3758                         return ret;
3759
3760                 if (cur_phy_fw_ver != new_phy_fw_vers) {
3761                         CH_WARN(adap, "PHY Firmware did not update: "
3762                                 "version on adapter %#x, "
3763                                 "version flashed %#x\n",
3764                                 cur_phy_fw_ver, new_phy_fw_vers);
3765                         return -ENXIO;
3766                 }
3767         }
3768
3769         return 1;
3770 }
3771
3772 /**
3773  *      t4_fwcache - firmware cache operation
3774  *      @adap: the adapter
3775  *      @op  : the operation (flush or flush and invalidate)
3776  */
3777 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3778 {
3779         struct fw_params_cmd c;
3780
3781         memset(&c, 0, sizeof(c));
3782         c.op_to_vfn =
3783                 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3784                             FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3785                             FW_PARAMS_CMD_PFN_V(adap->pf) |
3786                             FW_PARAMS_CMD_VFN_V(0));
3787         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3788         c.param[0].mnem =
3789                 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3790                             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3791         c.param[0].val = (__force __be32)op;
3792
3793         return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3794 }
3795
3796 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3797                         unsigned int *pif_req_wrptr,
3798                         unsigned int *pif_rsp_wrptr)
3799 {
3800         int i, j;
3801         u32 cfg, val, req, rsp;
3802
3803         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3804         if (cfg & LADBGEN_F)
3805                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3806
3807         val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3808         req = POLADBGWRPTR_G(val);
3809         rsp = PILADBGWRPTR_G(val);
3810         if (pif_req_wrptr)
3811                 *pif_req_wrptr = req;
3812         if (pif_rsp_wrptr)
3813                 *pif_rsp_wrptr = rsp;
3814
3815         for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3816                 for (j = 0; j < 6; j++) {
3817                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3818                                      PILADBGRDPTR_V(rsp));
3819                         *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3820                         *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3821                         req++;
3822                         rsp++;
3823                 }
3824                 req = (req + 2) & POLADBGRDPTR_M;
3825                 rsp = (rsp + 2) & PILADBGRDPTR_M;
3826         }
3827         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3828 }
3829
3830 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3831 {
3832         u32 cfg;
3833         int i, j, idx;
3834
3835         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3836         if (cfg & LADBGEN_F)
3837                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3838
3839         for (i = 0; i < CIM_MALA_SIZE; i++) {
3840                 for (j = 0; j < 5; j++) {
3841                         idx = 8 * i + j;
3842                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3843                                      PILADBGRDPTR_V(idx));
3844                         *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3845                         *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3846                 }
3847         }
3848         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3849 }
3850
3851 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3852 {
3853         unsigned int i, j;
3854
3855         for (i = 0; i < 8; i++) {
3856                 u32 *p = la_buf + i;
3857
3858                 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3859                 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3860                 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3861                 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3862                         *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3863         }
3864 }
3865
3866 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3867                      FW_PORT_CAP32_ANEG)
3868
3869 /**
3870  *      fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3871  *      @caps16: a 16-bit Port Capabilities value
3872  *
3873  *      Returns the equivalent 32-bit Port Capabilities value.
3874  */
3875 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3876 {
3877         fw_port_cap32_t caps32 = 0;
3878
3879         #define CAP16_TO_CAP32(__cap) \
3880                 do { \
3881                         if (caps16 & FW_PORT_CAP_##__cap) \
3882                                 caps32 |= FW_PORT_CAP32_##__cap; \
3883                 } while (0)
3884
3885         CAP16_TO_CAP32(SPEED_100M);
3886         CAP16_TO_CAP32(SPEED_1G);
3887         CAP16_TO_CAP32(SPEED_25G);
3888         CAP16_TO_CAP32(SPEED_10G);
3889         CAP16_TO_CAP32(SPEED_40G);
3890         CAP16_TO_CAP32(SPEED_100G);
3891         CAP16_TO_CAP32(FC_RX);
3892         CAP16_TO_CAP32(FC_TX);
3893         CAP16_TO_CAP32(ANEG);
3894         CAP16_TO_CAP32(MDIX);
3895         CAP16_TO_CAP32(MDIAUTO);
3896         CAP16_TO_CAP32(FEC_RS);
3897         CAP16_TO_CAP32(FEC_BASER_RS);
3898         CAP16_TO_CAP32(802_3_PAUSE);
3899         CAP16_TO_CAP32(802_3_ASM_DIR);
3900
3901         #undef CAP16_TO_CAP32
3902
3903         return caps32;
3904 }
3905
3906 /**
3907  *      fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3908  *      @caps32: a 32-bit Port Capabilities value
3909  *
3910  *      Returns the equivalent 16-bit Port Capabilities value.  Note that
3911  *      not all 32-bit Port Capabilities can be represented in the 16-bit
3912  *      Port Capabilities and some fields/values may not make it.
3913  */
3914 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
3915 {
3916         fw_port_cap16_t caps16 = 0;
3917
3918         #define CAP32_TO_CAP16(__cap) \
3919                 do { \
3920                         if (caps32 & FW_PORT_CAP32_##__cap) \
3921                                 caps16 |= FW_PORT_CAP_##__cap; \
3922                 } while (0)
3923
3924         CAP32_TO_CAP16(SPEED_100M);
3925         CAP32_TO_CAP16(SPEED_1G);
3926         CAP32_TO_CAP16(SPEED_10G);
3927         CAP32_TO_CAP16(SPEED_25G);
3928         CAP32_TO_CAP16(SPEED_40G);
3929         CAP32_TO_CAP16(SPEED_100G);
3930         CAP32_TO_CAP16(FC_RX);
3931         CAP32_TO_CAP16(FC_TX);
3932         CAP32_TO_CAP16(802_3_PAUSE);
3933         CAP32_TO_CAP16(802_3_ASM_DIR);
3934         CAP32_TO_CAP16(ANEG);
3935         CAP32_TO_CAP16(MDIX);
3936         CAP32_TO_CAP16(MDIAUTO);
3937         CAP32_TO_CAP16(FEC_RS);
3938         CAP32_TO_CAP16(FEC_BASER_RS);
3939
3940         #undef CAP32_TO_CAP16
3941
3942         return caps16;
3943 }
3944
3945 /* Translate Firmware Port Capabilities Pause specification to Common Code */
3946 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
3947 {
3948         enum cc_pause cc_pause = 0;
3949
3950         if (fw_pause & FW_PORT_CAP32_FC_RX)
3951                 cc_pause |= PAUSE_RX;
3952         if (fw_pause & FW_PORT_CAP32_FC_TX)
3953                 cc_pause |= PAUSE_TX;
3954
3955         return cc_pause;
3956 }
3957
3958 /* Translate Common Code Pause specification into Firmware Port Capabilities */
3959 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
3960 {
3961         fw_port_cap32_t fw_pause = 0;
3962
3963         if (cc_pause & PAUSE_RX)
3964                 fw_pause |= FW_PORT_CAP32_FC_RX;
3965         if (cc_pause & PAUSE_TX)
3966                 fw_pause |= FW_PORT_CAP32_FC_TX;
3967
3968         return fw_pause;
3969 }
3970
3971 /* Translate Firmware Forward Error Correction specification to Common Code */
3972 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
3973 {
3974         enum cc_fec cc_fec = 0;
3975
3976         if (fw_fec & FW_PORT_CAP32_FEC_RS)
3977                 cc_fec |= FEC_RS;
3978         if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
3979                 cc_fec |= FEC_BASER_RS;
3980
3981         return cc_fec;
3982 }
3983
3984 /* Translate Common Code Forward Error Correction specification to Firmware */
3985 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
3986 {
3987         fw_port_cap32_t fw_fec = 0;
3988
3989         if (cc_fec & FEC_RS)
3990                 fw_fec |= FW_PORT_CAP32_FEC_RS;
3991         if (cc_fec & FEC_BASER_RS)
3992                 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
3993
3994         return fw_fec;
3995 }
3996
3997 /**
3998  *      t4_link_l1cfg - apply link configuration to MAC/PHY
3999  *      @adapter: the adapter
4000  *      @mbox: the Firmware Mailbox to use
4001  *      @port: the Port ID
4002  *      @lc: the Port's Link Configuration
4003  *
4004  *      Set up a port's MAC and PHY according to a desired link configuration.
4005  *      - If the PHY can auto-negotiate first decide what to advertise, then
4006  *        enable/disable auto-negotiation as desired, and reset.
4007  *      - If the PHY does not auto-negotiate just reset it.
4008  *      - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4009  *        otherwise do it later based on the outcome of auto-negotiation.
4010  */
4011 int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
4012                   unsigned int port, struct link_config *lc)
4013 {
4014         unsigned int fw_caps = adapter->params.fw_caps_support;
4015         struct fw_port_cmd cmd;
4016         unsigned int fw_mdi = FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO);
4017         fw_port_cap32_t fw_fc, cc_fec, fw_fec, rcap;
4018
4019         lc->link_ok = 0;
4020
4021         /* Convert driver coding of Pause Frame Flow Control settings into the
4022          * Firmware's API.
4023          */
4024         fw_fc = cc_to_fwcap_pause(lc->requested_fc);
4025
4026         /* Convert Common Code Forward Error Control settings into the
4027          * Firmware's API.  If the current Requested FEC has "Automatic"
4028          * (IEEE 802.3) specified, then we use whatever the Firmware
4029          * sent us as part of it's IEEE 802.3-based interpratation of
4030          * the Transceiver Module EPROM FEC parameters.  Otherwise we
4031          * use whatever is in the current Requested FEC settings.
4032          */
4033         if (lc->requested_fec & FEC_AUTO)
4034                 cc_fec = fwcap_to_cc_fec(lc->def_acaps);
4035         else
4036                 cc_fec = lc->requested_fec;
4037         fw_fec = cc_to_fwcap_fec(cc_fec);
4038
4039         /* Figure out what our Requested Port Capabilities are going to be.
4040          */
4041         if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4042                 rcap = (lc->pcaps & ADVERT_MASK) | fw_fc | fw_fec;
4043                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4044                 lc->fec = cc_fec;
4045         } else if (lc->autoneg == AUTONEG_DISABLE) {
4046                 rcap = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4047                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4048                 lc->fec = cc_fec;
4049         } else {
4050                 rcap = lc->acaps | fw_fc | fw_fec | fw_mdi;
4051         }
4052
4053         /* And send that on to the Firmware ...
4054          */
4055         memset(&cmd, 0, sizeof(cmd));
4056         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4057                                        FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4058                                        FW_PORT_CMD_PORTID_V(port));
4059         cmd.action_to_len16 =
4060                 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4061                                                  ? FW_PORT_ACTION_L1_CFG
4062                                                  : FW_PORT_ACTION_L1_CFG32) |
4063                             FW_LEN16(cmd));
4064         if (fw_caps == FW_CAPS16)
4065                 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4066         else
4067                 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4068         return t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4069 }
4070
4071 /**
4072  *      t4_restart_aneg - restart autonegotiation
4073  *      @adap: the adapter
4074  *      @mbox: mbox to use for the FW command
4075  *      @port: the port id
4076  *
4077  *      Restarts autonegotiation for the selected port.
4078  */
4079 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4080 {
4081         struct fw_port_cmd c;
4082
4083         memset(&c, 0, sizeof(c));
4084         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4085                                      FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4086                                      FW_PORT_CMD_PORTID_V(port));
4087         c.action_to_len16 =
4088                 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
4089                             FW_LEN16(c));
4090         c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP32_ANEG);
4091         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4092 }
4093
4094 typedef void (*int_handler_t)(struct adapter *adap);
4095
4096 struct intr_info {
4097         unsigned int mask;       /* bits to check in interrupt status */
4098         const char *msg;         /* message to print or NULL */
4099         short stat_idx;          /* stat counter to increment or -1 */
4100         unsigned short fatal;    /* whether the condition reported is fatal */
4101         int_handler_t int_handler; /* platform-specific int handler */
4102 };
4103
4104 /**
4105  *      t4_handle_intr_status - table driven interrupt handler
4106  *      @adapter: the adapter that generated the interrupt
4107  *      @reg: the interrupt status register to process
4108  *      @acts: table of interrupt actions
4109  *
4110  *      A table driven interrupt handler that applies a set of masks to an
4111  *      interrupt status word and performs the corresponding actions if the
4112  *      interrupts described by the mask have occurred.  The actions include
4113  *      optionally emitting a warning or alert message.  The table is terminated
4114  *      by an entry specifying mask 0.  Returns the number of fatal interrupt
4115  *      conditions.
4116  */
4117 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4118                                  const struct intr_info *acts)
4119 {
4120         int fatal = 0;
4121         unsigned int mask = 0;
4122         unsigned int status = t4_read_reg(adapter, reg);
4123
4124         for ( ; acts->mask; ++acts) {
4125                 if (!(status & acts->mask))
4126                         continue;
4127                 if (acts->fatal) {
4128                         fatal++;
4129                         dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4130                                   status & acts->mask);
4131                 } else if (acts->msg && printk_ratelimit())
4132                         dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4133                                  status & acts->mask);
4134                 if (acts->int_handler)
4135                         acts->int_handler(adapter);
4136                 mask |= acts->mask;
4137         }
4138         status &= mask;
4139         if (status)                           /* clear processed interrupts */
4140                 t4_write_reg(adapter, reg, status);
4141         return fatal;
4142 }
4143
4144 /*
4145  * Interrupt handler for the PCIE module.
4146  */
4147 static void pcie_intr_handler(struct adapter *adapter)
4148 {
4149         static const struct intr_info sysbus_intr_info[] = {
4150                 { RNPP_F, "RXNP array parity error", -1, 1 },
4151                 { RPCP_F, "RXPC array parity error", -1, 1 },
4152                 { RCIP_F, "RXCIF array parity error", -1, 1 },
4153                 { RCCP_F, "Rx completions control array parity error", -1, 1 },
4154                 { RFTP_F, "RXFT array parity error", -1, 1 },
4155                 { 0 }
4156         };
4157         static const struct intr_info pcie_port_intr_info[] = {
4158                 { TPCP_F, "TXPC array parity error", -1, 1 },
4159                 { TNPP_F, "TXNP array parity error", -1, 1 },
4160                 { TFTP_F, "TXFT array parity error", -1, 1 },
4161                 { TCAP_F, "TXCA array parity error", -1, 1 },
4162                 { TCIP_F, "TXCIF array parity error", -1, 1 },
4163                 { RCAP_F, "RXCA array parity error", -1, 1 },
4164                 { OTDD_F, "outbound request TLP discarded", -1, 1 },
4165                 { RDPE_F, "Rx data parity error", -1, 1 },
4166                 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4167                 { 0 }
4168         };
4169         static const struct intr_info pcie_intr_info[] = {
4170                 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4171                 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4172                 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4173                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4174                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4175                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4176                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4177                 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4178                 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4179                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4180                 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4181                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4182                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4183                 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4184                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4185                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4186                 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4187                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4188                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4189                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4190                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4191                 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4192                 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4193                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4194                 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4195                 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4196                 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4197                 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4198                 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4199                 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4200                   -1, 0 },
4201                 { 0 }
4202         };
4203
4204         static struct intr_info t5_pcie_intr_info[] = {
4205                 { MSTGRPPERR_F, "Master Response Read Queue parity error",
4206                   -1, 1 },
4207                 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4208                 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4209                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4210                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4211                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4212                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4213                 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4214                   -1, 1 },
4215                 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4216                   -1, 1 },
4217                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4218                 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4219                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4220                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4221                 { DREQWRPERR_F, "PCI DMA channel write request parity error",
4222                   -1, 1 },
4223                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4224                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4225                 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4226                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4227                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4228                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4229                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4230                 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4231                 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4232                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4233                 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4234                   -1, 1 },
4235                 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4236                   -1, 1 },
4237                 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4238                 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4239                 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4240                 { READRSPERR_F, "Outbound read error", -1, 0 },
4241                 { 0 }
4242         };
4243
4244         int fat;
4245
4246         if (is_t4(adapter->params.chip))
4247                 fat = t4_handle_intr_status(adapter,
4248                                 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4249                                 sysbus_intr_info) +
4250                         t4_handle_intr_status(adapter,
4251                                         PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4252                                         pcie_port_intr_info) +
4253                         t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4254                                               pcie_intr_info);
4255         else
4256                 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4257                                             t5_pcie_intr_info);
4258
4259         if (fat)
4260                 t4_fatal_err(adapter);
4261 }
4262
4263 /*
4264  * TP interrupt handler.
4265  */
4266 static void tp_intr_handler(struct adapter *adapter)
4267 {
4268         static const struct intr_info tp_intr_info[] = {
4269                 { 0x3fffffff, "TP parity error", -1, 1 },
4270                 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4271                 { 0 }
4272         };
4273
4274         if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4275                 t4_fatal_err(adapter);
4276 }
4277
4278 /*
4279  * SGE interrupt handler.
4280  */
4281 static void sge_intr_handler(struct adapter *adapter)
4282 {
4283         u64 v;
4284         u32 err;
4285
4286         static const struct intr_info sge_intr_info[] = {
4287                 { ERR_CPL_EXCEED_IQE_SIZE_F,
4288                   "SGE received CPL exceeding IQE size", -1, 1 },
4289                 { ERR_INVALID_CIDX_INC_F,
4290                   "SGE GTS CIDX increment too large", -1, 0 },
4291                 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4292                 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4293                 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4294                   "SGE IQID > 1023 received CPL for FL", -1, 0 },
4295                 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4296                   0 },
4297                 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4298                   0 },
4299                 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4300                   0 },
4301                 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4302                   0 },
4303                 { ERR_ING_CTXT_PRIO_F,
4304                   "SGE too many priority ingress contexts", -1, 0 },
4305                 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4306                 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4307                 { 0 }
4308         };
4309
4310         static struct intr_info t4t5_sge_intr_info[] = {
4311                 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4312                 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4313                 { ERR_EGR_CTXT_PRIO_F,
4314                   "SGE too many priority egress contexts", -1, 0 },
4315                 { 0 }
4316         };
4317
4318         v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
4319                 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
4320         if (v) {
4321                 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
4322                                 (unsigned long long)v);
4323                 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
4324                 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
4325         }
4326
4327         v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4328         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4329                 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4330                                            t4t5_sge_intr_info);
4331
4332         err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4333         if (err & ERROR_QID_VALID_F) {
4334                 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4335                         ERROR_QID_G(err));
4336                 if (err & UNCAPTURED_ERROR_F)
4337                         dev_err(adapter->pdev_dev,
4338                                 "SGE UNCAPTURED_ERROR set (clearing)\n");
4339                 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4340                              UNCAPTURED_ERROR_F);
4341         }
4342
4343         if (v != 0)
4344                 t4_fatal_err(adapter);
4345 }
4346
4347 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4348                       OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4349 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4350                       IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4351
4352 /*
4353  * CIM interrupt handler.
4354  */
4355 static void cim_intr_handler(struct adapter *adapter)
4356 {
4357         static const struct intr_info cim_intr_info[] = {
4358                 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4359                 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4360                 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4361                 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4362                 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4363                 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4364                 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4365                 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4366                 { 0 }
4367         };
4368         static const struct intr_info cim_upintr_info[] = {
4369                 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4370                 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4371                 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4372                 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4373                 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4374                 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4375                 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4376                 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4377                 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4378                 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4379                 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4380                 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4381                 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4382                 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4383                 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4384                 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4385                 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4386                 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4387                 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4388                 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4389                 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4390                 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4391                 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4392                 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4393                 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4394                 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4395                 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4396                 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4397                 { 0 }
4398         };
4399
4400         u32 val, fw_err;
4401         int fat;
4402
4403         fw_err = t4_read_reg(adapter, PCIE_FW_A);
4404         if (fw_err & PCIE_FW_ERR_F)
4405                 t4_report_fw_error(adapter);
4406
4407         /* When the Firmware detects an internal error which normally
4408          * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4409          * in order to make sure the Host sees the Firmware Crash.  So
4410          * if we have a Timer0 interrupt and don't see a Firmware Crash,
4411          * ignore the Timer0 interrupt.
4412          */
4413
4414         val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4415         if (val & TIMER0INT_F)
4416                 if (!(fw_err & PCIE_FW_ERR_F) ||
4417                     (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4418                         t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4419                                      TIMER0INT_F);
4420
4421         fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4422                                     cim_intr_info) +
4423               t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4424                                     cim_upintr_info);
4425         if (fat)
4426                 t4_fatal_err(adapter);
4427 }
4428
4429 /*
4430  * ULP RX interrupt handler.
4431  */
4432 static void ulprx_intr_handler(struct adapter *adapter)
4433 {
4434         static const struct intr_info ulprx_intr_info[] = {
4435                 { 0x1800000, "ULPRX context error", -1, 1 },
4436                 { 0x7fffff, "ULPRX parity error", -1, 1 },
4437                 { 0 }
4438         };
4439
4440         if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4441                 t4_fatal_err(adapter);
4442 }
4443
4444 /*
4445  * ULP TX interrupt handler.
4446  */
4447 static void ulptx_intr_handler(struct adapter *adapter)
4448 {
4449         static const struct intr_info ulptx_intr_info[] = {
4450                 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4451                   0 },
4452                 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4453                   0 },
4454                 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4455                   0 },
4456                 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4457                   0 },
4458                 { 0xfffffff, "ULPTX parity error", -1, 1 },
4459                 { 0 }
4460         };
4461
4462         if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4463                 t4_fatal_err(adapter);
4464 }
4465
4466 /*
4467  * PM TX interrupt handler.
4468  */
4469 static void pmtx_intr_handler(struct adapter *adapter)
4470 {
4471         static const struct intr_info pmtx_intr_info[] = {
4472                 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4473                 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4474                 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4475                 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4476                 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4477                 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4478                 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4479                   -1, 1 },
4480                 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4481                 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4482                 { 0 }
4483         };
4484
4485         if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4486                 t4_fatal_err(adapter);
4487 }
4488
4489 /*
4490  * PM RX interrupt handler.
4491  */
4492 static void pmrx_intr_handler(struct adapter *adapter)
4493 {
4494         static const struct intr_info pmrx_intr_info[] = {
4495                 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4496                 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4497                 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4498                 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4499                   -1, 1 },
4500                 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4501                 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4502                 { 0 }
4503         };
4504
4505         if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4506                 t4_fatal_err(adapter);
4507 }
4508
4509 /*
4510  * CPL switch interrupt handler.
4511  */
4512 static void cplsw_intr_handler(struct adapter *adapter)
4513 {
4514         static const struct intr_info cplsw_intr_info[] = {
4515                 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4516                 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4517                 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4518                 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4519                 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4520                 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4521                 { 0 }
4522         };
4523
4524         if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4525                 t4_fatal_err(adapter);
4526 }
4527
4528 /*
4529  * LE interrupt handler.
4530  */
4531 static void le_intr_handler(struct adapter *adap)
4532 {
4533         enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4534         static const struct intr_info le_intr_info[] = {
4535                 { LIPMISS_F, "LE LIP miss", -1, 0 },
4536                 { LIP0_F, "LE 0 LIP error", -1, 0 },
4537                 { PARITYERR_F, "LE parity error", -1, 1 },
4538                 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4539                 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4540                 { 0 }
4541         };
4542
4543         static struct intr_info t6_le_intr_info[] = {
4544                 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4545                 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4546                 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4547                 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4548                 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4549                 { 0 }
4550         };
4551
4552         if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4553                                   (chip <= CHELSIO_T5) ?
4554                                   le_intr_info : t6_le_intr_info))
4555                 t4_fatal_err(adap);
4556 }
4557
4558 /*
4559  * MPS interrupt handler.
4560  */
4561 static void mps_intr_handler(struct adapter *adapter)
4562 {
4563         static const struct intr_info mps_rx_intr_info[] = {
4564                 { 0xffffff, "MPS Rx parity error", -1, 1 },
4565                 { 0 }
4566         };
4567         static const struct intr_info mps_tx_intr_info[] = {
4568                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4569                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4570                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4571                   -1, 1 },
4572                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4573                   -1, 1 },
4574                 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4575                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4576                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4577                 { 0 }
4578         };
4579         static const struct intr_info t6_mps_tx_intr_info[] = {
4580                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4581                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4582                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4583                   -1, 1 },
4584                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4585                   -1, 1 },
4586                 /* MPS Tx Bubble is normal for T6 */
4587                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4588                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4589                 { 0 }
4590         };
4591         static const struct intr_info mps_trc_intr_info[] = {
4592                 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4593                 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4594                   -1, 1 },
4595                 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4596                 { 0 }
4597         };
4598         static const struct intr_info mps_stat_sram_intr_info[] = {
4599                 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4600                 { 0 }
4601         };
4602         static const struct intr_info mps_stat_tx_intr_info[] = {
4603                 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4604                 { 0 }
4605         };
4606         static const struct intr_info mps_stat_rx_intr_info[] = {
4607                 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4608                 { 0 }
4609         };
4610         static const struct intr_info mps_cls_intr_info[] = {
4611                 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4612                 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4613                 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4614                 { 0 }
4615         };
4616
4617         int fat;
4618
4619         fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4620                                     mps_rx_intr_info) +
4621               t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4622                                     is_t6(adapter->params.chip)
4623                                     ? t6_mps_tx_intr_info
4624                                     : mps_tx_intr_info) +
4625               t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4626                                     mps_trc_intr_info) +
4627               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4628                                     mps_stat_sram_intr_info) +
4629               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4630                                     mps_stat_tx_intr_info) +
4631               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4632                                     mps_stat_rx_intr_info) +
4633               t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4634                                     mps_cls_intr_info);
4635
4636         t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4637         t4_read_reg(adapter, MPS_INT_CAUSE_A);                    /* flush */
4638         if (fat)
4639                 t4_fatal_err(adapter);
4640 }
4641
4642 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4643                       ECC_UE_INT_CAUSE_F)
4644
4645 /*
4646  * EDC/MC interrupt handler.
4647  */
4648 static void mem_intr_handler(struct adapter *adapter, int idx)
4649 {
4650         static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4651
4652         unsigned int addr, cnt_addr, v;
4653
4654         if (idx <= MEM_EDC1) {
4655                 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4656                 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4657         } else if (idx == MEM_MC) {
4658                 if (is_t4(adapter->params.chip)) {
4659                         addr = MC_INT_CAUSE_A;
4660                         cnt_addr = MC_ECC_STATUS_A;
4661                 } else {
4662                         addr = MC_P_INT_CAUSE_A;
4663                         cnt_addr = MC_P_ECC_STATUS_A;
4664                 }
4665         } else {
4666                 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4667                 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4668         }
4669
4670         v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4671         if (v & PERR_INT_CAUSE_F)
4672                 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4673                           name[idx]);
4674         if (v & ECC_CE_INT_CAUSE_F) {
4675                 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4676
4677                 t4_edc_err_read(adapter, idx);
4678
4679                 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4680                 if (printk_ratelimit())
4681                         dev_warn(adapter->pdev_dev,
4682                                  "%u %s correctable ECC data error%s\n",
4683                                  cnt, name[idx], cnt > 1 ? "s" : "");
4684         }
4685         if (v & ECC_UE_INT_CAUSE_F)
4686                 dev_alert(adapter->pdev_dev,
4687                           "%s uncorrectable ECC data error\n", name[idx]);
4688
4689         t4_write_reg(adapter, addr, v);
4690         if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4691                 t4_fatal_err(adapter);
4692 }
4693
4694 /*
4695  * MA interrupt handler.
4696  */
4697 static void ma_intr_handler(struct adapter *adap)
4698 {
4699         u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4700
4701         if (status & MEM_PERR_INT_CAUSE_F) {
4702                 dev_alert(adap->pdev_dev,
4703                           "MA parity error, parity status %#x\n",
4704                           t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4705                 if (is_t5(adap->params.chip))
4706                         dev_alert(adap->pdev_dev,
4707                                   "MA parity error, parity status %#x\n",
4708                                   t4_read_reg(adap,
4709                                               MA_PARITY_ERROR_STATUS2_A));
4710         }
4711         if (status & MEM_WRAP_INT_CAUSE_F) {
4712                 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4713                 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4714                           "client %u to address %#x\n",
4715                           MEM_WRAP_CLIENT_NUM_G(v),
4716                           MEM_WRAP_ADDRESS_G(v) << 4);
4717         }
4718         t4_write_reg(adap, MA_INT_CAUSE_A, status);
4719         t4_fatal_err(adap);
4720 }
4721
4722 /*
4723  * SMB interrupt handler.
4724  */
4725 static void smb_intr_handler(struct adapter *adap)
4726 {
4727         static const struct intr_info smb_intr_info[] = {
4728                 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4729                 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4730                 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4731                 { 0 }
4732         };
4733
4734         if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4735                 t4_fatal_err(adap);
4736 }
4737
4738 /*
4739  * NC-SI interrupt handler.
4740  */
4741 static void ncsi_intr_handler(struct adapter *adap)
4742 {
4743         static const struct intr_info ncsi_intr_info[] = {
4744                 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4745                 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4746                 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4747                 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4748                 { 0 }
4749         };
4750
4751         if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4752                 t4_fatal_err(adap);
4753 }
4754
4755 /*
4756  * XGMAC interrupt handler.
4757  */
4758 static void xgmac_intr_handler(struct adapter *adap, int port)
4759 {
4760         u32 v, int_cause_reg;
4761
4762         if (is_t4(adap->params.chip))
4763                 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4764         else
4765                 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4766
4767         v = t4_read_reg(adap, int_cause_reg);
4768
4769         v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4770         if (!v)
4771                 return;
4772
4773         if (v & TXFIFO_PRTY_ERR_F)
4774                 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4775                           port);
4776         if (v & RXFIFO_PRTY_ERR_F)
4777                 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4778                           port);
4779         t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4780         t4_fatal_err(adap);
4781 }
4782
4783 /*
4784  * PL interrupt handler.
4785  */
4786 static void pl_intr_handler(struct adapter *adap)
4787 {
4788         static const struct intr_info pl_intr_info[] = {
4789                 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4790                 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4791                 { 0 }
4792         };
4793
4794         if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4795                 t4_fatal_err(adap);
4796 }
4797
4798 #define PF_INTR_MASK (PFSW_F)
4799 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4800                 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4801                 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
4802
4803 /**
4804  *      t4_slow_intr_handler - control path interrupt handler
4805  *      @adapter: the adapter
4806  *
4807  *      T4 interrupt handler for non-data global interrupt events, e.g., errors.
4808  *      The designation 'slow' is because it involves register reads, while
4809  *      data interrupts typically don't involve any MMIOs.
4810  */
4811 int t4_slow_intr_handler(struct adapter *adapter)
4812 {
4813         u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4814
4815         if (!(cause & GLBL_INTR_MASK))
4816                 return 0;
4817         if (cause & CIM_F)
4818                 cim_intr_handler(adapter);
4819         if (cause & MPS_F)
4820                 mps_intr_handler(adapter);
4821         if (cause & NCSI_F)
4822                 ncsi_intr_handler(adapter);
4823         if (cause & PL_F)
4824                 pl_intr_handler(adapter);
4825         if (cause & SMB_F)
4826                 smb_intr_handler(adapter);
4827         if (cause & XGMAC0_F)
4828                 xgmac_intr_handler(adapter, 0);
4829         if (cause & XGMAC1_F)
4830                 xgmac_intr_handler(adapter, 1);
4831         if (cause & XGMAC_KR0_F)
4832                 xgmac_intr_handler(adapter, 2);
4833         if (cause & XGMAC_KR1_F)
4834                 xgmac_intr_handler(adapter, 3);
4835         if (cause & PCIE_F)
4836                 pcie_intr_handler(adapter);
4837         if (cause & MC_F)
4838                 mem_intr_handler(adapter, MEM_MC);
4839         if (is_t5(adapter->params.chip) && (cause & MC1_F))
4840                 mem_intr_handler(adapter, MEM_MC1);
4841         if (cause & EDC0_F)
4842                 mem_intr_handler(adapter, MEM_EDC0);
4843         if (cause & EDC1_F)
4844                 mem_intr_handler(adapter, MEM_EDC1);
4845         if (cause & LE_F)
4846                 le_intr_handler(adapter);
4847         if (cause & TP_F)
4848                 tp_intr_handler(adapter);
4849         if (cause & MA_F)
4850                 ma_intr_handler(adapter);
4851         if (cause & PM_TX_F)
4852                 pmtx_intr_handler(adapter);
4853         if (cause & PM_RX_F)
4854                 pmrx_intr_handler(adapter);
4855         if (cause & ULP_RX_F)
4856                 ulprx_intr_handler(adapter);
4857         if (cause & CPL_SWITCH_F)
4858                 cplsw_intr_handler(adapter);
4859         if (cause & SGE_F)
4860                 sge_intr_handler(adapter);
4861         if (cause & ULP_TX_F)
4862                 ulptx_intr_handler(adapter);
4863
4864         /* Clear the interrupts just processed for which we are the master. */
4865         t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4866         (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4867         return 1;
4868 }
4869
4870 /**
4871  *      t4_intr_enable - enable interrupts
4872  *      @adapter: the adapter whose interrupts should be enabled
4873  *
4874  *      Enable PF-specific interrupts for the calling function and the top-level
4875  *      interrupt concentrator for global interrupts.  Interrupts are already
4876  *      enabled at each module, here we just enable the roots of the interrupt
4877  *      hierarchies.
4878  *
4879  *      Note: this function should be called only when the driver manages
4880  *      non PF-specific interrupts from the various HW modules.  Only one PCI
4881  *      function at a time should be doing this.
4882  */
4883 void t4_intr_enable(struct adapter *adapter)
4884 {
4885         u32 val = 0;
4886         u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4887         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4888                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4889
4890         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4891                 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4892         t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4893                      ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4894                      ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4895                      ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4896                      ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4897                      ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4898                      DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4899         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4900         t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4901 }
4902
4903 /**
4904  *      t4_intr_disable - disable interrupts
4905  *      @adapter: the adapter whose interrupts should be disabled
4906  *
4907  *      Disable interrupts.  We only disable the top-level interrupt
4908  *      concentrators.  The caller must be a PCI function managing global
4909  *      interrupts.
4910  */
4911 void t4_intr_disable(struct adapter *adapter)
4912 {
4913         u32 whoami, pf;
4914
4915         if (pci_channel_offline(adapter->pdev))
4916                 return;
4917
4918         whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4919         pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4920                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4921
4922         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4923         t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4924 }
4925
4926 /**
4927  *      t4_config_rss_range - configure a portion of the RSS mapping table
4928  *      @adapter: the adapter
4929  *      @mbox: mbox to use for the FW command
4930  *      @viid: virtual interface whose RSS subtable is to be written
4931  *      @start: start entry in the table to write
4932  *      @n: how many table entries to write
4933  *      @rspq: values for the response queue lookup table
4934  *      @nrspq: number of values in @rspq
4935  *
4936  *      Programs the selected part of the VI's RSS mapping table with the
4937  *      provided values.  If @nrspq < @n the supplied values are used repeatedly
4938  *      until the full table range is populated.
4939  *
4940  *      The caller must ensure the values in @rspq are in the range allowed for
4941  *      @viid.
4942  */
4943 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4944                         int start, int n, const u16 *rspq, unsigned int nrspq)
4945 {
4946         int ret;
4947         const u16 *rsp = rspq;
4948         const u16 *rsp_end = rspq + nrspq;
4949         struct fw_rss_ind_tbl_cmd cmd;
4950
4951         memset(&cmd, 0, sizeof(cmd));
4952         cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4953                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4954                                FW_RSS_IND_TBL_CMD_VIID_V(viid));
4955         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4956
4957         /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4958         while (n > 0) {
4959                 int nq = min(n, 32);
4960                 __be32 *qp = &cmd.iq0_to_iq2;
4961
4962                 cmd.niqid = cpu_to_be16(nq);
4963                 cmd.startidx = cpu_to_be16(start);
4964
4965                 start += nq;
4966                 n -= nq;
4967
4968                 while (nq > 0) {
4969                         unsigned int v;
4970
4971                         v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4972                         if (++rsp >= rsp_end)
4973                                 rsp = rspq;
4974                         v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4975                         if (++rsp >= rsp_end)
4976                                 rsp = rspq;
4977                         v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4978                         if (++rsp >= rsp_end)
4979                                 rsp = rspq;
4980
4981                         *qp++ = cpu_to_be32(v);
4982                         nq -= 3;
4983                 }
4984
4985                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4986                 if (ret)
4987                         return ret;
4988         }
4989         return 0;
4990 }
4991
4992 /**
4993  *      t4_config_glbl_rss - configure the global RSS mode
4994  *      @adapter: the adapter
4995  *      @mbox: mbox to use for the FW command
4996  *      @mode: global RSS mode
4997  *      @flags: mode-specific flags
4998  *
4999  *      Sets the global RSS mode.
5000  */
5001 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5002                        unsigned int flags)
5003 {
5004         struct fw_rss_glb_config_cmd c;
5005
5006         memset(&c, 0, sizeof(c));
5007         c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
5008                                     FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5009         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5010         if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5011                 c.u.manual.mode_pkd =
5012                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5013         } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5014                 c.u.basicvirtual.mode_pkd =
5015                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5016                 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5017         } else
5018                 return -EINVAL;
5019         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5020 }
5021
5022 /**
5023  *      t4_config_vi_rss - configure per VI RSS settings
5024  *      @adapter: the adapter
5025  *      @mbox: mbox to use for the FW command
5026  *      @viid: the VI id
5027  *      @flags: RSS flags
5028  *      @defq: id of the default RSS queue for the VI.
5029  *
5030  *      Configures VI-specific RSS properties.
5031  */
5032 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5033                      unsigned int flags, unsigned int defq)
5034 {
5035         struct fw_rss_vi_config_cmd c;
5036
5037         memset(&c, 0, sizeof(c));
5038         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5039                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5040                                    FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5041         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5042         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5043                                         FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5044         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5045 }
5046
5047 /* Read an RSS table row */
5048 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5049 {
5050         t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5051         return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5052                                    5, 0, val);
5053 }
5054
5055 /**
5056  *      t4_read_rss - read the contents of the RSS mapping table
5057  *      @adapter: the adapter
5058  *      @map: holds the contents of the RSS mapping table
5059  *
5060  *      Reads the contents of the RSS hash->queue mapping table.
5061  */
5062 int t4_read_rss(struct adapter *adapter, u16 *map)
5063 {
5064         u32 val;
5065         int i, ret;
5066
5067         for (i = 0; i < RSS_NENTRIES / 2; ++i) {
5068                 ret = rd_rss_row(adapter, i, &val);
5069                 if (ret)
5070                         return ret;
5071                 *map++ = LKPTBLQUEUE0_G(val);
5072                 *map++ = LKPTBLQUEUE1_G(val);
5073         }
5074         return 0;
5075 }
5076
5077 static unsigned int t4_use_ldst(struct adapter *adap)
5078 {
5079         return (adap->flags & FW_OK) || !adap->use_bd;
5080 }
5081
5082 /**
5083  * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5084  * @adap: the adapter
5085  * @cmd: TP fw ldst address space type
5086  * @vals: where the indirect register values are stored/written
5087  * @nregs: how many indirect registers to read/write
5088  * @start_idx: index of first indirect register to read/write
5089  * @rw: Read (1) or Write (0)
5090  * @sleep_ok: if true we may sleep while awaiting command completion
5091  *
5092  * Access TP indirect registers through LDST
5093  */
5094 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5095                             unsigned int nregs, unsigned int start_index,
5096                             unsigned int rw, bool sleep_ok)
5097 {
5098         int ret = 0;
5099         unsigned int i;
5100         struct fw_ldst_cmd c;
5101
5102         for (i = 0; i < nregs; i++) {
5103                 memset(&c, 0, sizeof(c));
5104                 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5105                                                 FW_CMD_REQUEST_F |
5106                                                 (rw ? FW_CMD_READ_F :
5107                                                       FW_CMD_WRITE_F) |
5108                                                 FW_LDST_CMD_ADDRSPACE_V(cmd));
5109                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5110
5111                 c.u.addrval.addr = cpu_to_be32(start_index + i);
5112                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
5113                 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5114                                       sleep_ok);
5115                 if (ret)
5116                         return ret;
5117
5118                 if (rw)
5119                         vals[i] = be32_to_cpu(c.u.addrval.val);
5120         }
5121         return 0;
5122 }
5123
5124 /**
5125  * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5126  * @adap: the adapter
5127  * @reg_addr: Address Register
5128  * @reg_data: Data register
5129  * @buff: where the indirect register values are stored/written
5130  * @nregs: how many indirect registers to read/write
5131  * @start_index: index of first indirect register to read/write
5132  * @rw: READ(1) or WRITE(0)
5133  * @sleep_ok: if true we may sleep while awaiting command completion
5134  *
5135  * Read/Write TP indirect registers through LDST if possible.
5136  * Else, use backdoor access
5137  **/
5138 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5139                               u32 *buff, u32 nregs, u32 start_index, int rw,
5140                               bool sleep_ok)
5141 {
5142         int rc = -EINVAL;
5143         int cmd;
5144
5145         switch (reg_addr) {
5146         case TP_PIO_ADDR_A:
5147                 cmd = FW_LDST_ADDRSPC_TP_PIO;
5148                 break;
5149         case TP_TM_PIO_ADDR_A:
5150                 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5151                 break;
5152         case TP_MIB_INDEX_A:
5153                 cmd = FW_LDST_ADDRSPC_TP_MIB;
5154                 break;
5155         default:
5156                 goto indirect_access;
5157         }
5158
5159         if (t4_use_ldst(adap))
5160                 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5161                                       sleep_ok);
5162
5163 indirect_access:
5164
5165         if (rc) {
5166                 if (rw)
5167                         t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5168                                          start_index);
5169                 else
5170                         t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5171                                           start_index);
5172         }
5173 }
5174
5175 /**
5176  * t4_tp_pio_read - Read TP PIO registers
5177  * @adap: the adapter
5178  * @buff: where the indirect register values are written
5179  * @nregs: how many indirect registers to read
5180  * @start_index: index of first indirect register to read
5181  * @sleep_ok: if true we may sleep while awaiting command completion
5182  *
5183  * Read TP PIO Registers
5184  **/
5185 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5186                     u32 start_index, bool sleep_ok)
5187 {
5188         t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5189                           start_index, 1, sleep_ok);
5190 }
5191
5192 /**
5193  * t4_tp_pio_write - Write TP PIO registers
5194  * @adap: the adapter
5195  * @buff: where the indirect register values are stored
5196  * @nregs: how many indirect registers to write
5197  * @start_index: index of first indirect register to write
5198  * @sleep_ok: if true we may sleep while awaiting command completion
5199  *
5200  * Write TP PIO Registers
5201  **/
5202 static void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs,
5203                             u32 start_index, bool sleep_ok)
5204 {
5205         t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5206                           start_index, 0, sleep_ok);
5207 }
5208
5209 /**
5210  * t4_tp_tm_pio_read - Read TP TM PIO registers
5211  * @adap: the adapter
5212  * @buff: where the indirect register values are written
5213  * @nregs: how many indirect registers to read
5214  * @start_index: index of first indirect register to read
5215  * @sleep_ok: if true we may sleep while awaiting command completion
5216  *
5217  * Read TP TM PIO Registers
5218  **/
5219 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5220                        u32 start_index, bool sleep_ok)
5221 {
5222         t4_tp_indirect_rw(adap, TP_TM_PIO_ADDR_A, TP_TM_PIO_DATA_A, buff,
5223                           nregs, start_index, 1, sleep_ok);
5224 }
5225
5226 /**
5227  * t4_tp_mib_read - Read TP MIB registers
5228  * @adap: the adapter
5229  * @buff: where the indirect register values are written
5230  * @nregs: how many indirect registers to read
5231  * @start_index: index of first indirect register to read
5232  * @sleep_ok: if true we may sleep while awaiting command completion
5233  *
5234  * Read TP MIB Registers
5235  **/
5236 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5237                     bool sleep_ok)
5238 {
5239         t4_tp_indirect_rw(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, buff, nregs,
5240                           start_index, 1, sleep_ok);
5241 }
5242
5243 /**
5244  *      t4_read_rss_key - read the global RSS key
5245  *      @adap: the adapter
5246  *      @key: 10-entry array holding the 320-bit RSS key
5247  *      @sleep_ok: if true we may sleep while awaiting command completion
5248  *
5249  *      Reads the global 320-bit RSS key.
5250  */
5251 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5252 {
5253         t4_tp_pio_read(adap, key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5254 }
5255
5256 /**
5257  *      t4_write_rss_key - program one of the RSS keys
5258  *      @adap: the adapter
5259  *      @key: 10-entry array holding the 320-bit RSS key
5260  *      @idx: which RSS key to write
5261  *      @sleep_ok: if true we may sleep while awaiting command completion
5262  *
5263  *      Writes one of the RSS keys with the given 320-bit value.  If @idx is
5264  *      0..15 the corresponding entry in the RSS key table is written,
5265  *      otherwise the global RSS key is written.
5266  */
5267 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5268                       bool sleep_ok)
5269 {
5270         u8 rss_key_addr_cnt = 16;
5271         u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5272
5273         /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5274          * allows access to key addresses 16-63 by using KeyWrAddrX
5275          * as index[5:4](upper 2) into key table
5276          */
5277         if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5278             (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5279                 rss_key_addr_cnt = 32;
5280
5281         t4_tp_pio_write(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5282
5283         if (idx >= 0 && idx < rss_key_addr_cnt) {
5284                 if (rss_key_addr_cnt > 16)
5285                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5286                                      KEYWRADDRX_V(idx >> 4) |
5287                                      T6_VFWRADDR_V(idx) | KEYWREN_F);
5288                 else
5289                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5290                                      KEYWRADDR_V(idx) | KEYWREN_F);
5291         }
5292 }
5293
5294 /**
5295  *      t4_read_rss_pf_config - read PF RSS Configuration Table
5296  *      @adapter: the adapter
5297  *      @index: the entry in the PF RSS table to read
5298  *      @valp: where to store the returned value
5299  *      @sleep_ok: if true we may sleep while awaiting command completion
5300  *
5301  *      Reads the PF RSS Configuration Table at the specified index and returns
5302  *      the value found there.
5303  */
5304 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5305                            u32 *valp, bool sleep_ok)
5306 {
5307         t4_tp_pio_read(adapter, valp, 1, TP_RSS_PF0_CONFIG_A + index, sleep_ok);
5308 }
5309
5310 /**
5311  *      t4_read_rss_vf_config - read VF RSS Configuration Table
5312  *      @adapter: the adapter
5313  *      @index: the entry in the VF RSS table to read
5314  *      @vfl: where to store the returned VFL
5315  *      @vfh: where to store the returned VFH
5316  *      @sleep_ok: if true we may sleep while awaiting command completion
5317  *
5318  *      Reads the VF RSS Configuration Table at the specified index and returns
5319  *      the (VFL, VFH) values found there.
5320  */
5321 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5322                            u32 *vfl, u32 *vfh, bool sleep_ok)
5323 {
5324         u32 vrt, mask, data;
5325
5326         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5327                 mask = VFWRADDR_V(VFWRADDR_M);
5328                 data = VFWRADDR_V(index);
5329         } else {
5330                  mask =  T6_VFWRADDR_V(T6_VFWRADDR_M);
5331                  data = T6_VFWRADDR_V(index);
5332         }
5333
5334         /* Request that the index'th VF Table values be read into VFL/VFH.
5335          */
5336         vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5337         vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5338         vrt |= data | VFRDEN_F;
5339         t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5340
5341         /* Grab the VFL/VFH values ...
5342          */
5343         t4_tp_pio_read(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, sleep_ok);
5344         t4_tp_pio_read(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, sleep_ok);
5345 }
5346
5347 /**
5348  *      t4_read_rss_pf_map - read PF RSS Map
5349  *      @adapter: the adapter
5350  *      @sleep_ok: if true we may sleep while awaiting command completion
5351  *
5352  *      Reads the PF RSS Map register and returns its value.
5353  */
5354 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5355 {
5356         u32 pfmap;
5357
5358         t4_tp_pio_read(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, sleep_ok);
5359         return pfmap;
5360 }
5361
5362 /**
5363  *      t4_read_rss_pf_mask - read PF RSS Mask
5364  *      @adapter: the adapter
5365  *      @sleep_ok: if true we may sleep while awaiting command completion
5366  *
5367  *      Reads the PF RSS Mask register and returns its value.
5368  */
5369 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
5370 {
5371         u32 pfmask;
5372
5373         t4_tp_pio_read(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, sleep_ok);
5374         return pfmask;
5375 }
5376
5377 /**
5378  *      t4_tp_get_tcp_stats - read TP's TCP MIB counters
5379  *      @adap: the adapter
5380  *      @v4: holds the TCP/IP counter values
5381  *      @v6: holds the TCP/IPv6 counter values
5382  *      @sleep_ok: if true we may sleep while awaiting command completion
5383  *
5384  *      Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5385  *      Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5386  */
5387 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5388                          struct tp_tcp_stats *v6, bool sleep_ok)
5389 {
5390         u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5391
5392 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5393 #define STAT(x)     val[STAT_IDX(x)]
5394 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5395
5396         if (v4) {
5397                 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5398                                TP_MIB_TCP_OUT_RST_A, sleep_ok);
5399                 v4->tcp_out_rsts = STAT(OUT_RST);
5400                 v4->tcp_in_segs  = STAT64(IN_SEG);
5401                 v4->tcp_out_segs = STAT64(OUT_SEG);
5402                 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5403         }
5404         if (v6) {
5405                 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5406                                TP_MIB_TCP_V6OUT_RST_A, sleep_ok);
5407                 v6->tcp_out_rsts = STAT(OUT_RST);
5408                 v6->tcp_in_segs  = STAT64(IN_SEG);
5409                 v6->tcp_out_segs = STAT64(OUT_SEG);
5410                 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5411         }
5412 #undef STAT64
5413 #undef STAT
5414 #undef STAT_IDX
5415 }
5416
5417 /**
5418  *      t4_tp_get_err_stats - read TP's error MIB counters
5419  *      @adap: the adapter
5420  *      @st: holds the counter values
5421  *      @sleep_ok: if true we may sleep while awaiting command completion
5422  *
5423  *      Returns the values of TP's error counters.
5424  */
5425 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
5426                          bool sleep_ok)
5427 {
5428         int nchan = adap->params.arch.nchan;
5429
5430         t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A,
5431                        sleep_ok);
5432         t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A,
5433                        sleep_ok);
5434         t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A,
5435                        sleep_ok);
5436         t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
5437                        TP_MIB_TNL_CNG_DROP_0_A, sleep_ok);
5438         t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
5439                        TP_MIB_OFD_CHN_DROP_0_A, sleep_ok);
5440         t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A,
5441                        sleep_ok);
5442         t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
5443                        TP_MIB_OFD_VLN_DROP_0_A, sleep_ok);
5444         t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
5445                        TP_MIB_TCP_V6IN_ERR_0_A, sleep_ok);
5446         t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A,
5447                        sleep_ok);
5448 }
5449
5450 /**
5451  *      t4_tp_get_cpl_stats - read TP's CPL MIB counters
5452  *      @adap: the adapter
5453  *      @st: holds the counter values
5454  *      @sleep_ok: if true we may sleep while awaiting command completion
5455  *
5456  *      Returns the values of TP's CPL counters.
5457  */
5458 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
5459                          bool sleep_ok)
5460 {
5461         int nchan = adap->params.arch.nchan;
5462
5463         t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok);
5464
5465         t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok);
5466 }
5467
5468 /**
5469  *      t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5470  *      @adap: the adapter
5471  *      @st: holds the counter values
5472  *      @sleep_ok: if true we may sleep while awaiting command completion
5473  *
5474  *      Returns the values of TP's RDMA counters.
5475  */
5476 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
5477                           bool sleep_ok)
5478 {
5479         t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
5480                        sleep_ok);
5481 }
5482
5483 /**
5484  *      t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5485  *      @adap: the adapter
5486  *      @idx: the port index
5487  *      @st: holds the counter values
5488  *      @sleep_ok: if true we may sleep while awaiting command completion
5489  *
5490  *      Returns the values of TP's FCoE counters for the selected port.
5491  */
5492 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5493                        struct tp_fcoe_stats *st, bool sleep_ok)
5494 {
5495         u32 val[2];
5496
5497         t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx,
5498                        sleep_ok);
5499
5500         t4_tp_mib_read(adap, &st->frames_drop, 1,
5501                        TP_MIB_FCOE_DROP_0_A + idx, sleep_ok);
5502
5503         t4_tp_mib_read(adap, val, 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx,
5504                        sleep_ok);
5505
5506         st->octets_ddp = ((u64)val[0] << 32) | val[1];
5507 }
5508
5509 /**
5510  *      t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5511  *      @adap: the adapter
5512  *      @st: holds the counter values
5513  *      @sleep_ok: if true we may sleep while awaiting command completion
5514  *
5515  *      Returns the values of TP's counters for non-TCP directly-placed packets.
5516  */
5517 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
5518                       bool sleep_ok)
5519 {
5520         u32 val[4];
5521
5522         t4_tp_mib_read(adap, val, 4, TP_MIB_USM_PKTS_A, sleep_ok);
5523         st->frames = val[0];
5524         st->drops = val[1];
5525         st->octets = ((u64)val[2] << 32) | val[3];
5526 }
5527
5528 /**
5529  *      t4_read_mtu_tbl - returns the values in the HW path MTU table
5530  *      @adap: the adapter
5531  *      @mtus: where to store the MTU values
5532  *      @mtu_log: where to store the MTU base-2 log (may be %NULL)
5533  *
5534  *      Reads the HW path MTU table.
5535  */
5536 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5537 {
5538         u32 v;
5539         int i;
5540
5541         for (i = 0; i < NMTUS; ++i) {
5542                 t4_write_reg(adap, TP_MTU_TABLE_A,
5543                              MTUINDEX_V(0xff) | MTUVALUE_V(i));
5544                 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5545                 mtus[i] = MTUVALUE_G(v);
5546                 if (mtu_log)
5547                         mtu_log[i] = MTUWIDTH_G(v);
5548         }
5549 }
5550
5551 /**
5552  *      t4_read_cong_tbl - reads the congestion control table
5553  *      @adap: the adapter
5554  *      @incr: where to store the alpha values
5555  *
5556  *      Reads the additive increments programmed into the HW congestion
5557  *      control table.
5558  */
5559 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5560 {
5561         unsigned int mtu, w;
5562
5563         for (mtu = 0; mtu < NMTUS; ++mtu)
5564                 for (w = 0; w < NCCTRL_WIN; ++w) {
5565                         t4_write_reg(adap, TP_CCTRL_TABLE_A,
5566                                      ROWINDEX_V(0xffff) | (mtu << 5) | w);
5567                         incr[mtu][w] = (u16)t4_read_reg(adap,
5568                                                 TP_CCTRL_TABLE_A) & 0x1fff;
5569                 }
5570 }
5571
5572 /**
5573  *      t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5574  *      @adap: the adapter
5575  *      @addr: the indirect TP register address
5576  *      @mask: specifies the field within the register to modify
5577  *      @val: new value for the field
5578  *
5579  *      Sets a field of an indirect TP register to the given value.
5580  */
5581 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5582                             unsigned int mask, unsigned int val)
5583 {
5584         t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5585         val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5586         t4_write_reg(adap, TP_PIO_DATA_A, val);
5587 }
5588
5589 /**
5590  *      init_cong_ctrl - initialize congestion control parameters
5591  *      @a: the alpha values for congestion control
5592  *      @b: the beta values for congestion control
5593  *
5594  *      Initialize the congestion control parameters.
5595  */
5596 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5597 {
5598         a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5599         a[9] = 2;
5600         a[10] = 3;
5601         a[11] = 4;
5602         a[12] = 5;
5603         a[13] = 6;
5604         a[14] = 7;
5605         a[15] = 8;
5606         a[16] = 9;
5607         a[17] = 10;
5608         a[18] = 14;
5609         a[19] = 17;
5610         a[20] = 21;
5611         a[21] = 25;
5612         a[22] = 30;
5613         a[23] = 35;
5614         a[24] = 45;
5615         a[25] = 60;
5616         a[26] = 80;
5617         a[27] = 100;
5618         a[28] = 200;
5619         a[29] = 300;
5620         a[30] = 400;
5621         a[31] = 500;
5622
5623         b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5624         b[9] = b[10] = 1;
5625         b[11] = b[12] = 2;
5626         b[13] = b[14] = b[15] = b[16] = 3;
5627         b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5628         b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5629         b[28] = b[29] = 6;
5630         b[30] = b[31] = 7;
5631 }
5632
5633 /* The minimum additive increment value for the congestion control table */
5634 #define CC_MIN_INCR 2U
5635
5636 /**
5637  *      t4_load_mtus - write the MTU and congestion control HW tables
5638  *      @adap: the adapter
5639  *      @mtus: the values for the MTU table
5640  *      @alpha: the values for the congestion control alpha parameter
5641  *      @beta: the values for the congestion control beta parameter
5642  *
5643  *      Write the HW MTU table with the supplied MTUs and the high-speed
5644  *      congestion control table with the supplied alpha, beta, and MTUs.
5645  *      We write the two tables together because the additive increments
5646  *      depend on the MTUs.
5647  */
5648 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5649                   const unsigned short *alpha, const unsigned short *beta)
5650 {
5651         static const unsigned int avg_pkts[NCCTRL_WIN] = {
5652                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5653                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5654                 28672, 40960, 57344, 81920, 114688, 163840, 229376
5655         };
5656
5657         unsigned int i, w;
5658
5659         for (i = 0; i < NMTUS; ++i) {
5660                 unsigned int mtu = mtus[i];
5661                 unsigned int log2 = fls(mtu);
5662
5663                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
5664                         log2--;
5665                 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5666                              MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5667
5668                 for (w = 0; w < NCCTRL_WIN; ++w) {
5669                         unsigned int inc;
5670
5671                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5672                                   CC_MIN_INCR);
5673
5674                         t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5675                                      (w << 16) | (beta[w] << 13) | inc);
5676                 }
5677         }
5678 }
5679
5680 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5681  * clocks.  The formula is
5682  *
5683  * bytes/s = bytes256 * 256 * ClkFreq / 4096
5684  *
5685  * which is equivalent to
5686  *
5687  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5688  */
5689 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5690 {
5691         u64 v = bytes256 * adap->params.vpd.cclk;
5692
5693         return v * 62 + v / 2;
5694 }
5695
5696 /**
5697  *      t4_get_chan_txrate - get the current per channel Tx rates
5698  *      @adap: the adapter
5699  *      @nic_rate: rates for NIC traffic
5700  *      @ofld_rate: rates for offloaded traffic
5701  *
5702  *      Return the current Tx rates in bytes/s for NIC and offloaded traffic
5703  *      for each channel.
5704  */
5705 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5706 {
5707         u32 v;
5708
5709         v = t4_read_reg(adap, TP_TX_TRATE_A);
5710         nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5711         nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5712         if (adap->params.arch.nchan == NCHAN) {
5713                 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5714                 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5715         }
5716
5717         v = t4_read_reg(adap, TP_TX_ORATE_A);
5718         ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5719         ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5720         if (adap->params.arch.nchan == NCHAN) {
5721                 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5722                 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5723         }
5724 }
5725
5726 /**
5727  *      t4_set_trace_filter - configure one of the tracing filters
5728  *      @adap: the adapter
5729  *      @tp: the desired trace filter parameters
5730  *      @idx: which filter to configure
5731  *      @enable: whether to enable or disable the filter
5732  *
5733  *      Configures one of the tracing filters available in HW.  If @enable is
5734  *      %0 @tp is not examined and may be %NULL. The user is responsible to
5735  *      set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5736  */
5737 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5738                         int idx, int enable)
5739 {
5740         int i, ofst = idx * 4;
5741         u32 data_reg, mask_reg, cfg;
5742         u32 multitrc = TRCMULTIFILTER_F;
5743
5744         if (!enable) {
5745                 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5746                 return 0;
5747         }
5748
5749         cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5750         if (cfg & TRCMULTIFILTER_F) {
5751                 /* If multiple tracers are enabled, then maximum
5752                  * capture size is 2.5KB (FIFO size of a single channel)
5753                  * minus 2 flits for CPL_TRACE_PKT header.
5754                  */
5755                 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5756                         return -EINVAL;
5757         } else {
5758                 /* If multiple tracers are disabled, to avoid deadlocks
5759                  * maximum packet capture size of 9600 bytes is recommended.
5760                  * Also in this mode, only trace0 can be enabled and running.
5761                  */
5762                 multitrc = 0;
5763                 if (tp->snap_len > 9600 || idx)
5764                         return -EINVAL;
5765         }
5766
5767         if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5768             tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5769             tp->min_len > TFMINPKTSIZE_M)
5770                 return -EINVAL;
5771
5772         /* stop the tracer we'll be changing */
5773         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5774
5775         idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5776         data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5777         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5778
5779         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5780                 t4_write_reg(adap, data_reg, tp->data[i]);
5781                 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5782         }
5783         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5784                      TFCAPTUREMAX_V(tp->snap_len) |
5785                      TFMINPKTSIZE_V(tp->min_len));
5786         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5787                      TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5788                      (is_t4(adap->params.chip) ?
5789                      TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5790                      T5_TFPORT_V(tp->port) | T5_TFEN_F |
5791                      T5_TFINVERTMATCH_V(tp->invert)));
5792
5793         return 0;
5794 }
5795
5796 /**
5797  *      t4_get_trace_filter - query one of the tracing filters
5798  *      @adap: the adapter
5799  *      @tp: the current trace filter parameters
5800  *      @idx: which trace filter to query
5801  *      @enabled: non-zero if the filter is enabled
5802  *
5803  *      Returns the current settings of one of the HW tracing filters.
5804  */
5805 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5806                          int *enabled)
5807 {
5808         u32 ctla, ctlb;
5809         int i, ofst = idx * 4;
5810         u32 data_reg, mask_reg;
5811
5812         ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5813         ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5814
5815         if (is_t4(adap->params.chip)) {
5816                 *enabled = !!(ctla & TFEN_F);
5817                 tp->port =  TFPORT_G(ctla);
5818                 tp->invert = !!(ctla & TFINVERTMATCH_F);
5819         } else {
5820                 *enabled = !!(ctla & T5_TFEN_F);
5821                 tp->port = T5_TFPORT_G(ctla);
5822                 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5823         }
5824         tp->snap_len = TFCAPTUREMAX_G(ctlb);
5825         tp->min_len = TFMINPKTSIZE_G(ctlb);
5826         tp->skip_ofst = TFOFFSET_G(ctla);
5827         tp->skip_len = TFLENGTH_G(ctla);
5828
5829         ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5830         data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5831         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5832
5833         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5834                 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5835                 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5836         }
5837 }
5838
5839 /**
5840  *      t4_pmtx_get_stats - returns the HW stats from PMTX
5841  *      @adap: the adapter
5842  *      @cnt: where to store the count statistics
5843  *      @cycles: where to store the cycle statistics
5844  *
5845  *      Returns performance statistics from PMTX.
5846  */
5847 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5848 {
5849         int i;
5850         u32 data[2];
5851
5852         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5853                 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5854                 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5855                 if (is_t4(adap->params.chip)) {
5856                         cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5857                 } else {
5858                         t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5859                                          PM_TX_DBG_DATA_A, data, 2,
5860                                          PM_TX_DBG_STAT_MSB_A);
5861                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5862                 }
5863         }
5864 }
5865
5866 /**
5867  *      t4_pmrx_get_stats - returns the HW stats from PMRX
5868  *      @adap: the adapter
5869  *      @cnt: where to store the count statistics
5870  *      @cycles: where to store the cycle statistics
5871  *
5872  *      Returns performance statistics from PMRX.
5873  */
5874 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5875 {
5876         int i;
5877         u32 data[2];
5878
5879         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5880                 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5881                 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5882                 if (is_t4(adap->params.chip)) {
5883                         cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5884                 } else {
5885                         t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5886                                          PM_RX_DBG_DATA_A, data, 2,
5887                                          PM_RX_DBG_STAT_MSB_A);
5888                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5889                 }
5890         }
5891 }
5892
5893 /**
5894  *      compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
5895  *      @adap: the adapter
5896  *      @pidx: the port index
5897  *
5898  *      Computes and returns a bitmap indicating which MPS buffer groups are
5899  *      associated with the given Port.  Bit i is set if buffer group i is
5900  *      used by the Port.
5901  */
5902 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
5903                                               int pidx)
5904 {
5905         unsigned int chip_version, nports;
5906
5907         chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5908         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
5909
5910         switch (chip_version) {
5911         case CHELSIO_T4:
5912         case CHELSIO_T5:
5913                 switch (nports) {
5914                 case 1: return 0xf;
5915                 case 2: return 3 << (2 * pidx);
5916                 case 4: return 1 << pidx;
5917                 }
5918                 break;
5919
5920         case CHELSIO_T6:
5921                 switch (nports) {
5922                 case 2: return 1 << (2 * pidx);
5923                 }
5924                 break;
5925         }
5926
5927         dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
5928                 chip_version, nports);
5929
5930         return 0;
5931 }
5932
5933 /**
5934  *      t4_get_mps_bg_map - return the buffer groups associated with a port
5935  *      @adapter: the adapter
5936  *      @pidx: the port index
5937  *
5938  *      Returns a bitmap indicating which MPS buffer groups are associated
5939  *      with the given Port.  Bit i is set if buffer group i is used by the
5940  *      Port.
5941  */
5942 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
5943 {
5944         u8 *mps_bg_map;
5945         unsigned int nports;
5946
5947         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
5948         if (pidx >= nports) {
5949                 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
5950                         pidx, nports);
5951                 return 0;
5952         }
5953
5954         /* If we've already retrieved/computed this, just return the result.
5955          */
5956         mps_bg_map = adapter->params.mps_bg_map;
5957         if (mps_bg_map[pidx])
5958                 return mps_bg_map[pidx];
5959
5960         /* Newer Firmware can tell us what the MPS Buffer Group Map is.
5961          * If we're talking to such Firmware, let it tell us.  If the new
5962          * API isn't supported, revert back to old hardcoded way.  The value
5963          * obtained from Firmware is encoded in below format:
5964          *
5965          * val = (( MPSBGMAP[Port 3] << 24 ) |
5966          *        ( MPSBGMAP[Port 2] << 16 ) |
5967          *        ( MPSBGMAP[Port 1] <<  8 ) |
5968          *        ( MPSBGMAP[Port 0] <<  0 ))
5969          */
5970         if (adapter->flags & FW_OK) {
5971                 u32 param, val;
5972                 int ret;
5973
5974                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5975                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
5976                 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
5977                                          0, 1, &param, &val);
5978                 if (!ret) {
5979                         int p;
5980
5981                         /* Store the BG Map for all of the Ports in order to
5982                          * avoid more calls to the Firmware in the future.
5983                          */
5984                         for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
5985                                 mps_bg_map[p] = val & 0xff;
5986
5987                         return mps_bg_map[pidx];
5988                 }
5989         }
5990
5991         /* Either we're not talking to the Firmware or we're dealing with
5992          * older Firmware which doesn't support the new API to get the MPS
5993          * Buffer Group Map.  Fall back to computing it ourselves.
5994          */
5995         mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
5996         return mps_bg_map[pidx];
5997 }
5998
5999 /**
6000  *      t4_get_tp_ch_map - return TP ingress channels associated with a port
6001  *      @adapter: the adapter
6002  *      @pidx: the port index
6003  *
6004  *      Returns a bitmap indicating which TP Ingress Channels are associated
6005  *      with a given Port.  Bit i is set if TP Ingress Channel i is used by
6006  *      the Port.
6007  */
6008 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
6009 {
6010         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
6011         unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
6012
6013         if (pidx >= nports) {
6014                 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
6015                          pidx, nports);
6016                 return 0;
6017         }
6018
6019         switch (chip_version) {
6020         case CHELSIO_T4:
6021         case CHELSIO_T5:
6022                 /* Note that this happens to be the same values as the MPS
6023                  * Buffer Group Map for these Chips.  But we replicate the code
6024                  * here because they're really separate concepts.
6025                  */
6026                 switch (nports) {
6027                 case 1: return 0xf;
6028                 case 2: return 3 << (2 * pidx);
6029                 case 4: return 1 << pidx;
6030                 }
6031                 break;
6032
6033         case CHELSIO_T6:
6034                 switch (nports) {
6035                 case 2: return 1 << pidx;
6036                 }
6037                 break;
6038         }
6039
6040         dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
6041                 chip_version, nports);
6042         return 0;
6043 }
6044
6045 /**
6046  *      t4_get_port_type_description - return Port Type string description
6047  *      @port_type: firmware Port Type enumeration
6048  */
6049 const char *t4_get_port_type_description(enum fw_port_type port_type)
6050 {
6051         static const char *const port_type_description[] = {
6052                 "Fiber_XFI",
6053                 "Fiber_XAUI",
6054                 "BT_SGMII",
6055                 "BT_XFI",
6056                 "BT_XAUI",
6057                 "KX4",
6058                 "CX4",
6059                 "KX",
6060                 "KR",
6061                 "SFP",
6062                 "BP_AP",
6063                 "BP4_AP",
6064                 "QSFP_10G",
6065                 "QSA",
6066                 "QSFP",
6067                 "BP40_BA",
6068                 "KR4_100G",
6069                 "CR4_QSFP",
6070                 "CR_QSFP",
6071                 "CR2_QSFP",
6072                 "SFP28",
6073                 "KR_SFP28",
6074         };
6075
6076         if (port_type < ARRAY_SIZE(port_type_description))
6077                 return port_type_description[port_type];
6078         return "UNKNOWN";
6079 }
6080
6081 /**
6082  *      t4_get_port_stats_offset - collect port stats relative to a previous
6083  *                                 snapshot
6084  *      @adap: The adapter
6085  *      @idx: The port
6086  *      @stats: Current stats to fill
6087  *      @offset: Previous stats snapshot
6088  */
6089 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6090                               struct port_stats *stats,
6091                               struct port_stats *offset)
6092 {
6093         u64 *s, *o;
6094         int i;
6095
6096         t4_get_port_stats(adap, idx, stats);
6097         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
6098                         i < (sizeof(struct port_stats) / sizeof(u64));
6099                         i++, s++, o++)
6100                 *s -= *o;
6101 }
6102
6103 /**
6104  *      t4_get_port_stats - collect port statistics
6105  *      @adap: the adapter
6106  *      @idx: the port index
6107  *      @p: the stats structure to fill
6108  *
6109  *      Collect statistics related to the given port from HW.
6110  */
6111 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6112 {
6113         u32 bgmap = t4_get_mps_bg_map(adap, idx);
6114         u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
6115
6116 #define GET_STAT(name) \
6117         t4_read_reg64(adap, \
6118         (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6119         T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6120 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6121
6122         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
6123         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
6124         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
6125         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
6126         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
6127         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
6128         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
6129         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
6130         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
6131         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
6132         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
6133         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6134         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
6135         p->tx_drop             = GET_STAT(TX_PORT_DROP);
6136         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
6137         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
6138         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
6139         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
6140         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
6141         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
6142         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
6143         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
6144         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
6145
6146         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6147                 if (stat_ctl & COUNTPAUSESTATTX_F)
6148                         p->tx_frames_64 -= p->tx_pause;
6149                 if (stat_ctl & COUNTPAUSEMCTX_F)
6150                         p->tx_mcast_frames -= p->tx_pause;
6151         }
6152         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
6153         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
6154         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
6155         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
6156         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
6157         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
6158         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6159         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
6160         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
6161         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
6162         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
6163         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
6164         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
6165         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
6166         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
6167         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
6168         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6169         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
6170         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
6171         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
6172         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
6173         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
6174         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
6175         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
6176         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
6177         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
6178         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
6179
6180         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6181                 if (stat_ctl & COUNTPAUSESTATRX_F)
6182                         p->rx_frames_64 -= p->rx_pause;
6183                 if (stat_ctl & COUNTPAUSEMCRX_F)
6184                         p->rx_mcast_frames -= p->rx_pause;
6185         }
6186
6187         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6188         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6189         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6190         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6191         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6192         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6193         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6194         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6195
6196 #undef GET_STAT
6197 #undef GET_STAT_COM
6198 }
6199
6200 /**
6201  *      t4_get_lb_stats - collect loopback port statistics
6202  *      @adap: the adapter
6203  *      @idx: the loopback port index
6204  *      @p: the stats structure to fill
6205  *
6206  *      Return HW statistics for the given loopback port.
6207  */
6208 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6209 {
6210         u32 bgmap = t4_get_mps_bg_map(adap, idx);
6211
6212 #define GET_STAT(name) \
6213         t4_read_reg64(adap, \
6214         (is_t4(adap->params.chip) ? \
6215         PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6216         T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6217 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6218
6219         p->octets           = GET_STAT(BYTES);
6220         p->frames           = GET_STAT(FRAMES);
6221         p->bcast_frames     = GET_STAT(BCAST);
6222         p->mcast_frames     = GET_STAT(MCAST);
6223         p->ucast_frames     = GET_STAT(UCAST);
6224         p->error_frames     = GET_STAT(ERROR);
6225
6226         p->frames_64        = GET_STAT(64B);
6227         p->frames_65_127    = GET_STAT(65B_127B);
6228         p->frames_128_255   = GET_STAT(128B_255B);
6229         p->frames_256_511   = GET_STAT(256B_511B);
6230         p->frames_512_1023  = GET_STAT(512B_1023B);
6231         p->frames_1024_1518 = GET_STAT(1024B_1518B);
6232         p->frames_1519_max  = GET_STAT(1519B_MAX);
6233         p->drop             = GET_STAT(DROP_FRAMES);
6234
6235         p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6236         p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6237         p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6238         p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6239         p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6240         p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6241         p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6242         p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6243
6244 #undef GET_STAT
6245 #undef GET_STAT_COM
6246 }
6247
6248 /*     t4_mk_filtdelwr - create a delete filter WR
6249  *     @ftid: the filter ID
6250  *     @wr: the filter work request to populate
6251  *     @qid: ingress queue to receive the delete notification
6252  *
6253  *     Creates a filter work request to delete the supplied filter.  If @qid is
6254  *     negative the delete notification is suppressed.
6255  */
6256 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6257 {
6258         memset(wr, 0, sizeof(*wr));
6259         wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6260         wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6261         wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6262                                     FW_FILTER_WR_NOREPLY_V(qid < 0));
6263         wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6264         if (qid >= 0)
6265                 wr->rx_chan_rx_rpl_iq =
6266                         cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6267 }
6268
6269 #define INIT_CMD(var, cmd, rd_wr) do { \
6270         (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6271                                         FW_CMD_REQUEST_F | \
6272                                         FW_CMD_##rd_wr##_F); \
6273         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6274 } while (0)
6275
6276 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6277                           u32 addr, u32 val)
6278 {
6279         u32 ldst_addrspace;
6280         struct fw_ldst_cmd c;
6281
6282         memset(&c, 0, sizeof(c));
6283         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6284         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6285                                         FW_CMD_REQUEST_F |
6286                                         FW_CMD_WRITE_F |
6287                                         ldst_addrspace);
6288         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6289         c.u.addrval.addr = cpu_to_be32(addr);
6290         c.u.addrval.val = cpu_to_be32(val);
6291
6292         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6293 }
6294
6295 /**
6296  *      t4_mdio_rd - read a PHY register through MDIO
6297  *      @adap: the adapter
6298  *      @mbox: mailbox to use for the FW command
6299  *      @phy_addr: the PHY address
6300  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6301  *      @reg: the register to read
6302  *      @valp: where to store the value
6303  *
6304  *      Issues a FW command through the given mailbox to read a PHY register.
6305  */
6306 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6307                unsigned int mmd, unsigned int reg, u16 *valp)
6308 {
6309         int ret;
6310         u32 ldst_addrspace;
6311         struct fw_ldst_cmd c;
6312
6313         memset(&c, 0, sizeof(c));
6314         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6315         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6316                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6317                                         ldst_addrspace);
6318         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6319         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6320                                          FW_LDST_CMD_MMD_V(mmd));
6321         c.u.mdio.raddr = cpu_to_be16(reg);
6322
6323         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6324         if (ret == 0)
6325                 *valp = be16_to_cpu(c.u.mdio.rval);
6326         return ret;
6327 }
6328
6329 /**
6330  *      t4_mdio_wr - write a PHY register through MDIO
6331  *      @adap: the adapter
6332  *      @mbox: mailbox to use for the FW command
6333  *      @phy_addr: the PHY address
6334  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6335  *      @reg: the register to write
6336  *      @valp: value to write
6337  *
6338  *      Issues a FW command through the given mailbox to write a PHY register.
6339  */
6340 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6341                unsigned int mmd, unsigned int reg, u16 val)
6342 {
6343         u32 ldst_addrspace;
6344         struct fw_ldst_cmd c;
6345
6346         memset(&c, 0, sizeof(c));
6347         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6348         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6349                                         FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6350                                         ldst_addrspace);
6351         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6352         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6353                                          FW_LDST_CMD_MMD_V(mmd));
6354         c.u.mdio.raddr = cpu_to_be16(reg);
6355         c.u.mdio.rval = cpu_to_be16(val);
6356
6357         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6358 }
6359
6360 /**
6361  *      t4_sge_decode_idma_state - decode the idma state
6362  *      @adap: the adapter
6363  *      @state: the state idma is stuck in
6364  */
6365 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6366 {
6367         static const char * const t4_decode[] = {
6368                 "IDMA_IDLE",
6369                 "IDMA_PUSH_MORE_CPL_FIFO",
6370                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6371                 "Not used",
6372                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6373                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6374                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6375                 "IDMA_SEND_FIFO_TO_IMSG",
6376                 "IDMA_FL_REQ_DATA_FL_PREP",
6377                 "IDMA_FL_REQ_DATA_FL",
6378                 "IDMA_FL_DROP",
6379                 "IDMA_FL_H_REQ_HEADER_FL",
6380                 "IDMA_FL_H_SEND_PCIEHDR",
6381                 "IDMA_FL_H_PUSH_CPL_FIFO",
6382                 "IDMA_FL_H_SEND_CPL",
6383                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6384                 "IDMA_FL_H_SEND_IP_HDR",
6385                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6386                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6387                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6388                 "IDMA_FL_D_SEND_PCIEHDR",
6389                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6390                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6391                 "IDMA_FL_SEND_PCIEHDR",
6392                 "IDMA_FL_PUSH_CPL_FIFO",
6393                 "IDMA_FL_SEND_CPL",
6394                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6395                 "IDMA_FL_SEND_PAYLOAD",
6396                 "IDMA_FL_REQ_NEXT_DATA_FL",
6397                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6398                 "IDMA_FL_SEND_PADDING",
6399                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6400                 "IDMA_FL_SEND_FIFO_TO_IMSG",
6401                 "IDMA_FL_REQ_DATAFL_DONE",
6402                 "IDMA_FL_REQ_HEADERFL_DONE",
6403         };
6404         static const char * const t5_decode[] = {
6405                 "IDMA_IDLE",
6406                 "IDMA_ALMOST_IDLE",
6407                 "IDMA_PUSH_MORE_CPL_FIFO",
6408                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6409                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6410                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6411                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6412                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6413                 "IDMA_SEND_FIFO_TO_IMSG",
6414                 "IDMA_FL_REQ_DATA_FL",
6415                 "IDMA_FL_DROP",
6416                 "IDMA_FL_DROP_SEND_INC",
6417                 "IDMA_FL_H_REQ_HEADER_FL",
6418                 "IDMA_FL_H_SEND_PCIEHDR",
6419                 "IDMA_FL_H_PUSH_CPL_FIFO",
6420                 "IDMA_FL_H_SEND_CPL",
6421                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6422                 "IDMA_FL_H_SEND_IP_HDR",
6423                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6424                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6425                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6426                 "IDMA_FL_D_SEND_PCIEHDR",
6427                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6428                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6429                 "IDMA_FL_SEND_PCIEHDR",
6430                 "IDMA_FL_PUSH_CPL_FIFO",
6431                 "IDMA_FL_SEND_CPL",
6432                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6433                 "IDMA_FL_SEND_PAYLOAD",
6434                 "IDMA_FL_REQ_NEXT_DATA_FL",
6435                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6436                 "IDMA_FL_SEND_PADDING",
6437                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6438         };
6439         static const char * const t6_decode[] = {
6440                 "IDMA_IDLE",
6441                 "IDMA_PUSH_MORE_CPL_FIFO",
6442                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6443                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6444                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6445                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6446                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6447                 "IDMA_FL_REQ_DATA_FL",
6448                 "IDMA_FL_DROP",
6449                 "IDMA_FL_DROP_SEND_INC",
6450                 "IDMA_FL_H_REQ_HEADER_FL",
6451                 "IDMA_FL_H_SEND_PCIEHDR",
6452                 "IDMA_FL_H_PUSH_CPL_FIFO",
6453                 "IDMA_FL_H_SEND_CPL",
6454                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6455                 "IDMA_FL_H_SEND_IP_HDR",
6456                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6457                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6458                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6459                 "IDMA_FL_D_SEND_PCIEHDR",
6460                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6461                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6462                 "IDMA_FL_SEND_PCIEHDR",
6463                 "IDMA_FL_PUSH_CPL_FIFO",
6464                 "IDMA_FL_SEND_CPL",
6465                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6466                 "IDMA_FL_SEND_PAYLOAD",
6467                 "IDMA_FL_REQ_NEXT_DATA_FL",
6468                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6469                 "IDMA_FL_SEND_PADDING",
6470                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6471         };
6472         static const u32 sge_regs[] = {
6473                 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6474                 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6475                 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6476         };
6477         const char **sge_idma_decode;
6478         int sge_idma_decode_nstates;
6479         int i;
6480         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6481
6482         /* Select the right set of decode strings to dump depending on the
6483          * adapter chip type.
6484          */
6485         switch (chip_version) {
6486         case CHELSIO_T4:
6487                 sge_idma_decode = (const char **)t4_decode;
6488                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6489                 break;
6490
6491         case CHELSIO_T5:
6492                 sge_idma_decode = (const char **)t5_decode;
6493                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6494                 break;
6495
6496         case CHELSIO_T6:
6497                 sge_idma_decode = (const char **)t6_decode;
6498                 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6499                 break;
6500
6501         default:
6502                 dev_err(adapter->pdev_dev,
6503                         "Unsupported chip version %d\n", chip_version);
6504                 return;
6505         }
6506
6507         if (is_t4(adapter->params.chip)) {
6508                 sge_idma_decode = (const char **)t4_decode;
6509                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6510         } else {
6511                 sge_idma_decode = (const char **)t5_decode;
6512                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6513         }
6514
6515         if (state < sge_idma_decode_nstates)
6516                 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6517         else
6518                 CH_WARN(adapter, "idma state %d unknown\n", state);
6519
6520         for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6521                 CH_WARN(adapter, "SGE register %#x value %#x\n",
6522                         sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6523 }
6524
6525 /**
6526  *      t4_sge_ctxt_flush - flush the SGE context cache
6527  *      @adap: the adapter
6528  *      @mbox: mailbox to use for the FW command
6529  *
6530  *      Issues a FW command through the given mailbox to flush the
6531  *      SGE context cache.
6532  */
6533 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
6534 {
6535         int ret;
6536         u32 ldst_addrspace;
6537         struct fw_ldst_cmd c;
6538
6539         memset(&c, 0, sizeof(c));
6540         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
6541         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6542                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6543                                         ldst_addrspace);
6544         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6545         c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6546
6547         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6548         return ret;
6549 }
6550
6551 /**
6552  *      t4_fw_hello - establish communication with FW
6553  *      @adap: the adapter
6554  *      @mbox: mailbox to use for the FW command
6555  *      @evt_mbox: mailbox to receive async FW events
6556  *      @master: specifies the caller's willingness to be the device master
6557  *      @state: returns the current device state (if non-NULL)
6558  *
6559  *      Issues a command to establish communication with FW.  Returns either
6560  *      an error (negative integer) or the mailbox of the Master PF.
6561  */
6562 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6563                 enum dev_master master, enum dev_state *state)
6564 {
6565         int ret;
6566         struct fw_hello_cmd c;
6567         u32 v;
6568         unsigned int master_mbox;
6569         int retries = FW_CMD_HELLO_RETRIES;
6570
6571 retry:
6572         memset(&c, 0, sizeof(c));
6573         INIT_CMD(c, HELLO, WRITE);
6574         c.err_to_clearinit = cpu_to_be32(
6575                 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6576                 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6577                 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6578                                         mbox : FW_HELLO_CMD_MBMASTER_M) |
6579                 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6580                 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6581                 FW_HELLO_CMD_CLEARINIT_F);
6582
6583         /*
6584          * Issue the HELLO command to the firmware.  If it's not successful
6585          * but indicates that we got a "busy" or "timeout" condition, retry
6586          * the HELLO until we exhaust our retry limit.  If we do exceed our
6587          * retry limit, check to see if the firmware left us any error
6588          * information and report that if so.
6589          */
6590         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6591         if (ret < 0) {
6592                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6593                         goto retry;
6594                 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6595                         t4_report_fw_error(adap);
6596                 return ret;
6597         }
6598
6599         v = be32_to_cpu(c.err_to_clearinit);
6600         master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6601         if (state) {
6602                 if (v & FW_HELLO_CMD_ERR_F)
6603                         *state = DEV_STATE_ERR;
6604                 else if (v & FW_HELLO_CMD_INIT_F)
6605                         *state = DEV_STATE_INIT;
6606                 else
6607                         *state = DEV_STATE_UNINIT;
6608         }
6609
6610         /*
6611          * If we're not the Master PF then we need to wait around for the
6612          * Master PF Driver to finish setting up the adapter.
6613          *
6614          * Note that we also do this wait if we're a non-Master-capable PF and
6615          * there is no current Master PF; a Master PF may show up momentarily
6616          * and we wouldn't want to fail pointlessly.  (This can happen when an
6617          * OS loads lots of different drivers rapidly at the same time).  In
6618          * this case, the Master PF returned by the firmware will be
6619          * PCIE_FW_MASTER_M so the test below will work ...
6620          */
6621         if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6622             master_mbox != mbox) {
6623                 int waiting = FW_CMD_HELLO_TIMEOUT;
6624
6625                 /*
6626                  * Wait for the firmware to either indicate an error or
6627                  * initialized state.  If we see either of these we bail out
6628                  * and report the issue to the caller.  If we exhaust the
6629                  * "hello timeout" and we haven't exhausted our retries, try
6630                  * again.  Otherwise bail with a timeout error.
6631                  */
6632                 for (;;) {
6633                         u32 pcie_fw;
6634
6635                         msleep(50);
6636                         waiting -= 50;
6637
6638                         /*
6639                          * If neither Error nor Initialialized are indicated
6640                          * by the firmware keep waiting till we exaust our
6641                          * timeout ... and then retry if we haven't exhausted
6642                          * our retries ...
6643                          */
6644                         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6645                         if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6646                                 if (waiting <= 0) {
6647                                         if (retries-- > 0)
6648                                                 goto retry;
6649
6650                                         return -ETIMEDOUT;
6651                                 }
6652                                 continue;
6653                         }
6654
6655                         /*
6656                          * We either have an Error or Initialized condition
6657                          * report errors preferentially.
6658                          */
6659                         if (state) {
6660                                 if (pcie_fw & PCIE_FW_ERR_F)
6661                                         *state = DEV_STATE_ERR;
6662                                 else if (pcie_fw & PCIE_FW_INIT_F)
6663                                         *state = DEV_STATE_INIT;
6664                         }
6665
6666                         /*
6667                          * If we arrived before a Master PF was selected and
6668                          * there's not a valid Master PF, grab its identity
6669                          * for our caller.
6670                          */
6671                         if (master_mbox == PCIE_FW_MASTER_M &&
6672                             (pcie_fw & PCIE_FW_MASTER_VLD_F))
6673                                 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6674                         break;
6675                 }
6676         }
6677
6678         return master_mbox;
6679 }
6680
6681 /**
6682  *      t4_fw_bye - end communication with FW
6683  *      @adap: the adapter
6684  *      @mbox: mailbox to use for the FW command
6685  *
6686  *      Issues a command to terminate communication with FW.
6687  */
6688 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6689 {
6690         struct fw_bye_cmd c;
6691
6692         memset(&c, 0, sizeof(c));
6693         INIT_CMD(c, BYE, WRITE);
6694         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6695 }
6696
6697 /**
6698  *      t4_init_cmd - ask FW to initialize the device
6699  *      @adap: the adapter
6700  *      @mbox: mailbox to use for the FW command
6701  *
6702  *      Issues a command to FW to partially initialize the device.  This
6703  *      performs initialization that generally doesn't depend on user input.
6704  */
6705 int t4_early_init(struct adapter *adap, unsigned int mbox)
6706 {
6707         struct fw_initialize_cmd c;
6708
6709         memset(&c, 0, sizeof(c));
6710         INIT_CMD(c, INITIALIZE, WRITE);
6711         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6712 }
6713
6714 /**
6715  *      t4_fw_reset - issue a reset to FW
6716  *      @adap: the adapter
6717  *      @mbox: mailbox to use for the FW command
6718  *      @reset: specifies the type of reset to perform
6719  *
6720  *      Issues a reset command of the specified type to FW.
6721  */
6722 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6723 {
6724         struct fw_reset_cmd c;
6725
6726         memset(&c, 0, sizeof(c));
6727         INIT_CMD(c, RESET, WRITE);
6728         c.val = cpu_to_be32(reset);
6729         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6730 }
6731
6732 /**
6733  *      t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6734  *      @adap: the adapter
6735  *      @mbox: mailbox to use for the FW RESET command (if desired)
6736  *      @force: force uP into RESET even if FW RESET command fails
6737  *
6738  *      Issues a RESET command to firmware (if desired) with a HALT indication
6739  *      and then puts the microprocessor into RESET state.  The RESET command
6740  *      will only be issued if a legitimate mailbox is provided (mbox <=
6741  *      PCIE_FW_MASTER_M).
6742  *
6743  *      This is generally used in order for the host to safely manipulate the
6744  *      adapter without fear of conflicting with whatever the firmware might
6745  *      be doing.  The only way out of this state is to RESTART the firmware
6746  *      ...
6747  */
6748 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6749 {
6750         int ret = 0;
6751
6752         /*
6753          * If a legitimate mailbox is provided, issue a RESET command
6754          * with a HALT indication.
6755          */
6756         if (mbox <= PCIE_FW_MASTER_M) {
6757                 struct fw_reset_cmd c;
6758
6759                 memset(&c, 0, sizeof(c));
6760                 INIT_CMD(c, RESET, WRITE);
6761                 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6762                 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6763                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6764         }
6765
6766         /*
6767          * Normally we won't complete the operation if the firmware RESET
6768          * command fails but if our caller insists we'll go ahead and put the
6769          * uP into RESET.  This can be useful if the firmware is hung or even
6770          * missing ...  We'll have to take the risk of putting the uP into
6771          * RESET without the cooperation of firmware in that case.
6772          *
6773          * We also force the firmware's HALT flag to be on in case we bypassed
6774          * the firmware RESET command above or we're dealing with old firmware
6775          * which doesn't have the HALT capability.  This will serve as a flag
6776          * for the incoming firmware to know that it's coming out of a HALT
6777          * rather than a RESET ... if it's new enough to understand that ...
6778          */
6779         if (ret == 0 || force) {
6780                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6781                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6782                                  PCIE_FW_HALT_F);
6783         }
6784
6785         /*
6786          * And we always return the result of the firmware RESET command
6787          * even when we force the uP into RESET ...
6788          */
6789         return ret;
6790 }
6791
6792 /**
6793  *      t4_fw_restart - restart the firmware by taking the uP out of RESET
6794  *      @adap: the adapter
6795  *      @reset: if we want to do a RESET to restart things
6796  *
6797  *      Restart firmware previously halted by t4_fw_halt().  On successful
6798  *      return the previous PF Master remains as the new PF Master and there
6799  *      is no need to issue a new HELLO command, etc.
6800  *
6801  *      We do this in two ways:
6802  *
6803  *       1. If we're dealing with newer firmware we'll simply want to take
6804  *          the chip's microprocessor out of RESET.  This will cause the
6805  *          firmware to start up from its start vector.  And then we'll loop
6806  *          until the firmware indicates it's started again (PCIE_FW.HALT
6807  *          reset to 0) or we timeout.
6808  *
6809  *       2. If we're dealing with older firmware then we'll need to RESET
6810  *          the chip since older firmware won't recognize the PCIE_FW.HALT
6811  *          flag and automatically RESET itself on startup.
6812  */
6813 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6814 {
6815         if (reset) {
6816                 /*
6817                  * Since we're directing the RESET instead of the firmware
6818                  * doing it automatically, we need to clear the PCIE_FW.HALT
6819                  * bit.
6820                  */
6821                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6822
6823                 /*
6824                  * If we've been given a valid mailbox, first try to get the
6825                  * firmware to do the RESET.  If that works, great and we can
6826                  * return success.  Otherwise, if we haven't been given a
6827                  * valid mailbox or the RESET command failed, fall back to
6828                  * hitting the chip with a hammer.
6829                  */
6830                 if (mbox <= PCIE_FW_MASTER_M) {
6831                         t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6832                         msleep(100);
6833                         if (t4_fw_reset(adap, mbox,
6834                                         PIORST_F | PIORSTMODE_F) == 0)
6835                                 return 0;
6836                 }
6837
6838                 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6839                 msleep(2000);
6840         } else {
6841                 int ms;
6842
6843                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6844                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6845                         if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6846                                 return 0;
6847                         msleep(100);
6848                         ms += 100;
6849                 }
6850                 return -ETIMEDOUT;
6851         }
6852         return 0;
6853 }
6854
6855 /**
6856  *      t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6857  *      @adap: the adapter
6858  *      @mbox: mailbox to use for the FW RESET command (if desired)
6859  *      @fw_data: the firmware image to write
6860  *      @size: image size
6861  *      @force: force upgrade even if firmware doesn't cooperate
6862  *
6863  *      Perform all of the steps necessary for upgrading an adapter's
6864  *      firmware image.  Normally this requires the cooperation of the
6865  *      existing firmware in order to halt all existing activities
6866  *      but if an invalid mailbox token is passed in we skip that step
6867  *      (though we'll still put the adapter microprocessor into RESET in
6868  *      that case).
6869  *
6870  *      On successful return the new firmware will have been loaded and
6871  *      the adapter will have been fully RESET losing all previous setup
6872  *      state.  On unsuccessful return the adapter may be completely hosed ...
6873  *      positive errno indicates that the adapter is ~probably~ intact, a
6874  *      negative errno indicates that things are looking bad ...
6875  */
6876 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6877                   const u8 *fw_data, unsigned int size, int force)
6878 {
6879         const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6880         int reset, ret;
6881
6882         if (!t4_fw_matches_chip(adap, fw_hdr))
6883                 return -EINVAL;
6884
6885         /* Disable FW_OK flag so that mbox commands with FW_OK flag set
6886          * wont be sent when we are flashing FW.
6887          */
6888         adap->flags &= ~FW_OK;
6889
6890         ret = t4_fw_halt(adap, mbox, force);
6891         if (ret < 0 && !force)
6892                 goto out;
6893
6894         ret = t4_load_fw(adap, fw_data, size);
6895         if (ret < 0)
6896                 goto out;
6897
6898         /*
6899          * If there was a Firmware Configuration File stored in FLASH,
6900          * there's a good chance that it won't be compatible with the new
6901          * Firmware.  In order to prevent difficult to diagnose adapter
6902          * initialization issues, we clear out the Firmware Configuration File
6903          * portion of the FLASH .  The user will need to re-FLASH a new
6904          * Firmware Configuration File which is compatible with the new
6905          * Firmware if that's desired.
6906          */
6907         (void)t4_load_cfg(adap, NULL, 0);
6908
6909         /*
6910          * Older versions of the firmware don't understand the new
6911          * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6912          * restart.  So for newly loaded older firmware we'll have to do the
6913          * RESET for it so it starts up on a clean slate.  We can tell if
6914          * the newly loaded firmware will handle this right by checking
6915          * its header flags to see if it advertises the capability.
6916          */
6917         reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6918         ret = t4_fw_restart(adap, mbox, reset);
6919
6920         /* Grab potentially new Firmware Device Log parameters so we can see
6921          * how healthy the new Firmware is.  It's okay to contact the new
6922          * Firmware for these parameters even though, as far as it's
6923          * concerned, we've never said "HELLO" to it ...
6924          */
6925         (void)t4_init_devlog_params(adap);
6926 out:
6927         adap->flags |= FW_OK;
6928         return ret;
6929 }
6930
6931 /**
6932  *      t4_fl_pkt_align - return the fl packet alignment
6933  *      @adap: the adapter
6934  *
6935  *      T4 has a single field to specify the packing and padding boundary.
6936  *      T5 onwards has separate fields for this and hence the alignment for
6937  *      next packet offset is maximum of these two.
6938  *
6939  */
6940 int t4_fl_pkt_align(struct adapter *adap)
6941 {
6942         u32 sge_control, sge_control2;
6943         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6944
6945         sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6946
6947         /* T4 uses a single control field to specify both the PCIe Padding and
6948          * Packing Boundary.  T5 introduced the ability to specify these
6949          * separately.  The actual Ingress Packet Data alignment boundary
6950          * within Packed Buffer Mode is the maximum of these two
6951          * specifications.  (Note that it makes no real practical sense to
6952          * have the Pading Boudary be larger than the Packing Boundary but you
6953          * could set the chip up that way and, in fact, legacy T4 code would
6954          * end doing this because it would initialize the Padding Boundary and
6955          * leave the Packing Boundary initialized to 0 (16 bytes).)
6956          * Padding Boundary values in T6 starts from 8B,
6957          * where as it is 32B for T4 and T5.
6958          */
6959         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6960                 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6961         else
6962                 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6963
6964         ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6965
6966         fl_align = ingpadboundary;
6967         if (!is_t4(adap->params.chip)) {
6968                 /* T5 has a weird interpretation of one of the PCIe Packing
6969                  * Boundary values.  No idea why ...
6970                  */
6971                 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6972                 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6973                 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6974                         ingpackboundary = 16;
6975                 else
6976                         ingpackboundary = 1 << (ingpackboundary +
6977                                                 INGPACKBOUNDARY_SHIFT_X);
6978
6979                 fl_align = max(ingpadboundary, ingpackboundary);
6980         }
6981         return fl_align;
6982 }
6983
6984 /**
6985  *      t4_fixup_host_params - fix up host-dependent parameters
6986  *      @adap: the adapter
6987  *      @page_size: the host's Base Page Size
6988  *      @cache_line_size: the host's Cache Line Size
6989  *
6990  *      Various registers in T4 contain values which are dependent on the
6991  *      host's Base Page and Cache Line Sizes.  This function will fix all of
6992  *      those registers with the appropriate values as passed in ...
6993  */
6994 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6995                          unsigned int cache_line_size)
6996 {
6997         unsigned int page_shift = fls(page_size) - 1;
6998         unsigned int sge_hps = page_shift - 10;
6999         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
7000         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
7001         unsigned int fl_align_log = fls(fl_align) - 1;
7002
7003         t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
7004                      HOSTPAGESIZEPF0_V(sge_hps) |
7005                      HOSTPAGESIZEPF1_V(sge_hps) |
7006                      HOSTPAGESIZEPF2_V(sge_hps) |
7007                      HOSTPAGESIZEPF3_V(sge_hps) |
7008                      HOSTPAGESIZEPF4_V(sge_hps) |
7009                      HOSTPAGESIZEPF5_V(sge_hps) |
7010                      HOSTPAGESIZEPF6_V(sge_hps) |
7011                      HOSTPAGESIZEPF7_V(sge_hps));
7012
7013         if (is_t4(adap->params.chip)) {
7014                 t4_set_reg_field(adap, SGE_CONTROL_A,
7015                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7016                                  EGRSTATUSPAGESIZE_F,
7017                                  INGPADBOUNDARY_V(fl_align_log -
7018                                                   INGPADBOUNDARY_SHIFT_X) |
7019                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
7020         } else {
7021                 unsigned int pack_align;
7022                 unsigned int ingpad, ingpack;
7023                 unsigned int pcie_cap;
7024
7025                 /* T5 introduced the separation of the Free List Padding and
7026                  * Packing Boundaries.  Thus, we can select a smaller Padding
7027                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
7028                  * Bandwidth, and use a Packing Boundary which is large enough
7029                  * to avoid false sharing between CPUs, etc.
7030                  *
7031                  * For the PCI Link, the smaller the Padding Boundary the
7032                  * better.  For the Memory Controller, a smaller Padding
7033                  * Boundary is better until we cross under the Memory Line
7034                  * Size (the minimum unit of transfer to/from Memory).  If we
7035                  * have a Padding Boundary which is smaller than the Memory
7036                  * Line Size, that'll involve a Read-Modify-Write cycle on the
7037                  * Memory Controller which is never good.
7038                  */
7039
7040                 /* We want the Packing Boundary to be based on the Cache Line
7041                  * Size in order to help avoid False Sharing performance
7042                  * issues between CPUs, etc.  We also want the Packing
7043                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
7044                  * get best performance when the Packing Boundary is a
7045                  * multiple of the Maximum Payload Size.
7046                  */
7047                 pack_align = fl_align;
7048                 pcie_cap = pci_find_capability(adap->pdev, PCI_CAP_ID_EXP);
7049                 if (pcie_cap) {
7050                         unsigned int mps, mps_log;
7051                         u16 devctl;
7052
7053                         /* The PCIe Device Control Maximum Payload Size field
7054                          * [bits 7:5] encodes sizes as powers of 2 starting at
7055                          * 128 bytes.
7056                          */
7057                         pci_read_config_word(adap->pdev,
7058                                              pcie_cap + PCI_EXP_DEVCTL,
7059                                              &devctl);
7060                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
7061                         mps = 1 << mps_log;
7062                         if (mps > pack_align)
7063                                 pack_align = mps;
7064                 }
7065
7066                 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7067                  * value for the Packing Boundary.  This corresponds to 16
7068                  * bytes instead of the expected 32 bytes.  So if we want 32
7069                  * bytes, the best we can really do is 64 bytes ...
7070                  */
7071                 if (pack_align <= 16) {
7072                         ingpack = INGPACKBOUNDARY_16B_X;
7073                         fl_align = 16;
7074                 } else if (pack_align == 32) {
7075                         ingpack = INGPACKBOUNDARY_64B_X;
7076                         fl_align = 64;
7077                 } else {
7078                         unsigned int pack_align_log = fls(pack_align) - 1;
7079
7080                         ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
7081                         fl_align = pack_align;
7082                 }
7083
7084                 /* Use the smallest Ingress Padding which isn't smaller than
7085                  * the Memory Controller Read/Write Size.  We'll take that as
7086                  * being 8 bytes since we don't know of any system with a
7087                  * wider Memory Controller Bus Width.
7088                  */
7089                 if (is_t5(adap->params.chip))
7090                         ingpad = INGPADBOUNDARY_32B_X;
7091                 else
7092                         ingpad = T6_INGPADBOUNDARY_8B_X;
7093
7094                 t4_set_reg_field(adap, SGE_CONTROL_A,
7095                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7096                                  EGRSTATUSPAGESIZE_F,
7097                                  INGPADBOUNDARY_V(ingpad) |
7098                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
7099                 t4_set_reg_field(adap, SGE_CONTROL2_A,
7100                                  INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
7101                                  INGPACKBOUNDARY_V(ingpack));
7102         }
7103         /*
7104          * Adjust various SGE Free List Host Buffer Sizes.
7105          *
7106          * This is something of a crock since we're using fixed indices into
7107          * the array which are also known by the sge.c code and the T4
7108          * Firmware Configuration File.  We need to come up with a much better
7109          * approach to managing this array.  For now, the first four entries
7110          * are:
7111          *
7112          *   0: Host Page Size
7113          *   1: 64KB
7114          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7115          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7116          *
7117          * For the single-MTU buffers in unpacked mode we need to include
7118          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7119          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7120          * Padding boundary.  All of these are accommodated in the Factory
7121          * Default Firmware Configuration File but we need to adjust it for
7122          * this host's cache line size.
7123          */
7124         t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
7125         t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
7126                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
7127                      & ~(fl_align-1));
7128         t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
7129                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
7130                      & ~(fl_align-1));
7131
7132         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
7133
7134         return 0;
7135 }
7136
7137 /**
7138  *      t4_fw_initialize - ask FW to initialize the device
7139  *      @adap: the adapter
7140  *      @mbox: mailbox to use for the FW command
7141  *
7142  *      Issues a command to FW to partially initialize the device.  This
7143  *      performs initialization that generally doesn't depend on user input.
7144  */
7145 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7146 {
7147         struct fw_initialize_cmd c;
7148
7149         memset(&c, 0, sizeof(c));
7150         INIT_CMD(c, INITIALIZE, WRITE);
7151         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7152 }
7153
7154 /**
7155  *      t4_query_params_rw - query FW or device parameters
7156  *      @adap: the adapter
7157  *      @mbox: mailbox to use for the FW command
7158  *      @pf: the PF
7159  *      @vf: the VF
7160  *      @nparams: the number of parameters
7161  *      @params: the parameter names
7162  *      @val: the parameter values
7163  *      @rw: Write and read flag
7164  *      @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7165  *
7166  *      Reads the value of FW or device parameters.  Up to 7 parameters can be
7167  *      queried at once.
7168  */
7169 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7170                        unsigned int vf, unsigned int nparams, const u32 *params,
7171                        u32 *val, int rw, bool sleep_ok)
7172 {
7173         int i, ret;
7174         struct fw_params_cmd c;
7175         __be32 *p = &c.param[0].mnem;
7176
7177         if (nparams > 7)
7178                 return -EINVAL;
7179
7180         memset(&c, 0, sizeof(c));
7181         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7182                                   FW_CMD_REQUEST_F | FW_CMD_READ_F |
7183                                   FW_PARAMS_CMD_PFN_V(pf) |
7184                                   FW_PARAMS_CMD_VFN_V(vf));
7185         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7186
7187         for (i = 0; i < nparams; i++) {
7188                 *p++ = cpu_to_be32(*params++);
7189                 if (rw)
7190                         *p = cpu_to_be32(*(val + i));
7191                 p++;
7192         }
7193
7194         ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7195         if (ret == 0)
7196                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7197                         *val++ = be32_to_cpu(*p);
7198         return ret;
7199 }
7200
7201 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7202                     unsigned int vf, unsigned int nparams, const u32 *params,
7203                     u32 *val)
7204 {
7205         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7206                                   true);
7207 }
7208
7209 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7210                        unsigned int vf, unsigned int nparams, const u32 *params,
7211                        u32 *val)
7212 {
7213         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7214                                   false);
7215 }
7216
7217 /**
7218  *      t4_set_params_timeout - sets FW or device parameters
7219  *      @adap: the adapter
7220  *      @mbox: mailbox to use for the FW command
7221  *      @pf: the PF
7222  *      @vf: the VF
7223  *      @nparams: the number of parameters
7224  *      @params: the parameter names
7225  *      @val: the parameter values
7226  *      @timeout: the timeout time
7227  *
7228  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7229  *      specified at once.
7230  */
7231 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7232                           unsigned int pf, unsigned int vf,
7233                           unsigned int nparams, const u32 *params,
7234                           const u32 *val, int timeout)
7235 {
7236         struct fw_params_cmd c;
7237         __be32 *p = &c.param[0].mnem;
7238
7239         if (nparams > 7)
7240                 return -EINVAL;
7241
7242         memset(&c, 0, sizeof(c));
7243         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7244                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7245                                   FW_PARAMS_CMD_PFN_V(pf) |
7246                                   FW_PARAMS_CMD_VFN_V(vf));
7247         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7248
7249         while (nparams--) {
7250                 *p++ = cpu_to_be32(*params++);
7251                 *p++ = cpu_to_be32(*val++);
7252         }
7253
7254         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7255 }
7256
7257 /**
7258  *      t4_set_params - sets FW or device parameters
7259  *      @adap: the adapter
7260  *      @mbox: mailbox to use for the FW command
7261  *      @pf: the PF
7262  *      @vf: the VF
7263  *      @nparams: the number of parameters
7264  *      @params: the parameter names
7265  *      @val: the parameter values
7266  *
7267  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7268  *      specified at once.
7269  */
7270 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7271                   unsigned int vf, unsigned int nparams, const u32 *params,
7272                   const u32 *val)
7273 {
7274         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7275                                      FW_CMD_MAX_TIMEOUT);
7276 }
7277
7278 /**
7279  *      t4_cfg_pfvf - configure PF/VF resource limits
7280  *      @adap: the adapter
7281  *      @mbox: mailbox to use for the FW command
7282  *      @pf: the PF being configured
7283  *      @vf: the VF being configured
7284  *      @txq: the max number of egress queues
7285  *      @txq_eth_ctrl: the max number of egress Ethernet or control queues
7286  *      @rxqi: the max number of interrupt-capable ingress queues
7287  *      @rxq: the max number of interruptless ingress queues
7288  *      @tc: the PCI traffic class
7289  *      @vi: the max number of virtual interfaces
7290  *      @cmask: the channel access rights mask for the PF/VF
7291  *      @pmask: the port access rights mask for the PF/VF
7292  *      @nexact: the maximum number of exact MPS filters
7293  *      @rcaps: read capabilities
7294  *      @wxcaps: write/execute capabilities
7295  *
7296  *      Configures resource limits and capabilities for a physical or virtual
7297  *      function.
7298  */
7299 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7300                 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7301                 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7302                 unsigned int vi, unsigned int cmask, unsigned int pmask,
7303                 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7304 {
7305         struct fw_pfvf_cmd c;
7306
7307         memset(&c, 0, sizeof(c));
7308         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7309                                   FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7310                                   FW_PFVF_CMD_VFN_V(vf));
7311         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7312         c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7313                                      FW_PFVF_CMD_NIQ_V(rxq));
7314         c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7315                                     FW_PFVF_CMD_PMASK_V(pmask) |
7316                                     FW_PFVF_CMD_NEQ_V(txq));
7317         c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7318                                       FW_PFVF_CMD_NVI_V(vi) |
7319                                       FW_PFVF_CMD_NEXACTF_V(nexact));
7320         c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7321                                         FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7322                                         FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7323         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7324 }
7325
7326 /**
7327  *      t4_alloc_vi - allocate a virtual interface
7328  *      @adap: the adapter
7329  *      @mbox: mailbox to use for the FW command
7330  *      @port: physical port associated with the VI
7331  *      @pf: the PF owning the VI
7332  *      @vf: the VF owning the VI
7333  *      @nmac: number of MAC addresses needed (1 to 5)
7334  *      @mac: the MAC addresses of the VI
7335  *      @rss_size: size of RSS table slice associated with this VI
7336  *
7337  *      Allocates a virtual interface for the given physical port.  If @mac is
7338  *      not %NULL it contains the MAC addresses of the VI as assigned by FW.
7339  *      @mac should be large enough to hold @nmac Ethernet addresses, they are
7340  *      stored consecutively so the space needed is @nmac * 6 bytes.
7341  *      Returns a negative error number or the non-negative VI id.
7342  */
7343 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7344                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7345                 unsigned int *rss_size)
7346 {
7347         int ret;
7348         struct fw_vi_cmd c;
7349
7350         memset(&c, 0, sizeof(c));
7351         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7352                                   FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7353                                   FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7354         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7355         c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7356         c.nmac = nmac - 1;
7357
7358         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7359         if (ret)
7360                 return ret;
7361
7362         if (mac) {
7363                 memcpy(mac, c.mac, sizeof(c.mac));
7364                 switch (nmac) {
7365                 case 5:
7366                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7367                 case 4:
7368                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7369                 case 3:
7370                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7371                 case 2:
7372                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
7373                 }
7374         }
7375         if (rss_size)
7376                 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7377         return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7378 }
7379
7380 /**
7381  *      t4_free_vi - free a virtual interface
7382  *      @adap: the adapter
7383  *      @mbox: mailbox to use for the FW command
7384  *      @pf: the PF owning the VI
7385  *      @vf: the VF owning the VI
7386  *      @viid: virtual interface identifiler
7387  *
7388  *      Free a previously allocated virtual interface.
7389  */
7390 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7391                unsigned int vf, unsigned int viid)
7392 {
7393         struct fw_vi_cmd c;
7394
7395         memset(&c, 0, sizeof(c));
7396         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7397                                   FW_CMD_REQUEST_F |
7398                                   FW_CMD_EXEC_F |
7399                                   FW_VI_CMD_PFN_V(pf) |
7400                                   FW_VI_CMD_VFN_V(vf));
7401         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7402         c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7403
7404         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7405 }
7406
7407 /**
7408  *      t4_set_rxmode - set Rx properties of a virtual interface
7409  *      @adap: the adapter
7410  *      @mbox: mailbox to use for the FW command
7411  *      @viid: the VI id
7412  *      @mtu: the new MTU or -1
7413  *      @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7414  *      @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7415  *      @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7416  *      @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7417  *      @sleep_ok: if true we may sleep while awaiting command completion
7418  *
7419  *      Sets Rx properties of a virtual interface.
7420  */
7421 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7422                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
7423                   bool sleep_ok)
7424 {
7425         struct fw_vi_rxmode_cmd c;
7426
7427         /* convert to FW values */
7428         if (mtu < 0)
7429                 mtu = FW_RXMODE_MTU_NO_CHG;
7430         if (promisc < 0)
7431                 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7432         if (all_multi < 0)
7433                 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7434         if (bcast < 0)
7435                 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7436         if (vlanex < 0)
7437                 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7438
7439         memset(&c, 0, sizeof(c));
7440         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7441                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7442                                    FW_VI_RXMODE_CMD_VIID_V(viid));
7443         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7444         c.mtu_to_vlanexen =
7445                 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7446                             FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7447                             FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7448                             FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7449                             FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7450         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7451 }
7452
7453 /**
7454  *      t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7455  *      @adap: the adapter
7456  *      @mbox: mailbox to use for the FW command
7457  *      @viid: the VI id
7458  *      @free: if true any existing filters for this VI id are first removed
7459  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7460  *      @addr: the MAC address(es)
7461  *      @idx: where to store the index of each allocated filter
7462  *      @hash: pointer to hash address filter bitmap
7463  *      @sleep_ok: call is allowed to sleep
7464  *
7465  *      Allocates an exact-match filter for each of the supplied addresses and
7466  *      sets it to the corresponding address.  If @idx is not %NULL it should
7467  *      have at least @naddr entries, each of which will be set to the index of
7468  *      the filter allocated for the corresponding MAC address.  If a filter
7469  *      could not be allocated for an address its index is set to 0xffff.
7470  *      If @hash is not %NULL addresses that fail to allocate an exact filter
7471  *      are hashed and update the hash filter bitmap pointed at by @hash.
7472  *
7473  *      Returns a negative error number or the number of filters allocated.
7474  */
7475 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7476                       unsigned int viid, bool free, unsigned int naddr,
7477                       const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7478 {
7479         int offset, ret = 0;
7480         struct fw_vi_mac_cmd c;
7481         unsigned int nfilters = 0;
7482         unsigned int max_naddr = adap->params.arch.mps_tcam_size;
7483         unsigned int rem = naddr;
7484
7485         if (naddr > max_naddr)
7486                 return -EINVAL;
7487
7488         for (offset = 0; offset < naddr ; /**/) {
7489                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
7490                                          rem : ARRAY_SIZE(c.u.exact));
7491                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7492                                                      u.exact[fw_naddr]), 16);
7493                 struct fw_vi_mac_exact *p;
7494                 int i;
7495
7496                 memset(&c, 0, sizeof(c));
7497                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7498                                            FW_CMD_REQUEST_F |
7499                                            FW_CMD_WRITE_F |
7500                                            FW_CMD_EXEC_V(free) |
7501                                            FW_VI_MAC_CMD_VIID_V(viid));
7502                 c.freemacs_to_len16 =
7503                         cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
7504                                     FW_CMD_LEN16_V(len16));
7505
7506                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7507                         p->valid_to_idx =
7508                                 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7509                                             FW_VI_MAC_CMD_IDX_V(
7510                                                     FW_VI_MAC_ADD_MAC));
7511                         memcpy(p->macaddr, addr[offset + i],
7512                                sizeof(p->macaddr));
7513                 }
7514
7515                 /* It's okay if we run out of space in our MAC address arena.
7516                  * Some of the addresses we submit may get stored so we need
7517                  * to run through the reply to see what the results were ...
7518                  */
7519                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7520                 if (ret && ret != -FW_ENOMEM)
7521                         break;
7522
7523                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7524                         u16 index = FW_VI_MAC_CMD_IDX_G(
7525                                         be16_to_cpu(p->valid_to_idx));
7526
7527                         if (idx)
7528                                 idx[offset + i] = (index >= max_naddr ?
7529                                                    0xffff : index);
7530                         if (index < max_naddr)
7531                                 nfilters++;
7532                         else if (hash)
7533                                 *hash |= (1ULL <<
7534                                           hash_mac_addr(addr[offset + i]));
7535                 }
7536
7537                 free = false;
7538                 offset += fw_naddr;
7539                 rem -= fw_naddr;
7540         }
7541
7542         if (ret == 0 || ret == -FW_ENOMEM)
7543                 ret = nfilters;
7544         return ret;
7545 }
7546
7547 /**
7548  *      t4_free_mac_filt - frees exact-match filters of given MAC addresses
7549  *      @adap: the adapter
7550  *      @mbox: mailbox to use for the FW command
7551  *      @viid: the VI id
7552  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7553  *      @addr: the MAC address(es)
7554  *      @sleep_ok: call is allowed to sleep
7555  *
7556  *      Frees the exact-match filter for each of the supplied addresses
7557  *
7558  *      Returns a negative error number or the number of filters freed.
7559  */
7560 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
7561                      unsigned int viid, unsigned int naddr,
7562                      const u8 **addr, bool sleep_ok)
7563 {
7564         int offset, ret = 0;
7565         struct fw_vi_mac_cmd c;
7566         unsigned int nfilters = 0;
7567         unsigned int max_naddr = is_t4(adap->params.chip) ?
7568                                        NUM_MPS_CLS_SRAM_L_INSTANCES :
7569                                        NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7570         unsigned int rem = naddr;
7571
7572         if (naddr > max_naddr)
7573                 return -EINVAL;
7574
7575         for (offset = 0; offset < (int)naddr ; /**/) {
7576                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
7577                                          ? rem
7578                                          : ARRAY_SIZE(c.u.exact));
7579                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7580                                                      u.exact[fw_naddr]), 16);
7581                 struct fw_vi_mac_exact *p;
7582                 int i;
7583
7584                 memset(&c, 0, sizeof(c));
7585                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7586                                      FW_CMD_REQUEST_F |
7587                                      FW_CMD_WRITE_F |
7588                                      FW_CMD_EXEC_V(0) |
7589                                      FW_VI_MAC_CMD_VIID_V(viid));
7590                 c.freemacs_to_len16 =
7591                                 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7592                                             FW_CMD_LEN16_V(len16));
7593
7594                 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
7595                         p->valid_to_idx = cpu_to_be16(
7596                                 FW_VI_MAC_CMD_VALID_F |
7597                                 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
7598                         memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
7599                 }
7600
7601                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7602                 if (ret)
7603                         break;
7604
7605                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7606                         u16 index = FW_VI_MAC_CMD_IDX_G(
7607                                                 be16_to_cpu(p->valid_to_idx));
7608
7609                         if (index < max_naddr)
7610                                 nfilters++;
7611                 }
7612
7613                 offset += fw_naddr;
7614                 rem -= fw_naddr;
7615         }
7616
7617         if (ret == 0)
7618                 ret = nfilters;
7619         return ret;
7620 }
7621
7622 /**
7623  *      t4_change_mac - modifies the exact-match filter for a MAC address
7624  *      @adap: the adapter
7625  *      @mbox: mailbox to use for the FW command
7626  *      @viid: the VI id
7627  *      @idx: index of existing filter for old value of MAC address, or -1
7628  *      @addr: the new MAC address value
7629  *      @persist: whether a new MAC allocation should be persistent
7630  *      @add_smt: if true also add the address to the HW SMT
7631  *
7632  *      Modifies an exact-match filter and sets it to the new MAC address.
7633  *      Note that in general it is not possible to modify the value of a given
7634  *      filter so the generic way to modify an address filter is to free the one
7635  *      being used by the old address value and allocate a new filter for the
7636  *      new address value.  @idx can be -1 if the address is a new addition.
7637  *
7638  *      Returns a negative error number or the index of the filter with the new
7639  *      MAC value.
7640  */
7641 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7642                   int idx, const u8 *addr, bool persist, bool add_smt)
7643 {
7644         int ret, mode;
7645         struct fw_vi_mac_cmd c;
7646         struct fw_vi_mac_exact *p = c.u.exact;
7647         unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
7648
7649         if (idx < 0)                             /* new allocation */
7650                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7651         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7652
7653         memset(&c, 0, sizeof(c));
7654         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7655                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7656                                    FW_VI_MAC_CMD_VIID_V(viid));
7657         c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
7658         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7659                                       FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
7660                                       FW_VI_MAC_CMD_IDX_V(idx));
7661         memcpy(p->macaddr, addr, sizeof(p->macaddr));
7662
7663         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7664         if (ret == 0) {
7665                 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7666                 if (ret >= max_mac_addr)
7667                         ret = -ENOMEM;
7668         }
7669         return ret;
7670 }
7671
7672 /**
7673  *      t4_set_addr_hash - program the MAC inexact-match hash filter
7674  *      @adap: the adapter
7675  *      @mbox: mailbox to use for the FW command
7676  *      @viid: the VI id
7677  *      @ucast: whether the hash filter should also match unicast addresses
7678  *      @vec: the value to be written to the hash filter
7679  *      @sleep_ok: call is allowed to sleep
7680  *
7681  *      Sets the 64-bit inexact-match hash filter for a virtual interface.
7682  */
7683 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7684                      bool ucast, u64 vec, bool sleep_ok)
7685 {
7686         struct fw_vi_mac_cmd c;
7687
7688         memset(&c, 0, sizeof(c));
7689         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7690                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7691                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7692         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
7693                                           FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
7694                                           FW_CMD_LEN16_V(1));
7695         c.u.hash.hashvec = cpu_to_be64(vec);
7696         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7697 }
7698
7699 /**
7700  *      t4_enable_vi_params - enable/disable a virtual interface
7701  *      @adap: the adapter
7702  *      @mbox: mailbox to use for the FW command
7703  *      @viid: the VI id
7704  *      @rx_en: 1=enable Rx, 0=disable Rx
7705  *      @tx_en: 1=enable Tx, 0=disable Tx
7706  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
7707  *
7708  *      Enables/disables a virtual interface.  Note that setting DCB Enable
7709  *      only makes sense when enabling a Virtual Interface ...
7710  */
7711 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7712                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7713 {
7714         struct fw_vi_enable_cmd c;
7715
7716         memset(&c, 0, sizeof(c));
7717         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7718                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7719                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7720         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
7721                                      FW_VI_ENABLE_CMD_EEN_V(tx_en) |
7722                                      FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
7723                                      FW_LEN16(c));
7724         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7725 }
7726
7727 /**
7728  *      t4_enable_vi - enable/disable a virtual interface
7729  *      @adap: the adapter
7730  *      @mbox: mailbox to use for the FW command
7731  *      @viid: the VI id
7732  *      @rx_en: 1=enable Rx, 0=disable Rx
7733  *      @tx_en: 1=enable Tx, 0=disable Tx
7734  *
7735  *      Enables/disables a virtual interface.
7736  */
7737 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7738                  bool rx_en, bool tx_en)
7739 {
7740         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7741 }
7742
7743 /**
7744  *      t4_identify_port - identify a VI's port by blinking its LED
7745  *      @adap: the adapter
7746  *      @mbox: mailbox to use for the FW command
7747  *      @viid: the VI id
7748  *      @nblinks: how many times to blink LED at 2.5 Hz
7749  *
7750  *      Identifies a VI's port by blinking its LED.
7751  */
7752 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
7753                      unsigned int nblinks)
7754 {
7755         struct fw_vi_enable_cmd c;
7756
7757         memset(&c, 0, sizeof(c));
7758         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7759                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7760                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7761         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
7762         c.blinkdur = cpu_to_be16(nblinks);
7763         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7764 }
7765
7766 /**
7767  *      t4_iq_stop - stop an ingress queue and its FLs
7768  *      @adap: the adapter
7769  *      @mbox: mailbox to use for the FW command
7770  *      @pf: the PF owning the queues
7771  *      @vf: the VF owning the queues
7772  *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7773  *      @iqid: ingress queue id
7774  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7775  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7776  *
7777  *      Stops an ingress queue and its associated FLs, if any.  This causes
7778  *      any current or future data/messages destined for these queues to be
7779  *      tossed.
7780  */
7781 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7782                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7783                unsigned int fl0id, unsigned int fl1id)
7784 {
7785         struct fw_iq_cmd c;
7786
7787         memset(&c, 0, sizeof(c));
7788         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7789                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7790                                   FW_IQ_CMD_VFN_V(vf));
7791         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
7792         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7793         c.iqid = cpu_to_be16(iqid);
7794         c.fl0id = cpu_to_be16(fl0id);
7795         c.fl1id = cpu_to_be16(fl1id);
7796         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7797 }
7798
7799 /**
7800  *      t4_iq_free - free an ingress queue and its FLs
7801  *      @adap: the adapter
7802  *      @mbox: mailbox to use for the FW command
7803  *      @pf: the PF owning the queues
7804  *      @vf: the VF owning the queues
7805  *      @iqtype: the ingress queue type
7806  *      @iqid: ingress queue id
7807  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7808  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7809  *
7810  *      Frees an ingress queue and its associated FLs, if any.
7811  */
7812 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7813                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7814                unsigned int fl0id, unsigned int fl1id)
7815 {
7816         struct fw_iq_cmd c;
7817
7818         memset(&c, 0, sizeof(c));
7819         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7820                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7821                                   FW_IQ_CMD_VFN_V(vf));
7822         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7823         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7824         c.iqid = cpu_to_be16(iqid);
7825         c.fl0id = cpu_to_be16(fl0id);
7826         c.fl1id = cpu_to_be16(fl1id);
7827         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7828 }
7829
7830 /**
7831  *      t4_eth_eq_free - free an Ethernet egress queue
7832  *      @adap: the adapter
7833  *      @mbox: mailbox to use for the FW command
7834  *      @pf: the PF owning the queue
7835  *      @vf: the VF owning the queue
7836  *      @eqid: egress queue id
7837  *
7838  *      Frees an Ethernet egress queue.
7839  */
7840 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7841                    unsigned int vf, unsigned int eqid)
7842 {
7843         struct fw_eq_eth_cmd c;
7844
7845         memset(&c, 0, sizeof(c));
7846         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7847                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7848                                   FW_EQ_ETH_CMD_PFN_V(pf) |
7849                                   FW_EQ_ETH_CMD_VFN_V(vf));
7850         c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7851         c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7852         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7853 }
7854
7855 /**
7856  *      t4_ctrl_eq_free - free a control egress queue
7857  *      @adap: the adapter
7858  *      @mbox: mailbox to use for the FW command
7859  *      @pf: the PF owning the queue
7860  *      @vf: the VF owning the queue
7861  *      @eqid: egress queue id
7862  *
7863  *      Frees a control egress queue.
7864  */
7865 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7866                     unsigned int vf, unsigned int eqid)
7867 {
7868         struct fw_eq_ctrl_cmd c;
7869
7870         memset(&c, 0, sizeof(c));
7871         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7872                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7873                                   FW_EQ_CTRL_CMD_PFN_V(pf) |
7874                                   FW_EQ_CTRL_CMD_VFN_V(vf));
7875         c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7876         c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7877         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7878 }
7879
7880 /**
7881  *      t4_ofld_eq_free - free an offload egress queue
7882  *      @adap: the adapter
7883  *      @mbox: mailbox to use for the FW command
7884  *      @pf: the PF owning the queue
7885  *      @vf: the VF owning the queue
7886  *      @eqid: egress queue id
7887  *
7888  *      Frees a control egress queue.
7889  */
7890 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7891                     unsigned int vf, unsigned int eqid)
7892 {
7893         struct fw_eq_ofld_cmd c;
7894
7895         memset(&c, 0, sizeof(c));
7896         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7897                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7898                                   FW_EQ_OFLD_CMD_PFN_V(pf) |
7899                                   FW_EQ_OFLD_CMD_VFN_V(vf));
7900         c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7901         c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7902         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7903 }
7904
7905 /**
7906  *      t4_link_down_rc_str - return a string for a Link Down Reason Code
7907  *      @adap: the adapter
7908  *      @link_down_rc: Link Down Reason Code
7909  *
7910  *      Returns a string representation of the Link Down Reason Code.
7911  */
7912 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
7913 {
7914         static const char * const reason[] = {
7915                 "Link Down",
7916                 "Remote Fault",
7917                 "Auto-negotiation Failure",
7918                 "Reserved",
7919                 "Insufficient Airflow",
7920                 "Unable To Determine Reason",
7921                 "No RX Signal Detected",
7922                 "Reserved",
7923         };
7924
7925         if (link_down_rc >= ARRAY_SIZE(reason))
7926                 return "Bad Reason Code";
7927
7928         return reason[link_down_rc];
7929 }
7930
7931 /**
7932  * Return the highest speed set in the port capabilities, in Mb/s.
7933  */
7934 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
7935 {
7936         #define TEST_SPEED_RETURN(__caps_speed, __speed) \
7937                 do { \
7938                         if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
7939                                 return __speed; \
7940                 } while (0)
7941
7942         TEST_SPEED_RETURN(400G, 400000);
7943         TEST_SPEED_RETURN(200G, 200000);
7944         TEST_SPEED_RETURN(100G, 100000);
7945         TEST_SPEED_RETURN(50G,   50000);
7946         TEST_SPEED_RETURN(40G,   40000);
7947         TEST_SPEED_RETURN(25G,   25000);
7948         TEST_SPEED_RETURN(10G,   10000);
7949         TEST_SPEED_RETURN(1G,     1000);
7950         TEST_SPEED_RETURN(100M,    100);
7951
7952         #undef TEST_SPEED_RETURN
7953
7954         return 0;
7955 }
7956
7957 /**
7958  *      fwcap_to_fwspeed - return highest speed in Port Capabilities
7959  *      @acaps: advertised Port Capabilities
7960  *
7961  *      Get the highest speed for the port from the advertised Port
7962  *      Capabilities.  It will be either the highest speed from the list of
7963  *      speeds or whatever user has set using ethtool.
7964  */
7965 static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
7966 {
7967         #define TEST_SPEED_RETURN(__caps_speed) \
7968                 do { \
7969                         if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
7970                                 return FW_PORT_CAP32_SPEED_##__caps_speed; \
7971                 } while (0)
7972
7973         TEST_SPEED_RETURN(400G);
7974         TEST_SPEED_RETURN(200G);
7975         TEST_SPEED_RETURN(100G);
7976         TEST_SPEED_RETURN(50G);
7977         TEST_SPEED_RETURN(40G);
7978         TEST_SPEED_RETURN(25G);
7979         TEST_SPEED_RETURN(10G);
7980         TEST_SPEED_RETURN(1G);
7981         TEST_SPEED_RETURN(100M);
7982
7983         #undef TEST_SPEED_RETURN
7984
7985         return 0;
7986 }
7987
7988 /**
7989  *      lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
7990  *      @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
7991  *
7992  *      Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
7993  *      32-bit Port Capabilities value.
7994  */
7995 static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
7996 {
7997         fw_port_cap32_t linkattr = 0;
7998
7999         /* Unfortunately the format of the Link Status in the old
8000          * 16-bit Port Information message isn't the same as the
8001          * 16-bit Port Capabilities bitfield used everywhere else ...
8002          */
8003         if (lstatus & FW_PORT_CMD_RXPAUSE_F)
8004                 linkattr |= FW_PORT_CAP32_FC_RX;
8005         if (lstatus & FW_PORT_CMD_TXPAUSE_F)
8006                 linkattr |= FW_PORT_CAP32_FC_TX;
8007         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
8008                 linkattr |= FW_PORT_CAP32_SPEED_100M;
8009         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
8010                 linkattr |= FW_PORT_CAP32_SPEED_1G;
8011         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
8012                 linkattr |= FW_PORT_CAP32_SPEED_10G;
8013         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
8014                 linkattr |= FW_PORT_CAP32_SPEED_25G;
8015         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
8016                 linkattr |= FW_PORT_CAP32_SPEED_40G;
8017         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
8018                 linkattr |= FW_PORT_CAP32_SPEED_100G;
8019
8020         return linkattr;
8021 }
8022
8023 /**
8024  *      t4_handle_get_port_info - process a FW reply message
8025  *      @pi: the port info
8026  *      @rpl: start of the FW message
8027  *
8028  *      Processes a GET_PORT_INFO FW reply message.
8029  */
8030 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
8031 {
8032         const struct fw_port_cmd *cmd = (const void *)rpl;
8033         int action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
8034         struct adapter *adapter = pi->adapter;
8035         struct link_config *lc = &pi->link_cfg;
8036         int link_ok, linkdnrc;
8037         enum fw_port_type port_type;
8038         enum fw_port_module_type mod_type;
8039         unsigned int speed, fc, fec;
8040         fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
8041
8042         /* Extract the various fields from the Port Information message.
8043          */
8044         switch (action) {
8045         case FW_PORT_ACTION_GET_PORT_INFO: {
8046                 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
8047
8048                 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
8049                 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
8050                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8051                 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
8052                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
8053                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
8054                 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
8055                 linkattr = lstatus_to_fwcap(lstatus);
8056                 break;
8057         }
8058
8059         case FW_PORT_ACTION_GET_PORT_INFO32: {
8060                 u32 lstatus32;
8061
8062                 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
8063                 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
8064                 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
8065                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8066                 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
8067                 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
8068                 acaps = be32_to_cpu(cmd->u.info32.acaps32);
8069                 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
8070                 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
8071                 break;
8072         }
8073
8074         default:
8075                 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
8076                         be32_to_cpu(cmd->action_to_len16));
8077                 return;
8078         }
8079
8080         fec = fwcap_to_cc_fec(acaps);
8081         fc = fwcap_to_cc_pause(linkattr);
8082         speed = fwcap_to_speed(linkattr);
8083
8084         if (mod_type != pi->mod_type) {
8085                 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8086                  * various fundamental Port Capabilities which used to be
8087                  * immutable can now change radically.  We can now have
8088                  * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8089                  * all change based on what Transceiver Module is inserted.
8090                  * So we need to record the Physical "Port" Capabilities on
8091                  * every Transceiver Module change.
8092                  */
8093                 lc->pcaps = pcaps;
8094
8095                 /* When a new Transceiver Module is inserted, the Firmware
8096                  * will examine its i2c EPROM to determine its type and
8097                  * general operating parameters including things like Forward
8098                  * Error Control, etc.  Various IEEE 802.3 standards dictate
8099                  * how to interpret these i2c values to determine default
8100                  * "sutomatic" settings.  We record these for future use when
8101                  * the user explicitly requests these standards-based values.
8102                  */
8103                 lc->def_acaps = acaps;
8104
8105                 /* Some versions of the early T6 Firmware "cheated" when
8106                  * handling different Transceiver Modules by changing the
8107                  * underlaying Port Type reported to the Host Drivers.  As
8108                  * such we need to capture whatever Port Type the Firmware
8109                  * sends us and record it in case it's different from what we
8110                  * were told earlier.  Unfortunately, since Firmware is
8111                  * forever, we'll need to keep this code here forever, but in
8112                  * later T6 Firmware it should just be an assignment of the
8113                  * same value already recorded.
8114                  */
8115                 pi->port_type = port_type;
8116
8117                 pi->mod_type = mod_type;
8118                 t4_os_portmod_changed(adapter, pi->port_id);
8119         }
8120
8121         if (link_ok != lc->link_ok || speed != lc->speed ||
8122             fc != lc->fc || fec != lc->fec) {   /* something changed */
8123                 if (!link_ok && lc->link_ok) {
8124                         lc->link_down_rc = linkdnrc;
8125                         dev_warn(adapter->pdev_dev, "Port %d link down, reason: %s\n",
8126                                  pi->tx_chan, t4_link_down_rc_str(linkdnrc));
8127                 }
8128                 lc->link_ok = link_ok;
8129                 lc->speed = speed;
8130                 lc->fc = fc;
8131                 lc->fec = fec;
8132
8133                 lc->lpacaps = lpacaps;
8134                 lc->acaps = acaps & ADVERT_MASK;
8135
8136                 if (lc->acaps & FW_PORT_CAP32_ANEG) {
8137                         lc->autoneg = AUTONEG_ENABLE;
8138                 } else {
8139                         /* When Autoneg is disabled, user needs to set
8140                          * single speed.
8141                          * Similar to cxgb4_ethtool.c: set_link_ksettings
8142                          */
8143                         lc->acaps = 0;
8144                         lc->speed_caps = fwcap_to_fwspeed(acaps);
8145                         lc->autoneg = AUTONEG_DISABLE;
8146                 }
8147
8148                 t4_os_link_changed(adapter, pi->port_id, link_ok);
8149         }
8150 }
8151
8152 /**
8153  *      t4_update_port_info - retrieve and update port information if changed
8154  *      @pi: the port_info
8155  *
8156  *      We issue a Get Port Information Command to the Firmware and, if
8157  *      successful, we check to see if anything is different from what we
8158  *      last recorded and update things accordingly.
8159  */
8160 int t4_update_port_info(struct port_info *pi)
8161 {
8162         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8163         struct fw_port_cmd port_cmd;
8164         int ret;
8165
8166         memset(&port_cmd, 0, sizeof(port_cmd));
8167         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8168                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8169                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8170         port_cmd.action_to_len16 = cpu_to_be32(
8171                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8172                                      ? FW_PORT_ACTION_GET_PORT_INFO
8173                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
8174                 FW_LEN16(port_cmd));
8175         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8176                          &port_cmd, sizeof(port_cmd), &port_cmd);
8177         if (ret)
8178                 return ret;
8179
8180         t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8181         return 0;
8182 }
8183
8184 /**
8185  *      t4_get_link_params - retrieve basic link parameters for given port
8186  *      @pi: the port
8187  *      @link_okp: value return pointer for link up/down
8188  *      @speedp: value return pointer for speed (Mb/s)
8189  *      @mtup: value return pointer for mtu
8190  *
8191  *      Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8192  *      and MTU for a specified port.  A negative error is returned on
8193  *      failure; 0 on success.
8194  */
8195 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8196                        unsigned int *speedp, unsigned int *mtup)
8197 {
8198         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8199         struct fw_port_cmd port_cmd;
8200         unsigned int action, link_ok, speed, mtu;
8201         fw_port_cap32_t linkattr;
8202         int ret;
8203
8204         memset(&port_cmd, 0, sizeof(port_cmd));
8205         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8206                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8207                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8208         action = (fw_caps == FW_CAPS16
8209                   ? FW_PORT_ACTION_GET_PORT_INFO
8210                   : FW_PORT_ACTION_GET_PORT_INFO32);
8211         port_cmd.action_to_len16 = cpu_to_be32(
8212                 FW_PORT_CMD_ACTION_V(action) |
8213                 FW_LEN16(port_cmd));
8214         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8215                          &port_cmd, sizeof(port_cmd), &port_cmd);
8216         if (ret)
8217                 return ret;
8218
8219         if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8220                 u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8221
8222                 link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8223                 linkattr = lstatus_to_fwcap(lstatus);
8224                 mtu = be16_to_cpu(port_cmd.u.info.mtu);
8225         } else {
8226                 u32 lstatus32 =
8227                            be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8228
8229                 link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8230                 linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8231                 mtu = FW_PORT_CMD_MTU32_G(
8232                         be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8233         }
8234         speed = fwcap_to_speed(linkattr);
8235
8236         *link_okp = link_ok;
8237         *speedp = fwcap_to_speed(linkattr);
8238         *mtup = mtu;
8239
8240         return 0;
8241 }
8242
8243 /**
8244  *      t4_handle_fw_rpl - process a FW reply message
8245  *      @adap: the adapter
8246  *      @rpl: start of the FW message
8247  *
8248  *      Processes a FW message, such as link state change messages.
8249  */
8250 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8251 {
8252         u8 opcode = *(const u8 *)rpl;
8253
8254         /* This might be a port command ... this simplifies the following
8255          * conditionals ...  We can get away with pre-dereferencing
8256          * action_to_len16 because it's in the first 16 bytes and all messages
8257          * will be at least that long.
8258          */
8259         const struct fw_port_cmd *p = (const void *)rpl;
8260         unsigned int action =
8261                 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8262
8263         if (opcode == FW_PORT_CMD &&
8264             (action == FW_PORT_ACTION_GET_PORT_INFO ||
8265              action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8266                 int i;
8267                 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8268                 struct port_info *pi = NULL;
8269
8270                 for_each_port(adap, i) {
8271                         pi = adap2pinfo(adap, i);
8272                         if (pi->tx_chan == chan)
8273                                 break;
8274                 }
8275
8276                 t4_handle_get_port_info(pi, rpl);
8277         } else {
8278                 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8279                          opcode);
8280                 return -EINVAL;
8281         }
8282         return 0;
8283 }
8284
8285 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8286 {
8287         u16 val;
8288
8289         if (pci_is_pcie(adapter->pdev)) {
8290                 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8291                 p->speed = val & PCI_EXP_LNKSTA_CLS;
8292                 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8293         }
8294 }
8295
8296 /**
8297  *      init_link_config - initialize a link's SW state
8298  *      @lc: pointer to structure holding the link state
8299  *      @pcaps: link Port Capabilities
8300  *      @acaps: link current Advertised Port Capabilities
8301  *
8302  *      Initializes the SW state maintained for each link, including the link's
8303  *      capabilities and default speed/flow-control/autonegotiation settings.
8304  */
8305 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8306                              fw_port_cap32_t acaps)
8307 {
8308         lc->pcaps = pcaps;
8309         lc->def_acaps = acaps;
8310         lc->lpacaps = 0;
8311         lc->speed_caps = 0;
8312         lc->speed = 0;
8313         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8314
8315         /* For Forward Error Control, we default to whatever the Firmware
8316          * tells us the Link is currently advertising.
8317          */
8318         lc->requested_fec = FEC_AUTO;
8319         lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8320
8321         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8322                 lc->acaps = lc->pcaps & ADVERT_MASK;
8323                 lc->autoneg = AUTONEG_ENABLE;
8324                 lc->requested_fc |= PAUSE_AUTONEG;
8325         } else {
8326                 lc->acaps = 0;
8327                 lc->autoneg = AUTONEG_DISABLE;
8328         }
8329 }
8330
8331 #define CIM_PF_NOACCESS 0xeeeeeeee
8332
8333 int t4_wait_dev_ready(void __iomem *regs)
8334 {
8335         u32 whoami;
8336
8337         whoami = readl(regs + PL_WHOAMI_A);
8338         if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8339                 return 0;
8340
8341         msleep(500);
8342         whoami = readl(regs + PL_WHOAMI_A);
8343         return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8344 }
8345
8346 struct flash_desc {
8347         u32 vendor_and_model_id;
8348         u32 size_mb;
8349 };
8350
8351 static int t4_get_flash_params(struct adapter *adap)
8352 {
8353         /* Table for non-Numonix supported flash parts.  Numonix parts are left
8354          * to the preexisting code.  All flash parts have 64KB sectors.
8355          */
8356         static struct flash_desc supported_flash[] = {
8357                 { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
8358         };
8359
8360         unsigned int part, manufacturer;
8361         unsigned int density, size;
8362         u32 flashid = 0;
8363         int ret;
8364
8365         /* Issue a Read ID Command to the Flash part.  We decode supported
8366          * Flash parts and their sizes from this.  There's a newer Query
8367          * Command which can retrieve detailed geometry information but many
8368          * Flash parts don't support it.
8369          */
8370
8371         ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8372         if (!ret)
8373                 ret = sf1_read(adap, 3, 0, 1, &flashid);
8374         t4_write_reg(adap, SF_OP_A, 0);                    /* unlock SF */
8375         if (ret)
8376                 return ret;
8377
8378         /* Check to see if it's one of our non-standard supported Flash parts.
8379          */
8380         for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
8381                 if (supported_flash[part].vendor_and_model_id == flashid) {
8382                         adap->params.sf_size = supported_flash[part].size_mb;
8383                         adap->params.sf_nsec =
8384                                 adap->params.sf_size / SF_SEC_SIZE;
8385                         goto found;
8386                 }
8387
8388         /* Decode Flash part size.  The code below looks repetative with
8389          * common encodings, but that's not guaranteed in the JEDEC
8390          * specification for the Read JADEC ID command.  The only thing that
8391          * we're guaranteed by the JADEC specification is where the
8392          * Manufacturer ID is in the returned result.  After that each
8393          * Manufacturer ~could~ encode things completely differently.
8394          * Note, all Flash parts must have 64KB sectors.
8395          */
8396         manufacturer = flashid & 0xff;
8397         switch (manufacturer) {
8398         case 0x20: { /* Micron/Numonix */
8399                 /* This Density -> Size decoding table is taken from Micron
8400                  * Data Sheets.
8401                  */
8402                 density = (flashid >> 16) & 0xff;
8403                 switch (density) {
8404                 case 0x14: /* 1MB */
8405                         size = 1 << 20;
8406                         break;
8407                 case 0x15: /* 2MB */
8408                         size = 1 << 21;
8409                         break;
8410                 case 0x16: /* 4MB */
8411                         size = 1 << 22;
8412                         break;
8413                 case 0x17: /* 8MB */
8414                         size = 1 << 23;
8415                         break;
8416                 case 0x18: /* 16MB */
8417                         size = 1 << 24;
8418                         break;
8419                 case 0x19: /* 32MB */
8420                         size = 1 << 25;
8421                         break;
8422                 case 0x20: /* 64MB */
8423                         size = 1 << 26;
8424                         break;
8425                 case 0x21: /* 128MB */
8426                         size = 1 << 27;
8427                         break;
8428                 case 0x22: /* 256MB */
8429                         size = 1 << 28;
8430                         break;
8431
8432                 default:
8433                         dev_err(adap->pdev_dev, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
8434                                 flashid, density);
8435                         return -EINVAL;
8436                 }
8437                 break;
8438         }
8439         case 0xc2: { /* Macronix */
8440                 /* This Density -> Size decoding table is taken from Macronix
8441                  * Data Sheets.
8442                  */
8443                 density = (flashid >> 16) & 0xff;
8444                 switch (density) {
8445                 case 0x17: /* 8MB */
8446                         size = 1 << 23;
8447                         break;
8448                 case 0x18: /* 16MB */
8449                         size = 1 << 24;
8450                         break;
8451                 default:
8452                         dev_err(adap->pdev_dev, "Macronix Flash Part has bad size, ID = %#x, Density code = %#x\n",
8453                                 flashid, density);
8454                         return -EINVAL;
8455                 }
8456                 break;
8457         }
8458         case 0xef: { /* Winbond */
8459                 /* This Density -> Size decoding table is taken from Winbond
8460                  * Data Sheets.
8461                  */
8462                 density = (flashid >> 16) & 0xff;
8463                 switch (density) {
8464                 case 0x17: /* 8MB */
8465                         size = 1 << 23;
8466                         break;
8467                 case 0x18: /* 16MB */
8468                         size = 1 << 24;
8469                         break;
8470                 default:
8471                         dev_err(adap->pdev_dev, "Winbond Flash Part has bad size, ID = %#x, Density code = %#x\n",
8472                                 flashid, density);
8473                         return -EINVAL;
8474                 }
8475                 break;
8476         }
8477         default:
8478                 dev_err(adap->pdev_dev, "Unsupported Flash Part, ID = %#x\n",
8479                         flashid);
8480                 return -EINVAL;
8481         }
8482
8483         /* Store decoded Flash size and fall through into vetting code. */
8484         adap->params.sf_size = size;
8485         adap->params.sf_nsec = size / SF_SEC_SIZE;
8486
8487 found:
8488         if (adap->params.sf_size < FLASH_MIN_SIZE)
8489                 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
8490                          flashid, adap->params.sf_size, FLASH_MIN_SIZE);
8491         return 0;
8492 }
8493
8494 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
8495 {
8496         u16 val;
8497         u32 pcie_cap;
8498
8499         pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
8500         if (pcie_cap) {
8501                 pci_read_config_word(adapter->pdev,
8502                                      pcie_cap + PCI_EXP_DEVCTL2, &val);
8503                 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
8504                 val |= range;
8505                 pci_write_config_word(adapter->pdev,
8506                                       pcie_cap + PCI_EXP_DEVCTL2, val);
8507         }
8508 }
8509
8510 /**
8511  *      t4_prep_adapter - prepare SW and HW for operation
8512  *      @adapter: the adapter
8513  *      @reset: if true perform a HW reset
8514  *
8515  *      Initialize adapter SW state for the various HW modules, set initial
8516  *      values for some adapter tunables, take PHYs out of reset, and
8517  *      initialize the MDIO interface.
8518  */
8519 int t4_prep_adapter(struct adapter *adapter)
8520 {
8521         int ret, ver;
8522         uint16_t device_id;
8523         u32 pl_rev;
8524
8525         get_pci_mode(adapter, &adapter->params.pci);
8526         pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
8527
8528         ret = t4_get_flash_params(adapter);
8529         if (ret < 0) {
8530                 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
8531                 return ret;
8532         }
8533
8534         /* Retrieve adapter's device ID
8535          */
8536         pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
8537         ver = device_id >> 12;
8538         adapter->params.chip = 0;
8539         switch (ver) {
8540         case CHELSIO_T4:
8541                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
8542                 adapter->params.arch.sge_fl_db = DBPRIO_F;
8543                 adapter->params.arch.mps_tcam_size =
8544                                  NUM_MPS_CLS_SRAM_L_INSTANCES;
8545                 adapter->params.arch.mps_rplc_size = 128;
8546                 adapter->params.arch.nchan = NCHAN;
8547                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8548                 adapter->params.arch.vfcount = 128;
8549                 /* Congestion map is for 4 channels so that
8550                  * MPS can have 4 priority per port.
8551                  */
8552                 adapter->params.arch.cng_ch_bits_log = 2;
8553                 break;
8554         case CHELSIO_T5:
8555                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
8556                 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
8557                 adapter->params.arch.mps_tcam_size =
8558                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8559                 adapter->params.arch.mps_rplc_size = 128;
8560                 adapter->params.arch.nchan = NCHAN;
8561                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8562                 adapter->params.arch.vfcount = 128;
8563                 adapter->params.arch.cng_ch_bits_log = 2;
8564                 break;
8565         case CHELSIO_T6:
8566                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
8567                 adapter->params.arch.sge_fl_db = 0;
8568                 adapter->params.arch.mps_tcam_size =
8569                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8570                 adapter->params.arch.mps_rplc_size = 256;
8571                 adapter->params.arch.nchan = 2;
8572                 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
8573                 adapter->params.arch.vfcount = 256;
8574                 /* Congestion map will be for 2 channels so that
8575                  * MPS can have 8 priority per port.
8576                  */
8577                 adapter->params.arch.cng_ch_bits_log = 3;
8578                 break;
8579         default:
8580                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
8581                         device_id);
8582                 return -EINVAL;
8583         }
8584
8585         adapter->params.cim_la_size = CIMLA_SIZE;
8586         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
8587
8588         /*
8589          * Default port for debugging in case we can't reach FW.
8590          */
8591         adapter->params.nports = 1;
8592         adapter->params.portvec = 1;
8593         adapter->params.vpd.cclk = 50000;
8594
8595         /* Set pci completion timeout value to 4 seconds. */
8596         set_pcie_completion_timeout(adapter, 0xd);
8597         return 0;
8598 }
8599
8600 /**
8601  *      t4_shutdown_adapter - shut down adapter, host & wire
8602  *      @adapter: the adapter
8603  *
8604  *      Perform an emergency shutdown of the adapter and stop it from
8605  *      continuing any further communication on the ports or DMA to the
8606  *      host.  This is typically used when the adapter and/or firmware
8607  *      have crashed and we want to prevent any further accidental
8608  *      communication with the rest of the world.  This will also force
8609  *      the port Link Status to go down -- if register writes work --
8610  *      which should help our peers figure out that we're down.
8611  */
8612 int t4_shutdown_adapter(struct adapter *adapter)
8613 {
8614         int port;
8615
8616         t4_intr_disable(adapter);
8617         t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
8618         for_each_port(adapter, port) {
8619                 u32 a_port_cfg = is_t4(adapter->params.chip) ?
8620                                        PORT_REG(port, XGMAC_PORT_CFG_A) :
8621                                        T5_PORT_REG(port, MAC_PORT_CFG_A);
8622
8623                 t4_write_reg(adapter, a_port_cfg,
8624                              t4_read_reg(adapter, a_port_cfg)
8625                              & ~SIGNAL_DET_V(1));
8626         }
8627         t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
8628
8629         return 0;
8630 }
8631
8632 /**
8633  *      t4_bar2_sge_qregs - return BAR2 SGE Queue register information
8634  *      @adapter: the adapter
8635  *      @qid: the Queue ID
8636  *      @qtype: the Ingress or Egress type for @qid
8637  *      @user: true if this request is for a user mode queue
8638  *      @pbar2_qoffset: BAR2 Queue Offset
8639  *      @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
8640  *
8641  *      Returns the BAR2 SGE Queue Registers information associated with the
8642  *      indicated Absolute Queue ID.  These are passed back in return value
8643  *      pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
8644  *      and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
8645  *
8646  *      This may return an error which indicates that BAR2 SGE Queue
8647  *      registers aren't available.  If an error is not returned, then the
8648  *      following values are returned:
8649  *
8650  *        *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
8651  *        *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
8652  *
8653  *      If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
8654  *      require the "Inferred Queue ID" ability may be used.  E.g. the
8655  *      Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
8656  *      then these "Inferred Queue ID" register may not be used.
8657  */
8658 int t4_bar2_sge_qregs(struct adapter *adapter,
8659                       unsigned int qid,
8660                       enum t4_bar2_qtype qtype,
8661                       int user,
8662                       u64 *pbar2_qoffset,
8663                       unsigned int *pbar2_qid)
8664 {
8665         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
8666         u64 bar2_page_offset, bar2_qoffset;
8667         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
8668
8669         /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
8670         if (!user && is_t4(adapter->params.chip))
8671                 return -EINVAL;
8672
8673         /* Get our SGE Page Size parameters.
8674          */
8675         page_shift = adapter->params.sge.hps + 10;
8676         page_size = 1 << page_shift;
8677
8678         /* Get the right Queues per Page parameters for our Queue.
8679          */
8680         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
8681                      ? adapter->params.sge.eq_qpp
8682                      : adapter->params.sge.iq_qpp);
8683         qpp_mask = (1 << qpp_shift) - 1;
8684
8685         /*  Calculate the basics of the BAR2 SGE Queue register area:
8686          *  o The BAR2 page the Queue registers will be in.
8687          *  o The BAR2 Queue ID.
8688          *  o The BAR2 Queue ID Offset into the BAR2 page.
8689          */
8690         bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
8691         bar2_qid = qid & qpp_mask;
8692         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
8693
8694         /* If the BAR2 Queue ID Offset is less than the Page Size, then the
8695          * hardware will infer the Absolute Queue ID simply from the writes to
8696          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
8697          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
8698          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
8699          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
8700          * from the BAR2 Page and BAR2 Queue ID.
8701          *
8702          * One important censequence of this is that some BAR2 SGE registers
8703          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
8704          * there.  But other registers synthesize the SGE Queue ID purely
8705          * from the writes to the registers -- the Write Combined Doorbell
8706          * Buffer is a good example.  These BAR2 SGE Registers are only
8707          * available for those BAR2 SGE Register areas where the SGE Absolute
8708          * Queue ID can be inferred from simple writes.
8709          */
8710         bar2_qoffset = bar2_page_offset;
8711         bar2_qinferred = (bar2_qid_offset < page_size);
8712         if (bar2_qinferred) {
8713                 bar2_qoffset += bar2_qid_offset;
8714                 bar2_qid = 0;
8715         }
8716
8717         *pbar2_qoffset = bar2_qoffset;
8718         *pbar2_qid = bar2_qid;
8719         return 0;
8720 }
8721
8722 /**
8723  *      t4_init_devlog_params - initialize adapter->params.devlog
8724  *      @adap: the adapter
8725  *
8726  *      Initialize various fields of the adapter's Firmware Device Log
8727  *      Parameters structure.
8728  */
8729 int t4_init_devlog_params(struct adapter *adap)
8730 {
8731         struct devlog_params *dparams = &adap->params.devlog;
8732         u32 pf_dparams;
8733         unsigned int devlog_meminfo;
8734         struct fw_devlog_cmd devlog_cmd;
8735         int ret;
8736
8737         /* If we're dealing with newer firmware, the Device Log Paramerters
8738          * are stored in a designated register which allows us to access the
8739          * Device Log even if we can't talk to the firmware.
8740          */
8741         pf_dparams =
8742                 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
8743         if (pf_dparams) {
8744                 unsigned int nentries, nentries128;
8745
8746                 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
8747                 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
8748
8749                 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
8750                 nentries = (nentries128 + 1) * 128;
8751                 dparams->size = nentries * sizeof(struct fw_devlog_e);
8752
8753                 return 0;
8754         }
8755
8756         /* Otherwise, ask the firmware for it's Device Log Parameters.
8757          */
8758         memset(&devlog_cmd, 0, sizeof(devlog_cmd));
8759         devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
8760                                              FW_CMD_REQUEST_F | FW_CMD_READ_F);
8761         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
8762         ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
8763                          &devlog_cmd);
8764         if (ret)
8765                 return ret;
8766
8767         devlog_meminfo =
8768                 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
8769         dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
8770         dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
8771         dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
8772
8773         return 0;
8774 }
8775
8776 /**
8777  *      t4_init_sge_params - initialize adap->params.sge
8778  *      @adapter: the adapter
8779  *
8780  *      Initialize various fields of the adapter's SGE Parameters structure.
8781  */
8782 int t4_init_sge_params(struct adapter *adapter)
8783 {
8784         struct sge_params *sge_params = &adapter->params.sge;
8785         u32 hps, qpp;
8786         unsigned int s_hps, s_qpp;
8787
8788         /* Extract the SGE Page Size for our PF.
8789          */
8790         hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
8791         s_hps = (HOSTPAGESIZEPF0_S +
8792                  (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
8793         sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
8794
8795         /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
8796          */
8797         s_qpp = (QUEUESPERPAGEPF0_S +
8798                 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
8799         qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
8800         sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
8801         qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
8802         sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
8803
8804         return 0;
8805 }
8806
8807 /**
8808  *      t4_init_tp_params - initialize adap->params.tp
8809  *      @adap: the adapter
8810  *      @sleep_ok: if true we may sleep while awaiting command completion
8811  *
8812  *      Initialize various fields of the adapter's TP Parameters structure.
8813  */
8814 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
8815 {
8816         int chan;
8817         u32 v;
8818
8819         v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
8820         adap->params.tp.tre = TIMERRESOLUTION_G(v);
8821         adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
8822
8823         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
8824         for (chan = 0; chan < NCHAN; chan++)
8825                 adap->params.tp.tx_modq[chan] = chan;
8826
8827         /* Cache the adapter's Compressed Filter Mode and global Incress
8828          * Configuration.
8829          */
8830         t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
8831                        TP_VLAN_PRI_MAP_A, sleep_ok);
8832         t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1,
8833                        TP_INGRESS_CONFIG_A, sleep_ok);
8834
8835         /* For T6, cache the adapter's compressed error vector
8836          * and passing outer header info for encapsulated packets.
8837          */
8838         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
8839                 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
8840                 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
8841         }
8842
8843         /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
8844          * shift positions of several elements of the Compressed Filter Tuple
8845          * for this adapter which we need frequently ...
8846          */
8847         adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
8848         adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
8849         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
8850         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
8851         adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
8852         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
8853                                                                PROTOCOL_F);
8854         adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
8855                                                                 ETHERTYPE_F);
8856         adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
8857                                                                MACMATCH_F);
8858         adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
8859                                                                 MPSHITTYPE_F);
8860         adap->params.tp.frag_shift = t4_filter_field_shift(adap,
8861                                                            FRAGMENTATION_F);
8862
8863         /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
8864          * represents the presence of an Outer VLAN instead of a VNIC ID.
8865          */
8866         if ((adap->params.tp.ingress_config & VNIC_F) == 0)
8867                 adap->params.tp.vnic_shift = -1;
8868
8869         v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
8870         adap->params.tp.hash_filter_mask = v;
8871         v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
8872         adap->params.tp.hash_filter_mask |= ((u64)v << 32);
8873         return 0;
8874 }
8875
8876 /**
8877  *      t4_filter_field_shift - calculate filter field shift
8878  *      @adap: the adapter
8879  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
8880  *
8881  *      Return the shift position of a filter field within the Compressed
8882  *      Filter Tuple.  The filter field is specified via its selection bit
8883  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
8884  */
8885 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
8886 {
8887         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
8888         unsigned int sel;
8889         int field_shift;
8890
8891         if ((filter_mode & filter_sel) == 0)
8892                 return -1;
8893
8894         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
8895                 switch (filter_mode & sel) {
8896                 case FCOE_F:
8897                         field_shift += FT_FCOE_W;
8898                         break;
8899                 case PORT_F:
8900                         field_shift += FT_PORT_W;
8901                         break;
8902                 case VNIC_ID_F:
8903                         field_shift += FT_VNIC_ID_W;
8904                         break;
8905                 case VLAN_F:
8906                         field_shift += FT_VLAN_W;
8907                         break;
8908                 case TOS_F:
8909                         field_shift += FT_TOS_W;
8910                         break;
8911                 case PROTOCOL_F:
8912                         field_shift += FT_PROTOCOL_W;
8913                         break;
8914                 case ETHERTYPE_F:
8915                         field_shift += FT_ETHERTYPE_W;
8916                         break;
8917                 case MACMATCH_F:
8918                         field_shift += FT_MACMATCH_W;
8919                         break;
8920                 case MPSHITTYPE_F:
8921                         field_shift += FT_MPSHITTYPE_W;
8922                         break;
8923                 case FRAGMENTATION_F:
8924                         field_shift += FT_FRAGMENTATION_W;
8925                         break;
8926                 }
8927         }
8928         return field_shift;
8929 }
8930
8931 int t4_init_rss_mode(struct adapter *adap, int mbox)
8932 {
8933         int i, ret;
8934         struct fw_rss_vi_config_cmd rvc;
8935
8936         memset(&rvc, 0, sizeof(rvc));
8937
8938         for_each_port(adap, i) {
8939                 struct port_info *p = adap2pinfo(adap, i);
8940
8941                 rvc.op_to_viid =
8942                         cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
8943                                     FW_CMD_REQUEST_F | FW_CMD_READ_F |
8944                                     FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
8945                 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
8946                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
8947                 if (ret)
8948                         return ret;
8949                 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
8950         }
8951         return 0;
8952 }
8953
8954 /**
8955  *      t4_init_portinfo - allocate a virtual interface and initialize port_info
8956  *      @pi: the port_info
8957  *      @mbox: mailbox to use for the FW command
8958  *      @port: physical port associated with the VI
8959  *      @pf: the PF owning the VI
8960  *      @vf: the VF owning the VI
8961  *      @mac: the MAC address of the VI
8962  *
8963  *      Allocates a virtual interface for the given physical port.  If @mac is
8964  *      not %NULL it contains the MAC address of the VI as assigned by FW.
8965  *      @mac should be large enough to hold an Ethernet address.
8966  *      Returns < 0 on error.
8967  */
8968 int t4_init_portinfo(struct port_info *pi, int mbox,
8969                      int port, int pf, int vf, u8 mac[])
8970 {
8971         struct adapter *adapter = pi->adapter;
8972         unsigned int fw_caps = adapter->params.fw_caps_support;
8973         struct fw_port_cmd cmd;
8974         unsigned int rss_size;
8975         enum fw_port_type port_type;
8976         int mdio_addr;
8977         fw_port_cap32_t pcaps, acaps;
8978         int ret;
8979
8980         /* If we haven't yet determined whether we're talking to Firmware
8981          * which knows the new 32-bit Port Capabilities, it's time to find
8982          * out now.  This will also tell new Firmware to send us Port Status
8983          * Updates using the new 32-bit Port Capabilities version of the
8984          * Port Information message.
8985          */
8986         if (fw_caps == FW_CAPS_UNKNOWN) {
8987                 u32 param, val;
8988
8989                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
8990                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
8991                 val = 1;
8992                 ret = t4_set_params(adapter, mbox, pf, vf, 1, &param, &val);
8993                 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
8994                 adapter->params.fw_caps_support = fw_caps;
8995         }
8996
8997         memset(&cmd, 0, sizeof(cmd));
8998         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8999                                        FW_CMD_REQUEST_F | FW_CMD_READ_F |
9000                                        FW_PORT_CMD_PORTID_V(port));
9001         cmd.action_to_len16 = cpu_to_be32(
9002                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
9003                                      ? FW_PORT_ACTION_GET_PORT_INFO
9004                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
9005                 FW_LEN16(cmd));
9006         ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
9007         if (ret)
9008                 return ret;
9009
9010         /* Extract the various fields from the Port Information message.
9011          */
9012         if (fw_caps == FW_CAPS16) {
9013                 u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
9014
9015                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
9016                 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
9017                              ? FW_PORT_CMD_MDIOADDR_G(lstatus)
9018                              : -1);
9019                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
9020                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
9021         } else {
9022                 u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
9023
9024                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
9025                 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
9026                              ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
9027                              : -1);
9028                 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
9029                 acaps = be32_to_cpu(cmd.u.info32.acaps32);
9030         }
9031
9032         ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
9033         if (ret < 0)
9034                 return ret;
9035
9036         pi->viid = ret;
9037         pi->tx_chan = port;
9038         pi->lport = port;
9039         pi->rss_size = rss_size;
9040
9041         pi->port_type = port_type;
9042         pi->mdio_addr = mdio_addr;
9043         pi->mod_type = FW_PORT_MOD_TYPE_NA;
9044
9045         init_link_config(&pi->link_cfg, pcaps, acaps);
9046         return 0;
9047 }
9048
9049 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
9050 {
9051         u8 addr[6];
9052         int ret, i, j = 0;
9053
9054         for_each_port(adap, i) {
9055                 struct port_info *pi = adap2pinfo(adap, i);
9056
9057                 while ((adap->params.portvec & (1 << j)) == 0)
9058                         j++;
9059
9060                 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
9061                 if (ret)
9062                         return ret;
9063
9064                 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
9065                 j++;
9066         }
9067         return 0;
9068 }
9069
9070 /**
9071  *      t4_read_cimq_cfg - read CIM queue configuration
9072  *      @adap: the adapter
9073  *      @base: holds the queue base addresses in bytes
9074  *      @size: holds the queue sizes in bytes
9075  *      @thres: holds the queue full thresholds in bytes
9076  *
9077  *      Returns the current configuration of the CIM queues, starting with
9078  *      the IBQs, then the OBQs.
9079  */
9080 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9081 {
9082         unsigned int i, v;
9083         int cim_num_obq = is_t4(adap->params.chip) ?
9084                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9085
9086         for (i = 0; i < CIM_NUM_IBQ; i++) {
9087                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
9088                              QUENUMSELECT_V(i));
9089                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9090                 /* value is in 256-byte units */
9091                 *base++ = CIMQBASE_G(v) * 256;
9092                 *size++ = CIMQSIZE_G(v) * 256;
9093                 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
9094         }
9095         for (i = 0; i < cim_num_obq; i++) {
9096                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9097                              QUENUMSELECT_V(i));
9098                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9099                 /* value is in 256-byte units */
9100                 *base++ = CIMQBASE_G(v) * 256;
9101                 *size++ = CIMQSIZE_G(v) * 256;
9102         }
9103 }
9104
9105 /**
9106  *      t4_read_cim_ibq - read the contents of a CIM inbound queue
9107  *      @adap: the adapter
9108  *      @qid: the queue index
9109  *      @data: where to store the queue contents
9110  *      @n: capacity of @data in 32-bit words
9111  *
9112  *      Reads the contents of the selected CIM queue starting at address 0 up
9113  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9114  *      error and the number of 32-bit words actually read on success.
9115  */
9116 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9117 {
9118         int i, err, attempts;
9119         unsigned int addr;
9120         const unsigned int nwords = CIM_IBQ_SIZE * 4;
9121
9122         if (qid > 5 || (n & 3))
9123                 return -EINVAL;
9124
9125         addr = qid * nwords;
9126         if (n > nwords)
9127                 n = nwords;
9128
9129         /* It might take 3-10ms before the IBQ debug read access is allowed.
9130          * Wait for 1 Sec with a delay of 1 usec.
9131          */
9132         attempts = 1000000;
9133
9134         for (i = 0; i < n; i++, addr++) {
9135                 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
9136                              IBQDBGEN_F);
9137                 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
9138                                       attempts, 1);
9139                 if (err)
9140                         return err;
9141                 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
9142         }
9143         t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
9144         return i;
9145 }
9146
9147 /**
9148  *      t4_read_cim_obq - read the contents of a CIM outbound queue
9149  *      @adap: the adapter
9150  *      @qid: the queue index
9151  *      @data: where to store the queue contents
9152  *      @n: capacity of @data in 32-bit words
9153  *
9154  *      Reads the contents of the selected CIM queue starting at address 0 up
9155  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9156  *      error and the number of 32-bit words actually read on success.
9157  */
9158 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9159 {
9160         int i, err;
9161         unsigned int addr, v, nwords;
9162         int cim_num_obq = is_t4(adap->params.chip) ?
9163                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9164
9165         if ((qid > (cim_num_obq - 1)) || (n & 3))
9166                 return -EINVAL;
9167
9168         t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9169                      QUENUMSELECT_V(qid));
9170         v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9171
9172         addr = CIMQBASE_G(v) * 64;    /* muliple of 256 -> muliple of 4 */
9173         nwords = CIMQSIZE_G(v) * 64;  /* same */
9174         if (n > nwords)
9175                 n = nwords;
9176
9177         for (i = 0; i < n; i++, addr++) {
9178                 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
9179                              OBQDBGEN_F);
9180                 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
9181                                       2, 1);
9182                 if (err)
9183                         return err;
9184                 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9185         }
9186         t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
9187         return i;
9188 }
9189
9190 /**
9191  *      t4_cim_read - read a block from CIM internal address space
9192  *      @adap: the adapter
9193  *      @addr: the start address within the CIM address space
9194  *      @n: number of words to read
9195  *      @valp: where to store the result
9196  *
9197  *      Reads a block of 4-byte words from the CIM intenal address space.
9198  */
9199 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9200                 unsigned int *valp)
9201 {
9202         int ret = 0;
9203
9204         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9205                 return -EBUSY;
9206
9207         for ( ; !ret && n--; addr += 4) {
9208                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
9209                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9210                                       0, 5, 2);
9211                 if (!ret)
9212                         *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9213         }
9214         return ret;
9215 }
9216
9217 /**
9218  *      t4_cim_write - write a block into CIM internal address space
9219  *      @adap: the adapter
9220  *      @addr: the start address within the CIM address space
9221  *      @n: number of words to write
9222  *      @valp: set of values to write
9223  *
9224  *      Writes a block of 4-byte words into the CIM intenal address space.
9225  */
9226 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9227                  const unsigned int *valp)
9228 {
9229         int ret = 0;
9230
9231         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9232                 return -EBUSY;
9233
9234         for ( ; !ret && n--; addr += 4) {
9235                 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
9236                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
9237                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9238                                       0, 5, 2);
9239         }
9240         return ret;
9241 }
9242
9243 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9244                          unsigned int val)
9245 {
9246         return t4_cim_write(adap, addr, 1, &val);
9247 }
9248
9249 /**
9250  *      t4_cim_read_la - read CIM LA capture buffer
9251  *      @adap: the adapter
9252  *      @la_buf: where to store the LA data
9253  *      @wrptr: the HW write pointer within the capture buffer
9254  *
9255  *      Reads the contents of the CIM LA buffer with the most recent entry at
9256  *      the end of the returned data and with the entry at @wrptr first.
9257  *      We try to leave the LA in the running state we find it in.
9258  */
9259 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9260 {
9261         int i, ret;
9262         unsigned int cfg, val, idx;
9263
9264         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9265         if (ret)
9266                 return ret;
9267
9268         if (cfg & UPDBGLAEN_F) {        /* LA is running, freeze it */
9269                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9270                 if (ret)
9271                         return ret;
9272         }
9273
9274         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9275         if (ret)
9276                 goto restart;
9277
9278         idx = UPDBGLAWRPTR_G(val);
9279         if (wrptr)
9280                 *wrptr = idx;
9281
9282         for (i = 0; i < adap->params.cim_la_size; i++) {
9283                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9284                                     UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9285                 if (ret)
9286                         break;
9287                 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9288                 if (ret)
9289                         break;
9290                 if (val & UPDBGLARDEN_F) {
9291                         ret = -ETIMEDOUT;
9292                         break;
9293                 }
9294                 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9295                 if (ret)
9296                         break;
9297
9298                 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9299                  * identify the 32-bit portion of the full 312-bit data
9300                  */
9301                 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9302                         idx = (idx & 0xff0) + 0x10;
9303                 else
9304                         idx++;
9305                 /* address can't exceed 0xfff */
9306                 idx &= UPDBGLARDPTR_M;
9307         }
9308 restart:
9309         if (cfg & UPDBGLAEN_F) {
9310                 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9311                                       cfg & ~UPDBGLARDEN_F);
9312                 if (!ret)
9313                         ret = r;
9314         }
9315         return ret;
9316 }
9317
9318 /**
9319  *      t4_tp_read_la - read TP LA capture buffer
9320  *      @adap: the adapter
9321  *      @la_buf: where to store the LA data
9322  *      @wrptr: the HW write pointer within the capture buffer
9323  *
9324  *      Reads the contents of the TP LA buffer with the most recent entry at
9325  *      the end of the returned data and with the entry at @wrptr first.
9326  *      We leave the LA in the running state we find it in.
9327  */
9328 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
9329 {
9330         bool last_incomplete;
9331         unsigned int i, cfg, val, idx;
9332
9333         cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
9334         if (cfg & DBGLAENABLE_F)                        /* freeze LA */
9335                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9336                              adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
9337
9338         val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
9339         idx = DBGLAWPTR_G(val);
9340         last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
9341         if (last_incomplete)
9342                 idx = (idx + 1) & DBGLARPTR_M;
9343         if (wrptr)
9344                 *wrptr = idx;
9345
9346         val &= 0xffff;
9347         val &= ~DBGLARPTR_V(DBGLARPTR_M);
9348         val |= adap->params.tp.la_mask;
9349
9350         for (i = 0; i < TPLA_SIZE; i++) {
9351                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
9352                 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
9353                 idx = (idx + 1) & DBGLARPTR_M;
9354         }
9355
9356         /* Wipe out last entry if it isn't valid */
9357         if (last_incomplete)
9358                 la_buf[TPLA_SIZE - 1] = ~0ULL;
9359
9360         if (cfg & DBGLAENABLE_F)                    /* restore running state */
9361                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9362                              cfg | adap->params.tp.la_mask);
9363 }
9364
9365 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
9366  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
9367  * state for more than the Warning Threshold then we'll issue a warning about
9368  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
9369  * appears to be hung every Warning Repeat second till the situation clears.
9370  * If the situation clears, we'll note that as well.
9371  */
9372 #define SGE_IDMA_WARN_THRESH 1
9373 #define SGE_IDMA_WARN_REPEAT 300
9374
9375 /**
9376  *      t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
9377  *      @adapter: the adapter
9378  *      @idma: the adapter IDMA Monitor state
9379  *
9380  *      Initialize the state of an SGE Ingress DMA Monitor.
9381  */
9382 void t4_idma_monitor_init(struct adapter *adapter,
9383                           struct sge_idma_monitor_state *idma)
9384 {
9385         /* Initialize the state variables for detecting an SGE Ingress DMA
9386          * hang.  The SGE has internal counters which count up on each clock
9387          * tick whenever the SGE finds its Ingress DMA State Engines in the
9388          * same state they were on the previous clock tick.  The clock used is
9389          * the Core Clock so we have a limit on the maximum "time" they can
9390          * record; typically a very small number of seconds.  For instance,
9391          * with a 600MHz Core Clock, we can only count up to a bit more than
9392          * 7s.  So we'll synthesize a larger counter in order to not run the
9393          * risk of having the "timers" overflow and give us the flexibility to
9394          * maintain a Hung SGE State Machine of our own which operates across
9395          * a longer time frame.
9396          */
9397         idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
9398         idma->idma_stalled[0] = 0;
9399         idma->idma_stalled[1] = 0;
9400 }
9401
9402 /**
9403  *      t4_idma_monitor - monitor SGE Ingress DMA state
9404  *      @adapter: the adapter
9405  *      @idma: the adapter IDMA Monitor state
9406  *      @hz: number of ticks/second
9407  *      @ticks: number of ticks since the last IDMA Monitor call
9408  */
9409 void t4_idma_monitor(struct adapter *adapter,
9410                      struct sge_idma_monitor_state *idma,
9411                      int hz, int ticks)
9412 {
9413         int i, idma_same_state_cnt[2];
9414
9415          /* Read the SGE Debug Ingress DMA Same State Count registers.  These
9416           * are counters inside the SGE which count up on each clock when the
9417           * SGE finds its Ingress DMA State Engines in the same states they
9418           * were in the previous clock.  The counters will peg out at
9419           * 0xffffffff without wrapping around so once they pass the 1s
9420           * threshold they'll stay above that till the IDMA state changes.
9421           */
9422         t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
9423         idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
9424         idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9425
9426         for (i = 0; i < 2; i++) {
9427                 u32 debug0, debug11;
9428
9429                 /* If the Ingress DMA Same State Counter ("timer") is less
9430                  * than 1s, then we can reset our synthesized Stall Timer and
9431                  * continue.  If we have previously emitted warnings about a
9432                  * potential stalled Ingress Queue, issue a note indicating
9433                  * that the Ingress Queue has resumed forward progress.
9434                  */
9435                 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
9436                         if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
9437                                 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
9438                                          "resumed after %d seconds\n",
9439                                          i, idma->idma_qid[i],
9440                                          idma->idma_stalled[i] / hz);
9441                         idma->idma_stalled[i] = 0;
9442                         continue;
9443                 }
9444
9445                 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
9446                  * domain.  The first time we get here it'll be because we
9447                  * passed the 1s Threshold; each additional time it'll be
9448                  * because the RX Timer Callback is being fired on its regular
9449                  * schedule.
9450                  *
9451                  * If the stall is below our Potential Hung Ingress Queue
9452                  * Warning Threshold, continue.
9453                  */
9454                 if (idma->idma_stalled[i] == 0) {
9455                         idma->idma_stalled[i] = hz;
9456                         idma->idma_warn[i] = 0;
9457                 } else {
9458                         idma->idma_stalled[i] += ticks;
9459                         idma->idma_warn[i] -= ticks;
9460                 }
9461
9462                 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
9463                         continue;
9464
9465                 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
9466                  */
9467                 if (idma->idma_warn[i] > 0)
9468                         continue;
9469                 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
9470
9471                 /* Read and save the SGE IDMA State and Queue ID information.
9472                  * We do this every time in case it changes across time ...
9473                  * can't be too careful ...
9474                  */
9475                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
9476                 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9477                 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
9478
9479                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
9480                 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9481                 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
9482
9483                 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
9484                          "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
9485                          i, idma->idma_qid[i], idma->idma_state[i],
9486                          idma->idma_stalled[i] / hz,
9487                          debug0, debug11);
9488                 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
9489         }
9490 }
9491
9492 /**
9493  *      t4_load_cfg - download config file
9494  *      @adap: the adapter
9495  *      @cfg_data: the cfg text file to write
9496  *      @size: text file size
9497  *
9498  *      Write the supplied config text file to the card's serial flash.
9499  */
9500 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
9501 {
9502         int ret, i, n, cfg_addr;
9503         unsigned int addr;
9504         unsigned int flash_cfg_start_sec;
9505         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
9506
9507         cfg_addr = t4_flash_cfg_addr(adap);
9508         if (cfg_addr < 0)
9509                 return cfg_addr;
9510
9511         addr = cfg_addr;
9512         flash_cfg_start_sec = addr / SF_SEC_SIZE;
9513
9514         if (size > FLASH_CFG_MAX_SIZE) {
9515                 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
9516                         FLASH_CFG_MAX_SIZE);
9517                 return -EFBIG;
9518         }
9519
9520         i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,    /* # of sectors spanned */
9521                          sf_sec_size);
9522         ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
9523                                      flash_cfg_start_sec + i - 1);
9524         /* If size == 0 then we're simply erasing the FLASH sectors associated
9525          * with the on-adapter Firmware Configuration File.
9526          */
9527         if (ret || size == 0)
9528                 goto out;
9529
9530         /* this will write to the flash up to SF_PAGE_SIZE at a time */
9531         for (i = 0; i < size; i += SF_PAGE_SIZE) {
9532                 if ((size - i) <  SF_PAGE_SIZE)
9533                         n = size - i;
9534                 else
9535                         n = SF_PAGE_SIZE;
9536                 ret = t4_write_flash(adap, addr, n, cfg_data);
9537                 if (ret)
9538                         goto out;
9539
9540                 addr += SF_PAGE_SIZE;
9541                 cfg_data += SF_PAGE_SIZE;
9542         }
9543
9544 out:
9545         if (ret)
9546                 dev_err(adap->pdev_dev, "config file %s failed %d\n",
9547                         (size == 0 ? "clear" : "download"), ret);
9548         return ret;
9549 }
9550
9551 /**
9552  *      t4_set_vf_mac - Set MAC address for the specified VF
9553  *      @adapter: The adapter
9554  *      @vf: one of the VFs instantiated by the specified PF
9555  *      @naddr: the number of MAC addresses
9556  *      @addr: the MAC address(es) to be set to the specified VF
9557  */
9558 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
9559                       unsigned int naddr, u8 *addr)
9560 {
9561         struct fw_acl_mac_cmd cmd;
9562
9563         memset(&cmd, 0, sizeof(cmd));
9564         cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
9565                                     FW_CMD_REQUEST_F |
9566                                     FW_CMD_WRITE_F |
9567                                     FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
9568                                     FW_ACL_MAC_CMD_VFN_V(vf));
9569
9570         /* Note: Do not enable the ACL */
9571         cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
9572         cmd.nmac = naddr;
9573
9574         switch (adapter->pf) {
9575         case 3:
9576                 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
9577                 break;
9578         case 2:
9579                 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
9580                 break;
9581         case 1:
9582                 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
9583                 break;
9584         case 0:
9585                 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
9586                 break;
9587         }
9588
9589         return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
9590 }
9591
9592 /**
9593  * t4_read_pace_tbl - read the pace table
9594  * @adap: the adapter
9595  * @pace_vals: holds the returned values
9596  *
9597  * Returns the values of TP's pace table in microseconds.
9598  */
9599 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
9600 {
9601         unsigned int i, v;
9602
9603         for (i = 0; i < NTX_SCHED; i++) {
9604                 t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
9605                 v = t4_read_reg(adap, TP_PACE_TABLE_A);
9606                 pace_vals[i] = dack_ticks_to_usec(adap, v);
9607         }
9608 }
9609
9610 /**
9611  * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
9612  * @adap: the adapter
9613  * @sched: the scheduler index
9614  * @kbps: the byte rate in Kbps
9615  * @ipg: the interpacket delay in tenths of nanoseconds
9616  * @sleep_ok: if true we may sleep while awaiting command completion
9617  *
9618  * Return the current configuration of a HW Tx scheduler.
9619  */
9620 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
9621                      unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
9622 {
9623         unsigned int v, addr, bpt, cpt;
9624
9625         if (kbps) {
9626                 addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2;
9627                 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
9628                 if (sched & 1)
9629                         v >>= 16;
9630                 bpt = (v >> 8) & 0xff;
9631                 cpt = v & 0xff;
9632                 if (!cpt) {
9633                         *kbps = 0;      /* scheduler disabled */
9634                 } else {
9635                         v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
9636                         *kbps = (v * bpt) / 125;
9637                 }
9638         }
9639         if (ipg) {
9640                 addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2;
9641                 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
9642                 if (sched & 1)
9643                         v >>= 16;
9644                 v &= 0xffff;
9645                 *ipg = (10000 * v) / core_ticks_per_usec(adap);
9646         }
9647 }
9648
9649 /* t4_sge_ctxt_rd - read an SGE context through FW
9650  * @adap: the adapter
9651  * @mbox: mailbox to use for the FW command
9652  * @cid: the context id
9653  * @ctype: the context type
9654  * @data: where to store the context data
9655  *
9656  * Issues a FW command through the given mailbox to read an SGE context.
9657  */
9658 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
9659                    enum ctxt_type ctype, u32 *data)
9660 {
9661         struct fw_ldst_cmd c;
9662         int ret;
9663
9664         if (ctype == CTXT_FLM)
9665                 ret = FW_LDST_ADDRSPC_SGE_FLMC;
9666         else
9667                 ret = FW_LDST_ADDRSPC_SGE_CONMC;
9668
9669         memset(&c, 0, sizeof(c));
9670         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
9671                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
9672                                         FW_LDST_CMD_ADDRSPACE_V(ret));
9673         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
9674         c.u.idctxt.physid = cpu_to_be32(cid);
9675
9676         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
9677         if (ret == 0) {
9678                 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
9679                 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
9680                 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
9681                 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
9682                 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
9683                 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
9684         }
9685         return ret;
9686 }
9687
9688 /**
9689  * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
9690  * @adap: the adapter
9691  * @cid: the context id
9692  * @ctype: the context type
9693  * @data: where to store the context data
9694  *
9695  * Reads an SGE context directly, bypassing FW.  This is only for
9696  * debugging when FW is unavailable.
9697  */
9698 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
9699                       enum ctxt_type ctype, u32 *data)
9700 {
9701         int i, ret;
9702
9703         t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
9704         ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
9705         if (!ret)
9706                 for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
9707                         *data++ = t4_read_reg(adap, i);
9708         return ret;
9709 }
9710
9711 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
9712                     int rateunit, int ratemode, int channel, int class,
9713                     int minrate, int maxrate, int weight, int pktsize)
9714 {
9715         struct fw_sched_cmd cmd;
9716
9717         memset(&cmd, 0, sizeof(cmd));
9718         cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
9719                                       FW_CMD_REQUEST_F |
9720                                       FW_CMD_WRITE_F);
9721         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9722
9723         cmd.u.params.sc = FW_SCHED_SC_PARAMS;
9724         cmd.u.params.type = type;
9725         cmd.u.params.level = level;
9726         cmd.u.params.mode = mode;
9727         cmd.u.params.ch = channel;
9728         cmd.u.params.cl = class;
9729         cmd.u.params.unit = rateunit;
9730         cmd.u.params.rate = ratemode;
9731         cmd.u.params.min = cpu_to_be32(minrate);
9732         cmd.u.params.max = cpu_to_be32(maxrate);
9733         cmd.u.params.weight = cpu_to_be16(weight);
9734         cmd.u.params.pktsize = cpu_to_be16(pktsize);
9735
9736         return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
9737                                NULL, 1);
9738 }