97683c1c5b6958c775600e72d7750685eab46ab1
[sfrench/cifs-2.6.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_main.c
1 /*
2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
3  *
4  * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  */
34
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
44 #include <linux/if.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <asm/uaccess.h>
65
66 #include "cxgb4.h"
67 #include "t4_regs.h"
68 #include "t4_msg.h"
69 #include "t4fw_api.h"
70 #include "cxgb4_dcb.h"
71 #include "l2t.h"
72
73 #include <../drivers/net/bonding/bonding.h>
74
75 #ifdef DRV_VERSION
76 #undef DRV_VERSION
77 #endif
78 #define DRV_VERSION "2.0.0-ko"
79 #define DRV_DESC "Chelsio T4/T5 Network Driver"
80
81 /*
82  * Max interrupt hold-off timer value in us.  Queues fall back to this value
83  * under extreme memory pressure so it's largish to give the system time to
84  * recover.
85  */
86 #define MAX_SGE_TIMERVAL 200U
87
88 enum {
89         /*
90          * Physical Function provisioning constants.
91          */
92         PFRES_NVI = 4,                  /* # of Virtual Interfaces */
93         PFRES_NETHCTRL = 128,           /* # of EQs used for ETH or CTRL Qs */
94         PFRES_NIQFLINT = 128,           /* # of ingress Qs/w Free List(s)/intr
95                                          */
96         PFRES_NEQ = 256,                /* # of egress queues */
97         PFRES_NIQ = 0,                  /* # of ingress queues */
98         PFRES_TC = 0,                   /* PCI-E traffic class */
99         PFRES_NEXACTF = 128,            /* # of exact MPS filters */
100
101         PFRES_R_CAPS = FW_CMD_CAP_PF,
102         PFRES_WX_CAPS = FW_CMD_CAP_PF,
103
104 #ifdef CONFIG_PCI_IOV
105         /*
106          * Virtual Function provisioning constants.  We need two extra Ingress
107          * Queues with Interrupt capability to serve as the VF's Firmware
108          * Event Queue and Forwarded Interrupt Queue (when using MSI mode) --
109          * neither will have Free Lists associated with them).  For each
110          * Ethernet/Control Egress Queue and for each Free List, we need an
111          * Egress Context.
112          */
113         VFRES_NPORTS = 1,               /* # of "ports" per VF */
114         VFRES_NQSETS = 2,               /* # of "Queue Sets" per VF */
115
116         VFRES_NVI = VFRES_NPORTS,       /* # of Virtual Interfaces */
117         VFRES_NETHCTRL = VFRES_NQSETS,  /* # of EQs used for ETH or CTRL Qs */
118         VFRES_NIQFLINT = VFRES_NQSETS+2,/* # of ingress Qs/w Free List(s)/intr */
119         VFRES_NEQ = VFRES_NQSETS*2,     /* # of egress queues */
120         VFRES_NIQ = 0,                  /* # of non-fl/int ingress queues */
121         VFRES_TC = 0,                   /* PCI-E traffic class */
122         VFRES_NEXACTF = 16,             /* # of exact MPS filters */
123
124         VFRES_R_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF|FW_CMD_CAP_PORT,
125         VFRES_WX_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF,
126 #endif
127 };
128
129 /*
130  * Provide a Port Access Rights Mask for the specified PF/VF.  This is very
131  * static and likely not to be useful in the long run.  We really need to
132  * implement some form of persistent configuration which the firmware
133  * controls.
134  */
135 static unsigned int pfvfres_pmask(struct adapter *adapter,
136                                   unsigned int pf, unsigned int vf)
137 {
138         unsigned int portn, portvec;
139
140         /*
141          * Give PF's access to all of the ports.
142          */
143         if (vf == 0)
144                 return FW_PFVF_CMD_PMASK_MASK;
145
146         /*
147          * For VFs, we'll assign them access to the ports based purely on the
148          * PF.  We assign active ports in order, wrapping around if there are
149          * fewer active ports than PFs: e.g. active port[pf % nports].
150          * Unfortunately the adapter's port_info structs haven't been
151          * initialized yet so we have to compute this.
152          */
153         if (adapter->params.nports == 0)
154                 return 0;
155
156         portn = pf % adapter->params.nports;
157         portvec = adapter->params.portvec;
158         for (;;) {
159                 /*
160                  * Isolate the lowest set bit in the port vector.  If we're at
161                  * the port number that we want, return that as the pmask.
162                  * otherwise mask that bit out of the port vector and
163                  * decrement our port number ...
164                  */
165                 unsigned int pmask = portvec ^ (portvec & (portvec-1));
166                 if (portn == 0)
167                         return pmask;
168                 portn--;
169                 portvec &= ~pmask;
170         }
171         /*NOTREACHED*/
172 }
173
174 enum {
175         MAX_TXQ_ENTRIES      = 16384,
176         MAX_CTRL_TXQ_ENTRIES = 1024,
177         MAX_RSPQ_ENTRIES     = 16384,
178         MAX_RX_BUFFERS       = 16384,
179         MIN_TXQ_ENTRIES      = 32,
180         MIN_CTRL_TXQ_ENTRIES = 32,
181         MIN_RSPQ_ENTRIES     = 128,
182         MIN_FL_ENTRIES       = 16
183 };
184
185 /* Host shadow copy of ingress filter entry.  This is in host native format
186  * and doesn't match the ordering or bit order, etc. of the hardware of the
187  * firmware command.  The use of bit-field structure elements is purely to
188  * remind ourselves of the field size limitations and save memory in the case
189  * where the filter table is large.
190  */
191 struct filter_entry {
192         /* Administrative fields for filter.
193          */
194         u32 valid:1;            /* filter allocated and valid */
195         u32 locked:1;           /* filter is administratively locked */
196
197         u32 pending:1;          /* filter action is pending firmware reply */
198         u32 smtidx:8;           /* Source MAC Table index for smac */
199         struct l2t_entry *l2t;  /* Layer Two Table entry for dmac */
200
201         /* The filter itself.  Most of this is a straight copy of information
202          * provided by the extended ioctl().  Some fields are translated to
203          * internal forms -- for instance the Ingress Queue ID passed in from
204          * the ioctl() is translated into the Absolute Ingress Queue ID.
205          */
206         struct ch_filter_specification fs;
207 };
208
209 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
210                          NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
211                          NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
212
213 #define CH_DEVICE(devid, data) { PCI_VDEVICE(CHELSIO, devid), (data) }
214
215 static const struct pci_device_id cxgb4_pci_tbl[] = {
216         CH_DEVICE(0xa000, 0),  /* PE10K */
217         CH_DEVICE(0x4001, -1),
218         CH_DEVICE(0x4002, -1),
219         CH_DEVICE(0x4003, -1),
220         CH_DEVICE(0x4004, -1),
221         CH_DEVICE(0x4005, -1),
222         CH_DEVICE(0x4006, -1),
223         CH_DEVICE(0x4007, -1),
224         CH_DEVICE(0x4008, -1),
225         CH_DEVICE(0x4009, -1),
226         CH_DEVICE(0x400a, -1),
227         CH_DEVICE(0x400d, -1),
228         CH_DEVICE(0x400e, -1),
229         CH_DEVICE(0x4080, -1),
230         CH_DEVICE(0x4081, -1),
231         CH_DEVICE(0x4082, -1),
232         CH_DEVICE(0x4083, -1),
233         CH_DEVICE(0x4084, -1),
234         CH_DEVICE(0x4085, -1),
235         CH_DEVICE(0x4086, -1),
236         CH_DEVICE(0x4087, -1),
237         CH_DEVICE(0x4088, -1),
238         CH_DEVICE(0x4401, 4),
239         CH_DEVICE(0x4402, 4),
240         CH_DEVICE(0x4403, 4),
241         CH_DEVICE(0x4404, 4),
242         CH_DEVICE(0x4405, 4),
243         CH_DEVICE(0x4406, 4),
244         CH_DEVICE(0x4407, 4),
245         CH_DEVICE(0x4408, 4),
246         CH_DEVICE(0x4409, 4),
247         CH_DEVICE(0x440a, 4),
248         CH_DEVICE(0x440d, 4),
249         CH_DEVICE(0x440e, 4),
250         CH_DEVICE(0x4480, 4),
251         CH_DEVICE(0x4481, 4),
252         CH_DEVICE(0x4482, 4),
253         CH_DEVICE(0x4483, 4),
254         CH_DEVICE(0x4484, 4),
255         CH_DEVICE(0x4485, 4),
256         CH_DEVICE(0x4486, 4),
257         CH_DEVICE(0x4487, 4),
258         CH_DEVICE(0x4488, 4),
259         CH_DEVICE(0x5001, 4),
260         CH_DEVICE(0x5002, 4),
261         CH_DEVICE(0x5003, 4),
262         CH_DEVICE(0x5004, 4),
263         CH_DEVICE(0x5005, 4),
264         CH_DEVICE(0x5006, 4),
265         CH_DEVICE(0x5007, 4),
266         CH_DEVICE(0x5008, 4),
267         CH_DEVICE(0x5009, 4),
268         CH_DEVICE(0x500A, 4),
269         CH_DEVICE(0x500B, 4),
270         CH_DEVICE(0x500C, 4),
271         CH_DEVICE(0x500D, 4),
272         CH_DEVICE(0x500E, 4),
273         CH_DEVICE(0x500F, 4),
274         CH_DEVICE(0x5010, 4),
275         CH_DEVICE(0x5011, 4),
276         CH_DEVICE(0x5012, 4),
277         CH_DEVICE(0x5013, 4),
278         CH_DEVICE(0x5014, 4),
279         CH_DEVICE(0x5015, 4),
280         CH_DEVICE(0x5080, 4),
281         CH_DEVICE(0x5081, 4),
282         CH_DEVICE(0x5082, 4),
283         CH_DEVICE(0x5083, 4),
284         CH_DEVICE(0x5084, 4),
285         CH_DEVICE(0x5085, 4),
286         CH_DEVICE(0x5086, 4),
287         CH_DEVICE(0x5087, 4),
288         CH_DEVICE(0x5088, 4),
289         CH_DEVICE(0x5401, 4),
290         CH_DEVICE(0x5402, 4),
291         CH_DEVICE(0x5403, 4),
292         CH_DEVICE(0x5404, 4),
293         CH_DEVICE(0x5405, 4),
294         CH_DEVICE(0x5406, 4),
295         CH_DEVICE(0x5407, 4),
296         CH_DEVICE(0x5408, 4),
297         CH_DEVICE(0x5409, 4),
298         CH_DEVICE(0x540A, 4),
299         CH_DEVICE(0x540B, 4),
300         CH_DEVICE(0x540C, 4),
301         CH_DEVICE(0x540D, 4),
302         CH_DEVICE(0x540E, 4),
303         CH_DEVICE(0x540F, 4),
304         CH_DEVICE(0x5410, 4),
305         CH_DEVICE(0x5411, 4),
306         CH_DEVICE(0x5412, 4),
307         CH_DEVICE(0x5413, 4),
308         CH_DEVICE(0x5414, 4),
309         CH_DEVICE(0x5415, 4),
310         CH_DEVICE(0x5480, 4),
311         CH_DEVICE(0x5481, 4),
312         CH_DEVICE(0x5482, 4),
313         CH_DEVICE(0x5483, 4),
314         CH_DEVICE(0x5484, 4),
315         CH_DEVICE(0x5485, 4),
316         CH_DEVICE(0x5486, 4),
317         CH_DEVICE(0x5487, 4),
318         CH_DEVICE(0x5488, 4),
319         { 0, }
320 };
321
322 #define FW4_FNAME "cxgb4/t4fw.bin"
323 #define FW5_FNAME "cxgb4/t5fw.bin"
324 #define FW4_CFNAME "cxgb4/t4-config.txt"
325 #define FW5_CFNAME "cxgb4/t5-config.txt"
326
327 MODULE_DESCRIPTION(DRV_DESC);
328 MODULE_AUTHOR("Chelsio Communications");
329 MODULE_LICENSE("Dual BSD/GPL");
330 MODULE_VERSION(DRV_VERSION);
331 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
332 MODULE_FIRMWARE(FW4_FNAME);
333 MODULE_FIRMWARE(FW5_FNAME);
334
335 /*
336  * Normally we're willing to become the firmware's Master PF but will be happy
337  * if another PF has already become the Master and initialized the adapter.
338  * Setting "force_init" will cause this driver to forcibly establish itself as
339  * the Master PF and initialize the adapter.
340  */
341 static uint force_init;
342
343 module_param(force_init, uint, 0644);
344 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
345
346 /*
347  * Normally if the firmware we connect to has Configuration File support, we
348  * use that and only fall back to the old Driver-based initialization if the
349  * Configuration File fails for some reason.  If force_old_init is set, then
350  * we'll always use the old Driver-based initialization sequence.
351  */
352 static uint force_old_init;
353
354 module_param(force_old_init, uint, 0644);
355 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence");
356
357 static int dflt_msg_enable = DFLT_MSG_ENABLE;
358
359 module_param(dflt_msg_enable, int, 0644);
360 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
361
362 /*
363  * The driver uses the best interrupt scheme available on a platform in the
364  * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
365  * of these schemes the driver may consider as follows:
366  *
367  * msi = 2: choose from among all three options
368  * msi = 1: only consider MSI and INTx interrupts
369  * msi = 0: force INTx interrupts
370  */
371 static int msi = 2;
372
373 module_param(msi, int, 0644);
374 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
375
376 /*
377  * Queue interrupt hold-off timer values.  Queues default to the first of these
378  * upon creation.
379  */
380 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
381
382 module_param_array(intr_holdoff, uint, NULL, 0644);
383 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
384                  "0..4 in microseconds");
385
386 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
387
388 module_param_array(intr_cnt, uint, NULL, 0644);
389 MODULE_PARM_DESC(intr_cnt,
390                  "thresholds 1..3 for queue interrupt packet counters");
391
392 /*
393  * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
394  * offset by 2 bytes in order to have the IP headers line up on 4-byte
395  * boundaries.  This is a requirement for many architectures which will throw
396  * a machine check fault if an attempt is made to access one of the 4-byte IP
397  * header fields on a non-4-byte boundary.  And it's a major performance issue
398  * even on some architectures which allow it like some implementations of the
399  * x86 ISA.  However, some architectures don't mind this and for some very
400  * edge-case performance sensitive applications (like forwarding large volumes
401  * of small packets), setting this DMA offset to 0 will decrease the number of
402  * PCI-E Bus transfers enough to measurably affect performance.
403  */
404 static int rx_dma_offset = 2;
405
406 static bool vf_acls;
407
408 #ifdef CONFIG_PCI_IOV
409 module_param(vf_acls, bool, 0644);
410 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement");
411
412 /* Configure the number of PCI-E Virtual Function which are to be instantiated
413  * on SR-IOV Capable Physical Functions.
414  */
415 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
416
417 module_param_array(num_vf, uint, NULL, 0644);
418 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
419 #endif
420
421 /* TX Queue select used to determine what algorithm to use for selecting TX
422  * queue. Select between the kernel provided function (select_queue=0) or user
423  * cxgb_select_queue function (select_queue=1)
424  *
425  * Default: select_queue=0
426  */
427 static int select_queue;
428 module_param(select_queue, int, 0644);
429 MODULE_PARM_DESC(select_queue,
430                  "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
431
432 /*
433  * The filter TCAM has a fixed portion and a variable portion.  The fixed
434  * portion can match on source/destination IP IPv4/IPv6 addresses and TCP/UDP
435  * ports.  The variable portion is 36 bits which can include things like Exact
436  * Match MAC Index (9 bits), Ether Type (16 bits), IP Protocol (8 bits),
437  * [Inner] VLAN Tag (17 bits), etc. which, if all were somehow selected, would
438  * far exceed the 36-bit budget for this "compressed" header portion of the
439  * filter.  Thus, we have a scarce resource which must be carefully managed.
440  *
441  * By default we set this up to mostly match the set of filter matching
442  * capabilities of T3 but with accommodations for some of T4's more
443  * interesting features:
444  *
445  *   { IP Fragment (1), MPS Match Type (3), IP Protocol (8),
446  *     [Inner] VLAN (17), Port (3), FCoE (1) }
447  */
448 enum {
449         TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC,
450         TP_VLAN_PRI_MAP_FIRST = FCOE_SHIFT,
451         TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_SHIFT,
452 };
453
454 static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
455
456 module_param(tp_vlan_pri_map, uint, 0644);
457 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration");
458
459 static struct dentry *cxgb4_debugfs_root;
460
461 static LIST_HEAD(adapter_list);
462 static DEFINE_MUTEX(uld_mutex);
463 /* Adapter list to be accessed from atomic context */
464 static LIST_HEAD(adap_rcu_list);
465 static DEFINE_SPINLOCK(adap_rcu_lock);
466 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
467 static const char *uld_str[] = { "RDMA", "iSCSI" };
468
469 static void link_report(struct net_device *dev)
470 {
471         if (!netif_carrier_ok(dev))
472                 netdev_info(dev, "link down\n");
473         else {
474                 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
475
476                 const char *s = "10Mbps";
477                 const struct port_info *p = netdev_priv(dev);
478
479                 switch (p->link_cfg.speed) {
480                 case 10000:
481                         s = "10Gbps";
482                         break;
483                 case 1000:
484                         s = "1000Mbps";
485                         break;
486                 case 100:
487                         s = "100Mbps";
488                         break;
489                 case 40000:
490                         s = "40Gbps";
491                         break;
492                 }
493
494                 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
495                             fc[p->link_cfg.fc]);
496         }
497 }
498
499 #ifdef CONFIG_CHELSIO_T4_DCB
500 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
501 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
502 {
503         struct port_info *pi = netdev_priv(dev);
504         struct adapter *adap = pi->adapter;
505         struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
506         int i;
507
508         /* We use a simple mapping of Port TX Queue Index to DCB
509          * Priority when we're enabling DCB.
510          */
511         for (i = 0; i < pi->nqsets; i++, txq++) {
512                 u32 name, value;
513                 int err;
514
515                 name = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
516                         FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
517                         FW_PARAMS_PARAM_YZ(txq->q.cntxt_id));
518                 value = enable ? i : 0xffffffff;
519
520                 /* Since we can be called while atomic (from "interrupt
521                  * level") we need to issue the Set Parameters Commannd
522                  * without sleeping (timeout < 0).
523                  */
524                 err = t4_set_params_nosleep(adap, adap->mbox, adap->fn, 0, 1,
525                                             &name, &value);
526
527                 if (err)
528                         dev_err(adap->pdev_dev,
529                                 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
530                                 enable ? "set" : "unset", pi->port_id, i, -err);
531                 else
532                         txq->dcb_prio = value;
533         }
534 }
535 #endif /* CONFIG_CHELSIO_T4_DCB */
536
537 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
538 {
539         struct net_device *dev = adapter->port[port_id];
540
541         /* Skip changes from disabled ports. */
542         if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
543                 if (link_stat)
544                         netif_carrier_on(dev);
545                 else {
546 #ifdef CONFIG_CHELSIO_T4_DCB
547                         cxgb4_dcb_state_init(dev);
548                         dcb_tx_queue_prio_enable(dev, false);
549 #endif /* CONFIG_CHELSIO_T4_DCB */
550                         netif_carrier_off(dev);
551                 }
552
553                 link_report(dev);
554         }
555 }
556
557 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
558 {
559         static const char *mod_str[] = {
560                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
561         };
562
563         const struct net_device *dev = adap->port[port_id];
564         const struct port_info *pi = netdev_priv(dev);
565
566         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
567                 netdev_info(dev, "port module unplugged\n");
568         else if (pi->mod_type < ARRAY_SIZE(mod_str))
569                 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
570 }
571
572 /*
573  * Configure the exact and hash address filters to handle a port's multicast
574  * and secondary unicast MAC addresses.
575  */
576 static int set_addr_filters(const struct net_device *dev, bool sleep)
577 {
578         u64 mhash = 0;
579         u64 uhash = 0;
580         bool free = true;
581         u16 filt_idx[7];
582         const u8 *addr[7];
583         int ret, naddr = 0;
584         const struct netdev_hw_addr *ha;
585         int uc_cnt = netdev_uc_count(dev);
586         int mc_cnt = netdev_mc_count(dev);
587         const struct port_info *pi = netdev_priv(dev);
588         unsigned int mb = pi->adapter->fn;
589
590         /* first do the secondary unicast addresses */
591         netdev_for_each_uc_addr(ha, dev) {
592                 addr[naddr++] = ha->addr;
593                 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
594                         ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
595                                         naddr, addr, filt_idx, &uhash, sleep);
596                         if (ret < 0)
597                                 return ret;
598
599                         free = false;
600                         naddr = 0;
601                 }
602         }
603
604         /* next set up the multicast addresses */
605         netdev_for_each_mc_addr(ha, dev) {
606                 addr[naddr++] = ha->addr;
607                 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
608                         ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
609                                         naddr, addr, filt_idx, &mhash, sleep);
610                         if (ret < 0)
611                                 return ret;
612
613                         free = false;
614                         naddr = 0;
615                 }
616         }
617
618         return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
619                                 uhash | mhash, sleep);
620 }
621
622 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
623 module_param(dbfifo_int_thresh, int, 0644);
624 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
625
626 /*
627  * usecs to sleep while draining the dbfifo
628  */
629 static int dbfifo_drain_delay = 1000;
630 module_param(dbfifo_drain_delay, int, 0644);
631 MODULE_PARM_DESC(dbfifo_drain_delay,
632                  "usecs to sleep while draining the dbfifo");
633
634 /*
635  * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
636  * If @mtu is -1 it is left unchanged.
637  */
638 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
639 {
640         int ret;
641         struct port_info *pi = netdev_priv(dev);
642
643         ret = set_addr_filters(dev, sleep_ok);
644         if (ret == 0)
645                 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
646                                     (dev->flags & IFF_PROMISC) ? 1 : 0,
647                                     (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
648                                     sleep_ok);
649         return ret;
650 }
651
652 /**
653  *      link_start - enable a port
654  *      @dev: the port to enable
655  *
656  *      Performs the MAC and PHY actions needed to enable a port.
657  */
658 static int link_start(struct net_device *dev)
659 {
660         int ret;
661         struct port_info *pi = netdev_priv(dev);
662         unsigned int mb = pi->adapter->fn;
663
664         /*
665          * We do not set address filters and promiscuity here, the stack does
666          * that step explicitly.
667          */
668         ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
669                             !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
670         if (ret == 0) {
671                 ret = t4_change_mac(pi->adapter, mb, pi->viid,
672                                     pi->xact_addr_filt, dev->dev_addr, true,
673                                     true);
674                 if (ret >= 0) {
675                         pi->xact_addr_filt = ret;
676                         ret = 0;
677                 }
678         }
679         if (ret == 0)
680                 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
681                                     &pi->link_cfg);
682         if (ret == 0) {
683                 local_bh_disable();
684                 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
685                                           true, CXGB4_DCB_ENABLED);
686                 local_bh_enable();
687         }
688
689         return ret;
690 }
691
692 int cxgb4_dcb_enabled(const struct net_device *dev)
693 {
694 #ifdef CONFIG_CHELSIO_T4_DCB
695         struct port_info *pi = netdev_priv(dev);
696
697         if (!pi->dcb.enabled)
698                 return 0;
699
700         return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
701                 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
702 #else
703         return 0;
704 #endif
705 }
706 EXPORT_SYMBOL(cxgb4_dcb_enabled);
707
708 #ifdef CONFIG_CHELSIO_T4_DCB
709 /* Handle a Data Center Bridging update message from the firmware. */
710 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
711 {
712         int port = FW_PORT_CMD_PORTID_GET(ntohl(pcmd->op_to_portid));
713         struct net_device *dev = adap->port[port];
714         int old_dcb_enabled = cxgb4_dcb_enabled(dev);
715         int new_dcb_enabled;
716
717         cxgb4_dcb_handle_fw_update(adap, pcmd);
718         new_dcb_enabled = cxgb4_dcb_enabled(dev);
719
720         /* If the DCB has become enabled or disabled on the port then we're
721          * going to need to set up/tear down DCB Priority parameters for the
722          * TX Queues associated with the port.
723          */
724         if (new_dcb_enabled != old_dcb_enabled)
725                 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
726 }
727 #endif /* CONFIG_CHELSIO_T4_DCB */
728
729 /* Clear a filter and release any of its resources that we own.  This also
730  * clears the filter's "pending" status.
731  */
732 static void clear_filter(struct adapter *adap, struct filter_entry *f)
733 {
734         /* If the new or old filter have loopback rewriteing rules then we'll
735          * need to free any existing Layer Two Table (L2T) entries of the old
736          * filter rule.  The firmware will handle freeing up any Source MAC
737          * Table (SMT) entries used for rewriting Source MAC Addresses in
738          * loopback rules.
739          */
740         if (f->l2t)
741                 cxgb4_l2t_release(f->l2t);
742
743         /* The zeroing of the filter rule below clears the filter valid,
744          * pending, locked flags, l2t pointer, etc. so it's all we need for
745          * this operation.
746          */
747         memset(f, 0, sizeof(*f));
748 }
749
750 /* Handle a filter write/deletion reply.
751  */
752 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
753 {
754         unsigned int idx = GET_TID(rpl);
755         unsigned int nidx = idx - adap->tids.ftid_base;
756         unsigned int ret;
757         struct filter_entry *f;
758
759         if (idx >= adap->tids.ftid_base && nidx <
760            (adap->tids.nftids + adap->tids.nsftids)) {
761                 idx = nidx;
762                 ret = GET_TCB_COOKIE(rpl->cookie);
763                 f = &adap->tids.ftid_tab[idx];
764
765                 if (ret == FW_FILTER_WR_FLT_DELETED) {
766                         /* Clear the filter when we get confirmation from the
767                          * hardware that the filter has been deleted.
768                          */
769                         clear_filter(adap, f);
770                 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
771                         dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
772                                 idx);
773                         clear_filter(adap, f);
774                 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
775                         f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
776                         f->pending = 0;  /* asynchronous setup completed */
777                         f->valid = 1;
778                 } else {
779                         /* Something went wrong.  Issue a warning about the
780                          * problem and clear everything out.
781                          */
782                         dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
783                                 idx, ret);
784                         clear_filter(adap, f);
785                 }
786         }
787 }
788
789 /* Response queue handler for the FW event queue.
790  */
791 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
792                           const struct pkt_gl *gl)
793 {
794         u8 opcode = ((const struct rss_header *)rsp)->opcode;
795
796         rsp++;                                          /* skip RSS header */
797
798         /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
799          */
800         if (unlikely(opcode == CPL_FW4_MSG &&
801            ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
802                 rsp++;
803                 opcode = ((const struct rss_header *)rsp)->opcode;
804                 rsp++;
805                 if (opcode != CPL_SGE_EGR_UPDATE) {
806                         dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
807                                 , opcode);
808                         goto out;
809                 }
810         }
811
812         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
813                 const struct cpl_sge_egr_update *p = (void *)rsp;
814                 unsigned int qid = EGR_QID(ntohl(p->opcode_qid));
815                 struct sge_txq *txq;
816
817                 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
818                 txq->restarts++;
819                 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
820                         struct sge_eth_txq *eq;
821
822                         eq = container_of(txq, struct sge_eth_txq, q);
823                         netif_tx_wake_queue(eq->txq);
824                 } else {
825                         struct sge_ofld_txq *oq;
826
827                         oq = container_of(txq, struct sge_ofld_txq, q);
828                         tasklet_schedule(&oq->qresume_tsk);
829                 }
830         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
831                 const struct cpl_fw6_msg *p = (void *)rsp;
832
833 #ifdef CONFIG_CHELSIO_T4_DCB
834                 const struct fw_port_cmd *pcmd = (const void *)p->data;
835                 unsigned int cmd = FW_CMD_OP_GET(ntohl(pcmd->op_to_portid));
836                 unsigned int action =
837                         FW_PORT_CMD_ACTION_GET(ntohl(pcmd->action_to_len16));
838
839                 if (cmd == FW_PORT_CMD &&
840                     action == FW_PORT_ACTION_GET_PORT_INFO) {
841                         int port = FW_PORT_CMD_PORTID_GET(
842                                         be32_to_cpu(pcmd->op_to_portid));
843                         struct net_device *dev = q->adap->port[port];
844                         int state_input = ((pcmd->u.info.dcbxdis_pkd &
845                                             FW_PORT_CMD_DCBXDIS)
846                                            ? CXGB4_DCB_INPUT_FW_DISABLED
847                                            : CXGB4_DCB_INPUT_FW_ENABLED);
848
849                         cxgb4_dcb_state_fsm(dev, state_input);
850                 }
851
852                 if (cmd == FW_PORT_CMD &&
853                     action == FW_PORT_ACTION_L2_DCB_CFG)
854                         dcb_rpl(q->adap, pcmd);
855                 else
856 #endif
857                         if (p->type == 0)
858                                 t4_handle_fw_rpl(q->adap, p->data);
859         } else if (opcode == CPL_L2T_WRITE_RPL) {
860                 const struct cpl_l2t_write_rpl *p = (void *)rsp;
861
862                 do_l2t_write_rpl(q->adap, p);
863         } else if (opcode == CPL_SET_TCB_RPL) {
864                 const struct cpl_set_tcb_rpl *p = (void *)rsp;
865
866                 filter_rpl(q->adap, p);
867         } else
868                 dev_err(q->adap->pdev_dev,
869                         "unexpected CPL %#x on FW event queue\n", opcode);
870 out:
871         return 0;
872 }
873
874 /**
875  *      uldrx_handler - response queue handler for ULD queues
876  *      @q: the response queue that received the packet
877  *      @rsp: the response queue descriptor holding the offload message
878  *      @gl: the gather list of packet fragments
879  *
880  *      Deliver an ingress offload packet to a ULD.  All processing is done by
881  *      the ULD, we just maintain statistics.
882  */
883 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
884                          const struct pkt_gl *gl)
885 {
886         struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
887
888         /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
889          */
890         if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
891             ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
892                 rsp += 2;
893
894         if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
895                 rxq->stats.nomem++;
896                 return -1;
897         }
898         if (gl == NULL)
899                 rxq->stats.imm++;
900         else if (gl == CXGB4_MSG_AN)
901                 rxq->stats.an++;
902         else
903                 rxq->stats.pkts++;
904         return 0;
905 }
906
907 static void disable_msi(struct adapter *adapter)
908 {
909         if (adapter->flags & USING_MSIX) {
910                 pci_disable_msix(adapter->pdev);
911                 adapter->flags &= ~USING_MSIX;
912         } else if (adapter->flags & USING_MSI) {
913                 pci_disable_msi(adapter->pdev);
914                 adapter->flags &= ~USING_MSI;
915         }
916 }
917
918 /*
919  * Interrupt handler for non-data events used with MSI-X.
920  */
921 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
922 {
923         struct adapter *adap = cookie;
924
925         u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE));
926         if (v & PFSW) {
927                 adap->swintr = 1;
928                 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v);
929         }
930         t4_slow_intr_handler(adap);
931         return IRQ_HANDLED;
932 }
933
934 /*
935  * Name the MSI-X interrupts.
936  */
937 static void name_msix_vecs(struct adapter *adap)
938 {
939         int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
940
941         /* non-data interrupts */
942         snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
943
944         /* FW events */
945         snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
946                  adap->port[0]->name);
947
948         /* Ethernet queues */
949         for_each_port(adap, j) {
950                 struct net_device *d = adap->port[j];
951                 const struct port_info *pi = netdev_priv(d);
952
953                 for (i = 0; i < pi->nqsets; i++, msi_idx++)
954                         snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
955                                  d->name, i);
956         }
957
958         /* offload queues */
959         for_each_ofldrxq(&adap->sge, i)
960                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
961                          adap->port[0]->name, i);
962
963         for_each_rdmarxq(&adap->sge, i)
964                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
965                          adap->port[0]->name, i);
966
967         for_each_rdmaciq(&adap->sge, i)
968                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
969                          adap->port[0]->name, i);
970 }
971
972 static int request_msix_queue_irqs(struct adapter *adap)
973 {
974         struct sge *s = &adap->sge;
975         int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
976         int msi_index = 2;
977
978         err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
979                           adap->msix_info[1].desc, &s->fw_evtq);
980         if (err)
981                 return err;
982
983         for_each_ethrxq(s, ethqidx) {
984                 err = request_irq(adap->msix_info[msi_index].vec,
985                                   t4_sge_intr_msix, 0,
986                                   adap->msix_info[msi_index].desc,
987                                   &s->ethrxq[ethqidx].rspq);
988                 if (err)
989                         goto unwind;
990                 msi_index++;
991         }
992         for_each_ofldrxq(s, ofldqidx) {
993                 err = request_irq(adap->msix_info[msi_index].vec,
994                                   t4_sge_intr_msix, 0,
995                                   adap->msix_info[msi_index].desc,
996                                   &s->ofldrxq[ofldqidx].rspq);
997                 if (err)
998                         goto unwind;
999                 msi_index++;
1000         }
1001         for_each_rdmarxq(s, rdmaqidx) {
1002                 err = request_irq(adap->msix_info[msi_index].vec,
1003                                   t4_sge_intr_msix, 0,
1004                                   adap->msix_info[msi_index].desc,
1005                                   &s->rdmarxq[rdmaqidx].rspq);
1006                 if (err)
1007                         goto unwind;
1008                 msi_index++;
1009         }
1010         for_each_rdmaciq(s, rdmaciqqidx) {
1011                 err = request_irq(adap->msix_info[msi_index].vec,
1012                                   t4_sge_intr_msix, 0,
1013                                   adap->msix_info[msi_index].desc,
1014                                   &s->rdmaciq[rdmaciqqidx].rspq);
1015                 if (err)
1016                         goto unwind;
1017                 msi_index++;
1018         }
1019         return 0;
1020
1021 unwind:
1022         while (--rdmaciqqidx >= 0)
1023                 free_irq(adap->msix_info[--msi_index].vec,
1024                          &s->rdmaciq[rdmaciqqidx].rspq);
1025         while (--rdmaqidx >= 0)
1026                 free_irq(adap->msix_info[--msi_index].vec,
1027                          &s->rdmarxq[rdmaqidx].rspq);
1028         while (--ofldqidx >= 0)
1029                 free_irq(adap->msix_info[--msi_index].vec,
1030                          &s->ofldrxq[ofldqidx].rspq);
1031         while (--ethqidx >= 0)
1032                 free_irq(adap->msix_info[--msi_index].vec,
1033                          &s->ethrxq[ethqidx].rspq);
1034         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
1035         return err;
1036 }
1037
1038 static void free_msix_queue_irqs(struct adapter *adap)
1039 {
1040         int i, msi_index = 2;
1041         struct sge *s = &adap->sge;
1042
1043         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
1044         for_each_ethrxq(s, i)
1045                 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
1046         for_each_ofldrxq(s, i)
1047                 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
1048         for_each_rdmarxq(s, i)
1049                 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
1050         for_each_rdmaciq(s, i)
1051                 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
1052 }
1053
1054 /**
1055  *      write_rss - write the RSS table for a given port
1056  *      @pi: the port
1057  *      @queues: array of queue indices for RSS
1058  *
1059  *      Sets up the portion of the HW RSS table for the port's VI to distribute
1060  *      packets to the Rx queues in @queues.
1061  */
1062 static int write_rss(const struct port_info *pi, const u16 *queues)
1063 {
1064         u16 *rss;
1065         int i, err;
1066         const struct sge_eth_rxq *q = &pi->adapter->sge.ethrxq[pi->first_qset];
1067
1068         rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
1069         if (!rss)
1070                 return -ENOMEM;
1071
1072         /* map the queue indices to queue ids */
1073         for (i = 0; i < pi->rss_size; i++, queues++)
1074                 rss[i] = q[*queues].rspq.abs_id;
1075
1076         err = t4_config_rss_range(pi->adapter, pi->adapter->fn, pi->viid, 0,
1077                                   pi->rss_size, rss, pi->rss_size);
1078         kfree(rss);
1079         return err;
1080 }
1081
1082 /**
1083  *      setup_rss - configure RSS
1084  *      @adap: the adapter
1085  *
1086  *      Sets up RSS for each port.
1087  */
1088 static int setup_rss(struct adapter *adap)
1089 {
1090         int i, err;
1091
1092         for_each_port(adap, i) {
1093                 const struct port_info *pi = adap2pinfo(adap, i);
1094
1095                 err = write_rss(pi, pi->rss);
1096                 if (err)
1097                         return err;
1098         }
1099         return 0;
1100 }
1101
1102 /*
1103  * Return the channel of the ingress queue with the given qid.
1104  */
1105 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
1106 {
1107         qid -= p->ingr_start;
1108         return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
1109 }
1110
1111 /*
1112  * Wait until all NAPI handlers are descheduled.
1113  */
1114 static void quiesce_rx(struct adapter *adap)
1115 {
1116         int i;
1117
1118         for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1119                 struct sge_rspq *q = adap->sge.ingr_map[i];
1120
1121                 if (q && q->handler)
1122                         napi_disable(&q->napi);
1123         }
1124 }
1125
1126 /*
1127  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1128  */
1129 static void enable_rx(struct adapter *adap)
1130 {
1131         int i;
1132
1133         for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1134                 struct sge_rspq *q = adap->sge.ingr_map[i];
1135
1136                 if (!q)
1137                         continue;
1138                 if (q->handler)
1139                         napi_enable(&q->napi);
1140                 /* 0-increment GTS to start the timer and enable interrupts */
1141                 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
1142                              SEINTARM(q->intr_params) |
1143                              INGRESSQID(q->cntxt_id));
1144         }
1145 }
1146
1147 /**
1148  *      setup_sge_queues - configure SGE Tx/Rx/response queues
1149  *      @adap: the adapter
1150  *
1151  *      Determines how many sets of SGE queues to use and initializes them.
1152  *      We support multiple queue sets per port if we have MSI-X, otherwise
1153  *      just one queue set per port.
1154  */
1155 static int setup_sge_queues(struct adapter *adap)
1156 {
1157         int err, msi_idx, i, j;
1158         struct sge *s = &adap->sge;
1159
1160         bitmap_zero(s->starving_fl, MAX_EGRQ);
1161         bitmap_zero(s->txq_maperr, MAX_EGRQ);
1162
1163         if (adap->flags & USING_MSIX)
1164                 msi_idx = 1;         /* vector 0 is for non-queue interrupts */
1165         else {
1166                 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1167                                        NULL, NULL);
1168                 if (err)
1169                         return err;
1170                 msi_idx = -((int)s->intrq.abs_id + 1);
1171         }
1172
1173         err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1174                                msi_idx, NULL, fwevtq_handler);
1175         if (err) {
1176 freeout:        t4_free_sge_resources(adap);
1177                 return err;
1178         }
1179
1180         for_each_port(adap, i) {
1181                 struct net_device *dev = adap->port[i];
1182                 struct port_info *pi = netdev_priv(dev);
1183                 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1184                 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1185
1186                 for (j = 0; j < pi->nqsets; j++, q++) {
1187                         if (msi_idx > 0)
1188                                 msi_idx++;
1189                         err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1190                                                msi_idx, &q->fl,
1191                                                t4_ethrx_handler);
1192                         if (err)
1193                                 goto freeout;
1194                         q->rspq.idx = j;
1195                         memset(&q->stats, 0, sizeof(q->stats));
1196                 }
1197                 for (j = 0; j < pi->nqsets; j++, t++) {
1198                         err = t4_sge_alloc_eth_txq(adap, t, dev,
1199                                         netdev_get_tx_queue(dev, j),
1200                                         s->fw_evtq.cntxt_id);
1201                         if (err)
1202                                 goto freeout;
1203                 }
1204         }
1205
1206         j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1207         for_each_ofldrxq(s, i) {
1208                 struct sge_ofld_rxq *q = &s->ofldrxq[i];
1209                 struct net_device *dev = adap->port[i / j];
1210
1211                 if (msi_idx > 0)
1212                         msi_idx++;
1213                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, msi_idx,
1214                                        q->fl.size ? &q->fl : NULL,
1215                                        uldrx_handler);
1216                 if (err)
1217                         goto freeout;
1218                 memset(&q->stats, 0, sizeof(q->stats));
1219                 s->ofld_rxq[i] = q->rspq.abs_id;
1220                 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], dev,
1221                                             s->fw_evtq.cntxt_id);
1222                 if (err)
1223                         goto freeout;
1224         }
1225
1226         for_each_rdmarxq(s, i) {
1227                 struct sge_ofld_rxq *q = &s->rdmarxq[i];
1228
1229                 if (msi_idx > 0)
1230                         msi_idx++;
1231                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1232                                        msi_idx, q->fl.size ? &q->fl : NULL,
1233                                        uldrx_handler);
1234                 if (err)
1235                         goto freeout;
1236                 memset(&q->stats, 0, sizeof(q->stats));
1237                 s->rdma_rxq[i] = q->rspq.abs_id;
1238         }
1239
1240         for_each_rdmaciq(s, i) {
1241                 struct sge_ofld_rxq *q = &s->rdmaciq[i];
1242
1243                 if (msi_idx > 0)
1244                         msi_idx++;
1245                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1246                                        msi_idx, q->fl.size ? &q->fl : NULL,
1247                                        uldrx_handler);
1248                 if (err)
1249                         goto freeout;
1250                 memset(&q->stats, 0, sizeof(q->stats));
1251                 s->rdma_ciq[i] = q->rspq.abs_id;
1252         }
1253
1254         for_each_port(adap, i) {
1255                 /*
1256                  * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1257                  * have RDMA queues, and that's the right value.
1258                  */
1259                 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1260                                             s->fw_evtq.cntxt_id,
1261                                             s->rdmarxq[i].rspq.cntxt_id);
1262                 if (err)
1263                         goto freeout;
1264         }
1265
1266         t4_write_reg(adap, is_t4(adap->params.chip) ?
1267                                 MPS_TRC_RSS_CONTROL :
1268                                 MPS_T5_TRC_RSS_CONTROL,
1269                      RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
1270                      QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
1271         return 0;
1272 }
1273
1274 /*
1275  * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1276  * The allocated memory is cleared.
1277  */
1278 void *t4_alloc_mem(size_t size)
1279 {
1280         void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
1281
1282         if (!p)
1283                 p = vzalloc(size);
1284         return p;
1285 }
1286
1287 /*
1288  * Free memory allocated through alloc_mem().
1289  */
1290 static void t4_free_mem(void *addr)
1291 {
1292         if (is_vmalloc_addr(addr))
1293                 vfree(addr);
1294         else
1295                 kfree(addr);
1296 }
1297
1298 /* Send a Work Request to write the filter at a specified index.  We construct
1299  * a Firmware Filter Work Request to have the work done and put the indicated
1300  * filter into "pending" mode which will prevent any further actions against
1301  * it till we get a reply from the firmware on the completion status of the
1302  * request.
1303  */
1304 static int set_filter_wr(struct adapter *adapter, int fidx)
1305 {
1306         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1307         struct sk_buff *skb;
1308         struct fw_filter_wr *fwr;
1309         unsigned int ftid;
1310
1311         /* If the new filter requires loopback Destination MAC and/or VLAN
1312          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1313          * the filter.
1314          */
1315         if (f->fs.newdmac || f->fs.newvlan) {
1316                 /* allocate L2T entry for new filter */
1317                 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1318                 if (f->l2t == NULL)
1319                         return -EAGAIN;
1320                 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1321                                         f->fs.eport, f->fs.dmac)) {
1322                         cxgb4_l2t_release(f->l2t);
1323                         f->l2t = NULL;
1324                         return -ENOMEM;
1325                 }
1326         }
1327
1328         ftid = adapter->tids.ftid_base + fidx;
1329
1330         skb = alloc_skb(sizeof(*fwr), GFP_KERNEL | __GFP_NOFAIL);
1331         fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1332         memset(fwr, 0, sizeof(*fwr));
1333
1334         /* It would be nice to put most of the following in t4_hw.c but most
1335          * of the work is translating the cxgbtool ch_filter_specification
1336          * into the Work Request and the definition of that structure is
1337          * currently in cxgbtool.h which isn't appropriate to pull into the
1338          * common code.  We may eventually try to come up with a more neutral
1339          * filter specification structure but for now it's easiest to simply
1340          * put this fairly direct code in line ...
1341          */
1342         fwr->op_pkd = htonl(FW_WR_OP(FW_FILTER_WR));
1343         fwr->len16_pkd = htonl(FW_WR_LEN16(sizeof(*fwr)/16));
1344         fwr->tid_to_iq =
1345                 htonl(V_FW_FILTER_WR_TID(ftid) |
1346                       V_FW_FILTER_WR_RQTYPE(f->fs.type) |
1347                       V_FW_FILTER_WR_NOREPLY(0) |
1348                       V_FW_FILTER_WR_IQ(f->fs.iq));
1349         fwr->del_filter_to_l2tix =
1350                 htonl(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
1351                       V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
1352                       V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
1353                       V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
1354                       V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
1355                       V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
1356                       V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
1357                       V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
1358                       V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
1359                                              f->fs.newvlan == VLAN_REWRITE) |
1360                       V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
1361                                             f->fs.newvlan == VLAN_REWRITE) |
1362                       V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
1363                       V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
1364                       V_FW_FILTER_WR_PRIO(f->fs.prio) |
1365                       V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
1366         fwr->ethtype = htons(f->fs.val.ethtype);
1367         fwr->ethtypem = htons(f->fs.mask.ethtype);
1368         fwr->frag_to_ovlan_vldm =
1369                 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
1370                  V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
1371                  V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
1372                  V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
1373                  V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
1374                  V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
1375         fwr->smac_sel = 0;
1376         fwr->rx_chan_rx_rpl_iq =
1377                 htons(V_FW_FILTER_WR_RX_CHAN(0) |
1378                       V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id));
1379         fwr->maci_to_matchtypem =
1380                 htonl(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
1381                       V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
1382                       V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
1383                       V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
1384                       V_FW_FILTER_WR_PORT(f->fs.val.iport) |
1385                       V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
1386                       V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
1387                       V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
1388         fwr->ptcl = f->fs.val.proto;
1389         fwr->ptclm = f->fs.mask.proto;
1390         fwr->ttyp = f->fs.val.tos;
1391         fwr->ttypm = f->fs.mask.tos;
1392         fwr->ivlan = htons(f->fs.val.ivlan);
1393         fwr->ivlanm = htons(f->fs.mask.ivlan);
1394         fwr->ovlan = htons(f->fs.val.ovlan);
1395         fwr->ovlanm = htons(f->fs.mask.ovlan);
1396         memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1397         memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1398         memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1399         memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1400         fwr->lp = htons(f->fs.val.lport);
1401         fwr->lpm = htons(f->fs.mask.lport);
1402         fwr->fp = htons(f->fs.val.fport);
1403         fwr->fpm = htons(f->fs.mask.fport);
1404         if (f->fs.newsmac)
1405                 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1406
1407         /* Mark the filter as "pending" and ship off the Filter Work Request.
1408          * When we get the Work Request Reply we'll clear the pending status.
1409          */
1410         f->pending = 1;
1411         set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1412         t4_ofld_send(adapter, skb);
1413         return 0;
1414 }
1415
1416 /* Delete the filter at a specified index.
1417  */
1418 static int del_filter_wr(struct adapter *adapter, int fidx)
1419 {
1420         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1421         struct sk_buff *skb;
1422         struct fw_filter_wr *fwr;
1423         unsigned int len, ftid;
1424
1425         len = sizeof(*fwr);
1426         ftid = adapter->tids.ftid_base + fidx;
1427
1428         skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL);
1429         fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1430         t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1431
1432         /* Mark the filter as "pending" and ship off the Filter Work Request.
1433          * When we get the Work Request Reply we'll clear the pending status.
1434          */
1435         f->pending = 1;
1436         t4_mgmt_tx(adapter, skb);
1437         return 0;
1438 }
1439
1440 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1441                              void *accel_priv, select_queue_fallback_t fallback)
1442 {
1443         int txq;
1444
1445 #ifdef CONFIG_CHELSIO_T4_DCB
1446         /* If a Data Center Bridging has been successfully negotiated on this
1447          * link then we'll use the skb's priority to map it to a TX Queue.
1448          * The skb's priority is determined via the VLAN Tag Priority Code
1449          * Point field.
1450          */
1451         if (cxgb4_dcb_enabled(dev)) {
1452                 u16 vlan_tci;
1453                 int err;
1454
1455                 err = vlan_get_tag(skb, &vlan_tci);
1456                 if (unlikely(err)) {
1457                         if (net_ratelimit())
1458                                 netdev_warn(dev,
1459                                             "TX Packet without VLAN Tag on DCB Link\n");
1460                         txq = 0;
1461                 } else {
1462                         txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1463                 }
1464                 return txq;
1465         }
1466 #endif /* CONFIG_CHELSIO_T4_DCB */
1467
1468         if (select_queue) {
1469                 txq = (skb_rx_queue_recorded(skb)
1470                         ? skb_get_rx_queue(skb)
1471                         : smp_processor_id());
1472
1473                 while (unlikely(txq >= dev->real_num_tx_queues))
1474                         txq -= dev->real_num_tx_queues;
1475
1476                 return txq;
1477         }
1478
1479         return fallback(dev, skb) % dev->real_num_tx_queues;
1480 }
1481
1482 static inline int is_offload(const struct adapter *adap)
1483 {
1484         return adap->params.offload;
1485 }
1486
1487 /*
1488  * Implementation of ethtool operations.
1489  */
1490
1491 static u32 get_msglevel(struct net_device *dev)
1492 {
1493         return netdev2adap(dev)->msg_enable;
1494 }
1495
1496 static void set_msglevel(struct net_device *dev, u32 val)
1497 {
1498         netdev2adap(dev)->msg_enable = val;
1499 }
1500
1501 static char stats_strings[][ETH_GSTRING_LEN] = {
1502         "TxOctetsOK         ",
1503         "TxFramesOK         ",
1504         "TxBroadcastFrames  ",
1505         "TxMulticastFrames  ",
1506         "TxUnicastFrames    ",
1507         "TxErrorFrames      ",
1508
1509         "TxFrames64         ",
1510         "TxFrames65To127    ",
1511         "TxFrames128To255   ",
1512         "TxFrames256To511   ",
1513         "TxFrames512To1023  ",
1514         "TxFrames1024To1518 ",
1515         "TxFrames1519ToMax  ",
1516
1517         "TxFramesDropped    ",
1518         "TxPauseFrames      ",
1519         "TxPPP0Frames       ",
1520         "TxPPP1Frames       ",
1521         "TxPPP2Frames       ",
1522         "TxPPP3Frames       ",
1523         "TxPPP4Frames       ",
1524         "TxPPP5Frames       ",
1525         "TxPPP6Frames       ",
1526         "TxPPP7Frames       ",
1527
1528         "RxOctetsOK         ",
1529         "RxFramesOK         ",
1530         "RxBroadcastFrames  ",
1531         "RxMulticastFrames  ",
1532         "RxUnicastFrames    ",
1533
1534         "RxFramesTooLong    ",
1535         "RxJabberErrors     ",
1536         "RxFCSErrors        ",
1537         "RxLengthErrors     ",
1538         "RxSymbolErrors     ",
1539         "RxRuntFrames       ",
1540
1541         "RxFrames64         ",
1542         "RxFrames65To127    ",
1543         "RxFrames128To255   ",
1544         "RxFrames256To511   ",
1545         "RxFrames512To1023  ",
1546         "RxFrames1024To1518 ",
1547         "RxFrames1519ToMax  ",
1548
1549         "RxPauseFrames      ",
1550         "RxPPP0Frames       ",
1551         "RxPPP1Frames       ",
1552         "RxPPP2Frames       ",
1553         "RxPPP3Frames       ",
1554         "RxPPP4Frames       ",
1555         "RxPPP5Frames       ",
1556         "RxPPP6Frames       ",
1557         "RxPPP7Frames       ",
1558
1559         "RxBG0FramesDropped ",
1560         "RxBG1FramesDropped ",
1561         "RxBG2FramesDropped ",
1562         "RxBG3FramesDropped ",
1563         "RxBG0FramesTrunc   ",
1564         "RxBG1FramesTrunc   ",
1565         "RxBG2FramesTrunc   ",
1566         "RxBG3FramesTrunc   ",
1567
1568         "TSO                ",
1569         "TxCsumOffload      ",
1570         "RxCsumGood         ",
1571         "VLANextractions    ",
1572         "VLANinsertions     ",
1573         "GROpackets         ",
1574         "GROmerged          ",
1575         "WriteCoalSuccess   ",
1576         "WriteCoalFail      ",
1577 };
1578
1579 static int get_sset_count(struct net_device *dev, int sset)
1580 {
1581         switch (sset) {
1582         case ETH_SS_STATS:
1583                 return ARRAY_SIZE(stats_strings);
1584         default:
1585                 return -EOPNOTSUPP;
1586         }
1587 }
1588
1589 #define T4_REGMAP_SIZE (160 * 1024)
1590 #define T5_REGMAP_SIZE (332 * 1024)
1591
1592 static int get_regs_len(struct net_device *dev)
1593 {
1594         struct adapter *adap = netdev2adap(dev);
1595         if (is_t4(adap->params.chip))
1596                 return T4_REGMAP_SIZE;
1597         else
1598                 return T5_REGMAP_SIZE;
1599 }
1600
1601 static int get_eeprom_len(struct net_device *dev)
1602 {
1603         return EEPROMSIZE;
1604 }
1605
1606 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1607 {
1608         struct adapter *adapter = netdev2adap(dev);
1609
1610         strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1611         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1612         strlcpy(info->bus_info, pci_name(adapter->pdev),
1613                 sizeof(info->bus_info));
1614
1615         if (adapter->params.fw_vers)
1616                 snprintf(info->fw_version, sizeof(info->fw_version),
1617                         "%u.%u.%u.%u, TP %u.%u.%u.%u",
1618                         FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers),
1619                         FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers),
1620                         FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers),
1621                         FW_HDR_FW_VER_BUILD_GET(adapter->params.fw_vers),
1622                         FW_HDR_FW_VER_MAJOR_GET(adapter->params.tp_vers),
1623                         FW_HDR_FW_VER_MINOR_GET(adapter->params.tp_vers),
1624                         FW_HDR_FW_VER_MICRO_GET(adapter->params.tp_vers),
1625                         FW_HDR_FW_VER_BUILD_GET(adapter->params.tp_vers));
1626 }
1627
1628 static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
1629 {
1630         if (stringset == ETH_SS_STATS)
1631                 memcpy(data, stats_strings, sizeof(stats_strings));
1632 }
1633
1634 /*
1635  * port stats maintained per queue of the port.  They should be in the same
1636  * order as in stats_strings above.
1637  */
1638 struct queue_port_stats {
1639         u64 tso;
1640         u64 tx_csum;
1641         u64 rx_csum;
1642         u64 vlan_ex;
1643         u64 vlan_ins;
1644         u64 gro_pkts;
1645         u64 gro_merged;
1646 };
1647
1648 static void collect_sge_port_stats(const struct adapter *adap,
1649                 const struct port_info *p, struct queue_port_stats *s)
1650 {
1651         int i;
1652         const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
1653         const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
1654
1655         memset(s, 0, sizeof(*s));
1656         for (i = 0; i < p->nqsets; i++, rx++, tx++) {
1657                 s->tso += tx->tso;
1658                 s->tx_csum += tx->tx_cso;
1659                 s->rx_csum += rx->stats.rx_cso;
1660                 s->vlan_ex += rx->stats.vlan_ex;
1661                 s->vlan_ins += tx->vlan_ins;
1662                 s->gro_pkts += rx->stats.lro_pkts;
1663                 s->gro_merged += rx->stats.lro_merged;
1664         }
1665 }
1666
1667 static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1668                       u64 *data)
1669 {
1670         struct port_info *pi = netdev_priv(dev);
1671         struct adapter *adapter = pi->adapter;
1672         u32 val1, val2;
1673
1674         t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data);
1675
1676         data += sizeof(struct port_stats) / sizeof(u64);
1677         collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
1678         data += sizeof(struct queue_port_stats) / sizeof(u64);
1679         if (!is_t4(adapter->params.chip)) {
1680                 t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7));
1681                 val1 = t4_read_reg(adapter, SGE_STAT_TOTAL);
1682                 val2 = t4_read_reg(adapter, SGE_STAT_MATCH);
1683                 *data = val1 - val2;
1684                 data++;
1685                 *data = val2;
1686                 data++;
1687         } else {
1688                 memset(data, 0, 2 * sizeof(u64));
1689                 *data += 2;
1690         }
1691 }
1692
1693 /*
1694  * Return a version number to identify the type of adapter.  The scheme is:
1695  * - bits 0..9: chip version
1696  * - bits 10..15: chip revision
1697  * - bits 16..23: register dump version
1698  */
1699 static inline unsigned int mk_adap_vers(const struct adapter *ap)
1700 {
1701         return CHELSIO_CHIP_VERSION(ap->params.chip) |
1702                 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1703 }
1704
1705 static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start,
1706                            unsigned int end)
1707 {
1708         u32 *p = buf + start;
1709
1710         for ( ; start <= end; start += sizeof(u32))
1711                 *p++ = t4_read_reg(ap, start);
1712 }
1713
1714 static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1715                      void *buf)
1716 {
1717         static const unsigned int t4_reg_ranges[] = {
1718                 0x1008, 0x1108,
1719                 0x1180, 0x11b4,
1720                 0x11fc, 0x123c,
1721                 0x1300, 0x173c,
1722                 0x1800, 0x18fc,
1723                 0x3000, 0x30d8,
1724                 0x30e0, 0x5924,
1725                 0x5960, 0x59d4,
1726                 0x5a00, 0x5af8,
1727                 0x6000, 0x6098,
1728                 0x6100, 0x6150,
1729                 0x6200, 0x6208,
1730                 0x6240, 0x6248,
1731                 0x6280, 0x6338,
1732                 0x6370, 0x638c,
1733                 0x6400, 0x643c,
1734                 0x6500, 0x6524,
1735                 0x6a00, 0x6a38,
1736                 0x6a60, 0x6a78,
1737                 0x6b00, 0x6b84,
1738                 0x6bf0, 0x6c84,
1739                 0x6cf0, 0x6d84,
1740                 0x6df0, 0x6e84,
1741                 0x6ef0, 0x6f84,
1742                 0x6ff0, 0x7084,
1743                 0x70f0, 0x7184,
1744                 0x71f0, 0x7284,
1745                 0x72f0, 0x7384,
1746                 0x73f0, 0x7450,
1747                 0x7500, 0x7530,
1748                 0x7600, 0x761c,
1749                 0x7680, 0x76cc,
1750                 0x7700, 0x7798,
1751                 0x77c0, 0x77fc,
1752                 0x7900, 0x79fc,
1753                 0x7b00, 0x7c38,
1754                 0x7d00, 0x7efc,
1755                 0x8dc0, 0x8e1c,
1756                 0x8e30, 0x8e78,
1757                 0x8ea0, 0x8f6c,
1758                 0x8fc0, 0x9074,
1759                 0x90fc, 0x90fc,
1760                 0x9400, 0x9458,
1761                 0x9600, 0x96bc,
1762                 0x9800, 0x9808,
1763                 0x9820, 0x983c,
1764                 0x9850, 0x9864,
1765                 0x9c00, 0x9c6c,
1766                 0x9c80, 0x9cec,
1767                 0x9d00, 0x9d6c,
1768                 0x9d80, 0x9dec,
1769                 0x9e00, 0x9e6c,
1770                 0x9e80, 0x9eec,
1771                 0x9f00, 0x9f6c,
1772                 0x9f80, 0x9fec,
1773                 0xd004, 0xd03c,
1774                 0xdfc0, 0xdfe0,
1775                 0xe000, 0xea7c,
1776                 0xf000, 0x11110,
1777                 0x11118, 0x11190,
1778                 0x19040, 0x1906c,
1779                 0x19078, 0x19080,
1780                 0x1908c, 0x19124,
1781                 0x19150, 0x191b0,
1782                 0x191d0, 0x191e8,
1783                 0x19238, 0x1924c,
1784                 0x193f8, 0x19474,
1785                 0x19490, 0x194f8,
1786                 0x19800, 0x19f30,
1787                 0x1a000, 0x1a06c,
1788                 0x1a0b0, 0x1a120,
1789                 0x1a128, 0x1a138,
1790                 0x1a190, 0x1a1c4,
1791                 0x1a1fc, 0x1a1fc,
1792                 0x1e040, 0x1e04c,
1793                 0x1e284, 0x1e28c,
1794                 0x1e2c0, 0x1e2c0,
1795                 0x1e2e0, 0x1e2e0,
1796                 0x1e300, 0x1e384,
1797                 0x1e3c0, 0x1e3c8,
1798                 0x1e440, 0x1e44c,
1799                 0x1e684, 0x1e68c,
1800                 0x1e6c0, 0x1e6c0,
1801                 0x1e6e0, 0x1e6e0,
1802                 0x1e700, 0x1e784,
1803                 0x1e7c0, 0x1e7c8,
1804                 0x1e840, 0x1e84c,
1805                 0x1ea84, 0x1ea8c,
1806                 0x1eac0, 0x1eac0,
1807                 0x1eae0, 0x1eae0,
1808                 0x1eb00, 0x1eb84,
1809                 0x1ebc0, 0x1ebc8,
1810                 0x1ec40, 0x1ec4c,
1811                 0x1ee84, 0x1ee8c,
1812                 0x1eec0, 0x1eec0,
1813                 0x1eee0, 0x1eee0,
1814                 0x1ef00, 0x1ef84,
1815                 0x1efc0, 0x1efc8,
1816                 0x1f040, 0x1f04c,
1817                 0x1f284, 0x1f28c,
1818                 0x1f2c0, 0x1f2c0,
1819                 0x1f2e0, 0x1f2e0,
1820                 0x1f300, 0x1f384,
1821                 0x1f3c0, 0x1f3c8,
1822                 0x1f440, 0x1f44c,
1823                 0x1f684, 0x1f68c,
1824                 0x1f6c0, 0x1f6c0,
1825                 0x1f6e0, 0x1f6e0,
1826                 0x1f700, 0x1f784,
1827                 0x1f7c0, 0x1f7c8,
1828                 0x1f840, 0x1f84c,
1829                 0x1fa84, 0x1fa8c,
1830                 0x1fac0, 0x1fac0,
1831                 0x1fae0, 0x1fae0,
1832                 0x1fb00, 0x1fb84,
1833                 0x1fbc0, 0x1fbc8,
1834                 0x1fc40, 0x1fc4c,
1835                 0x1fe84, 0x1fe8c,
1836                 0x1fec0, 0x1fec0,
1837                 0x1fee0, 0x1fee0,
1838                 0x1ff00, 0x1ff84,
1839                 0x1ffc0, 0x1ffc8,
1840                 0x20000, 0x2002c,
1841                 0x20100, 0x2013c,
1842                 0x20190, 0x201c8,
1843                 0x20200, 0x20318,
1844                 0x20400, 0x20528,
1845                 0x20540, 0x20614,
1846                 0x21000, 0x21040,
1847                 0x2104c, 0x21060,
1848                 0x210c0, 0x210ec,
1849                 0x21200, 0x21268,
1850                 0x21270, 0x21284,
1851                 0x212fc, 0x21388,
1852                 0x21400, 0x21404,
1853                 0x21500, 0x21518,
1854                 0x2152c, 0x2153c,
1855                 0x21550, 0x21554,
1856                 0x21600, 0x21600,
1857                 0x21608, 0x21628,
1858                 0x21630, 0x2163c,
1859                 0x21700, 0x2171c,
1860                 0x21780, 0x2178c,
1861                 0x21800, 0x21c38,
1862                 0x21c80, 0x21d7c,
1863                 0x21e00, 0x21e04,
1864                 0x22000, 0x2202c,
1865                 0x22100, 0x2213c,
1866                 0x22190, 0x221c8,
1867                 0x22200, 0x22318,
1868                 0x22400, 0x22528,
1869                 0x22540, 0x22614,
1870                 0x23000, 0x23040,
1871                 0x2304c, 0x23060,
1872                 0x230c0, 0x230ec,
1873                 0x23200, 0x23268,
1874                 0x23270, 0x23284,
1875                 0x232fc, 0x23388,
1876                 0x23400, 0x23404,
1877                 0x23500, 0x23518,
1878                 0x2352c, 0x2353c,
1879                 0x23550, 0x23554,
1880                 0x23600, 0x23600,
1881                 0x23608, 0x23628,
1882                 0x23630, 0x2363c,
1883                 0x23700, 0x2371c,
1884                 0x23780, 0x2378c,
1885                 0x23800, 0x23c38,
1886                 0x23c80, 0x23d7c,
1887                 0x23e00, 0x23e04,
1888                 0x24000, 0x2402c,
1889                 0x24100, 0x2413c,
1890                 0x24190, 0x241c8,
1891                 0x24200, 0x24318,
1892                 0x24400, 0x24528,
1893                 0x24540, 0x24614,
1894                 0x25000, 0x25040,
1895                 0x2504c, 0x25060,
1896                 0x250c0, 0x250ec,
1897                 0x25200, 0x25268,
1898                 0x25270, 0x25284,
1899                 0x252fc, 0x25388,
1900                 0x25400, 0x25404,
1901                 0x25500, 0x25518,
1902                 0x2552c, 0x2553c,
1903                 0x25550, 0x25554,
1904                 0x25600, 0x25600,
1905                 0x25608, 0x25628,
1906                 0x25630, 0x2563c,
1907                 0x25700, 0x2571c,
1908                 0x25780, 0x2578c,
1909                 0x25800, 0x25c38,
1910                 0x25c80, 0x25d7c,
1911                 0x25e00, 0x25e04,
1912                 0x26000, 0x2602c,
1913                 0x26100, 0x2613c,
1914                 0x26190, 0x261c8,
1915                 0x26200, 0x26318,
1916                 0x26400, 0x26528,
1917                 0x26540, 0x26614,
1918                 0x27000, 0x27040,
1919                 0x2704c, 0x27060,
1920                 0x270c0, 0x270ec,
1921                 0x27200, 0x27268,
1922                 0x27270, 0x27284,
1923                 0x272fc, 0x27388,
1924                 0x27400, 0x27404,
1925                 0x27500, 0x27518,
1926                 0x2752c, 0x2753c,
1927                 0x27550, 0x27554,
1928                 0x27600, 0x27600,
1929                 0x27608, 0x27628,
1930                 0x27630, 0x2763c,
1931                 0x27700, 0x2771c,
1932                 0x27780, 0x2778c,
1933                 0x27800, 0x27c38,
1934                 0x27c80, 0x27d7c,
1935                 0x27e00, 0x27e04
1936         };
1937
1938         static const unsigned int t5_reg_ranges[] = {
1939                 0x1008, 0x1148,
1940                 0x1180, 0x11b4,
1941                 0x11fc, 0x123c,
1942                 0x1280, 0x173c,
1943                 0x1800, 0x18fc,
1944                 0x3000, 0x3028,
1945                 0x3060, 0x30d8,
1946                 0x30e0, 0x30fc,
1947                 0x3140, 0x357c,
1948                 0x35a8, 0x35cc,
1949                 0x35ec, 0x35ec,
1950                 0x3600, 0x5624,
1951                 0x56cc, 0x575c,
1952                 0x580c, 0x5814,
1953                 0x5890, 0x58bc,
1954                 0x5940, 0x59dc,
1955                 0x59fc, 0x5a18,
1956                 0x5a60, 0x5a9c,
1957                 0x5b9c, 0x5bfc,
1958                 0x6000, 0x6040,
1959                 0x6058, 0x614c,
1960                 0x7700, 0x7798,
1961                 0x77c0, 0x78fc,
1962                 0x7b00, 0x7c54,
1963                 0x7d00, 0x7efc,
1964                 0x8dc0, 0x8de0,
1965                 0x8df8, 0x8e84,
1966                 0x8ea0, 0x8f84,
1967                 0x8fc0, 0x90f8,
1968                 0x9400, 0x9470,
1969                 0x9600, 0x96f4,
1970                 0x9800, 0x9808,
1971                 0x9820, 0x983c,
1972                 0x9850, 0x9864,
1973                 0x9c00, 0x9c6c,
1974                 0x9c80, 0x9cec,
1975                 0x9d00, 0x9d6c,
1976                 0x9d80, 0x9dec,
1977                 0x9e00, 0x9e6c,
1978                 0x9e80, 0x9eec,
1979                 0x9f00, 0x9f6c,
1980                 0x9f80, 0xa020,
1981                 0xd004, 0xd03c,
1982                 0xdfc0, 0xdfe0,
1983                 0xe000, 0x11088,
1984                 0x1109c, 0x11110,
1985                 0x11118, 0x1117c,
1986                 0x11190, 0x11204,
1987                 0x19040, 0x1906c,
1988                 0x19078, 0x19080,
1989                 0x1908c, 0x19124,
1990                 0x19150, 0x191b0,
1991                 0x191d0, 0x191e8,
1992                 0x19238, 0x19290,
1993                 0x193f8, 0x19474,
1994                 0x19490, 0x194cc,
1995                 0x194f0, 0x194f8,
1996                 0x19c00, 0x19c60,
1997                 0x19c94, 0x19e10,
1998                 0x19e50, 0x19f34,
1999                 0x19f40, 0x19f50,
2000                 0x19f90, 0x19fe4,
2001                 0x1a000, 0x1a06c,
2002                 0x1a0b0, 0x1a120,
2003                 0x1a128, 0x1a138,
2004                 0x1a190, 0x1a1c4,
2005                 0x1a1fc, 0x1a1fc,
2006                 0x1e008, 0x1e00c,
2007                 0x1e040, 0x1e04c,
2008                 0x1e284, 0x1e290,
2009                 0x1e2c0, 0x1e2c0,
2010                 0x1e2e0, 0x1e2e0,
2011                 0x1e300, 0x1e384,
2012                 0x1e3c0, 0x1e3c8,
2013                 0x1e408, 0x1e40c,
2014                 0x1e440, 0x1e44c,
2015                 0x1e684, 0x1e690,
2016                 0x1e6c0, 0x1e6c0,
2017                 0x1e6e0, 0x1e6e0,
2018                 0x1e700, 0x1e784,
2019                 0x1e7c0, 0x1e7c8,
2020                 0x1e808, 0x1e80c,
2021                 0x1e840, 0x1e84c,
2022                 0x1ea84, 0x1ea90,
2023                 0x1eac0, 0x1eac0,
2024                 0x1eae0, 0x1eae0,
2025                 0x1eb00, 0x1eb84,
2026                 0x1ebc0, 0x1ebc8,
2027                 0x1ec08, 0x1ec0c,
2028                 0x1ec40, 0x1ec4c,
2029                 0x1ee84, 0x1ee90,
2030                 0x1eec0, 0x1eec0,
2031                 0x1eee0, 0x1eee0,
2032                 0x1ef00, 0x1ef84,
2033                 0x1efc0, 0x1efc8,
2034                 0x1f008, 0x1f00c,
2035                 0x1f040, 0x1f04c,
2036                 0x1f284, 0x1f290,
2037                 0x1f2c0, 0x1f2c0,
2038                 0x1f2e0, 0x1f2e0,
2039                 0x1f300, 0x1f384,
2040                 0x1f3c0, 0x1f3c8,
2041                 0x1f408, 0x1f40c,
2042                 0x1f440, 0x1f44c,
2043                 0x1f684, 0x1f690,
2044                 0x1f6c0, 0x1f6c0,
2045                 0x1f6e0, 0x1f6e0,
2046                 0x1f700, 0x1f784,
2047                 0x1f7c0, 0x1f7c8,
2048                 0x1f808, 0x1f80c,
2049                 0x1f840, 0x1f84c,
2050                 0x1fa84, 0x1fa90,
2051                 0x1fac0, 0x1fac0,
2052                 0x1fae0, 0x1fae0,
2053                 0x1fb00, 0x1fb84,
2054                 0x1fbc0, 0x1fbc8,
2055                 0x1fc08, 0x1fc0c,
2056                 0x1fc40, 0x1fc4c,
2057                 0x1fe84, 0x1fe90,
2058                 0x1fec0, 0x1fec0,
2059                 0x1fee0, 0x1fee0,
2060                 0x1ff00, 0x1ff84,
2061                 0x1ffc0, 0x1ffc8,
2062                 0x30000, 0x30030,
2063                 0x30100, 0x30144,
2064                 0x30190, 0x301d0,
2065                 0x30200, 0x30318,
2066                 0x30400, 0x3052c,
2067                 0x30540, 0x3061c,
2068                 0x30800, 0x30834,
2069                 0x308c0, 0x30908,
2070                 0x30910, 0x309ac,
2071                 0x30a00, 0x30a04,
2072                 0x30a0c, 0x30a2c,
2073                 0x30a44, 0x30a50,
2074                 0x30a74, 0x30c24,
2075                 0x30d08, 0x30d14,
2076                 0x30d1c, 0x30d20,
2077                 0x30d3c, 0x30d50,
2078                 0x31200, 0x3120c,
2079                 0x31220, 0x31220,
2080                 0x31240, 0x31240,
2081                 0x31600, 0x31600,
2082                 0x31608, 0x3160c,
2083                 0x31a00, 0x31a1c,
2084                 0x31e04, 0x31e20,
2085                 0x31e38, 0x31e3c,
2086                 0x31e80, 0x31e80,
2087                 0x31e88, 0x31ea8,
2088                 0x31eb0, 0x31eb4,
2089                 0x31ec8, 0x31ed4,
2090                 0x31fb8, 0x32004,
2091                 0x32208, 0x3223c,
2092                 0x32600, 0x32630,
2093                 0x32a00, 0x32abc,
2094                 0x32b00, 0x32b70,
2095                 0x33000, 0x33048,
2096                 0x33060, 0x3309c,
2097                 0x330f0, 0x33148,
2098                 0x33160, 0x3319c,
2099                 0x331f0, 0x332e4,
2100                 0x332f8, 0x333e4,
2101                 0x333f8, 0x33448,
2102                 0x33460, 0x3349c,
2103                 0x334f0, 0x33548,
2104                 0x33560, 0x3359c,
2105                 0x335f0, 0x336e4,
2106                 0x336f8, 0x337e4,
2107                 0x337f8, 0x337fc,
2108                 0x33814, 0x33814,
2109                 0x3382c, 0x3382c,
2110                 0x33880, 0x3388c,
2111                 0x338e8, 0x338ec,
2112                 0x33900, 0x33948,
2113                 0x33960, 0x3399c,
2114                 0x339f0, 0x33ae4,
2115                 0x33af8, 0x33b10,
2116                 0x33b28, 0x33b28,
2117                 0x33b3c, 0x33b50,
2118                 0x33bf0, 0x33c10,
2119                 0x33c28, 0x33c28,
2120                 0x33c3c, 0x33c50,
2121                 0x33cf0, 0x33cfc,
2122                 0x34000, 0x34030,
2123                 0x34100, 0x34144,
2124                 0x34190, 0x341d0,
2125                 0x34200, 0x34318,
2126                 0x34400, 0x3452c,
2127                 0x34540, 0x3461c,
2128                 0x34800, 0x34834,
2129                 0x348c0, 0x34908,
2130                 0x34910, 0x349ac,
2131                 0x34a00, 0x34a04,
2132                 0x34a0c, 0x34a2c,
2133                 0x34a44, 0x34a50,
2134                 0x34a74, 0x34c24,
2135                 0x34d08, 0x34d14,
2136                 0x34d1c, 0x34d20,
2137                 0x34d3c, 0x34d50,
2138                 0x35200, 0x3520c,
2139                 0x35220, 0x35220,
2140                 0x35240, 0x35240,
2141                 0x35600, 0x35600,
2142                 0x35608, 0x3560c,
2143                 0x35a00, 0x35a1c,
2144                 0x35e04, 0x35e20,
2145                 0x35e38, 0x35e3c,
2146                 0x35e80, 0x35e80,
2147                 0x35e88, 0x35ea8,
2148                 0x35eb0, 0x35eb4,
2149                 0x35ec8, 0x35ed4,
2150                 0x35fb8, 0x36004,
2151                 0x36208, 0x3623c,
2152                 0x36600, 0x36630,
2153                 0x36a00, 0x36abc,
2154                 0x36b00, 0x36b70,
2155                 0x37000, 0x37048,
2156                 0x37060, 0x3709c,
2157                 0x370f0, 0x37148,
2158                 0x37160, 0x3719c,
2159                 0x371f0, 0x372e4,
2160                 0x372f8, 0x373e4,
2161                 0x373f8, 0x37448,
2162                 0x37460, 0x3749c,
2163                 0x374f0, 0x37548,
2164                 0x37560, 0x3759c,
2165                 0x375f0, 0x376e4,
2166                 0x376f8, 0x377e4,
2167                 0x377f8, 0x377fc,
2168                 0x37814, 0x37814,
2169                 0x3782c, 0x3782c,
2170                 0x37880, 0x3788c,
2171                 0x378e8, 0x378ec,
2172                 0x37900, 0x37948,
2173                 0x37960, 0x3799c,
2174                 0x379f0, 0x37ae4,
2175                 0x37af8, 0x37b10,
2176                 0x37b28, 0x37b28,
2177                 0x37b3c, 0x37b50,
2178                 0x37bf0, 0x37c10,
2179                 0x37c28, 0x37c28,
2180                 0x37c3c, 0x37c50,
2181                 0x37cf0, 0x37cfc,
2182                 0x38000, 0x38030,
2183                 0x38100, 0x38144,
2184                 0x38190, 0x381d0,
2185                 0x38200, 0x38318,
2186                 0x38400, 0x3852c,
2187                 0x38540, 0x3861c,
2188                 0x38800, 0x38834,
2189                 0x388c0, 0x38908,
2190                 0x38910, 0x389ac,
2191                 0x38a00, 0x38a04,
2192                 0x38a0c, 0x38a2c,
2193                 0x38a44, 0x38a50,
2194                 0x38a74, 0x38c24,
2195                 0x38d08, 0x38d14,
2196                 0x38d1c, 0x38d20,
2197                 0x38d3c, 0x38d50,
2198                 0x39200, 0x3920c,
2199                 0x39220, 0x39220,
2200                 0x39240, 0x39240,
2201                 0x39600, 0x39600,
2202                 0x39608, 0x3960c,
2203                 0x39a00, 0x39a1c,
2204                 0x39e04, 0x39e20,
2205                 0x39e38, 0x39e3c,
2206                 0x39e80, 0x39e80,
2207                 0x39e88, 0x39ea8,
2208                 0x39eb0, 0x39eb4,
2209                 0x39ec8, 0x39ed4,
2210                 0x39fb8, 0x3a004,
2211                 0x3a208, 0x3a23c,
2212                 0x3a600, 0x3a630,
2213                 0x3aa00, 0x3aabc,
2214                 0x3ab00, 0x3ab70,
2215                 0x3b000, 0x3b048,
2216                 0x3b060, 0x3b09c,
2217                 0x3b0f0, 0x3b148,
2218                 0x3b160, 0x3b19c,
2219                 0x3b1f0, 0x3b2e4,
2220                 0x3b2f8, 0x3b3e4,
2221                 0x3b3f8, 0x3b448,
2222                 0x3b460, 0x3b49c,
2223                 0x3b4f0, 0x3b548,
2224                 0x3b560, 0x3b59c,
2225                 0x3b5f0, 0x3b6e4,
2226                 0x3b6f8, 0x3b7e4,
2227                 0x3b7f8, 0x3b7fc,
2228                 0x3b814, 0x3b814,
2229                 0x3b82c, 0x3b82c,
2230                 0x3b880, 0x3b88c,
2231                 0x3b8e8, 0x3b8ec,
2232                 0x3b900, 0x3b948,
2233                 0x3b960, 0x3b99c,
2234                 0x3b9f0, 0x3bae4,
2235                 0x3baf8, 0x3bb10,
2236                 0x3bb28, 0x3bb28,
2237                 0x3bb3c, 0x3bb50,
2238                 0x3bbf0, 0x3bc10,
2239                 0x3bc28, 0x3bc28,
2240                 0x3bc3c, 0x3bc50,
2241                 0x3bcf0, 0x3bcfc,
2242                 0x3c000, 0x3c030,
2243                 0x3c100, 0x3c144,
2244                 0x3c190, 0x3c1d0,
2245                 0x3c200, 0x3c318,
2246                 0x3c400, 0x3c52c,
2247                 0x3c540, 0x3c61c,
2248                 0x3c800, 0x3c834,
2249                 0x3c8c0, 0x3c908,
2250                 0x3c910, 0x3c9ac,
2251                 0x3ca00, 0x3ca04,
2252                 0x3ca0c, 0x3ca2c,
2253                 0x3ca44, 0x3ca50,
2254                 0x3ca74, 0x3cc24,
2255                 0x3cd08, 0x3cd14,
2256                 0x3cd1c, 0x3cd20,
2257                 0x3cd3c, 0x3cd50,
2258                 0x3d200, 0x3d20c,
2259                 0x3d220, 0x3d220,
2260                 0x3d240, 0x3d240,
2261                 0x3d600, 0x3d600,
2262                 0x3d608, 0x3d60c,
2263                 0x3da00, 0x3da1c,
2264                 0x3de04, 0x3de20,
2265                 0x3de38, 0x3de3c,
2266                 0x3de80, 0x3de80,
2267                 0x3de88, 0x3dea8,
2268                 0x3deb0, 0x3deb4,
2269                 0x3dec8, 0x3ded4,
2270                 0x3dfb8, 0x3e004,
2271                 0x3e208, 0x3e23c,
2272                 0x3e600, 0x3e630,
2273                 0x3ea00, 0x3eabc,
2274                 0x3eb00, 0x3eb70,
2275                 0x3f000, 0x3f048,
2276                 0x3f060, 0x3f09c,
2277                 0x3f0f0, 0x3f148,
2278                 0x3f160, 0x3f19c,
2279                 0x3f1f0, 0x3f2e4,
2280                 0x3f2f8, 0x3f3e4,
2281                 0x3f3f8, 0x3f448,
2282                 0x3f460, 0x3f49c,
2283                 0x3f4f0, 0x3f548,
2284                 0x3f560, 0x3f59c,
2285                 0x3f5f0, 0x3f6e4,
2286                 0x3f6f8, 0x3f7e4,
2287                 0x3f7f8, 0x3f7fc,
2288                 0x3f814, 0x3f814,
2289                 0x3f82c, 0x3f82c,
2290                 0x3f880, 0x3f88c,
2291                 0x3f8e8, 0x3f8ec,
2292                 0x3f900, 0x3f948,
2293                 0x3f960, 0x3f99c,
2294                 0x3f9f0, 0x3fae4,
2295                 0x3faf8, 0x3fb10,
2296                 0x3fb28, 0x3fb28,
2297                 0x3fb3c, 0x3fb50,
2298                 0x3fbf0, 0x3fc10,
2299                 0x3fc28, 0x3fc28,
2300                 0x3fc3c, 0x3fc50,
2301                 0x3fcf0, 0x3fcfc,
2302                 0x40000, 0x4000c,
2303                 0x40040, 0x40068,
2304                 0x40080, 0x40144,
2305                 0x40180, 0x4018c,
2306                 0x40200, 0x40298,
2307                 0x402ac, 0x4033c,
2308                 0x403f8, 0x403fc,
2309                 0x41304, 0x413c4,
2310                 0x41400, 0x4141c,
2311                 0x41480, 0x414d0,
2312                 0x44000, 0x44078,
2313                 0x440c0, 0x44278,
2314                 0x442c0, 0x44478,
2315                 0x444c0, 0x44678,
2316                 0x446c0, 0x44878,
2317                 0x448c0, 0x449fc,
2318                 0x45000, 0x45068,
2319                 0x45080, 0x45084,
2320                 0x450a0, 0x450b0,
2321                 0x45200, 0x45268,
2322                 0x45280, 0x45284,
2323                 0x452a0, 0x452b0,
2324                 0x460c0, 0x460e4,
2325                 0x47000, 0x4708c,
2326                 0x47200, 0x47250,
2327                 0x47400, 0x47420,
2328                 0x47600, 0x47618,
2329                 0x47800, 0x47814,
2330                 0x48000, 0x4800c,
2331                 0x48040, 0x48068,
2332                 0x48080, 0x48144,
2333                 0x48180, 0x4818c,
2334                 0x48200, 0x48298,
2335                 0x482ac, 0x4833c,
2336                 0x483f8, 0x483fc,
2337                 0x49304, 0x493c4,
2338                 0x49400, 0x4941c,
2339                 0x49480, 0x494d0,
2340                 0x4c000, 0x4c078,
2341                 0x4c0c0, 0x4c278,
2342                 0x4c2c0, 0x4c478,
2343                 0x4c4c0, 0x4c678,
2344                 0x4c6c0, 0x4c878,
2345                 0x4c8c0, 0x4c9fc,
2346                 0x4d000, 0x4d068,
2347                 0x4d080, 0x4d084,
2348                 0x4d0a0, 0x4d0b0,
2349                 0x4d200, 0x4d268,
2350                 0x4d280, 0x4d284,
2351                 0x4d2a0, 0x4d2b0,
2352                 0x4e0c0, 0x4e0e4,
2353                 0x4f000, 0x4f08c,
2354                 0x4f200, 0x4f250,
2355                 0x4f400, 0x4f420,
2356                 0x4f600, 0x4f618,
2357                 0x4f800, 0x4f814,
2358                 0x50000, 0x500cc,
2359                 0x50400, 0x50400,
2360                 0x50800, 0x508cc,
2361                 0x50c00, 0x50c00,
2362                 0x51000, 0x5101c,
2363                 0x51300, 0x51308,
2364         };
2365
2366         int i;
2367         struct adapter *ap = netdev2adap(dev);
2368         static const unsigned int *reg_ranges;
2369         int arr_size = 0, buf_size = 0;
2370
2371         if (is_t4(ap->params.chip)) {
2372                 reg_ranges = &t4_reg_ranges[0];
2373                 arr_size = ARRAY_SIZE(t4_reg_ranges);
2374                 buf_size = T4_REGMAP_SIZE;
2375         } else {
2376                 reg_ranges = &t5_reg_ranges[0];
2377                 arr_size = ARRAY_SIZE(t5_reg_ranges);
2378                 buf_size = T5_REGMAP_SIZE;
2379         }
2380
2381         regs->version = mk_adap_vers(ap);
2382
2383         memset(buf, 0, buf_size);
2384         for (i = 0; i < arr_size; i += 2)
2385                 reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]);
2386 }
2387
2388 static int restart_autoneg(struct net_device *dev)
2389 {
2390         struct port_info *p = netdev_priv(dev);
2391
2392         if (!netif_running(dev))
2393                 return -EAGAIN;
2394         if (p->link_cfg.autoneg != AUTONEG_ENABLE)
2395                 return -EINVAL;
2396         t4_restart_aneg(p->adapter, p->adapter->fn, p->tx_chan);
2397         return 0;
2398 }
2399
2400 static int identify_port(struct net_device *dev,
2401                          enum ethtool_phys_id_state state)
2402 {
2403         unsigned int val;
2404         struct adapter *adap = netdev2adap(dev);
2405
2406         if (state == ETHTOOL_ID_ACTIVE)
2407                 val = 0xffff;
2408         else if (state == ETHTOOL_ID_INACTIVE)
2409                 val = 0;
2410         else
2411                 return -EINVAL;
2412
2413         return t4_identify_port(adap, adap->fn, netdev2pinfo(dev)->viid, val);
2414 }
2415
2416 static unsigned int from_fw_linkcaps(unsigned int type, unsigned int caps)
2417 {
2418         unsigned int v = 0;
2419
2420         if (type == FW_PORT_TYPE_BT_SGMII || type == FW_PORT_TYPE_BT_XFI ||
2421             type == FW_PORT_TYPE_BT_XAUI) {
2422                 v |= SUPPORTED_TP;
2423                 if (caps & FW_PORT_CAP_SPEED_100M)
2424                         v |= SUPPORTED_100baseT_Full;
2425                 if (caps & FW_PORT_CAP_SPEED_1G)
2426                         v |= SUPPORTED_1000baseT_Full;
2427                 if (caps & FW_PORT_CAP_SPEED_10G)
2428                         v |= SUPPORTED_10000baseT_Full;
2429         } else if (type == FW_PORT_TYPE_KX4 || type == FW_PORT_TYPE_KX) {
2430                 v |= SUPPORTED_Backplane;
2431                 if (caps & FW_PORT_CAP_SPEED_1G)
2432                         v |= SUPPORTED_1000baseKX_Full;
2433                 if (caps & FW_PORT_CAP_SPEED_10G)
2434                         v |= SUPPORTED_10000baseKX4_Full;
2435         } else if (type == FW_PORT_TYPE_KR)
2436                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
2437         else if (type == FW_PORT_TYPE_BP_AP)
2438                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2439                      SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full;
2440         else if (type == FW_PORT_TYPE_BP4_AP)
2441                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2442                      SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full |
2443                      SUPPORTED_10000baseKX4_Full;
2444         else if (type == FW_PORT_TYPE_FIBER_XFI ||
2445                  type == FW_PORT_TYPE_FIBER_XAUI || type == FW_PORT_TYPE_SFP)
2446                 v |= SUPPORTED_FIBRE;
2447         else if (type == FW_PORT_TYPE_BP40_BA)
2448                 v |= SUPPORTED_40000baseSR4_Full;
2449
2450         if (caps & FW_PORT_CAP_ANEG)
2451                 v |= SUPPORTED_Autoneg;
2452         return v;
2453 }
2454
2455 static unsigned int to_fw_linkcaps(unsigned int caps)
2456 {
2457         unsigned int v = 0;
2458
2459         if (caps & ADVERTISED_100baseT_Full)
2460                 v |= FW_PORT_CAP_SPEED_100M;
2461         if (caps & ADVERTISED_1000baseT_Full)
2462                 v |= FW_PORT_CAP_SPEED_1G;
2463         if (caps & ADVERTISED_10000baseT_Full)
2464                 v |= FW_PORT_CAP_SPEED_10G;
2465         if (caps & ADVERTISED_40000baseSR4_Full)
2466                 v |= FW_PORT_CAP_SPEED_40G;
2467         return v;
2468 }
2469
2470 static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2471 {
2472         const struct port_info *p = netdev_priv(dev);
2473
2474         if (p->port_type == FW_PORT_TYPE_BT_SGMII ||
2475             p->port_type == FW_PORT_TYPE_BT_XFI ||
2476             p->port_type == FW_PORT_TYPE_BT_XAUI)
2477                 cmd->port = PORT_TP;
2478         else if (p->port_type == FW_PORT_TYPE_FIBER_XFI ||
2479                  p->port_type == FW_PORT_TYPE_FIBER_XAUI)
2480                 cmd->port = PORT_FIBRE;
2481         else if (p->port_type == FW_PORT_TYPE_SFP ||
2482                  p->port_type == FW_PORT_TYPE_QSFP_10G ||
2483                  p->port_type == FW_PORT_TYPE_QSFP) {
2484                 if (p->mod_type == FW_PORT_MOD_TYPE_LR ||
2485                     p->mod_type == FW_PORT_MOD_TYPE_SR ||
2486                     p->mod_type == FW_PORT_MOD_TYPE_ER ||
2487                     p->mod_type == FW_PORT_MOD_TYPE_LRM)
2488                         cmd->port = PORT_FIBRE;
2489                 else if (p->mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
2490                          p->mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
2491                         cmd->port = PORT_DA;
2492                 else
2493                         cmd->port = PORT_OTHER;
2494         } else
2495                 cmd->port = PORT_OTHER;
2496
2497         if (p->mdio_addr >= 0) {
2498                 cmd->phy_address = p->mdio_addr;
2499                 cmd->transceiver = XCVR_EXTERNAL;
2500                 cmd->mdio_support = p->port_type == FW_PORT_TYPE_BT_SGMII ?
2501                         MDIO_SUPPORTS_C22 : MDIO_SUPPORTS_C45;
2502         } else {
2503                 cmd->phy_address = 0;  /* not really, but no better option */
2504                 cmd->transceiver = XCVR_INTERNAL;
2505                 cmd->mdio_support = 0;
2506         }
2507
2508         cmd->supported = from_fw_linkcaps(p->port_type, p->link_cfg.supported);
2509         cmd->advertising = from_fw_linkcaps(p->port_type,
2510                                             p->link_cfg.advertising);
2511         ethtool_cmd_speed_set(cmd,
2512                               netif_carrier_ok(dev) ? p->link_cfg.speed : 0);
2513         cmd->duplex = DUPLEX_FULL;
2514         cmd->autoneg = p->link_cfg.autoneg;
2515         cmd->maxtxpkt = 0;
2516         cmd->maxrxpkt = 0;
2517         return 0;
2518 }
2519
2520 static unsigned int speed_to_caps(int speed)
2521 {
2522         if (speed == 100)
2523                 return FW_PORT_CAP_SPEED_100M;
2524         if (speed == 1000)
2525                 return FW_PORT_CAP_SPEED_1G;
2526         if (speed == 10000)
2527                 return FW_PORT_CAP_SPEED_10G;
2528         if (speed == 40000)
2529                 return FW_PORT_CAP_SPEED_40G;
2530         return 0;
2531 }
2532
2533 static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2534 {
2535         unsigned int cap;
2536         struct port_info *p = netdev_priv(dev);
2537         struct link_config *lc = &p->link_cfg;
2538         u32 speed = ethtool_cmd_speed(cmd);
2539
2540         if (cmd->duplex != DUPLEX_FULL)     /* only full-duplex supported */
2541                 return -EINVAL;
2542
2543         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2544                 /*
2545                  * PHY offers a single speed.  See if that's what's
2546                  * being requested.
2547                  */
2548                 if (cmd->autoneg == AUTONEG_DISABLE &&
2549                     (lc->supported & speed_to_caps(speed)))
2550                         return 0;
2551                 return -EINVAL;
2552         }
2553
2554         if (cmd->autoneg == AUTONEG_DISABLE) {
2555                 cap = speed_to_caps(speed);
2556
2557                 if (!(lc->supported & cap) ||
2558                     (speed == 1000) ||
2559                     (speed == 10000) ||
2560                     (speed == 40000))
2561                         return -EINVAL;
2562                 lc->requested_speed = cap;
2563                 lc->advertising = 0;
2564         } else {
2565                 cap = to_fw_linkcaps(cmd->advertising);
2566                 if (!(lc->supported & cap))
2567                         return -EINVAL;
2568                 lc->requested_speed = 0;
2569                 lc->advertising = cap | FW_PORT_CAP_ANEG;
2570         }
2571         lc->autoneg = cmd->autoneg;
2572
2573         if (netif_running(dev))
2574                 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2575                                      lc);
2576         return 0;
2577 }
2578
2579 static void get_pauseparam(struct net_device *dev,
2580                            struct ethtool_pauseparam *epause)
2581 {
2582         struct port_info *p = netdev_priv(dev);
2583
2584         epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
2585         epause->rx_pause = (p->link_cfg.fc & PAUSE_RX) != 0;
2586         epause->tx_pause = (p->link_cfg.fc & PAUSE_TX) != 0;
2587 }
2588
2589 static int set_pauseparam(struct net_device *dev,
2590                           struct ethtool_pauseparam *epause)
2591 {
2592         struct port_info *p = netdev_priv(dev);
2593         struct link_config *lc = &p->link_cfg;
2594
2595         if (epause->autoneg == AUTONEG_DISABLE)
2596                 lc->requested_fc = 0;
2597         else if (lc->supported & FW_PORT_CAP_ANEG)
2598                 lc->requested_fc = PAUSE_AUTONEG;
2599         else
2600                 return -EINVAL;
2601
2602         if (epause->rx_pause)
2603                 lc->requested_fc |= PAUSE_RX;
2604         if (epause->tx_pause)
2605                 lc->requested_fc |= PAUSE_TX;
2606         if (netif_running(dev))
2607                 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2608                                      lc);
2609         return 0;
2610 }
2611
2612 static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2613 {
2614         const struct port_info *pi = netdev_priv(dev);
2615         const struct sge *s = &pi->adapter->sge;
2616
2617         e->rx_max_pending = MAX_RX_BUFFERS;
2618         e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
2619         e->rx_jumbo_max_pending = 0;
2620         e->tx_max_pending = MAX_TXQ_ENTRIES;
2621
2622         e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
2623         e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
2624         e->rx_jumbo_pending = 0;
2625         e->tx_pending = s->ethtxq[pi->first_qset].q.size;
2626 }
2627
2628 static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2629 {
2630         int i;
2631         const struct port_info *pi = netdev_priv(dev);
2632         struct adapter *adapter = pi->adapter;
2633         struct sge *s = &adapter->sge;
2634
2635         if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
2636             e->tx_pending > MAX_TXQ_ENTRIES ||
2637             e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
2638             e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
2639             e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
2640                 return -EINVAL;
2641
2642         if (adapter->flags & FULL_INIT_DONE)
2643                 return -EBUSY;
2644
2645         for (i = 0; i < pi->nqsets; ++i) {
2646                 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
2647                 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
2648                 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
2649         }
2650         return 0;
2651 }
2652
2653 static int closest_timer(const struct sge *s, int time)
2654 {
2655         int i, delta, match = 0, min_delta = INT_MAX;
2656
2657         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
2658                 delta = time - s->timer_val[i];
2659                 if (delta < 0)
2660                         delta = -delta;
2661                 if (delta < min_delta) {
2662                         min_delta = delta;
2663                         match = i;
2664                 }
2665         }
2666         return match;
2667 }
2668
2669 static int closest_thres(const struct sge *s, int thres)
2670 {
2671         int i, delta, match = 0, min_delta = INT_MAX;
2672
2673         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
2674                 delta = thres - s->counter_val[i];
2675                 if (delta < 0)
2676                         delta = -delta;
2677                 if (delta < min_delta) {
2678                         min_delta = delta;
2679                         match = i;
2680                 }
2681         }
2682         return match;
2683 }
2684
2685 /*
2686  * Return a queue's interrupt hold-off time in us.  0 means no timer.
2687  */
2688 static unsigned int qtimer_val(const struct adapter *adap,
2689                                const struct sge_rspq *q)
2690 {
2691         unsigned int idx = q->intr_params >> 1;
2692
2693         return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
2694 }
2695
2696 /**
2697  *      set_rspq_intr_params - set a queue's interrupt holdoff parameters
2698  *      @q: the Rx queue
2699  *      @us: the hold-off time in us, or 0 to disable timer
2700  *      @cnt: the hold-off packet count, or 0 to disable counter
2701  *
2702  *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
2703  *      one of the two needs to be enabled for the queue to generate interrupts.
2704  */
2705 static int set_rspq_intr_params(struct sge_rspq *q,
2706                                 unsigned int us, unsigned int cnt)
2707 {
2708         struct adapter *adap = q->adap;
2709
2710         if ((us | cnt) == 0)
2711                 cnt = 1;
2712
2713         if (cnt) {
2714                 int err;
2715                 u32 v, new_idx;
2716
2717                 new_idx = closest_thres(&adap->sge, cnt);
2718                 if (q->desc && q->pktcnt_idx != new_idx) {
2719                         /* the queue has already been created, update it */
2720                         v = FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2721                             FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
2722                             FW_PARAMS_PARAM_YZ(q->cntxt_id);
2723                         err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
2724                                             &new_idx);
2725                         if (err)
2726                                 return err;
2727                 }
2728                 q->pktcnt_idx = new_idx;
2729         }
2730
2731         us = us == 0 ? 6 : closest_timer(&adap->sge, us);
2732         q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
2733         return 0;
2734 }
2735
2736 /**
2737  * set_rx_intr_params - set a net devices's RX interrupt holdoff paramete!
2738  * @dev: the network device
2739  * @us: the hold-off time in us, or 0 to disable timer
2740  * @cnt: the hold-off packet count, or 0 to disable counter
2741  *
2742  * Set the RX interrupt hold-off parameters for a network device.
2743  */
2744 static int set_rx_intr_params(struct net_device *dev,
2745                               unsigned int us, unsigned int cnt)
2746 {
2747         int i, err;
2748         struct port_info *pi = netdev_priv(dev);
2749         struct adapter *adap = pi->adapter;
2750         struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2751
2752         for (i = 0; i < pi->nqsets; i++, q++) {
2753                 err = set_rspq_intr_params(&q->rspq, us, cnt);
2754                 if (err)
2755                         return err;
2756         }
2757         return 0;
2758 }
2759
2760 static int set_adaptive_rx_setting(struct net_device *dev, int adaptive_rx)
2761 {
2762         int i;
2763         struct port_info *pi = netdev_priv(dev);
2764         struct adapter *adap = pi->adapter;
2765         struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2766
2767         for (i = 0; i < pi->nqsets; i++, q++)
2768                 q->rspq.adaptive_rx = adaptive_rx;
2769
2770         return 0;
2771 }
2772
2773 static int get_adaptive_rx_setting(struct net_device *dev)
2774 {
2775         struct port_info *pi = netdev_priv(dev);
2776         struct adapter *adap = pi->adapter;
2777         struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2778
2779         return q->rspq.adaptive_rx;
2780 }
2781
2782 static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2783 {
2784         set_adaptive_rx_setting(dev, c->use_adaptive_rx_coalesce);
2785         return set_rx_intr_params(dev, c->rx_coalesce_usecs,
2786                                   c->rx_max_coalesced_frames);
2787 }
2788
2789 static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2790 {
2791         const struct port_info *pi = netdev_priv(dev);
2792         const struct adapter *adap = pi->adapter;
2793         const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
2794
2795         c->rx_coalesce_usecs = qtimer_val(adap, rq);
2796         c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN) ?
2797                 adap->sge.counter_val[rq->pktcnt_idx] : 0;
2798         c->use_adaptive_rx_coalesce = get_adaptive_rx_setting(dev);
2799         return 0;
2800 }
2801
2802 /**
2803  *      eeprom_ptov - translate a physical EEPROM address to virtual
2804  *      @phys_addr: the physical EEPROM address
2805  *      @fn: the PCI function number
2806  *      @sz: size of function-specific area
2807  *
2808  *      Translate a physical EEPROM address to virtual.  The first 1K is
2809  *      accessed through virtual addresses starting at 31K, the rest is
2810  *      accessed through virtual addresses starting at 0.
2811  *
2812  *      The mapping is as follows:
2813  *      [0..1K) -> [31K..32K)
2814  *      [1K..1K+A) -> [31K-A..31K)
2815  *      [1K+A..ES) -> [0..ES-A-1K)
2816  *
2817  *      where A = @fn * @sz, and ES = EEPROM size.
2818  */
2819 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2820 {
2821         fn *= sz;
2822         if (phys_addr < 1024)
2823                 return phys_addr + (31 << 10);
2824         if (phys_addr < 1024 + fn)
2825                 return 31744 - fn + phys_addr - 1024;
2826         if (phys_addr < EEPROMSIZE)
2827                 return phys_addr - 1024 - fn;
2828         return -EINVAL;
2829 }
2830
2831 /*
2832  * The next two routines implement eeprom read/write from physical addresses.
2833  */
2834 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
2835 {
2836         int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2837
2838         if (vaddr >= 0)
2839                 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
2840         return vaddr < 0 ? vaddr : 0;
2841 }
2842
2843 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
2844 {
2845         int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2846
2847         if (vaddr >= 0)
2848                 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
2849         return vaddr < 0 ? vaddr : 0;
2850 }
2851
2852 #define EEPROM_MAGIC 0x38E2F10C
2853
2854 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2855                       u8 *data)
2856 {
2857         int i, err = 0;
2858         struct adapter *adapter = netdev2adap(dev);
2859
2860         u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2861         if (!buf)
2862                 return -ENOMEM;
2863
2864         e->magic = EEPROM_MAGIC;
2865         for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
2866                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
2867
2868         if (!err)
2869                 memcpy(data, buf + e->offset, e->len);
2870         kfree(buf);
2871         return err;
2872 }
2873
2874 static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2875                       u8 *data)
2876 {
2877         u8 *buf;
2878         int err = 0;
2879         u32 aligned_offset, aligned_len, *p;
2880         struct adapter *adapter = netdev2adap(dev);
2881
2882         if (eeprom->magic != EEPROM_MAGIC)
2883                 return -EINVAL;
2884
2885         aligned_offset = eeprom->offset & ~3;
2886         aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2887
2888         if (adapter->fn > 0) {
2889                 u32 start = 1024 + adapter->fn * EEPROMPFSIZE;
2890
2891                 if (aligned_offset < start ||
2892                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
2893                         return -EPERM;
2894         }
2895
2896         if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2897                 /*
2898                  * RMW possibly needed for first or last words.
2899                  */
2900                 buf = kmalloc(aligned_len, GFP_KERNEL);
2901                 if (!buf)
2902                         return -ENOMEM;
2903                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
2904                 if (!err && aligned_len > 4)
2905                         err = eeprom_rd_phys(adapter,
2906                                              aligned_offset + aligned_len - 4,
2907                                              (u32 *)&buf[aligned_len - 4]);
2908                 if (err)
2909                         goto out;
2910                 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2911         } else
2912                 buf = data;
2913
2914         err = t4_seeprom_wp(adapter, false);
2915         if (err)
2916                 goto out;
2917
2918         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
2919                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
2920                 aligned_offset += 4;
2921         }
2922
2923         if (!err)
2924                 err = t4_seeprom_wp(adapter, true);
2925 out:
2926         if (buf != data)
2927                 kfree(buf);
2928         return err;
2929 }
2930
2931 static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
2932 {
2933         int ret;
2934         const struct firmware *fw;
2935         struct adapter *adap = netdev2adap(netdev);
2936         unsigned int mbox = FW_PCIE_FW_MASTER_MASK + 1;
2937
2938         ef->data[sizeof(ef->data) - 1] = '\0';
2939         ret = request_firmware(&fw, ef->data, adap->pdev_dev);
2940         if (ret < 0)
2941                 return ret;
2942
2943         /* If the adapter has been fully initialized then we'll go ahead and
2944          * try to get the firmware's cooperation in upgrading to the new
2945          * firmware image otherwise we'll try to do the entire job from the
2946          * host ... and we always "force" the operation in this path.
2947          */
2948         if (adap->flags & FULL_INIT_DONE)
2949                 mbox = adap->mbox;
2950
2951         ret = t4_fw_upgrade(adap, mbox, fw->data, fw->size, 1);
2952         release_firmware(fw);
2953         if (!ret)
2954                 dev_info(adap->pdev_dev, "loaded firmware %s,"
2955                          " reload cxgb4 driver\n", ef->data);