1 /**********************************************************************
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
7 * Copyright (c) 2003-2016 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more details.
17 ***********************************************************************/
18 /*! \file liquidio_common.h
19 * \brief Common: Structures and macros used in PCI-NIC package by core and
23 #ifndef __LIQUIDIO_COMMON_H__
24 #define __LIQUIDIO_COMMON_H__
26 #include "octeon_config.h"
28 #define LIQUIDIO_PACKAGE ""
29 #define LIQUIDIO_BASE_MAJOR_VERSION 1
30 #define LIQUIDIO_BASE_MINOR_VERSION 7
31 #define LIQUIDIO_BASE_MICRO_VERSION 2
32 #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
33 __stringify(LIQUIDIO_BASE_MINOR_VERSION)
34 #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
35 #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \
36 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
37 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \
38 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
48 /** Tag types used by Octeon cores in its work. */
49 enum octeon_tag_type {
56 /* pre-defined host->NIC tag values */
57 #define LIO_CONTROL (0x11111110)
58 #define LIO_DATA(i) (0x11111111 + (i))
60 /* Opcodes used by host driver/apps to perform operations on the core.
61 * These are used to identify the major subsystem that the operation
64 #define OPCODE_CORE 0 /* used for generic core operations */
65 #define OPCODE_NIC 1 /* used for NIC operations */
66 /* Subcodes are used by host driver/apps to identify the sub-operation
67 * for the core. They only need to by unique for a given subsystem.
69 #define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f))
71 /** OPCODE_CORE subcodes. For future use. */
73 /** OPCODE_NIC subcodes */
75 /* This subcode is sent by core PCI driver to indicate cores are ready. */
76 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01
77 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */
78 #define OPCODE_NIC_CMD 0x03
79 #define OPCODE_NIC_INFO 0x04
80 #define OPCODE_NIC_PORT_STATS 0x05
81 #define OPCODE_NIC_MDIO45 0x06
82 #define OPCODE_NIC_TIMESTAMP 0x07
83 #define OPCODE_NIC_INTRMOD_CFG 0x08
84 #define OPCODE_NIC_IF_CFG 0x09
85 #define OPCODE_NIC_VF_DRV_NOTICE 0x0A
86 #define OPCODE_NIC_INTRMOD_PARAMS 0x0B
87 #define OPCODE_NIC_QCOUNT_UPDATE 0x12
88 #define OPCODE_NIC_SET_TRUSTED_VF 0x13
89 #define OPCODE_NIC_SYNC_OCTEON_TIME 0x14
90 #define VF_DRV_LOADED 1
91 #define VF_DRV_REMOVED -1
92 #define VF_DRV_MACADDR_CHANGED 2
94 #define OPCODE_NIC_VF_REP_PKT 0x15
95 #define OPCODE_NIC_VF_REP_CMD 0x16
96 #define OPCODE_NIC_UBOOT_CTL 0x17
98 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5
100 /* Application codes advertised by the core driver initialization packet. */
101 #define CVM_DRV_APP_START 0x0
102 #define CVM_DRV_NO_APP 0
103 #define CVM_DRV_APP_COUNT 0x2
104 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0)
105 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1)
106 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2)
107 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1)
109 #define BYTES_PER_DHLEN_UNIT 8
110 #define MAX_REG_CNT 2000000U
111 #define INTRNAMSIZ 32
112 #define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ)
113 #define MAX_IOQ_INTERRUPTS_PER_PF (64 * 2)
114 #define MAX_IOQ_INTERRUPTS_PER_VF (8 * 2)
116 #define SCR2_BIT_FW_LOADED 63
118 /* App specific capabilities from firmware to pf driver */
119 #define LIQUIDIO_TIME_SYNC_CAP 0x1
120 #define LIQUIDIO_SWITCHDEV_CAP 0x2
121 #define LIQUIDIO_SPOOFCHK_CAP 0x4
123 /* error status return from firmware */
124 #define OCTEON_REQUEST_NO_PERMISSION 0xc
126 static inline u32 incr_index(u32 index, u32 count, u32 max)
128 if ((index + count) >= max)
129 index = index + count - max;
136 #define OCT_BOARD_NAME 32
137 #define OCT_SERIAL_LEN 64
139 /* Structure used by core driver to send indication that the Octeon
140 * application is ready.
142 struct octeon_core_setup {
145 char boardname[OCT_BOARD_NAME];
147 char board_serial_number[OCT_SERIAL_LEN];
155 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/
157 /* The Scatter-Gather List Entry. The scatter or gather component used with
158 * a Octeon input instruction has this format.
160 struct octeon_sg_entry {
161 /** The first 64 bit gives the size of data in each dptr.*/
167 /** The 4 dptr pointers for this entry. */
172 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry))
174 /* \brief Add size to gather list
175 * @param sg_entry scatter/gather entry
176 * @param size size to add
177 * @param pos position to add it.
179 static inline void add_sg_size(struct octeon_sg_entry *sg_entry,
183 #ifdef __BIG_ENDIAN_BITFIELD
184 sg_entry->u.size[pos] = size;
186 sg_entry->u.size[3 - pos] = size;
190 /*------------------------- End Scatter/Gather ---------------------------*/
192 #define OCTNET_FRM_LENGTH_SIZE 8
194 #define OCTNET_FRM_PTP_HEADER_SIZE 8
196 #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */
198 #define OCTNET_MIN_FRM_SIZE 64
200 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE)
202 #define OCTNET_DEFAULT_MTU (1500)
203 #define OCTNET_DEFAULT_FRM_SIZE (OCTNET_DEFAULT_MTU + OCTNET_FRM_HEADER_SIZE)
205 /** NIC Commands are sent using this Octeon Input Queue */
206 #define OCTNET_CMD_Q 0
208 /* NIC Command types */
209 #define OCTNET_CMD_CHANGE_MTU 0x1
210 #define OCTNET_CMD_CHANGE_MACADDR 0x2
211 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3
212 #define OCTNET_CMD_RX_CTL 0x4
214 #define OCTNET_CMD_SET_MULTI_LIST 0x5
215 #define OCTNET_CMD_CLEAR_STATS 0x6
217 /* command for setting the speed, duplex & autoneg */
218 #define OCTNET_CMD_SET_SETTINGS 0x7
219 #define OCTNET_CMD_SET_FLOW_CTL 0x8
221 #define OCTNET_CMD_MDIO_READ_WRITE 0x9
222 #define OCTNET_CMD_GPIO_ACCESS 0xA
223 #define OCTNET_CMD_LRO_ENABLE 0xB
224 #define OCTNET_CMD_LRO_DISABLE 0xC
225 #define OCTNET_CMD_SET_RSS 0xD
226 #define OCTNET_CMD_WRITE_SA 0xE
227 #define OCTNET_CMD_DELETE_SA 0xF
228 #define OCTNET_CMD_UPDATE_SA 0x12
230 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10
231 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11
232 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13
233 #define OCTNET_CMD_VERBOSE_ENABLE 0x14
234 #define OCTNET_CMD_VERBOSE_DISABLE 0x15
236 #define OCTNET_CMD_VLAN_FILTER_CTL 0x16
237 #define OCTNET_CMD_ADD_VLAN_FILTER 0x17
238 #define OCTNET_CMD_DEL_VLAN_FILTER 0x18
239 #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19
241 #define OCTNET_CMD_ID_ACTIVE 0x1a
243 #define OCTNET_CMD_SET_UC_LIST 0x1b
244 #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c
246 #define OCTNET_CMD_QUEUE_COUNT_CTL 0x1f
248 #define OCTNET_CMD_GROUP1 1
249 #define OCTNET_CMD_SET_VF_SPOOFCHK 0x1
250 #define OCTNET_GROUP1_LAST_CMD OCTNET_CMD_SET_VF_SPOOFCHK
252 #define OCTNET_CMD_VXLAN_PORT_ADD 0x0
253 #define OCTNET_CMD_VXLAN_PORT_DEL 0x1
254 #define OCTNET_CMD_RXCSUM_ENABLE 0x0
255 #define OCTNET_CMD_RXCSUM_DISABLE 0x1
256 #define OCTNET_CMD_TXCSUM_ENABLE 0x0
257 #define OCTNET_CMD_TXCSUM_DISABLE 0x1
258 #define OCTNET_CMD_VLAN_FILTER_ENABLE 0x1
259 #define OCTNET_CMD_VLAN_FILTER_DISABLE 0x0
261 #define OCTNET_CMD_FAIL 0x1
263 #define SEAPI_CMD_FEC_SET 0x0
264 #define SEAPI_CMD_FEC_SET_DISABLE 0x0
265 #define SEAPI_CMD_FEC_SET_RS 0x1
266 #define SEAPI_CMD_FEC_GET 0x1
268 #define SEAPI_CMD_SPEED_SET 0x2
269 #define SEAPI_CMD_SPEED_GET 0x3
271 #define OPCODE_NIC_VF_PORT_STATS 0x22
273 #define LIO_CMD_WAIT_TM 100
275 /* RX(packets coming from wire) Checksum verification flags */
277 #define CNNIC_L4SUM_VERIFIED 0x1
278 #define CNNIC_IPSUM_VERIFIED 0x2
279 #define CNNIC_TUN_CSUM_VERIFIED 0x4
280 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED)
282 /*LROIPV4 and LROIPV6 Flags*/
283 #define OCTNIC_LROIPV4 0x1
284 #define OCTNIC_LROIPV6 0x2
286 /* Interface flags communicated between host driver and core app. */
287 enum octnet_ifflags {
288 OCTNET_IFFLAG_PROMISC = 0x01,
289 OCTNET_IFFLAG_ALLMULTI = 0x02,
290 OCTNET_IFFLAG_MULTICAST = 0x04,
291 OCTNET_IFFLAG_BROADCAST = 0x08,
292 OCTNET_IFFLAG_UNICAST = 0x10
316 #ifdef __BIG_ENDIAN_BITFIELD
319 u64 more:6; /* How many udd words follow the command */
346 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd))
348 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */
349 #define LIO_SOFTCMDRESP_IH2 40
350 #define LIO_SOFTCMDRESP_IH3 (40 + 8)
352 #define LIO_PCICMD_O2 24
353 #define LIO_PCICMD_O3 (24 + 8)
355 /* Instruction Header(DPI) - for OCTEON-III models */
356 struct octeon_instr_ih3 {
357 #ifdef __BIG_ENDIAN_BITFIELD
362 /** Gather indicator 1=gather*/
365 /** Data length OR no. of entries in gather list */
368 /** Front Data size */
374 /** PKI port kind - PKIND */
384 /** PKI port kind - PKIND */
390 /** Front Data size */
393 /** Data length OR no. of entries in gather list */
396 /** Gather indicator 1=gather*/
405 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */
406 /** BIG ENDIAN format. */
407 struct octeon_instr_pki_ih3 {
408 #ifdef __BIG_ENDIAN_BITFIELD
413 /** Raw mode indicator 1 = RAW */
478 /** Raw mode indicator 1 = RAW */
487 /** Instruction Header */
488 struct octeon_instr_ih2 {
489 #ifdef __BIG_ENDIAN_BITFIELD
490 /** Raw mode indicator 1 = RAW */
493 /** Gather indicator 1=gather*/
496 /** Data length OR no. of entries in gather list */
499 /** Front Data size */
502 /** Packet Order / Work Unit selection (1 of 8)*/
505 /** Core group selection (1 of 16) */
508 /** Short Raw Packet Indicator 1=short raw pkt */
523 /** Short Raw Packet Indicator 1=short raw pkt */
526 /** Core group selection (1 of 16) */
529 /** Packet Order / Work Unit selection (1 of 8)*/
532 /** Front Data size */
535 /** Data length OR no. of entries in gather list */
538 /** Gather indicator 1=gather*/
541 /** Raw mode indicator 1 = RAW */
546 /** Input Request Header */
547 struct octeon_instr_irh {
548 #ifdef __BIG_ENDIAN_BITFIELD
555 u64 ossp:32; /* opcode/subcode specific parameters */
557 u64 ossp:32; /* opcode/subcode specific parameters */
567 /** Return Data Parameters */
568 struct octeon_instr_rdp {
569 #ifdef __BIG_ENDIAN_BITFIELD
580 /** Receive Header */
582 #ifdef __BIG_ENDIAN_BITFIELD
587 u64 len:3; /** additional 64-bit words */
589 u64 ossp:32; /** opcode/subcode specific parameters */
594 u64 len:3; /** additional 64-bit words */
598 u64 csum_verified:3; /** checksum verified. */
599 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */
601 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */
606 u64 len:3; /** additional 64-bit words */
609 u64 max_nic_ports:10;
617 u64 len:3; /** additional 64-bit words */
625 u64 ossp:32; /** opcode/subcode specific parameters */
627 u64 len:3; /** additional 64-bit words */
632 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */
634 u64 has_hwtstamp:1; /** 1 = has hwtstamp */
635 u64 csum_verified:3; /** checksum verified. */
639 u64 len:3; /** additional 64-bit words */
647 u64 max_nic_ports:10;
650 u64 len:3; /** additional 64-bit words */
658 u64 len:3; /** additional 64-bit words */
665 #define OCT_RH_SIZE (sizeof(union octeon_rh))
667 union octnic_packet_params {
670 #ifdef __BIG_ENDIAN_BITFIELD
672 u32 ip_csum:1; /* Perform IP header checksum(s) */
673 /* Perform Outer transport header checksum */
674 u32 transport_csum:1;
675 /* Find tunnel, and perform transport csum. */
677 u32 tsflag:1; /* Timestamp this packet */
678 u32 ipsec_ops:4; /* IPsec operation */
683 u32 transport_csum:1;
690 /** Status of a RGMII Link on Octeon as seen by core driver. */
691 union oct_link_status {
695 #ifdef __BIG_ENDIAN_BITFIELD
722 LIO_PHY_PORT_TP = 0x0,
723 LIO_PHY_PORT_FIBRE = 0x1,
724 LIO_PHY_PORT_UNKNOWN,
727 /** The txpciq info passed to host from the firmware */
733 #ifdef __BIG_ENDIAN_BITFIELD
755 /** The rxpciq info passed to host from the firmware */
761 #ifdef __BIG_ENDIAN_BITFIELD
771 /** Information for a OCTEON ethernet interface shared between core & host. */
772 struct oct_link_info {
773 union oct_link_status link;
776 #ifdef __BIG_ENDIAN_BITFIELD
778 u64 macaddr_is_admin_asgnd:1;
780 u64 macaddr_spoofchk:1;
788 u64 macaddr_spoofchk:1;
790 u64 macaddr_is_admin_asgnd:1;
794 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF];
795 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF];
798 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info))
800 struct liquidio_if_cfg_info {
801 u64 iqmask; /** mask for IQs enabled for the port */
802 u64 oqmask; /** mask for OQs enabled for the port */
803 struct oct_link_info linfo; /** initial link information */
804 char liquidio_firmware_version[32];
807 /** Stats for each NIC port in RX direction. */
808 struct nic_rx_stats {
809 /* link-level stats */
810 u64 total_rcvd; /* Received packets */
811 u64 bytes_rcvd; /* Octets of received packets */
812 u64 total_bcst; /* Number of non-dropped L2 broadcast packets */
813 u64 total_mcst; /* Number of non-dropped L2 multicast packets */
814 u64 runts; /* Packets shorter than allowed */
815 u64 ctl_rcvd; /* Received PAUSE packets */
816 u64 fifo_err; /* Packets dropped due to RX FIFO full */
817 u64 dmac_drop; /* Packets dropped by the DMAC filter */
818 u64 fcs_err; /* Sum of fragment, overrun, and FCS errors */
819 u64 jabber_err; /* Packets larger than allowed */
820 u64 l2_err; /* Sum of DMA, parity, PCAM access, no memory,
821 * buffer overflow, malformed L2 header or
822 * length, oversize errors
824 u64 frame_err; /* Sum of IPv4 and L4 checksum errors */
825 u64 red_drops; /* Packets dropped by RED due to buffer
832 u64 fw_total_fwd_bytes;
843 u64 fw_lro_pkts; /* Number of packets that are LROed */
844 u64 fw_lro_octs; /* Number of octets that are LROed */
845 u64 fw_total_lro; /* Number of LRO packets formed */
846 u64 fw_lro_aborts; /* Number of times LRO of packet aborted */
847 u64 fw_lro_aborts_port;
848 u64 fw_lro_aborts_seq;
849 u64 fw_lro_aborts_tsval;
850 u64 fw_lro_aborts_timer; /* Timer setting error */
851 /* intrmod: packet forward rate */
855 /** Stats for each NIC port in RX direction. */
856 struct nic_tx_stats {
857 /* link-level stats */
858 u64 total_pkts_sent; /* Total frames sent on the interface */
859 u64 total_bytes_sent; /* Total octets sent on the interface */
860 u64 mcast_pkts_sent; /* Packets sent to the multicast DMAC */
861 u64 bcast_pkts_sent; /* Packets sent to a broadcast DMAC */
862 u64 ctl_sent; /* Control/PAUSE packets sent */
863 u64 one_collision_sent; /* Packets sent that experienced a
864 * single collision before successful
867 u64 multi_collision_sent; /* Packets sent that experienced
868 * multiple collisions before successful
871 u64 max_collision_fail; /* Packets dropped due to excessive
874 u64 max_deferral_fail; /* Packets not sent due to max
877 u64 fifo_err; /* Packets sent that experienced a
878 * transmit underflow and were
881 u64 runts; /* Packets sent with an octet count
884 u64 total_collisions; /* Packets dropped due to excessive
891 u64 fw_total_fwd_bytes;
892 u64 fw_total_mcast_sent;
893 u64 fw_total_bcast_sent;
898 u64 fw_tso; /* number of tso requests */
899 u64 fw_tso_fwd; /* number of packets segmented in tso */
904 struct oct_link_stats {
905 struct nic_rx_stats fromwire;
906 struct nic_tx_stats fromhost;
910 static inline int opcode_slow_path(union octeon_rh *rh)
912 u16 subcode1, subcode2;
914 subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode);
915 subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA);
917 return (subcode2 != subcode1);
920 #define LIO68XX_LED_CTRL_ADDR 0x3501
921 #define LIO68XX_LED_CTRL_CFGON 0x1f
922 #define LIO68XX_LED_CTRL_CFGOFF 0x100
923 #define LIO68XX_LED_BEACON_ADDR 0x3508
924 #define LIO68XX_LED_BEACON_CFGON 0x47fd
925 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc
926 #define VITESSE_PHY_GPIO_DRIVEON 0x1
927 #define VITESSE_PHY_GPIO_CFG 0x8
928 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4
929 #define VITESSE_PHY_GPIO_HIGH 0x2
930 #define VITESSE_PHY_GPIO_LOW 0x3
931 #define LED_IDENTIFICATION_ON 0x1
932 #define LED_IDENTIFICATION_OFF 0x0
933 #define LIO23XX_COPPERHEAD_LED_GPIO 0x2
935 struct oct_mdio_cmd {
943 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats))
945 struct oct_intrmod_cfg {
951 u64 rx_maxcnt_trigger;
952 u64 rx_mincnt_trigger;
953 u64 rx_maxtmr_trigger;
954 u64 rx_mintmr_trigger;
955 u64 tx_mincnt_trigger;
956 u64 tx_maxcnt_trigger;
962 #define BASE_QUEUE_NOT_REQUESTED 65535
964 union oct_nic_if_cfg {
967 #ifdef __BIG_ENDIAN_BITFIELD
983 struct lio_trusted_vf {
986 uint64_t reserved: 55;
990 s64 sec; /* seconds */
991 s64 nsec; /* nanoseconds */
994 struct lio_vf_rep_stats {
1004 enum lio_vf_rep_req_type {
1005 LIO_VF_REP_REQ_NONE,
1006 LIO_VF_REP_REQ_STATE,
1008 LIO_VF_REP_REQ_STATS,
1009 LIO_VF_REP_REQ_DEVNAME
1013 LIO_VF_REP_STATE_DOWN,
1017 #define LIO_IF_NAME_SIZE 16
1018 struct lio_vf_rep_req {
1024 struct lio_vf_rep_name {
1025 char name[LIO_IF_NAME_SIZE];
1028 struct lio_vf_rep_mtu {
1033 struct lio_vf_rep_state {
1040 struct lio_vf_rep_resp {