drivers/net/ethernet/broadcom/genet/bcmgenet.c

   1 /*
   2  * Broadcom GENET (Gigabit Ethernet) controller driver
   3  *
   4  * Copyright (c) 2014 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18  */
  19
  20 #define pr_fmt(fmt)                             "bcmgenet: " fmt
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/sched.h>
  25 #include <linux/types.h>
  26 #include <linux/fcntl.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/string.h>
  29 #include <linux/if_ether.h>
  30 #include <linux/init.h>
  31 #include <linux/errno.h>
  32 #include <linux/delay.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/pm.h>
  36 #include <linux/clk.h>
  37 #include <linux/of.h>
  38 #include <linux/of_address.h>
  39 #include <linux/of_irq.h>
  40 #include <linux/of_net.h>
  41 #include <linux/of_platform.h>
  42 #include <net/arp.h>
  43
  44 #include <linux/mii.h>
  45 #include <linux/ethtool.h>
  46 #include <linux/netdevice.h>
  47 #include <linux/inetdevice.h>
  48 #include <linux/etherdevice.h>
  49 #include <linux/skbuff.h>
  50 #include <linux/in.h>
  51 #include <linux/ip.h>
  52 #include <linux/ipv6.h>
  53 #include <linux/phy.h>
  54
  55 #include <asm/unaligned.h>
  56
  57 #include "bcmgenet.h"
  58
  59 /* Maximum number of hardware queues, downsized if needed */
  60 #define GENET_MAX_MQ_CNT        4
  61
  62 /* Default highest priority queue for multi queue support */
  63 #define GENET_Q0_PRIORITY       0
  64
  65 #define GENET_DEFAULT_BD_CNT    \
  66         (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
  67
  68 #define RX_BUF_LENGTH           2048
  69 #define SKB_ALIGNMENT           32
  70
  71 /* Tx/Rx DMA register offset, skip 256 descriptors */
  72 #define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
  73 #define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
  74
  75 #define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
  76                                 TOTAL_DESC * DMA_DESC_SIZE)
  77
  78 #define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
  79                                 TOTAL_DESC * DMA_DESC_SIZE)
  80
  81 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
  82                                                 void __iomem *d, u32 value)
  83 {
  84         __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
  85 }
  86
  87 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
  88                                                 void __iomem *d)
  89 {
  90         return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
  91 }
  92
  93 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
  94                                     void __iomem *d,
  95                                     dma_addr_t addr)
  96 {
  97         __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
  98
  99         /* Register writes to GISB bus can take couple hundred nanoseconds
 100          * and are done for each packet, save these expensive writes unless
 101          * the platform is explicitely configured for 64-bits/LPAE.
 102          */
 103 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 104         if (priv->hw_params->flags & GENET_HAS_40BITS)
 105                 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
 106 #endif
 107 }
 108
 109 /* Combined address + length/status setter */
 110 static inline void dmadesc_set(struct bcmgenet_priv *priv,
 111                                 void __iomem *d, dma_addr_t addr, u32 val)
 112 {
 113         dmadesc_set_length_status(priv, d, val);
 114         dmadesc_set_addr(priv, d, addr);
 115 }
 116
 117 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
 118                                           void __iomem *d)
 119 {
 120         dma_addr_t addr;
 121
 122         addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
 123
 124         /* Register writes to GISB bus can take couple hundred nanoseconds
 125          * and are done for each packet, save these expensive writes unless
 126          * the platform is explicitely configured for 64-bits/LPAE.
 127          */
 128 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 129         if (priv->hw_params->flags & GENET_HAS_40BITS)
 130                 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
 131 #endif
 132         return addr;
 133 }
 134
 135 #define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
 136
 137 #define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
 138                                 NETIF_MSG_LINK)
 139
 140 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
 141 {
 142         if (GENET_IS_V1(priv))
 143                 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
 144         else
 145                 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
 146 }
 147
 148 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 149 {
 150         if (GENET_IS_V1(priv))
 151                 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
 152         else
 153                 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
 154 }
 155
 156 /* These macros are defined to deal with register map change
 157  * between GENET1.1 and GENET2. Only those currently being used
 158  * by driver are defined.
 159  */
 160 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
 161 {
 162         if (GENET_IS_V1(priv))
 163                 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
 164         else
 165                 return __raw_readl(priv->base +
 166                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 167 }
 168
 169 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 170 {
 171         if (GENET_IS_V1(priv))
 172                 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
 173         else
 174                 __raw_writel(val, priv->base +
 175                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 176 }
 177
 178 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
 179 {
 180         if (GENET_IS_V1(priv))
 181                 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
 182         else
 183                 return __raw_readl(priv->base +
 184                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 185 }
 186
 187 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
 188 {
 189         if (GENET_IS_V1(priv))
 190                 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
 191         else
 192                 __raw_writel(val, priv->base +
 193                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 194 }
 195
 196 /* RX/TX DMA register accessors */
 197 enum dma_reg {
 198         DMA_RING_CFG = 0,
 199         DMA_CTRL,
 200         DMA_STATUS,
 201         DMA_SCB_BURST_SIZE,
 202         DMA_ARB_CTRL,
 203         DMA_PRIORITY,
 204         DMA_RING_PRIORITY,
 205 };
 206
 207 static const u8 bcmgenet_dma_regs_v3plus[] = {
 208         [DMA_RING_CFG]          = 0x00,
 209         [DMA_CTRL]              = 0x04,
 210         [DMA_STATUS]            = 0x08,
 211         [DMA_SCB_BURST_SIZE]    = 0x0C,
 212         [DMA_ARB_CTRL]          = 0x2C,
 213         [DMA_PRIORITY]          = 0x30,
 214         [DMA_RING_PRIORITY]     = 0x38,
 215 };
 216
 217 static const u8 bcmgenet_dma_regs_v2[] = {
 218         [DMA_RING_CFG]          = 0x00,
 219         [DMA_CTRL]              = 0x04,
 220         [DMA_STATUS]            = 0x08,
 221         [DMA_SCB_BURST_SIZE]    = 0x0C,
 222         [DMA_ARB_CTRL]          = 0x30,
 223         [DMA_PRIORITY]          = 0x34,
 224         [DMA_RING_PRIORITY]     = 0x3C,
 225 };
 226
 227 static const u8 bcmgenet_dma_regs_v1[] = {
 228         [DMA_CTRL]              = 0x00,
 229         [DMA_STATUS]            = 0x04,
 230         [DMA_SCB_BURST_SIZE]    = 0x0C,
 231         [DMA_ARB_CTRL]          = 0x30,
 232         [DMA_PRIORITY]          = 0x34,
 233         [DMA_RING_PRIORITY]     = 0x3C,
 234 };
 235
 236 /* Set at runtime once bcmgenet version is known */
 237 static const u8 *bcmgenet_dma_regs;
 238
 239 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
 240 {
 241         return netdev_priv(dev_get_drvdata(dev));
 242 }
 243
 244 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
 245                                         enum dma_reg r)
 246 {
 247         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 248                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 249 }
 250
 251 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
 252                                         u32 val, enum dma_reg r)
 253 {
 254         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 255                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 256 }
 257
 258 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
 259                                         enum dma_reg r)
 260 {
 261         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 262                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 263 }
 264
 265 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
 266                                         u32 val, enum dma_reg r)
 267 {
 268         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 269                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 270 }
 271
 272 /* RDMA/TDMA ring registers and accessors
 273  * we merge the common fields and just prefix with T/D the registers
 274  * having different meaning depending on the direction
 275  */
 276 enum dma_ring_reg {
 277         TDMA_READ_PTR = 0,
 278         RDMA_WRITE_PTR = TDMA_READ_PTR,
 279         TDMA_READ_PTR_HI,
 280         RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
 281         TDMA_CONS_INDEX,
 282         RDMA_PROD_INDEX = TDMA_CONS_INDEX,
 283         TDMA_PROD_INDEX,
 284         RDMA_CONS_INDEX = TDMA_PROD_INDEX,
 285         DMA_RING_BUF_SIZE,
 286         DMA_START_ADDR,
 287         DMA_START_ADDR_HI,
 288         DMA_END_ADDR,
 289         DMA_END_ADDR_HI,
 290         DMA_MBUF_DONE_THRESH,
 291         TDMA_FLOW_PERIOD,
 292         RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
 293         TDMA_WRITE_PTR,
 294         RDMA_READ_PTR = TDMA_WRITE_PTR,
 295         TDMA_WRITE_PTR_HI,
 296         RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
 297 };
 298
 299 /* GENET v4 supports 40-bits pointer addressing
 300  * for obvious reasons the LO and HI word parts
 301  * are contiguous, but this offsets the other
 302  * registers.
 303  */
 304 static const u8 genet_dma_ring_regs_v4[] = {
 305         [TDMA_READ_PTR]                 = 0x00,
 306         [TDMA_READ_PTR_HI]              = 0x04,
 307         [TDMA_CONS_INDEX]               = 0x08,
 308         [TDMA_PROD_INDEX]               = 0x0C,
 309         [DMA_RING_BUF_SIZE]             = 0x10,
 310         [DMA_START_ADDR]                = 0x14,
 311         [DMA_START_ADDR_HI]             = 0x18,
 312         [DMA_END_ADDR]                  = 0x1C,
 313         [DMA_END_ADDR_HI]               = 0x20,
 314         [DMA_MBUF_DONE_THRESH]          = 0x24,
 315         [TDMA_FLOW_PERIOD]              = 0x28,
 316         [TDMA_WRITE_PTR]                = 0x2C,
 317         [TDMA_WRITE_PTR_HI]             = 0x30,
 318 };
 319
 320 static const u8 genet_dma_ring_regs_v123[] = {
 321         [TDMA_READ_PTR]                 = 0x00,
 322         [TDMA_CONS_INDEX]               = 0x04,
 323         [TDMA_PROD_INDEX]               = 0x08,
 324         [DMA_RING_BUF_SIZE]             = 0x0C,
 325         [DMA_START_ADDR]                = 0x10,
 326         [DMA_END_ADDR]                  = 0x14,
 327         [DMA_MBUF_DONE_THRESH]          = 0x18,
 328         [TDMA_FLOW_PERIOD]              = 0x1C,
 329         [TDMA_WRITE_PTR]                = 0x20,
 330 };
 331
 332 /* Set at runtime once GENET version is known */
 333 static const u8 *genet_dma_ring_regs;
 334
 335 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
 336                                                 unsigned int ring,
 337                                                 enum dma_ring_reg r)
 338 {
 339         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 340                         (DMA_RING_SIZE * ring) +
 341                         genet_dma_ring_regs[r]);
 342 }
 343
 344 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
 345                                                 unsigned int ring,
 346                                                 u32 val,
 347                                                 enum dma_ring_reg r)
 348 {
 349         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 350                         (DMA_RING_SIZE * ring) +
 351                         genet_dma_ring_regs[r]);
 352 }
 353
 354 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
 355                                                 unsigned int ring,
 356                                                 enum dma_ring_reg r)
 357 {
 358         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 359                         (DMA_RING_SIZE * ring) +
 360                         genet_dma_ring_regs[r]);
 361 }
 362
 363 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
 364                                                 unsigned int ring,
 365                                                 u32 val,
 366                                                 enum dma_ring_reg r)
 367 {
 368         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 369                         (DMA_RING_SIZE * ring) +
 370                         genet_dma_ring_regs[r]);
 371 }
 372
 373 static int bcmgenet_get_settings(struct net_device *dev,
 374                 struct ethtool_cmd *cmd)
 375 {
 376         struct bcmgenet_priv *priv = netdev_priv(dev);
 377
 378         if (!netif_running(dev))
 379                 return -EINVAL;
 380
 381         if (!priv->phydev)
 382                 return -ENODEV;
 383
 384         return phy_ethtool_gset(priv->phydev, cmd);
 385 }
 386
 387 static int bcmgenet_set_settings(struct net_device *dev,
 388                 struct ethtool_cmd *cmd)
 389 {
 390         struct bcmgenet_priv *priv = netdev_priv(dev);
 391
 392         if (!netif_running(dev))
 393                 return -EINVAL;
 394
 395         if (!priv->phydev)
 396                 return -ENODEV;
 397
 398         return phy_ethtool_sset(priv->phydev, cmd);
 399 }
 400
 401 static int bcmgenet_set_rx_csum(struct net_device *dev,
 402                                 netdev_features_t wanted)
 403 {
 404         struct bcmgenet_priv *priv = netdev_priv(dev);
 405         u32 rbuf_chk_ctrl;
 406         bool rx_csum_en;
 407
 408         rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
 409
 410         rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
 411
 412         /* enable rx checksumming */
 413         if (rx_csum_en)
 414                 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
 415         else
 416                 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
 417         priv->desc_rxchk_en = rx_csum_en;
 418
 419         /* If UniMAC forwards CRC, we need to skip over it to get
 420          * a valid CHK bit to be set in the per-packet status word
 421         */
 422         if (rx_csum_en && priv->crc_fwd_en)
 423                 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
 424         else
 425                 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
 426
 427         bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
 428
 429         return 0;
 430 }
 431
 432 static int bcmgenet_set_tx_csum(struct net_device *dev,
 433                                 netdev_features_t wanted)
 434 {
 435         struct bcmgenet_priv *priv = netdev_priv(dev);
 436         bool desc_64b_en;
 437         u32 tbuf_ctrl, rbuf_ctrl;
 438
 439         tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
 440         rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
 441
 442         desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
 443
 444         /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
 445         if (desc_64b_en) {
 446                 tbuf_ctrl |= RBUF_64B_EN;
 447                 rbuf_ctrl |= RBUF_64B_EN;
 448         } else {
 449                 tbuf_ctrl &= ~RBUF_64B_EN;
 450                 rbuf_ctrl &= ~RBUF_64B_EN;
 451         }
 452         priv->desc_64b_en = desc_64b_en;
 453
 454         bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
 455         bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
 456
 457         return 0;
 458 }
 459
 460 static int bcmgenet_set_features(struct net_device *dev,
 461                 netdev_features_t features)
 462 {
 463         netdev_features_t changed = features ^ dev->features;
 464         netdev_features_t wanted = dev->wanted_features;
 465         int ret = 0;
 466
 467         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
 468                 ret = bcmgenet_set_tx_csum(dev, wanted);
 469         if (changed & (NETIF_F_RXCSUM))
 470                 ret = bcmgenet_set_rx_csum(dev, wanted);
 471
 472         return ret;
 473 }
 474
 475 static u32 bcmgenet_get_msglevel(struct net_device *dev)
 476 {
 477         struct bcmgenet_priv *priv = netdev_priv(dev);
 478
 479         return priv->msg_enable;
 480 }
 481
 482 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
 483 {
 484         struct bcmgenet_priv *priv = netdev_priv(dev);
 485
 486         priv->msg_enable = level;
 487 }
 488
 489 /* standard ethtool support functions. */
 490 enum bcmgenet_stat_type {
 491         BCMGENET_STAT_NETDEV = -1,
 492         BCMGENET_STAT_MIB_RX,
 493         BCMGENET_STAT_MIB_TX,
 494         BCMGENET_STAT_RUNT,
 495         BCMGENET_STAT_MISC,
 496 };
 497
 498 struct bcmgenet_stats {
 499         char stat_string[ETH_GSTRING_LEN];
 500         int stat_sizeof;
 501         int stat_offset;
 502         enum bcmgenet_stat_type type;
 503         /* reg offset from UMAC base for misc counters */
 504         u16 reg_offset;
 505 };
 506
 507 #define STAT_NETDEV(m) { \
 508         .stat_string = __stringify(m), \
 509         .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
 510         .stat_offset = offsetof(struct net_device_stats, m), \
 511         .type = BCMGENET_STAT_NETDEV, \
 512 }
 513
 514 #define STAT_GENET_MIB(str, m, _type) { \
 515         .stat_string = str, \
 516         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 517         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 518         .type = _type, \
 519 }
 520
 521 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
 522 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
 523 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
 524
 525 #define STAT_GENET_MISC(str, m, offset) { \
 526         .stat_string = str, \
 527         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 528         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 529         .type = BCMGENET_STAT_MISC, \
 530         .reg_offset = offset, \
 531 }
 532
 533
 534 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
 535  * between the end of TX stats and the beginning of the RX RUNT
 536  */
 537 #define BCMGENET_STAT_OFFSET    0xc
 538
 539 /* Hardware counters must be kept in sync because the order/offset
 540  * is important here (order in structure declaration = order in hardware)
 541  */
 542 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
 543         /* general stats */
 544         STAT_NETDEV(rx_packets),
 545         STAT_NETDEV(tx_packets),
 546         STAT_NETDEV(rx_bytes),
 547         STAT_NETDEV(tx_bytes),
 548         STAT_NETDEV(rx_errors),
 549         STAT_NETDEV(tx_errors),
 550         STAT_NETDEV(rx_dropped),
 551         STAT_NETDEV(tx_dropped),
 552         STAT_NETDEV(multicast),
 553         /* UniMAC RSV counters */
 554         STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
 555         STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
 556         STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
 557         STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
 558         STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
 559         STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
 560         STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
 561         STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
 562         STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
 563         STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
 564         STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
 565         STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
 566         STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
 567         STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
 568         STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
 569         STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
 570         STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
 571         STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
 572         STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
 573         STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
 574         STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
 575         STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
 576         STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
 577         STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
 578         STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
 579         STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
 580         STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
 581         STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
 582         STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
 583         /* UniMAC TSV counters */
 584         STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
 585         STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
 586         STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
 587         STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
 588         STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
 589         STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
 590         STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
 591         STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
 592         STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
 593         STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
 594         STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
 595         STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
 596         STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
 597         STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
 598         STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
 599         STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
 600         STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
 601         STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
 602         STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
 603         STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
 604         STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
 605         STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
 606         STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
 607         STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
 608         STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
 609         STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
 610         STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
 611         STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
 612         STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
 613         /* UniMAC RUNT counters */
 614         STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
 615         STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
 616         STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
 617         STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 618         /* Misc UniMAC counters */
 619         STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
 620                         UMAC_RBUF_OVFL_CNT),
 621         STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
 622         STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 623 };
 624
 625 #define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
 626
 627 static void bcmgenet_get_drvinfo(struct net_device *dev,
 628                 struct ethtool_drvinfo *info)
 629 {
 630         strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
 631         strlcpy(info->version, "v2.0", sizeof(info->version));
 632         info->n_stats = BCMGENET_STATS_LEN;
 633
 634 }
 635
 636 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
 637 {
 638         switch (string_set) {
 639         case ETH_SS_STATS:
 640                 return BCMGENET_STATS_LEN;
 641         default:
 642                 return -EOPNOTSUPP;
 643         }
 644 }
 645
 646 static void bcmgenet_get_strings(struct net_device *dev,
 647                                 u32 stringset, u8 *data)
 648 {
 649         int i;
 650
 651         switch (stringset) {
 652         case ETH_SS_STATS:
 653                 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 654                         memcpy(data + i * ETH_GSTRING_LEN,
 655                                 bcmgenet_gstrings_stats[i].stat_string,
 656                                 ETH_GSTRING_LEN);
 657                 }
 658                 break;
 659         }
 660 }
 661
 662 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 663 {
 664         int i, j = 0;
 665
 666         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 667                 const struct bcmgenet_stats *s;
 668                 u8 offset = 0;
 669                 u32 val = 0;
 670                 char *p;
 671
 672                 s = &bcmgenet_gstrings_stats[i];
 673                 switch (s->type) {
 674                 case BCMGENET_STAT_NETDEV:
 675                         continue;
 676                 case BCMGENET_STAT_MIB_RX:
 677                 case BCMGENET_STAT_MIB_TX:
 678                 case BCMGENET_STAT_RUNT:
 679                         if (s->type != BCMGENET_STAT_MIB_RX)
 680                                 offset = BCMGENET_STAT_OFFSET;
 681                         val = bcmgenet_umac_readl(priv, UMAC_MIB_START +
 682                                                                 j + offset);
 683                         break;
 684                 case BCMGENET_STAT_MISC:
 685                         val = bcmgenet_umac_readl(priv, s->reg_offset);
 686                         /* clear if overflowed */
 687                         if (val == ~0)
 688                                 bcmgenet_umac_writel(priv, 0, s->reg_offset);
 689                         break;
 690                 }
 691
 692                 j += s->stat_sizeof;
 693                 p = (char *)priv + s->stat_offset;
 694                 *(u32 *)p = val;
 695         }
 696 }
 697
 698 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
 699                                         struct ethtool_stats *stats,
 700                                         u64 *data)
 701 {
 702         struct bcmgenet_priv *priv = netdev_priv(dev);
 703         int i;
 704
 705         if (netif_running(dev))
 706                 bcmgenet_update_mib_counters(priv);
 707
 708         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 709                 const struct bcmgenet_stats *s;
 710                 char *p;
 711
 712                 s = &bcmgenet_gstrings_stats[i];
 713                 if (s->type == BCMGENET_STAT_NETDEV)
 714                         p = (char *)&dev->stats;
 715                 else
 716                         p = (char *)priv;
 717                 p += s->stat_offset;
 718                 data[i] = *(u32 *)p;
 719         }
 720 }
 721
 722 /* standard ethtool support functions. */
 723 static struct ethtool_ops bcmgenet_ethtool_ops = {
 724         .get_strings            = bcmgenet_get_strings,
 725         .get_sset_count         = bcmgenet_get_sset_count,
 726         .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
 727         .get_settings           = bcmgenet_get_settings,
 728         .set_settings           = bcmgenet_set_settings,
 729         .get_drvinfo            = bcmgenet_get_drvinfo,
 730         .get_link               = ethtool_op_get_link,
 731         .get_msglevel           = bcmgenet_get_msglevel,
 732         .set_msglevel           = bcmgenet_set_msglevel,
 733 };
 734
 735 /* Power down the unimac, based on mode. */
 736 static void bcmgenet_power_down(struct bcmgenet_priv *priv,
 737                                 enum bcmgenet_power_mode mode)
 738 {
 739         u32 reg;
 740
 741         switch (mode) {
 742         case GENET_POWER_CABLE_SENSE:
 743                 phy_detach(priv->phydev);
 744                 break;
 745
 746         case GENET_POWER_PASSIVE:
 747                 /* Power down LED */
 748                 bcmgenet_mii_reset(priv->dev);
 749                 if (priv->hw_params->flags & GENET_HAS_EXT) {
 750                         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 751                         reg |= (EXT_PWR_DOWN_PHY |
 752                                 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
 753                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 754                 }
 755                 break;
 756         default:
 757                 break;
 758         }
 759 }
 760
 761 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
 762                                 enum bcmgenet_power_mode mode)
 763 {
 764         u32 reg;
 765
 766         if (!(priv->hw_params->flags & GENET_HAS_EXT))
 767                 return;
 768
 769         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 770
 771         switch (mode) {
 772         case GENET_POWER_PASSIVE:
 773                 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
 774                                 EXT_PWR_DOWN_BIAS);
 775                 /* fallthrough */
 776         case GENET_POWER_CABLE_SENSE:
 777                 /* enable APD */
 778                 reg |= EXT_PWR_DN_EN_LD;
 779                 break;
 780         default:
 781                 break;
 782         }
 783
 784         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 785         bcmgenet_mii_reset(priv->dev);
 786 }
 787
 788 /* ioctl handle special commands that are not present in ethtool. */
 789 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 790 {
 791         struct bcmgenet_priv *priv = netdev_priv(dev);
 792         int val = 0;
 793
 794         if (!netif_running(dev))
 795                 return -EINVAL;
 796
 797         switch (cmd) {
 798         case SIOCGMIIPHY:
 799         case SIOCGMIIREG:
 800         case SIOCSMIIREG:
 801                 if (!priv->phydev)
 802                         val = -ENODEV;
 803                 else
 804                         val = phy_mii_ioctl(priv->phydev, rq, cmd);
 805                 break;
 806
 807         default:
 808                 val = -EINVAL;
 809                 break;
 810         }
 811
 812         return val;
 813 }
 814
 815 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
 816                                          struct bcmgenet_tx_ring *ring)
 817 {
 818         struct enet_cb *tx_cb_ptr;
 819
 820         tx_cb_ptr = ring->cbs;
 821         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
 822         tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE;
 823         /* Advancing local write pointer */
 824         if (ring->write_ptr == ring->end_ptr)
 825                 ring->write_ptr = ring->cb_ptr;
 826         else
 827                 ring->write_ptr++;
 828
 829         return tx_cb_ptr;
 830 }
 831
 832 /* Simple helper to free a control block's resources */
 833 static void bcmgenet_free_cb(struct enet_cb *cb)
 834 {
 835         dev_kfree_skb_any(cb->skb);
 836         cb->skb = NULL;
 837         dma_unmap_addr_set(cb, dma_addr, 0);
 838 }
 839
 840 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
 841                                                   struct bcmgenet_tx_ring *ring)
 842 {
 843         bcmgenet_intrl2_0_writel(priv,
 844                         UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
 845                         INTRL2_CPU_MASK_SET);
 846 }
 847
 848 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
 849                                                  struct bcmgenet_tx_ring *ring)
 850 {
 851         bcmgenet_intrl2_0_writel(priv,
 852                         UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
 853                         INTRL2_CPU_MASK_CLEAR);
 854 }
 855
 856 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
 857                                                 struct bcmgenet_tx_ring *ring)
 858 {
 859         bcmgenet_intrl2_1_writel(priv,
 860                         (1 << ring->index), INTRL2_CPU_MASK_CLEAR);
 861         priv->int1_mask &= ~(1 << ring->index);
 862 }
 863
 864 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
 865                                                 struct bcmgenet_tx_ring *ring)
 866 {
 867         bcmgenet_intrl2_1_writel(priv,
 868                         (1 << ring->index), INTRL2_CPU_MASK_SET);
 869         priv->int1_mask |= (1 << ring->index);
 870 }
 871
 872 /* Unlocked version of the reclaim routine */
 873 static void __bcmgenet_tx_reclaim(struct net_device *dev,
 874                                 struct bcmgenet_tx_ring *ring)
 875 {
 876         struct bcmgenet_priv *priv = netdev_priv(dev);
 877         int last_tx_cn, last_c_index, num_tx_bds;
 878         struct enet_cb *tx_cb_ptr;
 879         struct netdev_queue *txq;
 880         unsigned int c_index;
 881
 882         /* Compute how many buffers are transmited since last xmit call */
 883         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
 884         txq = netdev_get_tx_queue(dev, ring->queue);
 885
 886         last_c_index = ring->c_index;
 887         num_tx_bds = ring->size;
 888
 889         c_index &= (num_tx_bds - 1);
 890
 891         if (c_index >= last_c_index)
 892                 last_tx_cn = c_index - last_c_index;
 893         else
 894                 last_tx_cn = num_tx_bds - last_c_index + c_index;
 895
 896         netif_dbg(priv, tx_done, dev,
 897                         "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
 898                         __func__, ring->index,
 899                         c_index, last_tx_cn, last_c_index);
 900
 901         /* Reclaim transmitted buffers */
 902         while (last_tx_cn-- > 0) {
 903                 tx_cb_ptr = ring->cbs + last_c_index;
 904                 if (tx_cb_ptr->skb) {
 905                         dev->stats.tx_bytes += tx_cb_ptr->skb->len;
 906                         dma_unmap_single(&dev->dev,
 907                                         dma_unmap_addr(tx_cb_ptr, dma_addr),
 908                                         tx_cb_ptr->skb->len,
 909                                         DMA_TO_DEVICE);
 910                         bcmgenet_free_cb(tx_cb_ptr);
 911                 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
 912                         dev->stats.tx_bytes +=
 913                                 dma_unmap_len(tx_cb_ptr, dma_len);
 914                         dma_unmap_page(&dev->dev,
 915                                         dma_unmap_addr(tx_cb_ptr, dma_addr),
 916                                         dma_unmap_len(tx_cb_ptr, dma_len),
 917                                         DMA_TO_DEVICE);
 918                         dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
 919                 }
 920                 dev->stats.tx_packets++;
 921                 ring->free_bds += 1;
 922
 923                 last_c_index++;
 924                 last_c_index &= (num_tx_bds - 1);
 925         }
 926
 927         if (ring->free_bds > (MAX_SKB_FRAGS + 1))
 928                 ring->int_disable(priv, ring);
 929
 930         if (netif_tx_queue_stopped(txq))
 931                 netif_tx_wake_queue(txq);
 932
 933         ring->c_index = c_index;
 934 }
 935
 936 static void bcmgenet_tx_reclaim(struct net_device *dev,
 937                 struct bcmgenet_tx_ring *ring)
 938 {
 939         unsigned long flags;
 940
 941         spin_lock_irqsave(&ring->lock, flags);
 942         __bcmgenet_tx_reclaim(dev, ring);
 943         spin_unlock_irqrestore(&ring->lock, flags);
 944 }
 945
 946 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
 947 {
 948         struct bcmgenet_priv *priv = netdev_priv(dev);
 949         int i;
 950
 951         if (netif_is_multiqueue(dev)) {
 952                 for (i = 0; i < priv->hw_params->tx_queues; i++)
 953                         bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
 954         }
 955
 956         bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
 957 }
 958
 959 /* Transmits a single SKB (either head of a fragment or a single SKB)
 960  * caller must hold priv->lock
 961  */
 962 static int bcmgenet_xmit_single(struct net_device *dev,
 963                                 struct sk_buff *skb,
 964                                 u16 dma_desc_flags,
 965                                 struct bcmgenet_tx_ring *ring)
 966 {
 967         struct bcmgenet_priv *priv = netdev_priv(dev);
 968         struct device *kdev = &priv->pdev->dev;
 969         struct enet_cb *tx_cb_ptr;
 970         unsigned int skb_len;
 971         dma_addr_t mapping;
 972         u32 length_status;
 973         int ret;
 974
 975         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
 976
 977         if (unlikely(!tx_cb_ptr))
 978                 BUG();
 979
 980         tx_cb_ptr->skb = skb;
 981
 982         skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
 983
 984         mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
 985         ret = dma_mapping_error(kdev, mapping);
 986         if (ret) {
 987                 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
 988                 dev_kfree_skb(skb);
 989                 return ret;
 990         }
 991
 992         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
 993         dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
 994         length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
 995                         (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
 996                         DMA_TX_APPEND_CRC;
 997
 998         if (skb->ip_summed == CHECKSUM_PARTIAL)
 999                 length_status |= DMA_TX_DO_CSUM;
1000
1001         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1002
1003         /* Decrement total BD count and advance our write pointer */
1004         ring->free_bds -= 1;
1005         ring->prod_index += 1;
1006         ring->prod_index &= DMA_P_INDEX_MASK;
1007
1008         return 0;
1009 }
1010
1011 /* Transmit a SKB fragement */
1012 static int bcmgenet_xmit_frag(struct net_device *dev,
1013                                 skb_frag_t *frag,
1014                                 u16 dma_desc_flags,
1015                                 struct bcmgenet_tx_ring *ring)
1016 {
1017         struct bcmgenet_priv *priv = netdev_priv(dev);
1018         struct device *kdev = &priv->pdev->dev;
1019         struct enet_cb *tx_cb_ptr;
1020         dma_addr_t mapping;
1021         int ret;
1022
1023         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1024
1025         if (unlikely(!tx_cb_ptr))
1026                 BUG();
1027         tx_cb_ptr->skb = NULL;
1028
1029         mapping = skb_frag_dma_map(kdev, frag, 0,
1030                 skb_frag_size(frag), DMA_TO_DEVICE);
1031         ret = dma_mapping_error(kdev, mapping);
1032         if (ret) {
1033                 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1034                                 __func__);
1035                 return ret;
1036         }
1037
1038         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1039         dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1040
1041         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1042                         (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1043                         (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1044
1045
1046         ring->free_bds -= 1;
1047         ring->prod_index += 1;
1048         ring->prod_index &= DMA_P_INDEX_MASK;
1049
1050         return 0;
1051 }
1052
1053 /* Reallocate the SKB to put enough headroom in front of it and insert
1054  * the transmit checksum offsets in the descriptors
1055  */
1056 static int bcmgenet_put_tx_csum(struct net_device *dev, struct sk_buff *skb)
1057 {
1058         struct status_64 *status = NULL;
1059         struct sk_buff *new_skb;
1060         u16 offset;
1061         u8 ip_proto;
1062         u16 ip_ver;
1063         u32 tx_csum_info;
1064
1065         if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1066                 /* If 64 byte status block enabled, must make sure skb has
1067                  * enough headroom for us to insert 64B status block.
1068                  */
1069                 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1070                 dev_kfree_skb(skb);
1071                 if (!new_skb) {
1072                         dev->stats.tx_errors++;
1073                         dev->stats.tx_dropped++;
1074                         return -ENOMEM;
1075                 }
1076                 skb = new_skb;
1077         }
1078
1079         skb_push(skb, sizeof(*status));
1080         status = (struct status_64 *)skb->data;
1081
1082         if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1083                 ip_ver = htons(skb->protocol);
1084                 switch (ip_ver) {
1085                 case ETH_P_IP:
1086                         ip_proto = ip_hdr(skb)->protocol;
1087                         break;
1088                 case ETH_P_IPV6:
1089                         ip_proto = ipv6_hdr(skb)->nexthdr;
1090                         break;
1091                 default:
1092                         return 0;
1093                 }
1094
1095                 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1096                 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1097                                 (offset + skb->csum_offset);
1098
1099                 /* Set the length valid bit for TCP and UDP and just set
1100                  * the special UDP flag for IPv4, else just set to 0.
1101                  */
1102                 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1103                         tx_csum_info |= STATUS_TX_CSUM_LV;
1104                         if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1105                                 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1106                 } else
1107                         tx_csum_info = 0;
1108
1109                 status->tx_csum_info = tx_csum_info;
1110         }
1111
1112         return 0;
1113 }
1114
1115 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1116 {
1117         struct bcmgenet_priv *priv = netdev_priv(dev);
1118         struct bcmgenet_tx_ring *ring = NULL;
1119         struct netdev_queue *txq;
1120         unsigned long flags = 0;
1121         int nr_frags, index;
1122         u16 dma_desc_flags;
1123         int ret;
1124         int i;
1125
1126         index = skb_get_queue_mapping(skb);
1127         /* Mapping strategy:
1128          * queue_mapping = 0, unclassified, packet xmited through ring16
1129          * queue_mapping = 1, goes to ring 0. (highest priority queue
1130          * queue_mapping = 2, goes to ring 1.
1131          * queue_mapping = 3, goes to ring 2.
1132          * queue_mapping = 4, goes to ring 3.
1133          */
1134         if (index == 0)
1135                 index = DESC_INDEX;
1136         else
1137                 index -= 1;
1138
1139         nr_frags = skb_shinfo(skb)->nr_frags;
1140         ring = &priv->tx_rings[index];
1141         txq = netdev_get_tx_queue(dev, ring->queue);
1142
1143         spin_lock_irqsave(&ring->lock, flags);
1144         if (ring->free_bds <= nr_frags + 1) {
1145                 netif_tx_stop_queue(txq);
1146                 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1147                                 __func__, index, ring->queue);
1148                 ret = NETDEV_TX_BUSY;
1149                 goto out;
1150         }
1151
1152         if (skb_padto(skb, ETH_ZLEN)) {
1153                 ret = NETDEV_TX_OK;
1154                 goto out;
1155         }
1156
1157         /* set the SKB transmit checksum */
1158         if (priv->desc_64b_en) {
1159                 ret = bcmgenet_put_tx_csum(dev, skb);
1160                 if (ret) {
1161                         ret = NETDEV_TX_OK;
1162                         goto out;
1163                 }
1164         }
1165
1166         dma_desc_flags = DMA_SOP;
1167         if (nr_frags == 0)
1168                 dma_desc_flags |= DMA_EOP;
1169
1170         /* Transmit single SKB or head of fragment list */
1171         ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1172         if (ret) {
1173                 ret = NETDEV_TX_OK;
1174                 goto out;
1175         }
1176
1177         /* xmit fragment */
1178         for (i = 0; i < nr_frags; i++) {
1179                 ret = bcmgenet_xmit_frag(dev,
1180                                 &skb_shinfo(skb)->frags[i],
1181                                 (i == nr_frags - 1) ? DMA_EOP : 0, ring);
1182                 if (ret) {
1183                         ret = NETDEV_TX_OK;
1184                         goto out;
1185                 }
1186         }
1187
1188         skb_tx_timestamp(skb);
1189
1190         /* we kept a software copy of how much we should advance the TDMA
1191          * producer index, now write it down to the hardware
1192          */
1193         bcmgenet_tdma_ring_writel(priv, ring->index,
1194                         ring->prod_index, TDMA_PROD_INDEX);
1195
1196         if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) {
1197                 netif_tx_stop_queue(txq);
1198                 ring->int_enable(priv, ring);
1199         }
1200
1201 out:
1202         spin_unlock_irqrestore(&ring->lock, flags);
1203
1204         return ret;
1205 }
1206
1207
1208 static int bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1209                                 struct enet_cb *cb)
1210 {
1211         struct device *kdev = &priv->pdev->dev;
1212         struct sk_buff *skb;
1213         dma_addr_t mapping;
1214         int ret;
1215
1216         skb = netdev_alloc_skb(priv->dev,
1217                                 priv->rx_buf_len + SKB_ALIGNMENT);
1218         if (!skb)
1219                 return -ENOMEM;
1220
1221         /* a caller did not release this control block */
1222         WARN_ON(cb->skb != NULL);
1223         cb->skb = skb;
1224         mapping = dma_map_single(kdev, skb->data,
1225                         priv->rx_buf_len, DMA_FROM_DEVICE);
1226         ret = dma_mapping_error(kdev, mapping);
1227         if (ret) {
1228                 bcmgenet_free_cb(cb);
1229                 netif_err(priv, rx_err, priv->dev,
1230                                 "%s DMA map failed\n", __func__);
1231                 return ret;
1232         }
1233
1234         dma_unmap_addr_set(cb, dma_addr, mapping);
1235         /* assign packet, prepare descriptor, and advance pointer */
1236
1237         dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1238
1239         /* turn on the newly assigned BD for DMA to use */
1240         priv->rx_bd_assign_index++;
1241         priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1242
1243         priv->rx_bd_assign_ptr = priv->rx_bds +
1244                 (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1245
1246         return 0;
1247 }
1248
1249 /* bcmgenet_desc_rx - descriptor based rx process.
1250  * this could be called from bottom half, or from NAPI polling method.
1251  */
1252 static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1253                                      unsigned int budget)
1254 {
1255         struct net_device *dev = priv->dev;
1256         struct enet_cb *cb;
1257         struct sk_buff *skb;
1258         u32 dma_length_status;
1259         unsigned long dma_flag;
1260         int len, err;
1261         unsigned int rxpktprocessed = 0, rxpkttoprocess;
1262         unsigned int p_index;
1263         unsigned int chksum_ok = 0;
1264
1265         p_index = bcmgenet_rdma_ring_readl(priv,
1266                         DESC_INDEX, RDMA_PROD_INDEX);
1267         p_index &= DMA_P_INDEX_MASK;
1268
1269         if (p_index < priv->rx_c_index)
1270                 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1271                         priv->rx_c_index + p_index;
1272         else
1273                 rxpkttoprocess = p_index - priv->rx_c_index;
1274
1275         netif_dbg(priv, rx_status, dev,
1276                 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1277
1278         while ((rxpktprocessed < rxpkttoprocess) &&
1279                         (rxpktprocessed < budget)) {
1280
1281                 /* Unmap the packet contents such that we can use the
1282                  * RSV from the 64 bytes descriptor when enabled and save
1283                  * a 32-bits register read
1284                  */
1285                 cb = &priv->rx_cbs[priv->rx_read_ptr];
1286                 skb = cb->skb;
1287                 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
1288                                 priv->rx_buf_len, DMA_FROM_DEVICE);
1289
1290                 if (!priv->desc_64b_en) {
1291                         dma_length_status = dmadesc_get_length_status(priv,
1292                                                         priv->rx_bds +
1293                                                         (priv->rx_read_ptr *
1294                                                          DMA_DESC_SIZE));
1295                 } else {
1296                         struct status_64 *status;
1297                         status = (struct status_64 *)skb->data;
1298                         dma_length_status = status->length_status;
1299                 }
1300
1301                 /* DMA flags and length are still valid no matter how
1302                  * we got the Receive Status Vector (64B RSB or register)
1303                  */
1304                 dma_flag = dma_length_status & 0xffff;
1305                 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1306
1307                 netif_dbg(priv, rx_status, dev,
1308                         "%s: p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1309                         __func__, p_index, priv->rx_c_index, priv->rx_read_ptr,
1310                         dma_length_status);
1311
1312                 rxpktprocessed++;
1313
1314                 priv->rx_read_ptr++;
1315                 priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1316
1317                 /* out of memory, just drop packets at the hardware level */
1318                 if (unlikely(!skb)) {
1319                         dev->stats.rx_dropped++;
1320                         dev->stats.rx_errors++;
1321                         goto refill;
1322                 }
1323
1324                 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1325                         netif_err(priv, rx_status, dev,
1326                                         "Droping fragmented packet!\n");
1327                         dev->stats.rx_dropped++;
1328                         dev->stats.rx_errors++;
1329                         dev_kfree_skb_any(cb->skb);
1330                         cb->skb = NULL;
1331                         goto refill;
1332                 }
1333                 /* report errors */
1334                 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1335                                                 DMA_RX_OV |
1336                                                 DMA_RX_NO |
1337                                                 DMA_RX_LG |
1338                                                 DMA_RX_RXER))) {
1339                         netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1340                                                 (unsigned int)dma_flag);
1341                         if (dma_flag & DMA_RX_CRC_ERROR)
1342                                 dev->stats.rx_crc_errors++;
1343                         if (dma_flag & DMA_RX_OV)
1344                                 dev->stats.rx_over_errors++;
1345                         if (dma_flag & DMA_RX_NO)
1346                                 dev->stats.rx_frame_errors++;
1347                         if (dma_flag & DMA_RX_LG)
1348                                 dev->stats.rx_length_errors++;
1349                         dev->stats.rx_dropped++;
1350                         dev->stats.rx_errors++;
1351
1352                         /* discard the packet and advance consumer index.*/
1353                         dev_kfree_skb_any(cb->skb);
1354                         cb->skb = NULL;
1355                         goto refill;
1356                 } /* error packet */
1357
1358                 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1359                                 priv->desc_rxchk_en;
1360
1361                 skb_put(skb, len);
1362                 if (priv->desc_64b_en) {
1363                         skb_pull(skb, 64);
1364                         len -= 64;
1365                 }
1366
1367                 if (likely(chksum_ok))
1368                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1369
1370                 /* remove hardware 2bytes added for IP alignment */
1371                 skb_pull(skb, 2);
1372                 len -= 2;
1373
1374                 if (priv->crc_fwd_en) {
1375                         skb_trim(skb, len - ETH_FCS_LEN);
1376                         len -= ETH_FCS_LEN;
1377                 }
1378
1379                 /*Finish setting up the received SKB and send it to the kernel*/
1380                 skb->protocol = eth_type_trans(skb, priv->dev);
1381                 dev->stats.rx_packets++;
1382                 dev->stats.rx_bytes += len;
1383                 if (dma_flag & DMA_RX_MULT)
1384                         dev->stats.multicast++;
1385
1386                 /* Notify kernel */
1387                 napi_gro_receive(&priv->napi, skb);
1388                 cb->skb = NULL;
1389                 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1390
1391                 /* refill RX path on the current control block */
1392 refill:
1393                 err = bcmgenet_rx_refill(priv, cb);
1394                 if (err)
1395                         netif_err(priv, rx_err, dev, "Rx refill failed\n");
1396         }
1397
1398         return rxpktprocessed;
1399 }
1400
1401 /* Assign skb to RX DMA descriptor. */
1402 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1403 {
1404         struct enet_cb *cb;
1405         int ret = 0;
1406         int i;
1407
1408         netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1409
1410         /* loop here for each buffer needing assign */
1411         for (i = 0; i < priv->num_rx_bds; i++) {
1412                 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1413                 if (cb->skb)
1414                         continue;
1415
1416                 ret = bcmgenet_rx_refill(priv, cb);
1417                 if (ret)
1418                         break;
1419
1420         }
1421
1422         return ret;
1423 }
1424
1425 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1426 {
1427         struct enet_cb *cb;
1428         int i;
1429
1430         for (i = 0; i < priv->num_rx_bds; i++) {
1431                 cb = &priv->rx_cbs[i];
1432
1433                 if (dma_unmap_addr(cb, dma_addr)) {
1434                         dma_unmap_single(&priv->dev->dev,
1435                                         dma_unmap_addr(cb, dma_addr),
1436                                         priv->rx_buf_len, DMA_FROM_DEVICE);
1437                         dma_unmap_addr_set(cb, dma_addr, 0);
1438                 }
1439
1440                 if (cb->skb)
1441                         bcmgenet_free_cb(cb);
1442         }
1443 }
1444
1445 static int reset_umac(struct bcmgenet_priv *priv)
1446 {
1447         struct device *kdev = &priv->pdev->dev;
1448         unsigned int timeout = 0;
1449         u32 reg;
1450
1451         /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1452         bcmgenet_rbuf_ctrl_set(priv, 0);
1453         udelay(10);
1454
1455         /* disable MAC while updating its registers */
1456         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1457
1458         /* issue soft reset, wait for it to complete */
1459         bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1460         while (timeout++ < 1000) {
1461                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1462                 if (!(reg & CMD_SW_RESET))
1463                         return 0;
1464
1465                 udelay(1);
1466         }
1467
1468         if (timeout == 1000) {
1469                 dev_err(kdev,
1470                         "timeout waiting for MAC to come out of resetn\n");
1471                 return -ETIMEDOUT;
1472         }
1473
1474         return 0;
1475 }
1476
1477 static int init_umac(struct bcmgenet_priv *priv)
1478 {
1479         struct device *kdev = &priv->pdev->dev;
1480         int ret;
1481         u32 reg, cpu_mask_clear;
1482
1483         dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1484
1485         ret = reset_umac(priv);
1486         if (ret)
1487                 return ret;
1488
1489         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1490         /* clear tx/rx counter */
1491         bcmgenet_umac_writel(priv,
1492                 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, UMAC_MIB_CTRL);
1493         bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1494
1495         bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1496
1497         /* init rx registers, enable ip header optimization */
1498         reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1499         reg |= RBUF_ALIGN_2B;
1500         bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1501
1502         if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1503                 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1504
1505         /* Mask all interrupts.*/
1506         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1507         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1508         bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1509
1510         cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE;
1511
1512         dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1513
1514         /* Monitor cable plug/unpluged event for internal PHY */
1515         if (phy_is_internal(priv->phydev))
1516                 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1517         else if (priv->ext_phy)
1518                 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1519         else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1520                 reg = bcmgenet_bp_mc_get(priv);
1521                 reg |= BIT(priv->hw_params->bp_in_en_shift);
1522
1523                 /* bp_mask: back pressure mask */
1524                 if (netif_is_multiqueue(priv->dev))
1525                         reg |= priv->hw_params->bp_in_mask;
1526                 else
1527                         reg &= ~priv->hw_params->bp_in_mask;
1528                 bcmgenet_bp_mc_set(priv, reg);
1529         }
1530
1531         /* Enable MDIO interrupts on GENET v3+ */
1532         if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1533                 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1534
1535         bcmgenet_intrl2_0_writel(priv, cpu_mask_clear,
1536                 INTRL2_CPU_MASK_CLEAR);
1537
1538         /* Enable rx/tx engine.*/
1539         dev_dbg(kdev, "done init umac\n");
1540
1541         return 0;
1542 }
1543
1544 /* Initialize all house-keeping variables for a TX ring, along
1545  * with corresponding hardware registers
1546  */
1547 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1548                                   unsigned int index, unsigned int size,
1549                                   unsigned int write_ptr, unsigned int end_ptr)
1550 {
1551         struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1552         u32 words_per_bd = WORDS_PER_BD(priv);
1553         u32 flow_period_val = 0;
1554         unsigned int first_bd;
1555
1556         spin_lock_init(&ring->lock);
1557         ring->index = index;
1558         if (index == DESC_INDEX) {
1559                 ring->queue = 0;
1560                 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1561                 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1562         } else {
1563                 ring->queue = index + 1;
1564                 ring->int_enable = bcmgenet_tx_ring_int_enable;
1565                 ring->int_disable = bcmgenet_tx_ring_int_disable;
1566         }
1567         ring->cbs = priv->tx_cbs + write_ptr;
1568         ring->size = size;
1569         ring->c_index = 0;
1570         ring->free_bds = size;
1571         ring->write_ptr = write_ptr;
1572         ring->cb_ptr = write_ptr;
1573         ring->end_ptr = end_ptr - 1;
1574         ring->prod_index = 0;
1575
1576         /* Set flow period for ring != 16 */
1577         if (index != DESC_INDEX)
1578                 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1579
1580         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1581         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1582         bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1583         /* Disable rate control for now */
1584         bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1585                         TDMA_FLOW_PERIOD);
1586         /* Unclassified traffic goes to ring 16 */
1587         bcmgenet_tdma_ring_writel(priv, index,
1588                         ((size << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH),
1589                         DMA_RING_BUF_SIZE);
1590
1591         first_bd = write_ptr;
1592
1593         /* Set start and end address, read and write pointers */
1594         bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1595                         DMA_START_ADDR);
1596         bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1597                         TDMA_READ_PTR);
1598         bcmgenet_tdma_ring_writel(priv, index, first_bd,
1599                         TDMA_WRITE_PTR);
1600         bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1601                         DMA_END_ADDR);
1602 }
1603
1604 /* Initialize a RDMA ring */
1605 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
1606                                   unsigned int index, unsigned int size)
1607 {
1608         u32 words_per_bd = WORDS_PER_BD(priv);
1609         int ret;
1610
1611         priv->num_rx_bds = TOTAL_DESC;
1612         priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1613         priv->rx_bd_assign_ptr = priv->rx_bds;
1614         priv->rx_bd_assign_index = 0;
1615         priv->rx_c_index = 0;
1616         priv->rx_read_ptr = 0;
1617         priv->rx_cbs = kzalloc(priv->num_rx_bds * sizeof(struct enet_cb),
1618                                 GFP_KERNEL);
1619         if (!priv->rx_cbs)
1620                 return -ENOMEM;
1621
1622         ret = bcmgenet_alloc_rx_buffers(priv);
1623         if (ret) {
1624                 kfree(priv->rx_cbs);
1625                 return ret;
1626         }
1627
1628         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1629         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1630         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1631         bcmgenet_rdma_ring_writel(priv, index,
1632                 ((size << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH),
1633                 DMA_RING_BUF_SIZE);
1634         bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1635         bcmgenet_rdma_ring_writel(priv, index,
1636                 words_per_bd * size - 1, DMA_END_ADDR);
1637         bcmgenet_rdma_ring_writel(priv, index,
1638                         (DMA_FC_THRESH_LO << DMA_XOFF_THRESHOLD_SHIFT) |
1639                         DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1640         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
1641
1642         return ret;
1643 }
1644
1645 /* init multi xmit queues, only available for GENET2+
1646  * the queue is partitioned as follows:
1647  *
1648  * queue 0 - 3 is priority based, each one has 32 descriptors,
1649  * with queue 0 being the highest priority queue.
1650  *
1651  * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1652  * descriptors: 256 - (number of tx queues * bds per queues) = 128
1653  * descriptors.
1654  *
1655  * The transmit control block pool is then partitioned as following:
1656  * - tx_cbs[0...127] are for queue 16
1657  * - tx_ring_cbs[0] points to tx_cbs[128..159]
1658  * - tx_ring_cbs[1] points to tx_cbs[160..191]
1659  * - tx_ring_cbs[2] points to tx_cbs[192..223]
1660  * - tx_ring_cbs[3] points to tx_cbs[224..255]
1661  */
1662 static void bcmgenet_init_multiq(struct net_device *dev)
1663 {
1664         struct bcmgenet_priv *priv = netdev_priv(dev);
1665         unsigned int i, dma_enable;
1666         u32 reg, dma_ctrl, ring_cfg = 0, dma_priority = 0;
1667
1668         if (!netif_is_multiqueue(dev)) {
1669                 netdev_warn(dev, "called with non multi queue aware HW\n");
1670                 return;
1671         }
1672
1673         dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1674         dma_enable = dma_ctrl & DMA_EN;
1675         dma_ctrl &= ~DMA_EN;
1676         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1677
1678         /* Enable strict priority arbiter mode */
1679         bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1680
1681         for (i = 0; i < priv->hw_params->tx_queues; i++) {
1682                 /* first 64 tx_cbs are reserved for default tx queue
1683                  * (ring 16)
1684                  */
1685                 bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt,
1686                                         i * priv->hw_params->bds_cnt,
1687                                         (i + 1) * priv->hw_params->bds_cnt);
1688
1689                 /* Configure ring as decriptor ring and setup priority */
1690                 ring_cfg |= 1 << i;
1691                 dma_priority |= ((GENET_Q0_PRIORITY + i) <<
1692                                 (GENET_MAX_MQ_CNT + 1) * i);
1693                 dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT);
1694         }
1695
1696         /* Enable rings */
1697         reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG);
1698         reg |= ring_cfg;
1699         bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG);
1700
1701         /* Use configured rings priority and set ring #16 priority */
1702         reg = bcmgenet_tdma_readl(priv, DMA_RING_PRIORITY);
1703         reg |= ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 20);
1704         reg |= dma_priority;
1705         bcmgenet_tdma_writel(priv, reg, DMA_PRIORITY);
1706
1707         /* Configure ring as descriptor ring and re-enable DMA if enabled */
1708         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1709         reg |= dma_ctrl;
1710         if (dma_enable)
1711                 reg |= DMA_EN;
1712         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1713 }
1714
1715 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1716 {
1717         int i;
1718
1719         /* disable DMA */
1720         bcmgenet_rdma_writel(priv, 0, DMA_CTRL);
1721         bcmgenet_tdma_writel(priv, 0, DMA_CTRL);
1722
1723         for (i = 0; i < priv->num_tx_bds; i++) {
1724                 if (priv->tx_cbs[i].skb != NULL) {
1725                         dev_kfree_skb(priv->tx_cbs[i].skb);
1726                         priv->tx_cbs[i].skb = NULL;
1727                 }
1728         }
1729
1730         bcmgenet_free_rx_buffers(priv);
1731         kfree(priv->rx_cbs);
1732         kfree(priv->tx_cbs);
1733 }
1734
1735 /* init_edma: Initialize DMA control register */
1736 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1737 {
1738         int ret;
1739
1740         netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
1741
1742         /* by default, enable ring 16 (descriptor based) */
1743         ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1744         if (ret) {
1745                 netdev_err(priv->dev, "failed to initialize RX ring\n");
1746                 return ret;
1747         }
1748
1749         /* init rDma */
1750         bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1751
1752         /* Init tDma */
1753         bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1754
1755         /* Initialize commont TX ring structures */
1756         priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
1757         priv->num_tx_bds = TOTAL_DESC;
1758         priv->tx_cbs = kzalloc(priv->num_tx_bds * sizeof(struct enet_cb),
1759                                 GFP_KERNEL);
1760         if (!priv->tx_cbs) {
1761                 bcmgenet_fini_dma(priv);
1762                 return -ENOMEM;
1763         }
1764
1765         /* initialize multi xmit queue */
1766         bcmgenet_init_multiq(priv->dev);
1767
1768         /* initialize special ring 16 */
1769         bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT,
1770                         priv->hw_params->tx_queues * priv->hw_params->bds_cnt,
1771                         TOTAL_DESC);
1772
1773         return 0;
1774 }
1775
1776 /* NAPI polling method*/
1777 static int bcmgenet_poll(struct napi_struct *napi, int budget)
1778 {
1779         struct bcmgenet_priv *priv = container_of(napi,
1780                         struct bcmgenet_priv, napi);
1781         unsigned int work_done;
1782
1783         /* tx reclaim */
1784         bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1785
1786         work_done = bcmgenet_desc_rx(priv, budget);
1787
1788         /* Advancing our consumer index*/
1789         priv->rx_c_index += work_done;
1790         priv->rx_c_index &= DMA_C_INDEX_MASK;
1791         bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
1792                                 priv->rx_c_index, RDMA_CONS_INDEX);
1793         if (work_done < budget) {
1794                 napi_complete(napi);
1795                 bcmgenet_intrl2_0_writel(priv,
1796                         UMAC_IRQ_RXDMA_BDONE, INTRL2_CPU_MASK_CLEAR);
1797         }
1798
1799         return work_done;
1800 }
1801
1802 /* Interrupt bottom half */
1803 static void bcmgenet_irq_task(struct work_struct *work)
1804 {
1805         struct bcmgenet_priv *priv = container_of(
1806                         work, struct bcmgenet_priv, bcmgenet_irq_work);
1807
1808         netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
1809
1810         /* Link UP/DOWN event */
1811         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
1812                 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
1813                 phy_mac_interrupt(priv->phydev,
1814                         priv->irq0_stat & UMAC_IRQ_LINK_UP);
1815                 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
1816         }
1817 }
1818
1819 /* bcmgenet_isr1: interrupt handler for ring buffer. */
1820 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
1821 {
1822         struct bcmgenet_priv *priv = dev_id;
1823         unsigned int index;
1824
1825         /* Save irq status for bottom-half processing. */
1826         priv->irq1_stat =
1827                 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
1828                 ~priv->int1_mask;
1829         /* clear inerrupts*/
1830         bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
1831
1832         netif_dbg(priv, intr, priv->dev,
1833                 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
1834         /* Check the MBDONE interrupts.
1835          * packet is done, reclaim descriptors
1836          */
1837         if (priv->irq1_stat & 0x0000ffff) {
1838                 index = 0;
1839                 for (index = 0; index < 16; index++) {
1840                         if (priv->irq1_stat & (1 << index))
1841                                 bcmgenet_tx_reclaim(priv->dev,
1842                                                 &priv->tx_rings[index]);
1843                 }
1844         }
1845         return IRQ_HANDLED;
1846 }
1847
1848 /* bcmgenet_isr0: Handle various interrupts. */
1849 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
1850 {
1851         struct bcmgenet_priv *priv = dev_id;
1852
1853         /* Save irq status for bottom-half processing. */
1854         priv->irq0_stat =
1855                 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
1856                 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
1857         /* clear inerrupts*/
1858         bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
1859
1860         netif_dbg(priv, intr, priv->dev,
1861                 "IRQ=0x%x\n", priv->irq0_stat);
1862
1863         if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
1864                 /* We use NAPI(software interrupt throttling, if
1865                  * Rx Descriptor throttling is not used.
1866                  * Disable interrupt, will be enabled in the poll method.
1867                  */
1868                 if (likely(napi_schedule_prep(&priv->napi))) {
1869                         bcmgenet_intrl2_0_writel(priv,
1870                                 UMAC_IRQ_RXDMA_BDONE, INTRL2_CPU_MASK_SET);
1871                         __napi_schedule(&priv->napi);
1872                 }
1873         }
1874         if (priv->irq0_stat &
1875                         (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
1876                 /* Tx reclaim */
1877                 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1878         }
1879         if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
1880                                 UMAC_IRQ_PHY_DET_F |
1881                                 UMAC_IRQ_LINK_UP |
1882                                 UMAC_IRQ_LINK_DOWN |
1883                                 UMAC_IRQ_HFB_SM |
1884                                 UMAC_IRQ_HFB_MM |
1885                                 UMAC_IRQ_MPD_R)) {
1886                 /* all other interested interrupts handled in bottom half */
1887                 schedule_work(&priv->bcmgenet_irq_work);
1888         }
1889
1890         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
1891                 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1892                 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1893                 wake_up(&priv->wq);
1894         }
1895
1896         return IRQ_HANDLED;
1897 }
1898
1899 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
1900 {
1901         u32 reg;
1902
1903         reg = bcmgenet_rbuf_ctrl_get(priv);
1904         reg |= BIT(1);
1905         bcmgenet_rbuf_ctrl_set(priv, reg);
1906         udelay(10);
1907
1908         reg &= ~BIT(1);
1909         bcmgenet_rbuf_ctrl_set(priv, reg);
1910         udelay(10);
1911 }
1912
1913 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
1914                                   unsigned char *addr)
1915 {
1916         bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
1917                         (addr[2] << 8) | addr[3], UMAC_MAC0);
1918         bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
1919 }
1920
1921 static int bcmgenet_wol_resume(struct bcmgenet_priv *priv)
1922 {
1923         int ret;
1924
1925         /* From WOL-enabled suspend, switch to regular clock */
1926         clk_disable(priv->clk_wol);
1927         /* init umac registers to synchronize s/w with h/w */
1928         ret = init_umac(priv);
1929         if (ret)
1930                 return ret;
1931
1932         phy_init_hw(priv->phydev);
1933         /* Speed settings must be restored */
1934         bcmgenet_mii_config(priv->dev);
1935
1936         return 0;
1937 }
1938
1939 /* Returns a reusable dma control register value */
1940 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
1941 {
1942         u32 reg;
1943         u32 dma_ctrl;
1944
1945         /* disable DMA */
1946         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
1947         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1948         reg &= ~dma_ctrl;
1949         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1950
1951         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1952         reg &= ~dma_ctrl;
1953         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1954
1955         bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
1956         udelay(10);
1957         bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
1958
1959         return dma_ctrl;
1960 }
1961
1962 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
1963 {
1964         u32 reg;
1965
1966         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1967         reg |= dma_ctrl;
1968         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1969
1970         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1971         reg |= dma_ctrl;
1972         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1973 }
1974
1975 static int bcmgenet_open(struct net_device *dev)
1976 {
1977         struct bcmgenet_priv *priv = netdev_priv(dev);
1978         unsigned long dma_ctrl;
1979         u32 reg;
1980         int ret;
1981
1982         netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
1983
1984         /* Turn on the clock */
1985         if (!IS_ERR(priv->clk))
1986                 clk_prepare_enable(priv->clk);
1987
1988         /* take MAC out of reset */
1989         bcmgenet_umac_reset(priv);
1990
1991         ret = init_umac(priv);
1992         if (ret)
1993                 goto err_clk_disable;
1994
1995         /* disable ethernet MAC while updating its registers */
1996         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1997         reg &= ~(CMD_TX_EN | CMD_RX_EN);
1998         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1999
2000         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2001
2002         if (priv->wol_enabled) {
2003                 ret = bcmgenet_wol_resume(priv);
2004                 if (ret)
2005                         return ret;
2006         }
2007
2008         if (phy_is_internal(priv->phydev)) {
2009                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2010                 reg |= EXT_ENERGY_DET_MASK;
2011                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2012         }
2013
2014         /* Disable RX/TX DMA and flush TX queues */
2015         dma_ctrl = bcmgenet_dma_disable(priv);
2016
2017         /* Reinitialize TDMA and RDMA and SW housekeeping */
2018         ret = bcmgenet_init_dma(priv);
2019         if (ret) {
2020                 netdev_err(dev, "failed to initialize DMA\n");
2021                 goto err_fini_dma;
2022         }
2023
2024         /* Always enable ring 16 - descriptor ring */
2025         bcmgenet_enable_dma(priv, dma_ctrl);
2026
2027         ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2028                         dev->name, priv);
2029         if (ret < 0) {
2030                 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2031                 goto err_fini_dma;
2032         }
2033
2034         ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2035                                 dev->name, priv);
2036         if (ret < 0) {
2037                 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2038                 goto err_irq0;
2039         }
2040
2041         /* Start the network engine */
2042         napi_enable(&priv->napi);
2043
2044         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2045         reg |= (CMD_TX_EN | CMD_RX_EN);
2046         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2047
2048         /* Make sure we reflect the value of CRC_CMD_FWD */
2049         priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2050
2051         device_set_wakeup_capable(&dev->dev, 1);
2052
2053         if (phy_is_internal(priv->phydev))
2054                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2055
2056         netif_tx_start_all_queues(dev);
2057
2058         phy_start(priv->phydev);
2059
2060         return 0;
2061
2062 err_irq0:
2063         free_irq(priv->irq0, dev);
2064 err_fini_dma:
2065         bcmgenet_fini_dma(priv);
2066 err_clk_disable:
2067         if (!IS_ERR(priv->clk))
2068                 clk_disable_unprepare(priv->clk);
2069         return ret;
2070 }
2071
2072 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2073 {
2074         int ret = 0;
2075         int timeout = 0;
2076         u32 reg;
2077
2078         /* Disable TDMA to stop add more frames in TX DMA */
2079         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2080         reg &= ~DMA_EN;
2081         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2082
2083         /* Check TDMA status register to confirm TDMA is disabled */
2084         while (timeout++ < DMA_TIMEOUT_VAL) {
2085                 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2086                 if (reg & DMA_DISABLED)
2087                         break;
2088
2089                 udelay(1);
2090         }
2091
2092         if (timeout == DMA_TIMEOUT_VAL) {
2093                 netdev_warn(priv->dev,
2094                         "Timed out while disabling TX DMA\n");
2095                 ret = -ETIMEDOUT;
2096         }
2097
2098         /* Wait 10ms for packet drain in both tx and rx dma */
2099         usleep_range(10000, 20000);
2100
2101         /* Disable RDMA */
2102         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2103         reg &= ~DMA_EN;
2104         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2105
2106         timeout = 0;
2107         /* Check RDMA status register to confirm RDMA is disabled */
2108         while (timeout++ < DMA_TIMEOUT_VAL) {
2109                 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2110                 if (reg & DMA_DISABLED)
2111                         break;
2112
2113                 udelay(1);
2114         }
2115
2116         if (timeout == DMA_TIMEOUT_VAL) {
2117                 netdev_warn(priv->dev,
2118                         "Timed out while disabling RX DMA\n");
2119                         ret = -ETIMEDOUT;
2120         }
2121
2122         return ret;
2123 }
2124
2125 static int bcmgenet_close(struct net_device *dev)
2126 {
2127         struct bcmgenet_priv *priv = netdev_priv(dev);
2128         int ret;
2129         u32 reg;
2130
2131         netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2132
2133         phy_stop(priv->phydev);
2134
2135         /* Disable MAC receive */
2136         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2137         reg &= ~CMD_RX_EN;
2138         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2139
2140         netif_tx_stop_all_queues(dev);
2141
2142         ret = bcmgenet_dma_teardown(priv);
2143         if (ret)
2144                 return ret;
2145
2146         /* Disable MAC transmit. TX DMA disabled have to done before this */
2147         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2148         reg &= ~CMD_TX_EN;
2149         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2150
2151         napi_disable(&priv->napi);
2152
2153         /* tx reclaim */
2154         bcmgenet_tx_reclaim_all(dev);
2155         bcmgenet_fini_dma(priv);
2156
2157         free_irq(priv->irq0, priv);
2158         free_irq(priv->irq1, priv);
2159
2160         /* Wait for pending work items to complete - we are stopping
2161          * the clock now. Since interrupts are disabled, no new work
2162          * will be scheduled.
2163          */
2164         cancel_work_sync(&priv->bcmgenet_irq_work);
2165
2166         if (phy_is_internal(priv->phydev))
2167                 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2168
2169         if (priv->wol_enabled)
2170                 clk_enable(priv->clk_wol);
2171
2172         if (!IS_ERR(priv->clk))
2173                 clk_disable_unprepare(priv->clk);
2174
2175         return 0;
2176 }
2177
2178 static void bcmgenet_timeout(struct net_device *dev)
2179 {
2180         struct bcmgenet_priv *priv = netdev_priv(dev);
2181
2182         netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2183
2184         dev->trans_start = jiffies;
2185
2186         dev->stats.tx_errors++;
2187
2188         netif_tx_wake_all_queues(dev);
2189 }
2190
2191 #define MAX_MC_COUNT    16
2192
2193 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2194                                          unsigned char *addr,
2195                                          int *i,
2196                                          int *mc)
2197 {
2198         u32 reg;
2199
2200         bcmgenet_umac_writel(priv,
2201                         addr[0] << 8 | addr[1], UMAC_MDF_ADDR + (*i * 4));
2202         bcmgenet_umac_writel(priv,
2203                         addr[2] << 24 | addr[3] << 16 |
2204                         addr[4] << 8 | addr[5],
2205                         UMAC_MDF_ADDR + ((*i + 1) * 4));
2206         reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2207         reg |= (1 << (MAX_MC_COUNT - *mc));
2208         bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2209         *i += 2;
2210         (*mc)++;
2211 }
2212
2213 static void bcmgenet_set_rx_mode(struct net_device *dev)
2214 {
2215         struct bcmgenet_priv *priv = netdev_priv(dev);
2216         struct netdev_hw_addr *ha;
2217         int i, mc;
2218         u32 reg;
2219
2220         netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2221
2222         /* Promiscous mode */
2223         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2224         if (dev->flags & IFF_PROMISC) {
2225                 reg |= CMD_PROMISC;
2226                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2227                 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2228                 return;
2229         } else {
2230                 reg &= ~CMD_PROMISC;
2231                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2232         }
2233
2234         /* UniMac doesn't support ALLMULTI */
2235         if (dev->flags & IFF_ALLMULTI) {
2236                 netdev_warn(dev, "ALLMULTI is not supported\n");
2237                 return;
2238         }
2239
2240         /* update MDF filter */
2241         i = 0;
2242         mc = 0;
2243         /* Broadcast */
2244         bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2245         /* my own address.*/
2246         bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2247         /* Unicast list*/
2248         if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2249                 return;
2250
2251         if (!netdev_uc_empty(dev))
2252                 netdev_for_each_uc_addr(ha, dev)
2253                         bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2254         /* Multicast */
2255         if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2256                 return;
2257
2258         netdev_for_each_mc_addr(ha, dev)
2259                 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2260 }
2261
2262 /* Set the hardware MAC address. */
2263 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2264 {
2265         struct sockaddr *addr = p;
2266
2267         /* Setting the MAC address at the hardware level is not possible
2268          * without disabling the UniMAC RX/TX enable bits.
2269          */
2270         if (netif_running(dev))
2271                 return -EBUSY;
2272
2273         ether_addr_copy(dev->dev_addr, addr->sa_data);
2274
2275         return 0;
2276 }
2277
2278 static const struct net_device_ops bcmgenet_netdev_ops = {
2279         .ndo_open               = bcmgenet_open,
2280         .ndo_stop               = bcmgenet_close,
2281         .ndo_start_xmit         = bcmgenet_xmit,
2282         .ndo_tx_timeout         = bcmgenet_timeout,
2283         .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
2284         .ndo_set_mac_address    = bcmgenet_set_mac_addr,
2285         .ndo_do_ioctl           = bcmgenet_ioctl,
2286         .ndo_set_features       = bcmgenet_set_features,
2287 };
2288
2289 /* Array of GENET hardware parameters/characteristics */
2290 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2291         [GENET_V1] = {
2292                 .tx_queues = 0,
2293                 .rx_queues = 0,
2294                 .bds_cnt = 0,
2295                 .bp_in_en_shift = 16,
2296                 .bp_in_mask = 0xffff,
2297                 .hfb_filter_cnt = 16,
2298                 .qtag_mask = 0x1F,
2299                 .hfb_offset = 0x1000,
2300                 .rdma_offset = 0x2000,
2301                 .tdma_offset = 0x3000,
2302                 .words_per_bd = 2,
2303         },
2304         [GENET_V2] = {
2305                 .tx_queues = 4,
2306                 .rx_queues = 4,
2307                 .bds_cnt = 32,
2308                 .bp_in_en_shift = 16,
2309                 .bp_in_mask = 0xffff,
2310                 .hfb_filter_cnt = 16,
2311                 .qtag_mask = 0x1F,
2312                 .tbuf_offset = 0x0600,
2313                 .hfb_offset = 0x1000,
2314                 .hfb_reg_offset = 0x2000,
2315                 .rdma_offset = 0x3000,
2316                 .tdma_offset = 0x4000,
2317                 .words_per_bd = 2,
2318                 .flags = GENET_HAS_EXT,
2319         },
2320         [GENET_V3] = {
2321                 .tx_queues = 4,
2322                 .rx_queues = 4,
2323                 .bds_cnt = 32,
2324                 .bp_in_en_shift = 17,
2325                 .bp_in_mask = 0x1ffff,
2326                 .hfb_filter_cnt = 48,
2327                 .qtag_mask = 0x3F,
2328                 .tbuf_offset = 0x0600,
2329                 .hfb_offset = 0x8000,
2330                 .hfb_reg_offset = 0xfc00,
2331                 .rdma_offset = 0x10000,
2332                 .tdma_offset = 0x11000,
2333                 .words_per_bd = 2,
2334                 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2335         },
2336         [GENET_V4] = {
2337                 .tx_queues = 4,
2338                 .rx_queues = 4,
2339                 .bds_cnt = 32,
2340                 .bp_in_en_shift = 17,
2341                 .bp_in_mask = 0x1ffff,
2342                 .hfb_filter_cnt = 48,
2343                 .qtag_mask = 0x3F,
2344                 .tbuf_offset = 0x0600,
2345                 .hfb_offset = 0x8000,
2346                 .hfb_reg_offset = 0xfc00,
2347                 .rdma_offset = 0x2000,
2348                 .tdma_offset = 0x4000,
2349                 .words_per_bd = 3,
2350                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2351         },
2352 };
2353
2354 /* Infer hardware parameters from the detected GENET version */
2355 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2356 {
2357         struct bcmgenet_hw_params *params;
2358         u32 reg;
2359         u8 major;
2360
2361         if (GENET_IS_V4(priv)) {
2362                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2363                 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2364                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2365                 priv->version = GENET_V4;
2366         } else if (GENET_IS_V3(priv)) {
2367                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2368                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2369                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2370                 priv->version = GENET_V3;
2371         } else if (GENET_IS_V2(priv)) {
2372                 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2373                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2374                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2375                 priv->version = GENET_V2;
2376         } else if (GENET_IS_V1(priv)) {
2377                 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2378                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2379                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2380                 priv->version = GENET_V1;
2381         }
2382
2383         /* enum genet_version starts at 1 */
2384         priv->hw_params = &bcmgenet_hw_params[priv->version];
2385         params = priv->hw_params;
2386
2387         /* Read GENET HW version */
2388         reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2389         major = (reg >> 24 & 0x0f);
2390         if (major == 5)
2391                 major = 4;
2392         else if (major == 0)
2393                 major = 1;
2394         if (major != priv->version) {
2395                 dev_err(&priv->pdev->dev,
2396                         "GENET version mismatch, got: %d, configured for: %d\n",
2397                         major, priv->version);
2398         }
2399
2400         /* Print the GENET core version */
2401         dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
2402                 major, (reg >> 16) & 0x0f, reg & 0xffff);
2403
2404 #ifdef CONFIG_PHYS_ADDR_T_64BIT
2405         if (!(params->flags & GENET_HAS_40BITS))
2406                 pr_warn("GENET does not support 40-bits PA\n");
2407 #endif
2408
2409         pr_debug("Configuration for version: %d\n"
2410                 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2411                 "BP << en: %2d, BP msk: 0x%05x\n"
2412                 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2413                 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2414                 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2415                 "Words/BD: %d\n",
2416                 priv->version,
2417                 params->tx_queues, params->rx_queues, params->bds_cnt,
2418                 params->bp_in_en_shift, params->bp_in_mask,
2419                 params->hfb_filter_cnt, params->qtag_mask,
2420                 params->tbuf_offset, params->hfb_offset,
2421                 params->hfb_reg_offset,
2422                 params->rdma_offset, params->tdma_offset,
2423                 params->words_per_bd);
2424 }
2425
2426 static const struct of_device_id bcmgenet_match[] = {
2427         { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2428         { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2429         { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2430         { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2431         { },
2432 };
2433
2434 static int bcmgenet_probe(struct platform_device *pdev)
2435 {
2436         struct device_node *dn = pdev->dev.of_node;
2437         const struct of_device_id *of_id;
2438         struct bcmgenet_priv *priv;
2439         struct net_device *dev;
2440         const void *macaddr;
2441         struct resource *r;
2442         int err = -EIO;
2443
2444         /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2445         dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
2446         if (!dev) {
2447                 dev_err(&pdev->dev, "can't allocate net device\n");
2448                 return -ENOMEM;
2449         }
2450
2451         of_id = of_match_node(bcmgenet_match, dn);
2452         if (!of_id)
2453                 return -EINVAL;
2454
2455         priv = netdev_priv(dev);
2456         priv->irq0 = platform_get_irq(pdev, 0);
2457         priv->irq1 = platform_get_irq(pdev, 1);
2458         if (!priv->irq0 || !priv->irq1) {
2459                 dev_err(&pdev->dev, "can't find IRQs\n");
2460                 err = -EINVAL;
2461                 goto err;
2462         }
2463
2464         macaddr = of_get_mac_address(dn);
2465         if (!macaddr) {
2466                 dev_err(&pdev->dev, "can't find MAC address\n");
2467                 err = -EINVAL;
2468                 goto err;
2469         }
2470
2471         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2472         priv->base = devm_ioremap_resource(&pdev->dev, r);
2473         if (IS_ERR(priv->base)) {
2474                 err = PTR_ERR(priv->base);
2475                 goto err;
2476         }
2477
2478         SET_NETDEV_DEV(dev, &pdev->dev);
2479         dev_set_drvdata(&pdev->dev, dev);
2480         ether_addr_copy(dev->dev_addr, macaddr);
2481         dev->watchdog_timeo = 2 * HZ;
2482         dev->ethtool_ops = &bcmgenet_ethtool_ops;
2483         dev->netdev_ops = &bcmgenet_netdev_ops;
2484         netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2485
2486         priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2487
2488         /* Set hardware features */
2489         dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2490                 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2491
2492         /* Set the needed headroom to account for any possible
2493          * features enabling/disabling at runtime
2494          */
2495         dev->needed_headroom += 64;
2496
2497         netdev_boot_setup_check(dev);
2498
2499         priv->dev = dev;
2500         priv->pdev = pdev;
2501         priv->version = (enum bcmgenet_version)of_id->data;
2502
2503         bcmgenet_set_hw_params(priv);
2504
2505         /* Mii wait queue */
2506         init_waitqueue_head(&priv->wq);
2507         /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2508         priv->rx_buf_len = RX_BUF_LENGTH;
2509         INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2510
2511         priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2512         if (IS_ERR(priv->clk))
2513                 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2514
2515         priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2516         if (IS_ERR(priv->clk_wol))
2517                 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2518
2519         if (!IS_ERR(priv->clk))
2520                 clk_prepare_enable(priv->clk);
2521
2522         err = reset_umac(priv);
2523         if (err)
2524                 goto err_clk_disable;
2525
2526         err = bcmgenet_mii_init(dev);
2527         if (err)
2528                 goto err_clk_disable;
2529
2530         /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
2531          * just the ring 16 descriptor based TX
2532          */
2533         netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2534         netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2535
2536         /* libphy will determine the link state */
2537         netif_carrier_off(dev);
2538
2539         /* Turn off the main clock, WOL clock is handled separately */
2540         if (!IS_ERR(priv->clk))
2541                 clk_disable_unprepare(priv->clk);
2542
2543         err = register_netdev(dev);
2544         if (err)
2545                 goto err;
2546
2547         return err;
2548
2549 err_clk_disable:
2550         if (!IS_ERR(priv->clk))
2551                 clk_disable_unprepare(priv->clk);
2552 err:
2553         free_netdev(dev);
2554         return err;
2555 }
2556
2557 static int bcmgenet_remove(struct platform_device *pdev)
2558 {
2559         struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2560
2561         dev_set_drvdata(&pdev->dev, NULL);
2562         unregister_netdev(priv->dev);
2563         bcmgenet_mii_exit(priv->dev);
2564         free_netdev(priv->dev);
2565
2566         return 0;
2567 }
2568
2569
2570 static struct platform_driver bcmgenet_driver = {
2571         .probe  = bcmgenet_probe,
2572         .remove = bcmgenet_remove,
2573         .driver = {
2574                 .name   = "bcmgenet",
2575                 .owner  = THIS_MODULE,
2576                 .of_match_table = bcmgenet_match,
2577         },
2578 };
2579 module_platform_driver(bcmgenet_driver);
2580
2581 MODULE_AUTHOR("Broadcom Corporation");
2582 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2583 MODULE_ALIAS("platform:bcmgenet");
2584 MODULE_LICENSE("GPL");