drivers/net/ethernet/broadcom/bnxt/bnxt.h

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2017 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #ifndef BNXT_H
  12 #define BNXT_H
  13
  14 #define DRV_MODULE_NAME         "bnxt_en"
  15 #define DRV_MODULE_VERSION      "1.7.0"
  16
  17 #define DRV_VER_MAJ     1
  18 #define DRV_VER_MIN     7
  19 #define DRV_VER_UPD     0
  20
  21 #include <linux/interrupt.h>
  22
  23 struct tx_bd {
  24         __le32 tx_bd_len_flags_type;
  25         #define TX_BD_TYPE                                      (0x3f << 0)
  26          #define TX_BD_TYPE_SHORT_TX_BD                          (0x00 << 0)
  27          #define TX_BD_TYPE_LONG_TX_BD                           (0x10 << 0)
  28         #define TX_BD_FLAGS_PACKET_END                          (1 << 6)
  29         #define TX_BD_FLAGS_NO_CMPL                             (1 << 7)
  30         #define TX_BD_FLAGS_BD_CNT                              (0x1f << 8)
  31          #define TX_BD_FLAGS_BD_CNT_SHIFT                        8
  32         #define TX_BD_FLAGS_LHINT                               (3 << 13)
  33          #define TX_BD_FLAGS_LHINT_SHIFT                         13
  34          #define TX_BD_FLAGS_LHINT_512_AND_SMALLER               (0 << 13)
  35          #define TX_BD_FLAGS_LHINT_512_TO_1023                   (1 << 13)
  36          #define TX_BD_FLAGS_LHINT_1024_TO_2047                  (2 << 13)
  37          #define TX_BD_FLAGS_LHINT_2048_AND_LARGER               (3 << 13)
  38         #define TX_BD_FLAGS_COAL_NOW                            (1 << 15)
  39         #define TX_BD_LEN                                       (0xffff << 16)
  40          #define TX_BD_LEN_SHIFT                                 16
  41
  42         u32 tx_bd_opaque;
  43         __le64 tx_bd_haddr;
  44 } __packed;
  45
  46 struct tx_bd_ext {
  47         __le32 tx_bd_hsize_lflags;
  48         #define TX_BD_FLAGS_TCP_UDP_CHKSUM                      (1 << 0)
  49         #define TX_BD_FLAGS_IP_CKSUM                            (1 << 1)
  50         #define TX_BD_FLAGS_NO_CRC                              (1 << 2)
  51         #define TX_BD_FLAGS_STAMP                               (1 << 3)
  52         #define TX_BD_FLAGS_T_IP_CHKSUM                         (1 << 4)
  53         #define TX_BD_FLAGS_LSO                                 (1 << 5)
  54         #define TX_BD_FLAGS_IPID_FMT                            (1 << 6)
  55         #define TX_BD_FLAGS_T_IPID                              (1 << 7)
  56         #define TX_BD_HSIZE                                     (0xff << 16)
  57          #define TX_BD_HSIZE_SHIFT                               16
  58
  59         __le32 tx_bd_mss;
  60         __le32 tx_bd_cfa_action;
  61         #define TX_BD_CFA_ACTION                                (0xffff << 16)
  62          #define TX_BD_CFA_ACTION_SHIFT                          16
  63
  64         __le32 tx_bd_cfa_meta;
  65         #define TX_BD_CFA_META_MASK                             0xfffffff
  66         #define TX_BD_CFA_META_VID_MASK                         0xfff
  67         #define TX_BD_CFA_META_PRI_MASK                         (0xf << 12)
  68          #define TX_BD_CFA_META_PRI_SHIFT                        12
  69         #define TX_BD_CFA_META_TPID_MASK                        (3 << 16)
  70          #define TX_BD_CFA_META_TPID_SHIFT                       16
  71         #define TX_BD_CFA_META_KEY                              (0xf << 28)
  72          #define TX_BD_CFA_META_KEY_SHIFT                        28
  73         #define TX_BD_CFA_META_KEY_VLAN                         (1 << 28)
  74 };
  75
  76 struct rx_bd {
  77         __le32 rx_bd_len_flags_type;
  78         #define RX_BD_TYPE                                      (0x3f << 0)
  79          #define RX_BD_TYPE_RX_PACKET_BD                         0x4
  80          #define RX_BD_TYPE_RX_BUFFER_BD                         0x5
  81          #define RX_BD_TYPE_RX_AGG_BD                            0x6
  82          #define RX_BD_TYPE_16B_BD_SIZE                          (0 << 4)
  83          #define RX_BD_TYPE_32B_BD_SIZE                          (1 << 4)
  84          #define RX_BD_TYPE_48B_BD_SIZE                          (2 << 4)
  85          #define RX_BD_TYPE_64B_BD_SIZE                          (3 << 4)
  86         #define RX_BD_FLAGS_SOP                                 (1 << 6)
  87         #define RX_BD_FLAGS_EOP                                 (1 << 7)
  88         #define RX_BD_FLAGS_BUFFERS                             (3 << 8)
  89          #define RX_BD_FLAGS_1_BUFFER_PACKET                     (0 << 8)
  90          #define RX_BD_FLAGS_2_BUFFER_PACKET                     (1 << 8)
  91          #define RX_BD_FLAGS_3_BUFFER_PACKET                     (2 << 8)
  92          #define RX_BD_FLAGS_4_BUFFER_PACKET                     (3 << 8)
  93         #define RX_BD_LEN                                       (0xffff << 16)
  94          #define RX_BD_LEN_SHIFT                                 16
  95
  96         u32 rx_bd_opaque;
  97         __le64 rx_bd_haddr;
  98 };
  99
 100 struct tx_cmp {
 101         __le32 tx_cmp_flags_type;
 102         #define CMP_TYPE                                        (0x3f << 0)
 103          #define CMP_TYPE_TX_L2_CMP                              0
 104          #define CMP_TYPE_RX_L2_CMP                              17
 105          #define CMP_TYPE_RX_AGG_CMP                             18
 106          #define CMP_TYPE_RX_L2_TPA_START_CMP                    19
 107          #define CMP_TYPE_RX_L2_TPA_END_CMP                      21
 108          #define CMP_TYPE_STATUS_CMP                             32
 109          #define CMP_TYPE_REMOTE_DRIVER_REQ                      34
 110          #define CMP_TYPE_REMOTE_DRIVER_RESP                     36
 111          #define CMP_TYPE_ERROR_STATUS                           48
 112          #define CMPL_BASE_TYPE_STAT_EJECT                       0x1aUL
 113          #define CMPL_BASE_TYPE_HWRM_DONE                        0x20UL
 114          #define CMPL_BASE_TYPE_HWRM_FWD_REQ                     0x22UL
 115          #define CMPL_BASE_TYPE_HWRM_FWD_RESP                    0x24UL
 116          #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT                 0x2eUL
 117
 118         #define TX_CMP_FLAGS_ERROR                              (1 << 6)
 119         #define TX_CMP_FLAGS_PUSH                               (1 << 7)
 120
 121         u32 tx_cmp_opaque;
 122         __le32 tx_cmp_errors_v;
 123         #define TX_CMP_V                                        (1 << 0)
 124         #define TX_CMP_ERRORS_BUFFER_ERROR                      (7 << 1)
 125          #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR             0
 126          #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT           2
 127          #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG         4
 128          #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS          5
 129          #define TX_CMP_ERRORS_ZERO_LENGTH_PKT                   (1 << 4)
 130          #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN                  (1 << 5)
 131          #define TX_CMP_ERRORS_DMA_ERROR                         (1 << 6)
 132          #define TX_CMP_ERRORS_HINT_TOO_SHORT                    (1 << 7)
 133
 134         __le32 tx_cmp_unsed_3;
 135 };
 136
 137 struct rx_cmp {
 138         __le32 rx_cmp_len_flags_type;
 139         #define RX_CMP_CMP_TYPE                                 (0x3f << 0)
 140         #define RX_CMP_FLAGS_ERROR                              (1 << 6)
 141         #define RX_CMP_FLAGS_PLACEMENT                          (7 << 7)
 142         #define RX_CMP_FLAGS_RSS_VALID                          (1 << 10)
 143         #define RX_CMP_FLAGS_UNUSED                             (1 << 11)
 144          #define RX_CMP_FLAGS_ITYPES_SHIFT                       12
 145          #define RX_CMP_FLAGS_ITYPE_UNKNOWN                      (0 << 12)
 146          #define RX_CMP_FLAGS_ITYPE_IP                           (1 << 12)
 147          #define RX_CMP_FLAGS_ITYPE_TCP                          (2 << 12)
 148          #define RX_CMP_FLAGS_ITYPE_UDP                          (3 << 12)
 149          #define RX_CMP_FLAGS_ITYPE_FCOE                         (4 << 12)
 150          #define RX_CMP_FLAGS_ITYPE_ROCE                         (5 << 12)
 151          #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS                    (8 << 12)
 152          #define RX_CMP_FLAGS_ITYPE_PTP_W_TS                     (9 << 12)
 153         #define RX_CMP_LEN                                      (0xffff << 16)
 154          #define RX_CMP_LEN_SHIFT                                16
 155
 156         u32 rx_cmp_opaque;
 157         __le32 rx_cmp_misc_v1;
 158         #define RX_CMP_V1                                       (1 << 0)
 159         #define RX_CMP_AGG_BUFS                                 (0x1f << 1)
 160          #define RX_CMP_AGG_BUFS_SHIFT                           1
 161         #define RX_CMP_RSS_HASH_TYPE                            (0x7f << 9)
 162          #define RX_CMP_RSS_HASH_TYPE_SHIFT                      9
 163         #define RX_CMP_PAYLOAD_OFFSET                           (0xff << 16)
 164          #define RX_CMP_PAYLOAD_OFFSET_SHIFT                     16
 165
 166         __le32 rx_cmp_rss_hash;
 167 };
 168
 169 #define RX_CMP_HASH_VALID(rxcmp)                                \
 170         ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
 171
 172 #define RSS_PROFILE_ID_MASK     0x1f
 173
 174 #define RX_CMP_HASH_TYPE(rxcmp)                                 \
 175         (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
 176           RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
 177
 178 struct rx_cmp_ext {
 179         __le32 rx_cmp_flags2;
 180         #define RX_CMP_FLAGS2_IP_CS_CALC                        0x1
 181         #define RX_CMP_FLAGS2_L4_CS_CALC                        (0x1 << 1)
 182         #define RX_CMP_FLAGS2_T_IP_CS_CALC                      (0x1 << 2)
 183         #define RX_CMP_FLAGS2_T_L4_CS_CALC                      (0x1 << 3)
 184         #define RX_CMP_FLAGS2_META_FORMAT_VLAN                  (0x1 << 4)
 185         __le32 rx_cmp_meta_data;
 186         #define RX_CMP_FLAGS2_METADATA_VID_MASK                 0xfff
 187         #define RX_CMP_FLAGS2_METADATA_TPID_MASK                0xffff0000
 188          #define RX_CMP_FLAGS2_METADATA_TPID_SFT                 16
 189         __le32 rx_cmp_cfa_code_errors_v2;
 190         #define RX_CMP_V                                        (1 << 0)
 191         #define RX_CMPL_ERRORS_MASK                             (0x7fff << 1)
 192          #define RX_CMPL_ERRORS_SFT                              1
 193         #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK                (0x7 << 1)
 194          #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER           (0x0 << 1)
 195          #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT         (0x1 << 1)
 196          #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP         (0x2 << 1)
 197          #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT          (0x3 << 1)
 198         #define RX_CMPL_ERRORS_IP_CS_ERROR                      (0x1 << 4)
 199         #define RX_CMPL_ERRORS_L4_CS_ERROR                      (0x1 << 5)
 200         #define RX_CMPL_ERRORS_T_IP_CS_ERROR                    (0x1 << 6)
 201         #define RX_CMPL_ERRORS_T_L4_CS_ERROR                    (0x1 << 7)
 202         #define RX_CMPL_ERRORS_CRC_ERROR                        (0x1 << 8)
 203         #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK                 (0x7 << 9)
 204          #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR             (0x0 << 9)
 205          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION     (0x1 << 9)
 206          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN     (0x2 << 9)
 207          #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR   (0x3 << 9)
 208          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR     (0x4 << 9)
 209          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR    (0x5 << 9)
 210          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL         (0x6 << 9)
 211         #define RX_CMPL_ERRORS_PKT_ERROR_MASK                   (0xf << 12)
 212          #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR               (0x0 << 12)
 213          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION         (0x1 << 12)
 214          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN         (0x2 << 12)
 215          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL             (0x3 << 12)
 216          #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR         (0x4 << 12)
 217          #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR        (0x5 << 12)
 218          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN         (0x6 << 12)
 219          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
 220          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN         (0x8 << 12)
 221
 222         #define RX_CMPL_CFA_CODE_MASK                           (0xffff << 16)
 223          #define RX_CMPL_CFA_CODE_SFT                            16
 224
 225         __le32 rx_cmp_unused3;
 226 };
 227
 228 #define RX_CMP_L2_ERRORS                                                \
 229         cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
 230
 231 #define RX_CMP_L4_CS_BITS                                               \
 232         (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
 233
 234 #define RX_CMP_L4_CS_ERR_BITS                                           \
 235         (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
 236
 237 #define RX_CMP_L4_CS_OK(rxcmp1)                                         \
 238             (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) &&           \
 239              !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
 240
 241 #define RX_CMP_ENCAP(rxcmp1)                                            \
 242             ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &                    \
 243              RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
 244
 245 struct rx_agg_cmp {
 246         __le32 rx_agg_cmp_len_flags_type;
 247         #define RX_AGG_CMP_TYPE                                 (0x3f << 0)
 248         #define RX_AGG_CMP_LEN                                  (0xffff << 16)
 249          #define RX_AGG_CMP_LEN_SHIFT                            16
 250         u32 rx_agg_cmp_opaque;
 251         __le32 rx_agg_cmp_v;
 252         #define RX_AGG_CMP_V                                    (1 << 0)
 253         __le32 rx_agg_cmp_unused;
 254 };
 255
 256 struct rx_tpa_start_cmp {
 257         __le32 rx_tpa_start_cmp_len_flags_type;
 258         #define RX_TPA_START_CMP_TYPE                           (0x3f << 0)
 259         #define RX_TPA_START_CMP_FLAGS                          (0x3ff << 6)
 260          #define RX_TPA_START_CMP_FLAGS_SHIFT                    6
 261         #define RX_TPA_START_CMP_FLAGS_PLACEMENT                (0x7 << 7)
 262          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT          7
 263          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO          (0x1 << 7)
 264          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS            (0x2 << 7)
 265          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO      (0x5 << 7)
 266          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS        (0x6 << 7)
 267         #define RX_TPA_START_CMP_FLAGS_RSS_VALID                (0x1 << 10)
 268         #define RX_TPA_START_CMP_FLAGS_ITYPES                   (0xf << 12)
 269          #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT             12
 270          #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP                (0x2 << 12)
 271         #define RX_TPA_START_CMP_LEN                            (0xffff << 16)
 272          #define RX_TPA_START_CMP_LEN_SHIFT                      16
 273
 274         u32 rx_tpa_start_cmp_opaque;
 275         __le32 rx_tpa_start_cmp_misc_v1;
 276         #define RX_TPA_START_CMP_V1                             (0x1 << 0)
 277         #define RX_TPA_START_CMP_RSS_HASH_TYPE                  (0x7f << 9)
 278          #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT            9
 279         #define RX_TPA_START_CMP_AGG_ID                         (0x7f << 25)
 280          #define RX_TPA_START_CMP_AGG_ID_SHIFT                   25
 281
 282         __le32 rx_tpa_start_cmp_rss_hash;
 283 };
 284
 285 #define TPA_START_HASH_VALID(rx_tpa_start)                              \
 286         ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &              \
 287          cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
 288
 289 #define TPA_START_HASH_TYPE(rx_tpa_start)                               \
 290         (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &      \
 291            RX_TPA_START_CMP_RSS_HASH_TYPE) >>                           \
 292           RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
 293
 294 #define TPA_START_AGG_ID(rx_tpa_start)                                  \
 295         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &       \
 296          RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
 297
 298 struct rx_tpa_start_cmp_ext {
 299         __le32 rx_tpa_start_cmp_flags2;
 300         #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC              (0x1 << 0)
 301         #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC              (0x1 << 1)
 302         #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC            (0x1 << 2)
 303         #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC            (0x1 << 3)
 304         #define RX_TPA_START_CMP_FLAGS2_IP_TYPE                 (0x1 << 8)
 305
 306         __le32 rx_tpa_start_cmp_metadata;
 307         __le32 rx_tpa_start_cmp_cfa_code_v2;
 308         #define RX_TPA_START_CMP_V2                             (0x1 << 0)
 309         #define RX_TPA_START_CMP_CFA_CODE                       (0xffff << 16)
 310          #define RX_TPA_START_CMPL_CFA_CODE_SHIFT                16
 311         __le32 rx_tpa_start_cmp_hdr_info;
 312 };
 313
 314 struct rx_tpa_end_cmp {
 315         __le32 rx_tpa_end_cmp_len_flags_type;
 316         #define RX_TPA_END_CMP_TYPE                             (0x3f << 0)
 317         #define RX_TPA_END_CMP_FLAGS                            (0x3ff << 6)
 318          #define RX_TPA_END_CMP_FLAGS_SHIFT                      6
 319         #define RX_TPA_END_CMP_FLAGS_PLACEMENT                  (0x7 << 7)
 320          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT            7
 321          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO            (0x1 << 7)
 322          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS              (0x2 << 7)
 323          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO        (0x5 << 7)
 324          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS          (0x6 << 7)
 325         #define RX_TPA_END_CMP_FLAGS_RSS_VALID                  (0x1 << 10)
 326         #define RX_TPA_END_CMP_FLAGS_ITYPES                     (0xf << 12)
 327          #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT               12
 328          #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP                  (0x2 << 12)
 329         #define RX_TPA_END_CMP_LEN                              (0xffff << 16)
 330          #define RX_TPA_END_CMP_LEN_SHIFT                        16
 331
 332         u32 rx_tpa_end_cmp_opaque;
 333         __le32 rx_tpa_end_cmp_misc_v1;
 334         #define RX_TPA_END_CMP_V1                               (0x1 << 0)
 335         #define RX_TPA_END_CMP_AGG_BUFS                         (0x3f << 1)
 336          #define RX_TPA_END_CMP_AGG_BUFS_SHIFT                   1
 337         #define RX_TPA_END_CMP_TPA_SEGS                         (0xff << 8)
 338          #define RX_TPA_END_CMP_TPA_SEGS_SHIFT                   8
 339         #define RX_TPA_END_CMP_PAYLOAD_OFFSET                   (0xff << 16)
 340          #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT             16
 341         #define RX_TPA_END_CMP_AGG_ID                           (0x7f << 25)
 342          #define RX_TPA_END_CMP_AGG_ID_SHIFT                     25
 343
 344         __le32 rx_tpa_end_cmp_tsdelta;
 345         #define RX_TPA_END_GRO_TS                               (0x1 << 31)
 346 };
 347
 348 #define TPA_END_AGG_ID(rx_tpa_end)                                      \
 349         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 350          RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
 351
 352 #define TPA_END_TPA_SEGS(rx_tpa_end)                                    \
 353         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 354          RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
 355
 356 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO                          \
 357         cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO &          \
 358                     RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
 359
 360 #define TPA_END_GRO(rx_tpa_end)                                         \
 361         ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &                  \
 362          RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
 363
 364 #define TPA_END_GRO_TS(rx_tpa_end)                                      \
 365         (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta &                      \
 366             cpu_to_le32(RX_TPA_END_GRO_TS)))
 367
 368 struct rx_tpa_end_cmp_ext {
 369         __le32 rx_tpa_end_cmp_dup_acks;
 370         #define RX_TPA_END_CMP_TPA_DUP_ACKS                     (0xf << 0)
 371
 372         __le32 rx_tpa_end_cmp_seg_len;
 373         #define RX_TPA_END_CMP_TPA_SEG_LEN                      (0xffff << 0)
 374
 375         __le32 rx_tpa_end_cmp_errors_v2;
 376         #define RX_TPA_END_CMP_V2                               (0x1 << 0)
 377         #define RX_TPA_END_CMP_ERRORS                           (0x3 << 1)
 378         #define RX_TPA_END_CMPL_ERRORS_SHIFT                     1
 379
 380         u32 rx_tpa_end_cmp_start_opaque;
 381 };
 382
 383 #define TPA_END_ERRORS(rx_tpa_end_ext)                                  \
 384         ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 &                   \
 385          cpu_to_le32(RX_TPA_END_CMP_ERRORS))
 386
 387 #define DB_IDX_MASK                                             0xffffff
 388 #define DB_IDX_VALID                                            (0x1 << 26)
 389 #define DB_IRQ_DIS                                              (0x1 << 27)
 390 #define DB_KEY_TX                                               (0x0 << 28)
 391 #define DB_KEY_RX                                               (0x1 << 28)
 392 #define DB_KEY_CP                                               (0x2 << 28)
 393 #define DB_KEY_ST                                               (0x3 << 28)
 394 #define DB_KEY_TX_PUSH                                          (0x4 << 28)
 395 #define DB_LONG_TX_PUSH                                         (0x2 << 24)
 396
 397 #define BNXT_MIN_ROCE_CP_RINGS  2
 398 #define BNXT_MIN_ROCE_STAT_CTXS 1
 399
 400 #define INVALID_HW_RING_ID      ((u16)-1)
 401
 402 /* The hardware supports certain page sizes.  Use the supported page sizes
 403  * to allocate the rings.
 404  */
 405 #if (PAGE_SHIFT < 12)
 406 #define BNXT_PAGE_SHIFT 12
 407 #elif (PAGE_SHIFT <= 13)
 408 #define BNXT_PAGE_SHIFT PAGE_SHIFT
 409 #elif (PAGE_SHIFT < 16)
 410 #define BNXT_PAGE_SHIFT 13
 411 #else
 412 #define BNXT_PAGE_SHIFT 16
 413 #endif
 414
 415 #define BNXT_PAGE_SIZE  (1 << BNXT_PAGE_SHIFT)
 416
 417 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
 418 #if (PAGE_SHIFT > 15)
 419 #define BNXT_RX_PAGE_SHIFT 15
 420 #else
 421 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
 422 #endif
 423
 424 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
 425
 426 #define BNXT_MAX_MTU            9500
 427 #define BNXT_MAX_PAGE_MODE_MTU  \
 428         ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN -       \
 429          XDP_PACKET_HEADROOM)
 430
 431 #define BNXT_MIN_PKT_SIZE       52
 432
 433 #define BNXT_DEFAULT_RX_RING_SIZE       511
 434 #define BNXT_DEFAULT_TX_RING_SIZE       511
 435
 436 #define MAX_TPA         64
 437
 438 #if (BNXT_PAGE_SHIFT == 16)
 439 #define MAX_RX_PAGES    1
 440 #define MAX_RX_AGG_PAGES        4
 441 #define MAX_TX_PAGES    1
 442 #define MAX_CP_PAGES    8
 443 #else
 444 #define MAX_RX_PAGES    8
 445 #define MAX_RX_AGG_PAGES        32
 446 #define MAX_TX_PAGES    8
 447 #define MAX_CP_PAGES    64
 448 #endif
 449
 450 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
 451 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
 452 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
 453
 454 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
 455 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
 456
 457 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
 458
 459 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
 460 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
 461
 462 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
 463
 464 #define BNXT_MAX_RX_DESC_CNT            (RX_DESC_CNT * MAX_RX_PAGES - 1)
 465 #define BNXT_MAX_RX_JUM_DESC_CNT        (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
 466 #define BNXT_MAX_TX_DESC_CNT            (TX_DESC_CNT * MAX_TX_PAGES - 1)
 467
 468 #define RX_RING(x)      (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 469 #define RX_IDX(x)       ((x) & (RX_DESC_CNT - 1))
 470
 471 #define TX_RING(x)      (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 472 #define TX_IDX(x)       ((x) & (TX_DESC_CNT - 1))
 473
 474 #define CP_RING(x)      (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 475 #define CP_IDX(x)       ((x) & (CP_DESC_CNT - 1))
 476
 477 #define TX_CMP_VALID(txcmp, raw_cons)                                   \
 478         (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==        \
 479          !((raw_cons) & bp->cp_bit))
 480
 481 #define RX_CMP_VALID(rxcmp1, raw_cons)                                  \
 482         (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
 483          !((raw_cons) & bp->cp_bit))
 484
 485 #define RX_AGG_CMP_VALID(agg, raw_cons)                         \
 486         (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
 487          !((raw_cons) & bp->cp_bit))
 488
 489 #define TX_CMP_TYPE(txcmp)                                      \
 490         (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
 491
 492 #define RX_CMP_TYPE(rxcmp)                                      \
 493         (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
 494
 495 #define NEXT_RX(idx)            (((idx) + 1) & bp->rx_ring_mask)
 496
 497 #define NEXT_RX_AGG(idx)        (((idx) + 1) & bp->rx_agg_ring_mask)
 498
 499 #define NEXT_TX(idx)            (((idx) + 1) & bp->tx_ring_mask)
 500
 501 #define ADV_RAW_CMP(idx, n)     ((idx) + (n))
 502 #define NEXT_RAW_CMP(idx)       ADV_RAW_CMP(idx, 1)
 503 #define RING_CMP(idx)           ((idx) & bp->cp_ring_mask)
 504 #define NEXT_CMP(idx)           RING_CMP(ADV_RAW_CMP(idx, 1))
 505
 506 #define BNXT_HWRM_MAX_REQ_LEN           (bp->hwrm_max_req_len)
 507 #define DFLT_HWRM_CMD_TIMEOUT           500
 508 #define HWRM_CMD_TIMEOUT                (bp->hwrm_cmd_timeout)
 509 #define HWRM_RESET_TIMEOUT              ((HWRM_CMD_TIMEOUT) * 4)
 510 #define HWRM_RESP_ERR_CODE_MASK         0xffff
 511 #define HWRM_RESP_LEN_OFFSET            4
 512 #define HWRM_RESP_LEN_MASK              0xffff0000
 513 #define HWRM_RESP_LEN_SFT               16
 514 #define HWRM_RESP_VALID_MASK            0xff000000
 515 #define HWRM_SEQ_ID_INVALID             -1
 516 #define BNXT_HWRM_REQ_MAX_SIZE          128
 517 #define BNXT_HWRM_REQS_PER_PAGE         (BNXT_PAGE_SIZE /       \
 518                                          BNXT_HWRM_REQ_MAX_SIZE)
 519
 520 #define BNXT_RX_EVENT   1
 521 #define BNXT_AGG_EVENT  2
 522 #define BNXT_TX_EVENT   4
 523
 524 struct bnxt_sw_tx_bd {
 525         struct sk_buff          *skb;
 526         DEFINE_DMA_UNMAP_ADDR(mapping);
 527         u8                      is_gso;
 528         u8                      is_push;
 529         union {
 530                 unsigned short          nr_frags;
 531                 u16                     rx_prod;
 532         };
 533 };
 534
 535 struct bnxt_sw_rx_bd {
 536         void                    *data;
 537         u8                      *data_ptr;
 538         dma_addr_t              mapping;
 539 };
 540
 541 struct bnxt_sw_rx_agg_bd {
 542         struct page             *page;
 543         unsigned int            offset;
 544         dma_addr_t              mapping;
 545 };
 546
 547 struct bnxt_ring_struct {
 548         int                     nr_pages;
 549         int                     page_size;
 550         void                    **pg_arr;
 551         dma_addr_t              *dma_arr;
 552
 553         __le64                  *pg_tbl;
 554         dma_addr_t              pg_tbl_map;
 555
 556         int                     vmem_size;
 557         void                    **vmem;
 558
 559         u16                     fw_ring_id; /* Ring id filled by Chimp FW */
 560         u8                      queue_id;
 561 };
 562
 563 struct tx_push_bd {
 564         __le32                  doorbell;
 565         __le32                  tx_bd_len_flags_type;
 566         u32                     tx_bd_opaque;
 567         struct tx_bd_ext        txbd2;
 568 };
 569
 570 struct tx_push_buffer {
 571         struct tx_push_bd       push_bd;
 572         u32                     data[25];
 573 };
 574
 575 struct bnxt_tx_ring_info {
 576         struct bnxt_napi        *bnapi;
 577         u16                     tx_prod;
 578         u16                     tx_cons;
 579         u16                     txq_index;
 580         void __iomem            *tx_doorbell;
 581
 582         struct tx_bd            *tx_desc_ring[MAX_TX_PAGES];
 583         struct bnxt_sw_tx_bd    *tx_buf_ring;
 584
 585         dma_addr_t              tx_desc_mapping[MAX_TX_PAGES];
 586
 587         struct tx_push_buffer   *tx_push;
 588         dma_addr_t              tx_push_mapping;
 589         __le64                  data_mapping;
 590
 591 #define BNXT_DEV_STATE_CLOSING  0x1
 592         u32                     dev_state;
 593
 594         struct bnxt_ring_struct tx_ring_struct;
 595 };
 596
 597 struct bnxt_tpa_info {
 598         void                    *data;
 599         u8                      *data_ptr;
 600         dma_addr_t              mapping;
 601         u16                     len;
 602         unsigned short          gso_type;
 603         u32                     flags2;
 604         u32                     metadata;
 605         enum pkt_hash_types     hash_type;
 606         u32                     rss_hash;
 607         u32                     hdr_info;
 608
 609 #define BNXT_TPA_L4_SIZE(hdr_info)      \
 610         (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
 611
 612 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
 613         (((hdr_info) >> 18) & 0x1ff)
 614
 615 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
 616         (((hdr_info) >> 9) & 0x1ff)
 617
 618 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
 619         ((hdr_info) & 0x1ff)
 620 };
 621
 622 struct bnxt_rx_ring_info {
 623         struct bnxt_napi        *bnapi;
 624         u16                     rx_prod;
 625         u16                     rx_agg_prod;
 626         u16                     rx_sw_agg_prod;
 627         u16                     rx_next_cons;
 628         void __iomem            *rx_doorbell;
 629         void __iomem            *rx_agg_doorbell;
 630
 631         struct bpf_prog         *xdp_prog;
 632
 633         struct rx_bd            *rx_desc_ring[MAX_RX_PAGES];
 634         struct bnxt_sw_rx_bd    *rx_buf_ring;
 635
 636         struct rx_bd            *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
 637         struct bnxt_sw_rx_agg_bd        *rx_agg_ring;
 638
 639         unsigned long           *rx_agg_bmap;
 640         u16                     rx_agg_bmap_size;
 641
 642         struct page             *rx_page;
 643         unsigned int            rx_page_offset;
 644
 645         dma_addr_t              rx_desc_mapping[MAX_RX_PAGES];
 646         dma_addr_t              rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
 647
 648         struct bnxt_tpa_info    *rx_tpa;
 649
 650         struct bnxt_ring_struct rx_ring_struct;
 651         struct bnxt_ring_struct rx_agg_ring_struct;
 652 };
 653
 654 struct bnxt_cp_ring_info {
 655         u32                     cp_raw_cons;
 656         void __iomem            *cp_doorbell;
 657
 658         struct tx_cmp           *cp_desc_ring[MAX_CP_PAGES];
 659
 660         dma_addr_t              cp_desc_mapping[MAX_CP_PAGES];
 661
 662         struct ctx_hw_stats     *hw_stats;
 663         dma_addr_t              hw_stats_map;
 664         u32                     hw_stats_ctx_id;
 665         u64                     rx_l4_csum_errors;
 666
 667         struct bnxt_ring_struct cp_ring_struct;
 668 };
 669
 670 struct bnxt_napi {
 671         struct napi_struct      napi;
 672         struct bnxt             *bp;
 673
 674         int                     index;
 675         struct bnxt_cp_ring_info        cp_ring;
 676         struct bnxt_rx_ring_info        *rx_ring;
 677         struct bnxt_tx_ring_info        *tx_ring;
 678
 679         void                    (*tx_int)(struct bnxt *, struct bnxt_napi *,
 680                                           int);
 681         u32                     flags;
 682 #define BNXT_NAPI_FLAG_XDP      0x1
 683
 684         bool                    in_reset;
 685 };
 686
 687 struct bnxt_irq {
 688         irq_handler_t   handler;
 689         unsigned int    vector;
 690         u8              requested;
 691         char            name[IFNAMSIZ + 2];
 692 };
 693
 694 #define HWRM_RING_ALLOC_TX      0x1
 695 #define HWRM_RING_ALLOC_RX      0x2
 696 #define HWRM_RING_ALLOC_AGG     0x4
 697 #define HWRM_RING_ALLOC_CMPL    0x8
 698
 699 #define INVALID_STATS_CTX_ID    -1
 700
 701 struct bnxt_ring_grp_info {
 702         u16     fw_stats_ctx;
 703         u16     fw_grp_id;
 704         u16     rx_fw_ring_id;
 705         u16     agg_fw_ring_id;
 706         u16     cp_fw_ring_id;
 707 };
 708
 709 struct bnxt_vnic_info {
 710         u16             fw_vnic_id; /* returned by Chimp during alloc */
 711 #define BNXT_MAX_CTX_PER_VNIC   2
 712         u16             fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
 713         u16             fw_l2_ctx_id;
 714 #define BNXT_MAX_UC_ADDRS       4
 715         __le64          fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
 716                                 /* index 0 always dev_addr */
 717         u16             uc_filter_count;
 718         u8              *uc_list;
 719
 720         u16             *fw_grp_ids;
 721         dma_addr_t      rss_table_dma_addr;
 722         __le16          *rss_table;
 723         dma_addr_t      rss_hash_key_dma_addr;
 724         u64             *rss_hash_key;
 725         u32             rx_mask;
 726
 727         u8              *mc_list;
 728         int             mc_list_size;
 729         int             mc_list_count;
 730         dma_addr_t      mc_list_mapping;
 731 #define BNXT_MAX_MC_ADDRS       16
 732
 733         u32             flags;
 734 #define BNXT_VNIC_RSS_FLAG      1
 735 #define BNXT_VNIC_RFS_FLAG      2
 736 #define BNXT_VNIC_MCAST_FLAG    4
 737 #define BNXT_VNIC_UCAST_FLAG    8
 738 #define BNXT_VNIC_RFS_NEW_RSS_FLAG      0x10
 739 };
 740
 741 #if defined(CONFIG_BNXT_SRIOV)
 742 struct bnxt_vf_info {
 743         u16     fw_fid;
 744         u8      mac_addr[ETH_ALEN];
 745         u16     max_rsscos_ctxs;
 746         u16     max_cp_rings;
 747         u16     max_tx_rings;
 748         u16     max_rx_rings;
 749         u16     max_hw_ring_grps;
 750         u16     max_l2_ctxs;
 751         u16     max_irqs;
 752         u16     max_vnics;
 753         u16     max_stat_ctxs;
 754         u16     vlan;
 755         u32     flags;
 756 #define BNXT_VF_QOS             0x1
 757 #define BNXT_VF_SPOOFCHK        0x2
 758 #define BNXT_VF_LINK_FORCED     0x4
 759 #define BNXT_VF_LINK_UP         0x8
 760         u32     func_flags; /* func cfg flags */
 761         u32     min_tx_rate;
 762         u32     max_tx_rate;
 763         void    *hwrm_cmd_req_addr;
 764         dma_addr_t      hwrm_cmd_req_dma_addr;
 765 };
 766 #endif
 767
 768 struct bnxt_pf_info {
 769 #define BNXT_FIRST_PF_FID       1
 770 #define BNXT_FIRST_VF_FID       128
 771         u16     fw_fid;
 772         u16     port_id;
 773         u8      mac_addr[ETH_ALEN];
 774         u16     max_rsscos_ctxs;
 775         u16     max_cp_rings;
 776         u16     max_tx_rings; /* HW assigned max tx rings for this PF */
 777         u16     max_rx_rings; /* HW assigned max rx rings for this PF */
 778         u16     max_hw_ring_grps;
 779         u16     max_irqs;
 780         u16     max_l2_ctxs;
 781         u16     max_vnics;
 782         u16     max_stat_ctxs;
 783         u32     first_vf_id;
 784         u16     active_vfs;
 785         u16     max_vfs;
 786         u32     max_encap_records;
 787         u32     max_decap_records;
 788         u32     max_tx_em_flows;
 789         u32     max_tx_wm_flows;
 790         u32     max_rx_em_flows;
 791         u32     max_rx_wm_flows;
 792         unsigned long   *vf_event_bmap;
 793         u16     hwrm_cmd_req_pages;
 794         void                    *hwrm_cmd_req_addr[4];
 795         dma_addr_t              hwrm_cmd_req_dma_addr[4];
 796         struct bnxt_vf_info     *vf;
 797 };
 798
 799 struct bnxt_ntuple_filter {
 800         struct hlist_node       hash;
 801         u8                      dst_mac_addr[ETH_ALEN];
 802         u8                      src_mac_addr[ETH_ALEN];
 803         struct flow_keys        fkeys;
 804         __le64                  filter_id;
 805         u16                     sw_id;
 806         u8                      l2_fltr_idx;
 807         u16                     rxq;
 808         u32                     flow_id;
 809         unsigned long           state;
 810 #define BNXT_FLTR_VALID         0
 811 #define BNXT_FLTR_UPDATE        1
 812 };
 813
 814 struct bnxt_link_info {
 815         u8                      phy_type;
 816         u8                      media_type;
 817         u8                      transceiver;
 818         u8                      phy_addr;
 819         u8                      phy_link_status;
 820 #define BNXT_LINK_NO_LINK       PORT_PHY_QCFG_RESP_LINK_NO_LINK
 821 #define BNXT_LINK_SIGNAL        PORT_PHY_QCFG_RESP_LINK_SIGNAL
 822 #define BNXT_LINK_LINK          PORT_PHY_QCFG_RESP_LINK_LINK
 823         u8                      wire_speed;
 824         u8                      loop_back;
 825         u8                      link_up;
 826         u8                      duplex;
 827 #define BNXT_LINK_DUPLEX_HALF   PORT_PHY_QCFG_RESP_DUPLEX_HALF
 828 #define BNXT_LINK_DUPLEX_FULL   PORT_PHY_QCFG_RESP_DUPLEX_FULL
 829         u8                      pause;
 830 #define BNXT_LINK_PAUSE_TX      PORT_PHY_QCFG_RESP_PAUSE_TX
 831 #define BNXT_LINK_PAUSE_RX      PORT_PHY_QCFG_RESP_PAUSE_RX
 832 #define BNXT_LINK_PAUSE_BOTH    (PORT_PHY_QCFG_RESP_PAUSE_RX | \
 833                                  PORT_PHY_QCFG_RESP_PAUSE_TX)
 834         u8                      lp_pause;
 835         u8                      auto_pause_setting;
 836         u8                      force_pause_setting;
 837         u8                      duplex_setting;
 838         u8                      auto_mode;
 839 #define BNXT_AUTO_MODE(mode)    ((mode) > BNXT_LINK_AUTO_NONE && \
 840                                  (mode) <= BNXT_LINK_AUTO_MSK)
 841 #define BNXT_LINK_AUTO_NONE     PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
 842 #define BNXT_LINK_AUTO_ALLSPDS  PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
 843 #define BNXT_LINK_AUTO_ONESPD   PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
 844 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
 845 #define BNXT_LINK_AUTO_MSK      PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
 846 #define PHY_VER_LEN             3
 847         u8                      phy_ver[PHY_VER_LEN];
 848         u16                     link_speed;
 849 #define BNXT_LINK_SPEED_100MB   PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
 850 #define BNXT_LINK_SPEED_1GB     PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
 851 #define BNXT_LINK_SPEED_2GB     PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
 852 #define BNXT_LINK_SPEED_2_5GB   PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
 853 #define BNXT_LINK_SPEED_10GB    PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
 854 #define BNXT_LINK_SPEED_20GB    PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
 855 #define BNXT_LINK_SPEED_25GB    PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
 856 #define BNXT_LINK_SPEED_40GB    PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
 857 #define BNXT_LINK_SPEED_50GB    PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
 858 #define BNXT_LINK_SPEED_100GB   PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
 859         u16                     support_speeds;
 860         u16                     auto_link_speeds;       /* fw adv setting */
 861 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
 862 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
 863 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
 864 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
 865 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
 866 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
 867 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
 868 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
 869 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
 870 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
 871         u16                     support_auto_speeds;
 872         u16                     lp_auto_link_speeds;
 873         u16                     force_link_speed;
 874         u32                     preemphasis;
 875         u8                      module_status;
 876         u16                     fec_cfg;
 877 #define BNXT_FEC_AUTONEG        PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
 878 #define BNXT_FEC_ENC_BASE_R     PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
 879 #define BNXT_FEC_ENC_RS         PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED
 880
 881         /* copy of requested setting from ethtool cmd */
 882         u8                      autoneg;
 883 #define BNXT_AUTONEG_SPEED              1
 884 #define BNXT_AUTONEG_FLOW_CTRL          2
 885         u8                      req_duplex;
 886         u8                      req_flow_ctrl;
 887         u16                     req_link_speed;
 888         u16                     advertising;    /* user adv setting */
 889         bool                    force_link_chng;
 890
 891         /* a copy of phy_qcfg output used to report link
 892          * info to VF
 893          */
 894         struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
 895 };
 896
 897 #define BNXT_MAX_QUEUE  8
 898
 899 struct bnxt_queue_info {
 900         u8      queue_id;
 901         u8      queue_profile;
 902 };
 903
 904 #define BNXT_MAX_LED                    4
 905
 906 struct bnxt_led_info {
 907         u8      led_id;
 908         u8      led_type;
 909         u8      led_group_id;
 910         u8      unused;
 911         __le16  led_state_caps;
 912 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
 913         cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
 914
 915         __le16  led_color_caps;
 916 };
 917
 918 #define BNXT_MAX_TEST   8
 919
 920 struct bnxt_test_info {
 921         u8 offline_mask;
 922         u16 timeout;
 923         char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
 924 };
 925
 926 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
 927 #define BNXT_CAG_REG_LEGACY_INT_STATUS  0x4014
 928 #define BNXT_CAG_REG_BASE               0x300000
 929
 930 struct bnxt {
 931         void __iomem            *bar0;
 932         void __iomem            *bar1;
 933         void __iomem            *bar2;
 934
 935         u32                     reg_base;
 936         u16                     chip_num;
 937 #define CHIP_NUM_57301          0x16c8
 938 #define CHIP_NUM_57302          0x16c9
 939 #define CHIP_NUM_57304          0x16ca
 940 #define CHIP_NUM_58700          0x16cd
 941 #define CHIP_NUM_57402          0x16d0
 942 #define CHIP_NUM_57404          0x16d1
 943 #define CHIP_NUM_57406          0x16d2
 944
 945 #define CHIP_NUM_57311          0x16ce
 946 #define CHIP_NUM_57312          0x16cf
 947 #define CHIP_NUM_57314          0x16df
 948 #define CHIP_NUM_57412          0x16d6
 949 #define CHIP_NUM_57414          0x16d7
 950 #define CHIP_NUM_57416          0x16d8
 951 #define CHIP_NUM_57417          0x16d9
 952
 953 #define BNXT_CHIP_NUM_5730X(chip_num)           \
 954         ((chip_num) >= CHIP_NUM_57301 &&        \
 955          (chip_num) <= CHIP_NUM_57304)
 956
 957 #define BNXT_CHIP_NUM_5740X(chip_num)           \
 958         ((chip_num) >= CHIP_NUM_57402 &&        \
 959          (chip_num) <= CHIP_NUM_57406)
 960
 961 #define BNXT_CHIP_NUM_5731X(chip_num)           \
 962         ((chip_num) == CHIP_NUM_57311 ||        \
 963          (chip_num) == CHIP_NUM_57312 ||        \
 964          (chip_num) == CHIP_NUM_57314)
 965
 966 #define BNXT_CHIP_NUM_5741X(chip_num)           \
 967         ((chip_num) >= CHIP_NUM_57412 &&        \
 968          (chip_num) <= CHIP_NUM_57417)
 969
 970 #define BNXT_CHIP_NUM_57X0X(chip_num)           \
 971         (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
 972
 973 #define BNXT_CHIP_NUM_57X1X(chip_num)           \
 974         (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
 975
 976         struct net_device       *dev;
 977         struct pci_dev          *pdev;
 978
 979         atomic_t                intr_sem;
 980
 981         u32                     flags;
 982         #define BNXT_FLAG_DCB_ENABLED   0x1
 983         #define BNXT_FLAG_VF            0x2
 984         #define BNXT_FLAG_LRO           0x4
 985 #ifdef CONFIG_INET
 986         #define BNXT_FLAG_GRO           0x8
 987 #else
 988         /* Cannot support hardware GRO if CONFIG_INET is not set */
 989         #define BNXT_FLAG_GRO           0x0
 990 #endif
 991         #define BNXT_FLAG_TPA           (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
 992         #define BNXT_FLAG_JUMBO         0x10
 993         #define BNXT_FLAG_STRIP_VLAN    0x20
 994         #define BNXT_FLAG_AGG_RINGS     (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
 995                                          BNXT_FLAG_LRO)
 996         #define BNXT_FLAG_USING_MSIX    0x40
 997         #define BNXT_FLAG_MSIX_CAP      0x80
 998         #define BNXT_FLAG_RFS           0x100
 999         #define BNXT_FLAG_SHARED_RINGS  0x200
1000         #define BNXT_FLAG_PORT_STATS    0x400
1001         #define BNXT_FLAG_UDP_RSS_CAP   0x800
1002         #define BNXT_FLAG_EEE_CAP       0x1000
1003         #define BNXT_FLAG_NEW_RSS_CAP   0x2000
1004         #define BNXT_FLAG_WOL_CAP       0x4000
1005         #define BNXT_FLAG_ROCEV1_CAP    0x8000
1006         #define BNXT_FLAG_ROCEV2_CAP    0x10000
1007         #define BNXT_FLAG_ROCE_CAP      (BNXT_FLAG_ROCEV1_CAP | \
1008                                          BNXT_FLAG_ROCEV2_CAP)
1009         #define BNXT_FLAG_NO_AGG_RINGS  0x20000
1010         #define BNXT_FLAG_RX_PAGE_MODE  0x40000
1011         #define BNXT_FLAG_FW_LLDP_AGENT 0x80000
1012         #define BNXT_FLAG_MULTI_HOST    0x100000
1013         #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1014
1015         #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA |             \
1016                                             BNXT_FLAG_RFS |             \
1017                                             BNXT_FLAG_STRIP_VLAN)
1018
1019 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
1020 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
1021 #define BNXT_NPAR(bp)           ((bp)->port_partition_type)
1022 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1023 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1024 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1025 #define BNXT_RX_PAGE_MODE(bp)   ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1026
1027         struct bnxt_en_dev      *edev;
1028         struct bnxt_en_dev *    (*ulp_probe)(struct net_device *);
1029
1030         struct bnxt_napi        **bnapi;
1031
1032         struct bnxt_rx_ring_info        *rx_ring;
1033         struct bnxt_tx_ring_info        *tx_ring;
1034         u16                     *tx_ring_map;
1035
1036         struct sk_buff *        (*gro_func)(struct bnxt_tpa_info *, int, int,
1037                                             struct sk_buff *);
1038
1039         struct sk_buff *        (*rx_skb_func)(struct bnxt *,
1040                                                struct bnxt_rx_ring_info *,
1041                                                u16, void *, u8 *, dma_addr_t,
1042                                                unsigned int);
1043
1044         u32                     rx_buf_size;
1045         u32                     rx_buf_use_size;        /* useable size */
1046         u16                     rx_offset;
1047         u16                     rx_dma_offset;
1048         enum dma_data_direction rx_dir;
1049         u32                     rx_ring_size;
1050         u32                     rx_agg_ring_size;
1051         u32                     rx_copy_thresh;
1052         u32                     rx_ring_mask;
1053         u32                     rx_agg_ring_mask;
1054         int                     rx_nr_pages;
1055         int                     rx_agg_nr_pages;
1056         int                     rx_nr_rings;
1057         int                     rsscos_nr_ctxs;
1058
1059         u32                     tx_ring_size;
1060         u32                     tx_ring_mask;
1061         int                     tx_nr_pages;
1062         int                     tx_nr_rings;
1063         int                     tx_nr_rings_per_tc;
1064         int                     tx_nr_rings_xdp;
1065
1066         int                     tx_wake_thresh;
1067         int                     tx_push_thresh;
1068         int                     tx_push_size;
1069
1070         u32                     cp_ring_size;
1071         u32                     cp_ring_mask;
1072         u32                     cp_bit;
1073         int                     cp_nr_pages;
1074         int                     cp_nr_rings;
1075
1076         int                     num_stat_ctxs;
1077
1078         /* grp_info indexed by completion ring index */
1079         struct bnxt_ring_grp_info       *grp_info;
1080         struct bnxt_vnic_info   *vnic_info;
1081         int                     nr_vnics;
1082         u32                     rss_hash_cfg;
1083
1084         u8                      max_tc;
1085         u8                      max_lltc;       /* lossless TCs */
1086         struct bnxt_queue_info  q_info[BNXT_MAX_QUEUE];
1087
1088         unsigned int            current_interval;
1089 #define BNXT_TIMER_INTERVAL     HZ
1090
1091         struct timer_list       timer;
1092
1093         unsigned long           state;
1094 #define BNXT_STATE_OPEN         0
1095 #define BNXT_STATE_IN_SP_TASK   1
1096
1097         struct bnxt_irq *irq_tbl;
1098         int                     total_irqs;
1099         u8                      mac_addr[ETH_ALEN];
1100
1101 #ifdef CONFIG_BNXT_DCB
1102         struct ieee_pfc         *ieee_pfc;
1103         struct ieee_ets         *ieee_ets;
1104         u8                      dcbx_cap;
1105         u8                      default_pri;
1106 #endif /* CONFIG_BNXT_DCB */
1107
1108         u32                     msg_enable;
1109
1110         u32                     hwrm_spec_code;
1111         u16                     hwrm_cmd_seq;
1112         u32                     hwrm_intr_seq_id;
1113         void                    *hwrm_cmd_resp_addr;
1114         dma_addr_t              hwrm_cmd_resp_dma_addr;
1115         void                    *hwrm_dbg_resp_addr;
1116         dma_addr_t              hwrm_dbg_resp_dma_addr;
1117 #define HWRM_DBG_REG_BUF_SIZE   128
1118
1119         struct rx_port_stats    *hw_rx_port_stats;
1120         struct tx_port_stats    *hw_tx_port_stats;
1121         dma_addr_t              hw_rx_port_stats_map;
1122         dma_addr_t              hw_tx_port_stats_map;
1123         int                     hw_port_stats_size;
1124
1125         u16                     hwrm_max_req_len;
1126         int                     hwrm_cmd_timeout;
1127         struct mutex            hwrm_cmd_lock;  /* serialize hwrm messages */
1128         struct hwrm_ver_get_output      ver_resp;
1129 #define FW_VER_STR_LEN          32
1130 #define BC_HWRM_STR_LEN         21
1131 #define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1132         char                    fw_ver_str[FW_VER_STR_LEN];
1133         __be16                  vxlan_port;
1134         u8                      vxlan_port_cnt;
1135         __le16                  vxlan_fw_dst_port_id;
1136         __be16                  nge_port;
1137         u8                      nge_port_cnt;
1138         __le16                  nge_fw_dst_port_id;
1139         u8                      port_partition_type;
1140
1141         u16                     rx_coal_ticks;
1142         u16                     rx_coal_ticks_irq;
1143         u16                     rx_coal_bufs;
1144         u16                     rx_coal_bufs_irq;
1145         u16                     tx_coal_ticks;
1146         u16                     tx_coal_ticks_irq;
1147         u16                     tx_coal_bufs;
1148         u16                     tx_coal_bufs_irq;
1149
1150 #define BNXT_USEC_TO_COAL_TIMER(x)      ((x) * 25 / 2)
1151
1152         u32                     stats_coal_ticks;
1153 #define BNXT_DEF_STATS_COAL_TICKS        1000000
1154 #define BNXT_MIN_STATS_COAL_TICKS         250000
1155 #define BNXT_MAX_STATS_COAL_TICKS        1000000
1156
1157         struct work_struct      sp_task;
1158         unsigned long           sp_event;
1159 #define BNXT_RX_MASK_SP_EVENT           0
1160 #define BNXT_RX_NTP_FLTR_SP_EVENT       1
1161 #define BNXT_LINK_CHNG_SP_EVENT         2
1162 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1163 #define BNXT_VXLAN_ADD_PORT_SP_EVENT    4
1164 #define BNXT_VXLAN_DEL_PORT_SP_EVENT    5
1165 #define BNXT_RESET_TASK_SP_EVENT        6
1166 #define BNXT_RST_RING_SP_EVENT          7
1167 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT    8
1168 #define BNXT_PERIODIC_STATS_SP_EVENT    9
1169 #define BNXT_HWRM_PORT_MODULE_SP_EVENT  10
1170 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1171 #define BNXT_GENEVE_ADD_PORT_SP_EVENT   12
1172 #define BNXT_GENEVE_DEL_PORT_SP_EVENT   13
1173 #define BNXT_LINK_SPEED_CHNG_SP_EVENT   14
1174
1175         struct bnxt_pf_info     pf;
1176 #ifdef CONFIG_BNXT_SRIOV
1177         int                     nr_vfs;
1178         struct bnxt_vf_info     vf;
1179         wait_queue_head_t       sriov_cfg_wait;
1180         bool                    sriov_cfg;
1181 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1182 #endif
1183
1184 #define BNXT_NTP_FLTR_MAX_FLTR  4096
1185 #define BNXT_NTP_FLTR_HASH_SIZE 512
1186 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1187         struct hlist_head       ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1188         spinlock_t              ntp_fltr_lock;  /* for hash table add, del */
1189
1190         unsigned long           *ntp_fltr_bmap;
1191         int                     ntp_fltr_count;
1192
1193         struct bnxt_link_info   link_info;
1194         struct ethtool_eee      eee;
1195         u32                     lpi_tmr_lo;
1196         u32                     lpi_tmr_hi;
1197
1198         u8                      num_tests;
1199         struct bnxt_test_info   *test_info;
1200
1201         u8                      wol_filter_id;
1202         u8                      wol;
1203
1204         u8                      num_leds;
1205         struct bnxt_led_info    leds[BNXT_MAX_LED];
1206
1207         struct bpf_prog         *xdp_prog;
1208 };
1209
1210 #define BNXT_RX_STATS_OFFSET(counter)                   \
1211         (offsetof(struct rx_port_stats, counter) / 8)
1212
1213 #define BNXT_TX_STATS_OFFSET(counter)                   \
1214         ((offsetof(struct tx_port_stats, counter) +     \
1215           sizeof(struct rx_port_stats) + 512) / 8)
1216
1217 #define I2C_DEV_ADDR_A0                         0xa0
1218 #define I2C_DEV_ADDR_A2                         0xa2
1219 #define SFP_EEPROM_SFF_8472_COMP_ADDR           0x5e
1220 #define SFP_EEPROM_SFF_8472_COMP_SIZE           1
1221 #define SFF_MODULE_ID_SFP                       0x3
1222 #define SFF_MODULE_ID_QSFP                      0xc
1223 #define SFF_MODULE_ID_QSFP_PLUS                 0xd
1224 #define SFF_MODULE_ID_QSFP28                    0x11
1225 #define BNXT_MAX_PHY_I2C_RESP_SIZE              64
1226
1227 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
1228 {
1229         /* Tell compiler to fetch tx indices from memory. */
1230         barrier();
1231
1232         return bp->tx_ring_size -
1233                 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
1234 }
1235
1236 extern const u16 bnxt_lhint_arr[];
1237
1238 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1239                        u16 prod, gfp_t gfp);
1240 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
1241 void bnxt_set_tpa_flags(struct bnxt *bp);
1242 void bnxt_set_ring_params(struct bnxt *);
1243 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
1244 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
1245 int _hwrm_send_message(struct bnxt *, void *, u32, int);
1246 int hwrm_send_message(struct bnxt *, void *, u32, int);
1247 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
1248 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
1249                                      int bmap_size);
1250 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
1251 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
1252 int bnxt_hwrm_set_coal(struct bnxt *);
1253 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
1254 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max);
1255 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
1256 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max);
1257 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max);
1258 void bnxt_tx_disable(struct bnxt *bp);
1259 void bnxt_tx_enable(struct bnxt *bp);
1260 int bnxt_hwrm_set_pause(struct bnxt *);
1261 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
1262 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
1263 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
1264 int bnxt_hwrm_fw_set_time(struct bnxt *);
1265 int bnxt_open_nic(struct bnxt *, bool, bool);
1266 int bnxt_half_open_nic(struct bnxt *bp);
1267 void bnxt_half_close_nic(struct bnxt *bp);
1268 int bnxt_close_nic(struct bnxt *, bool, bool);
1269 int bnxt_reserve_rings(struct bnxt *bp, int tx, int rx, int tcs, int tx_xdp);
1270 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
1271 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
1272 void bnxt_restore_pf_fw_resources(struct bnxt *bp);
1273 #endif