drivers/net/ethernet/broadcom/bnxt/bnxt.h

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2018 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #ifndef BNXT_H
  12 #define BNXT_H
  13
  14 #define DRV_MODULE_NAME         "bnxt_en"
  15 #define DRV_MODULE_VERSION      "1.10.0"
  16
  17 #define DRV_VER_MAJ     1
  18 #define DRV_VER_MIN     10
  19 #define DRV_VER_UPD     0
  20
  21 #include <linux/interrupt.h>
  22 #include <linux/rhashtable.h>
  23 #include <net/devlink.h>
  24 #include <net/dst_metadata.h>
  25 #include <net/switchdev.h>
  26 #include <net/xdp.h>
  27 #include <linux/net_dim.h>
  28
  29 struct tx_bd {
  30         __le32 tx_bd_len_flags_type;
  31         #define TX_BD_TYPE                                      (0x3f << 0)
  32          #define TX_BD_TYPE_SHORT_TX_BD                          (0x00 << 0)
  33          #define TX_BD_TYPE_LONG_TX_BD                           (0x10 << 0)
  34         #define TX_BD_FLAGS_PACKET_END                          (1 << 6)
  35         #define TX_BD_FLAGS_NO_CMPL                             (1 << 7)
  36         #define TX_BD_FLAGS_BD_CNT                              (0x1f << 8)
  37          #define TX_BD_FLAGS_BD_CNT_SHIFT                        8
  38         #define TX_BD_FLAGS_LHINT                               (3 << 13)
  39          #define TX_BD_FLAGS_LHINT_SHIFT                         13
  40          #define TX_BD_FLAGS_LHINT_512_AND_SMALLER               (0 << 13)
  41          #define TX_BD_FLAGS_LHINT_512_TO_1023                   (1 << 13)
  42          #define TX_BD_FLAGS_LHINT_1024_TO_2047                  (2 << 13)
  43          #define TX_BD_FLAGS_LHINT_2048_AND_LARGER               (3 << 13)
  44         #define TX_BD_FLAGS_COAL_NOW                            (1 << 15)
  45         #define TX_BD_LEN                                       (0xffff << 16)
  46          #define TX_BD_LEN_SHIFT                                 16
  47
  48         u32 tx_bd_opaque;
  49         __le64 tx_bd_haddr;
  50 } __packed;
  51
  52 struct tx_bd_ext {
  53         __le32 tx_bd_hsize_lflags;
  54         #define TX_BD_FLAGS_TCP_UDP_CHKSUM                      (1 << 0)
  55         #define TX_BD_FLAGS_IP_CKSUM                            (1 << 1)
  56         #define TX_BD_FLAGS_NO_CRC                              (1 << 2)
  57         #define TX_BD_FLAGS_STAMP                               (1 << 3)
  58         #define TX_BD_FLAGS_T_IP_CHKSUM                         (1 << 4)
  59         #define TX_BD_FLAGS_LSO                                 (1 << 5)
  60         #define TX_BD_FLAGS_IPID_FMT                            (1 << 6)
  61         #define TX_BD_FLAGS_T_IPID                              (1 << 7)
  62         #define TX_BD_HSIZE                                     (0xff << 16)
  63          #define TX_BD_HSIZE_SHIFT                               16
  64
  65         __le32 tx_bd_mss;
  66         __le32 tx_bd_cfa_action;
  67         #define TX_BD_CFA_ACTION                                (0xffff << 16)
  68          #define TX_BD_CFA_ACTION_SHIFT                          16
  69
  70         __le32 tx_bd_cfa_meta;
  71         #define TX_BD_CFA_META_MASK                             0xfffffff
  72         #define TX_BD_CFA_META_VID_MASK                         0xfff
  73         #define TX_BD_CFA_META_PRI_MASK                         (0xf << 12)
  74          #define TX_BD_CFA_META_PRI_SHIFT                        12
  75         #define TX_BD_CFA_META_TPID_MASK                        (3 << 16)
  76          #define TX_BD_CFA_META_TPID_SHIFT                       16
  77         #define TX_BD_CFA_META_KEY                              (0xf << 28)
  78          #define TX_BD_CFA_META_KEY_SHIFT                        28
  79         #define TX_BD_CFA_META_KEY_VLAN                         (1 << 28)
  80 };
  81
  82 struct rx_bd {
  83         __le32 rx_bd_len_flags_type;
  84         #define RX_BD_TYPE                                      (0x3f << 0)
  85          #define RX_BD_TYPE_RX_PACKET_BD                         0x4
  86          #define RX_BD_TYPE_RX_BUFFER_BD                         0x5
  87          #define RX_BD_TYPE_RX_AGG_BD                            0x6
  88          #define RX_BD_TYPE_16B_BD_SIZE                          (0 << 4)
  89          #define RX_BD_TYPE_32B_BD_SIZE                          (1 << 4)
  90          #define RX_BD_TYPE_48B_BD_SIZE                          (2 << 4)
  91          #define RX_BD_TYPE_64B_BD_SIZE                          (3 << 4)
  92         #define RX_BD_FLAGS_SOP                                 (1 << 6)
  93         #define RX_BD_FLAGS_EOP                                 (1 << 7)
  94         #define RX_BD_FLAGS_BUFFERS                             (3 << 8)
  95          #define RX_BD_FLAGS_1_BUFFER_PACKET                     (0 << 8)
  96          #define RX_BD_FLAGS_2_BUFFER_PACKET                     (1 << 8)
  97          #define RX_BD_FLAGS_3_BUFFER_PACKET                     (2 << 8)
  98          #define RX_BD_FLAGS_4_BUFFER_PACKET                     (3 << 8)
  99         #define RX_BD_LEN                                       (0xffff << 16)
 100          #define RX_BD_LEN_SHIFT                                 16
 101
 102         u32 rx_bd_opaque;
 103         __le64 rx_bd_haddr;
 104 };
 105
 106 struct tx_cmp {
 107         __le32 tx_cmp_flags_type;
 108         #define CMP_TYPE                                        (0x3f << 0)
 109          #define CMP_TYPE_TX_L2_CMP                              0
 110          #define CMP_TYPE_RX_L2_CMP                              17
 111          #define CMP_TYPE_RX_AGG_CMP                             18
 112          #define CMP_TYPE_RX_L2_TPA_START_CMP                    19
 113          #define CMP_TYPE_RX_L2_TPA_END_CMP                      21
 114          #define CMP_TYPE_STATUS_CMP                             32
 115          #define CMP_TYPE_REMOTE_DRIVER_REQ                      34
 116          #define CMP_TYPE_REMOTE_DRIVER_RESP                     36
 117          #define CMP_TYPE_ERROR_STATUS                           48
 118          #define CMPL_BASE_TYPE_STAT_EJECT                       0x1aUL
 119          #define CMPL_BASE_TYPE_HWRM_DONE                        0x20UL
 120          #define CMPL_BASE_TYPE_HWRM_FWD_REQ                     0x22UL
 121          #define CMPL_BASE_TYPE_HWRM_FWD_RESP                    0x24UL
 122          #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT                 0x2eUL
 123
 124         #define TX_CMP_FLAGS_ERROR                              (1 << 6)
 125         #define TX_CMP_FLAGS_PUSH                               (1 << 7)
 126
 127         u32 tx_cmp_opaque;
 128         __le32 tx_cmp_errors_v;
 129         #define TX_CMP_V                                        (1 << 0)
 130         #define TX_CMP_ERRORS_BUFFER_ERROR                      (7 << 1)
 131          #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR             0
 132          #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT           2
 133          #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG         4
 134          #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS          5
 135          #define TX_CMP_ERRORS_ZERO_LENGTH_PKT                   (1 << 4)
 136          #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN                  (1 << 5)
 137          #define TX_CMP_ERRORS_DMA_ERROR                         (1 << 6)
 138          #define TX_CMP_ERRORS_HINT_TOO_SHORT                    (1 << 7)
 139
 140         __le32 tx_cmp_unsed_3;
 141 };
 142
 143 struct rx_cmp {
 144         __le32 rx_cmp_len_flags_type;
 145         #define RX_CMP_CMP_TYPE                                 (0x3f << 0)
 146         #define RX_CMP_FLAGS_ERROR                              (1 << 6)
 147         #define RX_CMP_FLAGS_PLACEMENT                          (7 << 7)
 148         #define RX_CMP_FLAGS_RSS_VALID                          (1 << 10)
 149         #define RX_CMP_FLAGS_UNUSED                             (1 << 11)
 150          #define RX_CMP_FLAGS_ITYPES_SHIFT                       12
 151          #define RX_CMP_FLAGS_ITYPE_UNKNOWN                      (0 << 12)
 152          #define RX_CMP_FLAGS_ITYPE_IP                           (1 << 12)
 153          #define RX_CMP_FLAGS_ITYPE_TCP                          (2 << 12)
 154          #define RX_CMP_FLAGS_ITYPE_UDP                          (3 << 12)
 155          #define RX_CMP_FLAGS_ITYPE_FCOE                         (4 << 12)
 156          #define RX_CMP_FLAGS_ITYPE_ROCE                         (5 << 12)
 157          #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS                    (8 << 12)
 158          #define RX_CMP_FLAGS_ITYPE_PTP_W_TS                     (9 << 12)
 159         #define RX_CMP_LEN                                      (0xffff << 16)
 160          #define RX_CMP_LEN_SHIFT                                16
 161
 162         u32 rx_cmp_opaque;
 163         __le32 rx_cmp_misc_v1;
 164         #define RX_CMP_V1                                       (1 << 0)
 165         #define RX_CMP_AGG_BUFS                                 (0x1f << 1)
 166          #define RX_CMP_AGG_BUFS_SHIFT                           1
 167         #define RX_CMP_RSS_HASH_TYPE                            (0x7f << 9)
 168          #define RX_CMP_RSS_HASH_TYPE_SHIFT                      9
 169         #define RX_CMP_PAYLOAD_OFFSET                           (0xff << 16)
 170          #define RX_CMP_PAYLOAD_OFFSET_SHIFT                     16
 171
 172         __le32 rx_cmp_rss_hash;
 173 };
 174
 175 #define RX_CMP_HASH_VALID(rxcmp)                                \
 176         ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
 177
 178 #define RSS_PROFILE_ID_MASK     0x1f
 179
 180 #define RX_CMP_HASH_TYPE(rxcmp)                                 \
 181         (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
 182           RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
 183
 184 struct rx_cmp_ext {
 185         __le32 rx_cmp_flags2;
 186         #define RX_CMP_FLAGS2_IP_CS_CALC                        0x1
 187         #define RX_CMP_FLAGS2_L4_CS_CALC                        (0x1 << 1)
 188         #define RX_CMP_FLAGS2_T_IP_CS_CALC                      (0x1 << 2)
 189         #define RX_CMP_FLAGS2_T_L4_CS_CALC                      (0x1 << 3)
 190         #define RX_CMP_FLAGS2_META_FORMAT_VLAN                  (0x1 << 4)
 191         __le32 rx_cmp_meta_data;
 192         #define RX_CMP_FLAGS2_METADATA_TCI_MASK                 0xffff
 193         #define RX_CMP_FLAGS2_METADATA_VID_MASK                 0xfff
 194         #define RX_CMP_FLAGS2_METADATA_TPID_MASK                0xffff0000
 195          #define RX_CMP_FLAGS2_METADATA_TPID_SFT                 16
 196         __le32 rx_cmp_cfa_code_errors_v2;
 197         #define RX_CMP_V                                        (1 << 0)
 198         #define RX_CMPL_ERRORS_MASK                             (0x7fff << 1)
 199          #define RX_CMPL_ERRORS_SFT                              1
 200         #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK                (0x7 << 1)
 201          #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER           (0x0 << 1)
 202          #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT         (0x1 << 1)
 203          #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP         (0x2 << 1)
 204          #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT          (0x3 << 1)
 205         #define RX_CMPL_ERRORS_IP_CS_ERROR                      (0x1 << 4)
 206         #define RX_CMPL_ERRORS_L4_CS_ERROR                      (0x1 << 5)
 207         #define RX_CMPL_ERRORS_T_IP_CS_ERROR                    (0x1 << 6)
 208         #define RX_CMPL_ERRORS_T_L4_CS_ERROR                    (0x1 << 7)
 209         #define RX_CMPL_ERRORS_CRC_ERROR                        (0x1 << 8)
 210         #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK                 (0x7 << 9)
 211          #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR             (0x0 << 9)
 212          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION     (0x1 << 9)
 213          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN     (0x2 << 9)
 214          #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR   (0x3 << 9)
 215          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR     (0x4 << 9)
 216          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR    (0x5 << 9)
 217          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL         (0x6 << 9)
 218         #define RX_CMPL_ERRORS_PKT_ERROR_MASK                   (0xf << 12)
 219          #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR               (0x0 << 12)
 220          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION         (0x1 << 12)
 221          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN         (0x2 << 12)
 222          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL             (0x3 << 12)
 223          #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR         (0x4 << 12)
 224          #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR        (0x5 << 12)
 225          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN         (0x6 << 12)
 226          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
 227          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN         (0x8 << 12)
 228
 229         #define RX_CMPL_CFA_CODE_MASK                           (0xffff << 16)
 230          #define RX_CMPL_CFA_CODE_SFT                            16
 231
 232         __le32 rx_cmp_unused3;
 233 };
 234
 235 #define RX_CMP_L2_ERRORS                                                \
 236         cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
 237
 238 #define RX_CMP_L4_CS_BITS                                               \
 239         (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
 240
 241 #define RX_CMP_L4_CS_ERR_BITS                                           \
 242         (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
 243
 244 #define RX_CMP_L4_CS_OK(rxcmp1)                                         \
 245             (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) &&           \
 246              !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
 247
 248 #define RX_CMP_ENCAP(rxcmp1)                                            \
 249             ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &                    \
 250              RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
 251
 252 #define RX_CMP_CFA_CODE(rxcmpl1)                                        \
 253         ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) &           \
 254           RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
 255
 256 struct rx_agg_cmp {
 257         __le32 rx_agg_cmp_len_flags_type;
 258         #define RX_AGG_CMP_TYPE                                 (0x3f << 0)
 259         #define RX_AGG_CMP_LEN                                  (0xffff << 16)
 260          #define RX_AGG_CMP_LEN_SHIFT                            16
 261         u32 rx_agg_cmp_opaque;
 262         __le32 rx_agg_cmp_v;
 263         #define RX_AGG_CMP_V                                    (1 << 0)
 264         __le32 rx_agg_cmp_unused;
 265 };
 266
 267 struct rx_tpa_start_cmp {
 268         __le32 rx_tpa_start_cmp_len_flags_type;
 269         #define RX_TPA_START_CMP_TYPE                           (0x3f << 0)
 270         #define RX_TPA_START_CMP_FLAGS                          (0x3ff << 6)
 271          #define RX_TPA_START_CMP_FLAGS_SHIFT                    6
 272         #define RX_TPA_START_CMP_FLAGS_PLACEMENT                (0x7 << 7)
 273          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT          7
 274          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO          (0x1 << 7)
 275          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS            (0x2 << 7)
 276          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO      (0x5 << 7)
 277          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS        (0x6 << 7)
 278         #define RX_TPA_START_CMP_FLAGS_RSS_VALID                (0x1 << 10)
 279         #define RX_TPA_START_CMP_FLAGS_ITYPES                   (0xf << 12)
 280          #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT             12
 281          #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP                (0x2 << 12)
 282         #define RX_TPA_START_CMP_LEN                            (0xffff << 16)
 283          #define RX_TPA_START_CMP_LEN_SHIFT                      16
 284
 285         u32 rx_tpa_start_cmp_opaque;
 286         __le32 rx_tpa_start_cmp_misc_v1;
 287         #define RX_TPA_START_CMP_V1                             (0x1 << 0)
 288         #define RX_TPA_START_CMP_RSS_HASH_TYPE                  (0x7f << 9)
 289          #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT            9
 290         #define RX_TPA_START_CMP_AGG_ID                         (0x7f << 25)
 291          #define RX_TPA_START_CMP_AGG_ID_SHIFT                   25
 292
 293         __le32 rx_tpa_start_cmp_rss_hash;
 294 };
 295
 296 #define TPA_START_HASH_VALID(rx_tpa_start)                              \
 297         ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &              \
 298          cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
 299
 300 #define TPA_START_HASH_TYPE(rx_tpa_start)                               \
 301         (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &      \
 302            RX_TPA_START_CMP_RSS_HASH_TYPE) >>                           \
 303           RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
 304
 305 #define TPA_START_AGG_ID(rx_tpa_start)                                  \
 306         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &       \
 307          RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
 308
 309 struct rx_tpa_start_cmp_ext {
 310         __le32 rx_tpa_start_cmp_flags2;
 311         #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC              (0x1 << 0)
 312         #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC              (0x1 << 1)
 313         #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC            (0x1 << 2)
 314         #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC            (0x1 << 3)
 315         #define RX_TPA_START_CMP_FLAGS2_IP_TYPE                 (0x1 << 8)
 316
 317         __le32 rx_tpa_start_cmp_metadata;
 318         __le32 rx_tpa_start_cmp_cfa_code_v2;
 319         #define RX_TPA_START_CMP_V2                             (0x1 << 0)
 320         #define RX_TPA_START_CMP_CFA_CODE                       (0xffff << 16)
 321          #define RX_TPA_START_CMPL_CFA_CODE_SHIFT                16
 322         __le32 rx_tpa_start_cmp_hdr_info;
 323 };
 324
 325 #define TPA_START_CFA_CODE(rx_tpa_start)                                \
 326         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &   \
 327          RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
 328
 329 #define TPA_START_IS_IPV6(rx_tpa_start)                         \
 330         (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 &           \
 331             cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
 332
 333 struct rx_tpa_end_cmp {
 334         __le32 rx_tpa_end_cmp_len_flags_type;
 335         #define RX_TPA_END_CMP_TYPE                             (0x3f << 0)
 336         #define RX_TPA_END_CMP_FLAGS                            (0x3ff << 6)
 337          #define RX_TPA_END_CMP_FLAGS_SHIFT                      6
 338         #define RX_TPA_END_CMP_FLAGS_PLACEMENT                  (0x7 << 7)
 339          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT            7
 340          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO            (0x1 << 7)
 341          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS              (0x2 << 7)
 342          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO        (0x5 << 7)
 343          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS          (0x6 << 7)
 344         #define RX_TPA_END_CMP_FLAGS_RSS_VALID                  (0x1 << 10)
 345         #define RX_TPA_END_CMP_FLAGS_ITYPES                     (0xf << 12)
 346          #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT               12
 347          #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP                  (0x2 << 12)
 348         #define RX_TPA_END_CMP_LEN                              (0xffff << 16)
 349          #define RX_TPA_END_CMP_LEN_SHIFT                        16
 350
 351         u32 rx_tpa_end_cmp_opaque;
 352         __le32 rx_tpa_end_cmp_misc_v1;
 353         #define RX_TPA_END_CMP_V1                               (0x1 << 0)
 354         #define RX_TPA_END_CMP_AGG_BUFS                         (0x3f << 1)
 355          #define RX_TPA_END_CMP_AGG_BUFS_SHIFT                   1
 356         #define RX_TPA_END_CMP_TPA_SEGS                         (0xff << 8)
 357          #define RX_TPA_END_CMP_TPA_SEGS_SHIFT                   8
 358         #define RX_TPA_END_CMP_PAYLOAD_OFFSET                   (0xff << 16)
 359          #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT             16
 360         #define RX_TPA_END_CMP_AGG_ID                           (0x7f << 25)
 361          #define RX_TPA_END_CMP_AGG_ID_SHIFT                     25
 362
 363         __le32 rx_tpa_end_cmp_tsdelta;
 364         #define RX_TPA_END_GRO_TS                               (0x1 << 31)
 365 };
 366
 367 #define TPA_END_AGG_ID(rx_tpa_end)                                      \
 368         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 369          RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
 370
 371 #define TPA_END_TPA_SEGS(rx_tpa_end)                                    \
 372         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 373          RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
 374
 375 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO                          \
 376         cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO &          \
 377                     RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
 378
 379 #define TPA_END_GRO(rx_tpa_end)                                         \
 380         ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &                  \
 381          RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
 382
 383 #define TPA_END_GRO_TS(rx_tpa_end)                                      \
 384         (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta &                      \
 385             cpu_to_le32(RX_TPA_END_GRO_TS)))
 386
 387 struct rx_tpa_end_cmp_ext {
 388         __le32 rx_tpa_end_cmp_dup_acks;
 389         #define RX_TPA_END_CMP_TPA_DUP_ACKS                     (0xf << 0)
 390
 391         __le32 rx_tpa_end_cmp_seg_len;
 392         #define RX_TPA_END_CMP_TPA_SEG_LEN                      (0xffff << 0)
 393
 394         __le32 rx_tpa_end_cmp_errors_v2;
 395         #define RX_TPA_END_CMP_V2                               (0x1 << 0)
 396         #define RX_TPA_END_CMP_ERRORS                           (0x3 << 1)
 397         #define RX_TPA_END_CMPL_ERRORS_SHIFT                     1
 398
 399         u32 rx_tpa_end_cmp_start_opaque;
 400 };
 401
 402 #define TPA_END_ERRORS(rx_tpa_end_ext)                                  \
 403         ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 &                   \
 404          cpu_to_le32(RX_TPA_END_CMP_ERRORS))
 405
 406 struct nqe_cn {
 407         __le16  type;
 408         #define NQ_CN_TYPE_MASK           0x3fUL
 409         #define NQ_CN_TYPE_SFT            0
 410         #define NQ_CN_TYPE_CQ_NOTIFICATION  0x30UL
 411         #define NQ_CN_TYPE_LAST            NQ_CN_TYPE_CQ_NOTIFICATION
 412         __le16  reserved16;
 413         __le32  cq_handle_low;
 414         __le32  v;
 415         #define NQ_CN_V     0x1UL
 416         __le32  cq_handle_high;
 417 };
 418
 419 #define DB_IDX_MASK                                             0xffffff
 420 #define DB_IDX_VALID                                            (0x1 << 26)
 421 #define DB_IRQ_DIS                                              (0x1 << 27)
 422 #define DB_KEY_TX                                               (0x0 << 28)
 423 #define DB_KEY_RX                                               (0x1 << 28)
 424 #define DB_KEY_CP                                               (0x2 << 28)
 425 #define DB_KEY_ST                                               (0x3 << 28)
 426 #define DB_KEY_TX_PUSH                                          (0x4 << 28)
 427 #define DB_LONG_TX_PUSH                                         (0x2 << 24)
 428
 429 #define BNXT_MIN_ROCE_CP_RINGS  2
 430 #define BNXT_MIN_ROCE_STAT_CTXS 1
 431
 432 /* 64-bit doorbell */
 433 #define DBR_INDEX_MASK                                  0x0000000000ffffffULL
 434 #define DBR_XID_MASK                                    0x000fffff00000000ULL
 435 #define DBR_XID_SFT                                     32
 436 #define DBR_PATH_L2                                     (0x1ULL << 56)
 437 #define DBR_TYPE_SQ                                     (0x0ULL << 60)
 438 #define DBR_TYPE_RQ                                     (0x1ULL << 60)
 439 #define DBR_TYPE_SRQ                                    (0x2ULL << 60)
 440 #define DBR_TYPE_SRQ_ARM                                (0x3ULL << 60)
 441 #define DBR_TYPE_CQ                                     (0x4ULL << 60)
 442 #define DBR_TYPE_CQ_ARMSE                               (0x5ULL << 60)
 443 #define DBR_TYPE_CQ_ARMALL                              (0x6ULL << 60)
 444 #define DBR_TYPE_CQ_ARMENA                              (0x7ULL << 60)
 445 #define DBR_TYPE_SRQ_ARMENA                             (0x8ULL << 60)
 446 #define DBR_TYPE_CQ_CUTOFF_ACK                          (0x9ULL << 60)
 447 #define DBR_TYPE_NQ                                     (0xaULL << 60)
 448 #define DBR_TYPE_NQ_ARM                                 (0xbULL << 60)
 449 #define DBR_TYPE_NULL                                   (0xfULL << 60)
 450
 451 #define INVALID_HW_RING_ID      ((u16)-1)
 452
 453 /* The hardware supports certain page sizes.  Use the supported page sizes
 454  * to allocate the rings.
 455  */
 456 #if (PAGE_SHIFT < 12)
 457 #define BNXT_PAGE_SHIFT 12
 458 #elif (PAGE_SHIFT <= 13)
 459 #define BNXT_PAGE_SHIFT PAGE_SHIFT
 460 #elif (PAGE_SHIFT < 16)
 461 #define BNXT_PAGE_SHIFT 13
 462 #else
 463 #define BNXT_PAGE_SHIFT 16
 464 #endif
 465
 466 #define BNXT_PAGE_SIZE  (1 << BNXT_PAGE_SHIFT)
 467
 468 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
 469 #if (PAGE_SHIFT > 15)
 470 #define BNXT_RX_PAGE_SHIFT 15
 471 #else
 472 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
 473 #endif
 474
 475 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
 476
 477 #define BNXT_MAX_MTU            9500
 478 #define BNXT_MAX_PAGE_MODE_MTU  \
 479         ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN -       \
 480          XDP_PACKET_HEADROOM)
 481
 482 #define BNXT_MIN_PKT_SIZE       52
 483
 484 #define BNXT_DEFAULT_RX_RING_SIZE       511
 485 #define BNXT_DEFAULT_TX_RING_SIZE       511
 486
 487 #define MAX_TPA         64
 488
 489 #if (BNXT_PAGE_SHIFT == 16)
 490 #define MAX_RX_PAGES    1
 491 #define MAX_RX_AGG_PAGES        4
 492 #define MAX_TX_PAGES    1
 493 #define MAX_CP_PAGES    8
 494 #else
 495 #define MAX_RX_PAGES    8
 496 #define MAX_RX_AGG_PAGES        32
 497 #define MAX_TX_PAGES    8
 498 #define MAX_CP_PAGES    64
 499 #endif
 500
 501 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
 502 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
 503 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
 504
 505 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
 506 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
 507
 508 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
 509
 510 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
 511 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
 512
 513 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
 514
 515 #define BNXT_MAX_RX_DESC_CNT            (RX_DESC_CNT * MAX_RX_PAGES - 1)
 516 #define BNXT_MAX_RX_JUM_DESC_CNT        (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
 517 #define BNXT_MAX_TX_DESC_CNT            (TX_DESC_CNT * MAX_TX_PAGES - 1)
 518
 519 #define RX_RING(x)      (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 520 #define RX_IDX(x)       ((x) & (RX_DESC_CNT - 1))
 521
 522 #define TX_RING(x)      (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 523 #define TX_IDX(x)       ((x) & (TX_DESC_CNT - 1))
 524
 525 #define CP_RING(x)      (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 526 #define CP_IDX(x)       ((x) & (CP_DESC_CNT - 1))
 527
 528 #define TX_CMP_VALID(txcmp, raw_cons)                                   \
 529         (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==        \
 530          !((raw_cons) & bp->cp_bit))
 531
 532 #define RX_CMP_VALID(rxcmp1, raw_cons)                                  \
 533         (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
 534          !((raw_cons) & bp->cp_bit))
 535
 536 #define RX_AGG_CMP_VALID(agg, raw_cons)                         \
 537         (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
 538          !((raw_cons) & bp->cp_bit))
 539
 540 #define NQ_CMP_VALID(nqcmp, raw_cons)                           \
 541         (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
 542
 543 #define TX_CMP_TYPE(txcmp)                                      \
 544         (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
 545
 546 #define RX_CMP_TYPE(rxcmp)                                      \
 547         (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
 548
 549 #define NEXT_RX(idx)            (((idx) + 1) & bp->rx_ring_mask)
 550
 551 #define NEXT_RX_AGG(idx)        (((idx) + 1) & bp->rx_agg_ring_mask)
 552
 553 #define NEXT_TX(idx)            (((idx) + 1) & bp->tx_ring_mask)
 554
 555 #define ADV_RAW_CMP(idx, n)     ((idx) + (n))
 556 #define NEXT_RAW_CMP(idx)       ADV_RAW_CMP(idx, 1)
 557 #define RING_CMP(idx)           ((idx) & bp->cp_ring_mask)
 558 #define NEXT_CMP(idx)           RING_CMP(ADV_RAW_CMP(idx, 1))
 559
 560 #define BNXT_HWRM_MAX_REQ_LEN           (bp->hwrm_max_req_len)
 561 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 562 #define DFLT_HWRM_CMD_TIMEOUT           500
 563 #define HWRM_CMD_TIMEOUT                (bp->hwrm_cmd_timeout)
 564 #define HWRM_RESET_TIMEOUT              ((HWRM_CMD_TIMEOUT) * 4)
 565 #define HWRM_RESP_ERR_CODE_MASK         0xffff
 566 #define HWRM_RESP_LEN_OFFSET            4
 567 #define HWRM_RESP_LEN_MASK              0xffff0000
 568 #define HWRM_RESP_LEN_SFT               16
 569 #define HWRM_RESP_VALID_MASK            0xff000000
 570 #define HWRM_SEQ_ID_INVALID             -1
 571 #define BNXT_HWRM_REQ_MAX_SIZE          128
 572 #define BNXT_HWRM_REQS_PER_PAGE         (BNXT_PAGE_SIZE /       \
 573                                          BNXT_HWRM_REQ_MAX_SIZE)
 574 #define HWRM_SHORT_MIN_TIMEOUT          3
 575 #define HWRM_SHORT_MAX_TIMEOUT          10
 576 #define HWRM_SHORT_TIMEOUT_COUNTER      5
 577
 578 #define HWRM_MIN_TIMEOUT                25
 579 #define HWRM_MAX_TIMEOUT                40
 580
 581 #define HWRM_TOTAL_TIMEOUT(n)   (((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ?  \
 582         ((n) * HWRM_SHORT_MIN_TIMEOUT) :                                \
 583         (HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT +          \
 584          ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT))
 585
 586 #define HWRM_VALID_BIT_DELAY_USEC       20
 587
 588 #define BNXT_RX_EVENT   1
 589 #define BNXT_AGG_EVENT  2
 590 #define BNXT_TX_EVENT   4
 591
 592 struct bnxt_sw_tx_bd {
 593         struct sk_buff          *skb;
 594         DEFINE_DMA_UNMAP_ADDR(mapping);
 595         u8                      is_gso;
 596         u8                      is_push;
 597         union {
 598                 unsigned short          nr_frags;
 599                 u16                     rx_prod;
 600         };
 601 };
 602
 603 struct bnxt_sw_rx_bd {
 604         void                    *data;
 605         u8                      *data_ptr;
 606         dma_addr_t              mapping;
 607 };
 608
 609 struct bnxt_sw_rx_agg_bd {
 610         struct page             *page;
 611         unsigned int            offset;
 612         dma_addr_t              mapping;
 613 };
 614
 615 struct bnxt_ring_mem_info {
 616         int                     nr_pages;
 617         int                     page_size;
 618         u32                     flags;
 619 #define BNXT_RMEM_VALID_PTE_FLAG        1
 620 #define BNXT_RMEM_RING_PTE_FLAG         2
 621
 622         void                    **pg_arr;
 623         dma_addr_t              *dma_arr;
 624
 625         __le64                  *pg_tbl;
 626         dma_addr_t              pg_tbl_map;
 627
 628         int                     vmem_size;
 629         void                    **vmem;
 630 };
 631
 632 struct bnxt_ring_struct {
 633         struct bnxt_ring_mem_info       ring_mem;
 634
 635         u16                     fw_ring_id; /* Ring id filled by Chimp FW */
 636         union {
 637                 u16             grp_idx;
 638                 u16             map_idx; /* Used by cmpl rings */
 639         };
 640         u32                     handle;
 641         u8                      queue_id;
 642 };
 643
 644 struct tx_push_bd {
 645         __le32                  doorbell;
 646         __le32                  tx_bd_len_flags_type;
 647         u32                     tx_bd_opaque;
 648         struct tx_bd_ext        txbd2;
 649 };
 650
 651 struct tx_push_buffer {
 652         struct tx_push_bd       push_bd;
 653         u32                     data[25];
 654 };
 655
 656 struct bnxt_db_info {
 657         void __iomem            *doorbell;
 658         union {
 659                 u64             db_key64;
 660                 u32             db_key32;
 661         };
 662 };
 663
 664 struct bnxt_tx_ring_info {
 665         struct bnxt_napi        *bnapi;
 666         u16                     tx_prod;
 667         u16                     tx_cons;
 668         u16                     txq_index;
 669         struct bnxt_db_info     tx_db;
 670
 671         struct tx_bd            *tx_desc_ring[MAX_TX_PAGES];
 672         struct bnxt_sw_tx_bd    *tx_buf_ring;
 673
 674         dma_addr_t              tx_desc_mapping[MAX_TX_PAGES];
 675
 676         struct tx_push_buffer   *tx_push;
 677         dma_addr_t              tx_push_mapping;
 678         __le64                  data_mapping;
 679
 680 #define BNXT_DEV_STATE_CLOSING  0x1
 681         u32                     dev_state;
 682
 683         struct bnxt_ring_struct tx_ring_struct;
 684 };
 685
 686 #define BNXT_LEGACY_COAL_CMPL_PARAMS                                    \
 687         (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN |           \
 688          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX |           \
 689          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET |               \
 690          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE |                 \
 691          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR |         \
 692          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
 693          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR |         \
 694          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
 695          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
 696
 697 #define BNXT_COAL_CMPL_ENABLES                                          \
 698         (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
 699          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
 700          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
 701          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
 702
 703 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE                                   \
 704         RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
 705
 706 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE                       \
 707         RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
 708
 709 struct bnxt_coal_cap {
 710         u32                     cmpl_params;
 711         u32                     nq_params;
 712         u16                     num_cmpl_dma_aggr_max;
 713         u16                     num_cmpl_dma_aggr_during_int_max;
 714         u16                     cmpl_aggr_dma_tmr_max;
 715         u16                     cmpl_aggr_dma_tmr_during_int_max;
 716         u16                     int_lat_tmr_min_max;
 717         u16                     int_lat_tmr_max_max;
 718         u16                     num_cmpl_aggr_int_max;
 719         u16                     timer_units;
 720 };
 721
 722 struct bnxt_coal {
 723         u16                     coal_ticks;
 724         u16                     coal_ticks_irq;
 725         u16                     coal_bufs;
 726         u16                     coal_bufs_irq;
 727                         /* RING_IDLE enabled when coal ticks < idle_thresh  */
 728         u16                     idle_thresh;
 729         u8                      bufs_per_record;
 730         u8                      budget;
 731 };
 732
 733 struct bnxt_tpa_info {
 734         void                    *data;
 735         u8                      *data_ptr;
 736         dma_addr_t              mapping;
 737         u16                     len;
 738         unsigned short          gso_type;
 739         u32                     flags2;
 740         u32                     metadata;
 741         enum pkt_hash_types     hash_type;
 742         u32                     rss_hash;
 743         u32                     hdr_info;
 744
 745 #define BNXT_TPA_L4_SIZE(hdr_info)      \
 746         (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
 747
 748 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
 749         (((hdr_info) >> 18) & 0x1ff)
 750
 751 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
 752         (((hdr_info) >> 9) & 0x1ff)
 753
 754 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
 755         ((hdr_info) & 0x1ff)
 756
 757         u16                     cfa_code; /* cfa_code in TPA start compl */
 758 };
 759
 760 struct bnxt_rx_ring_info {
 761         struct bnxt_napi        *bnapi;
 762         u16                     rx_prod;
 763         u16                     rx_agg_prod;
 764         u16                     rx_sw_agg_prod;
 765         u16                     rx_next_cons;
 766         struct bnxt_db_info     rx_db;
 767         struct bnxt_db_info     rx_agg_db;
 768
 769         struct bpf_prog         *xdp_prog;
 770
 771         struct rx_bd            *rx_desc_ring[MAX_RX_PAGES];
 772         struct bnxt_sw_rx_bd    *rx_buf_ring;
 773
 774         struct rx_bd            *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
 775         struct bnxt_sw_rx_agg_bd        *rx_agg_ring;
 776
 777         unsigned long           *rx_agg_bmap;
 778         u16                     rx_agg_bmap_size;
 779
 780         struct page             *rx_page;
 781         unsigned int            rx_page_offset;
 782
 783         dma_addr_t              rx_desc_mapping[MAX_RX_PAGES];
 784         dma_addr_t              rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
 785
 786         struct bnxt_tpa_info    *rx_tpa;
 787
 788         struct bnxt_ring_struct rx_ring_struct;
 789         struct bnxt_ring_struct rx_agg_ring_struct;
 790         struct xdp_rxq_info     xdp_rxq;
 791 };
 792
 793 struct bnxt_cp_ring_info {
 794         struct bnxt_napi        *bnapi;
 795         u32                     cp_raw_cons;
 796         struct bnxt_db_info     cp_db;
 797
 798         u8                      had_work_done:1;
 799         u8                      has_more_work:1;
 800
 801         u32                     last_cp_raw_cons;
 802
 803         struct bnxt_coal        rx_ring_coal;
 804         u64                     rx_packets;
 805         u64                     rx_bytes;
 806         u64                     event_ctr;
 807
 808         struct net_dim          dim;
 809
 810         union {
 811                 struct tx_cmp   *cp_desc_ring[MAX_CP_PAGES];
 812                 struct nqe_cn   *nq_desc_ring[MAX_CP_PAGES];
 813         };
 814
 815         dma_addr_t              cp_desc_mapping[MAX_CP_PAGES];
 816
 817         struct ctx_hw_stats     *hw_stats;
 818         dma_addr_t              hw_stats_map;
 819         u32                     hw_stats_ctx_id;
 820         u64                     rx_l4_csum_errors;
 821         u64                     missed_irqs;
 822
 823         struct bnxt_ring_struct cp_ring_struct;
 824
 825         struct bnxt_cp_ring_info *cp_ring_arr[2];
 826 #define BNXT_RX_HDL     0
 827 #define BNXT_TX_HDL     1
 828 };
 829
 830 struct bnxt_napi {
 831         struct napi_struct      napi;
 832         struct bnxt             *bp;
 833
 834         int                     index;
 835         struct bnxt_cp_ring_info        cp_ring;
 836         struct bnxt_rx_ring_info        *rx_ring;
 837         struct bnxt_tx_ring_info        *tx_ring;
 838
 839         void                    (*tx_int)(struct bnxt *, struct bnxt_napi *,
 840                                           int);
 841         int                     tx_pkts;
 842         u8                      events;
 843
 844         u32                     flags;
 845 #define BNXT_NAPI_FLAG_XDP      0x1
 846
 847         bool                    in_reset;
 848 };
 849
 850 struct bnxt_irq {
 851         irq_handler_t   handler;
 852         unsigned int    vector;
 853         u8              requested:1;
 854         u8              have_cpumask:1;
 855         char            name[IFNAMSIZ + 2];
 856         cpumask_var_t   cpu_mask;
 857 };
 858
 859 #define HWRM_RING_ALLOC_TX      0x1
 860 #define HWRM_RING_ALLOC_RX      0x2
 861 #define HWRM_RING_ALLOC_AGG     0x4
 862 #define HWRM_RING_ALLOC_CMPL    0x8
 863 #define HWRM_RING_ALLOC_NQ      0x10
 864
 865 #define INVALID_STATS_CTX_ID    -1
 866
 867 struct bnxt_ring_grp_info {
 868         u16     fw_stats_ctx;
 869         u16     fw_grp_id;
 870         u16     rx_fw_ring_id;
 871         u16     agg_fw_ring_id;
 872         u16     cp_fw_ring_id;
 873 };
 874
 875 struct bnxt_vnic_info {
 876         u16             fw_vnic_id; /* returned by Chimp during alloc */
 877 #define BNXT_MAX_CTX_PER_VNIC   8
 878         u16             fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
 879         u16             fw_l2_ctx_id;
 880 #define BNXT_MAX_UC_ADDRS       4
 881         __le64          fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
 882                                 /* index 0 always dev_addr */
 883         u16             uc_filter_count;
 884         u8              *uc_list;
 885
 886         u16             *fw_grp_ids;
 887         dma_addr_t      rss_table_dma_addr;
 888         __le16          *rss_table;
 889         dma_addr_t      rss_hash_key_dma_addr;
 890         u64             *rss_hash_key;
 891         u32             rx_mask;
 892
 893         u8              *mc_list;
 894         int             mc_list_size;
 895         int             mc_list_count;
 896         dma_addr_t      mc_list_mapping;
 897 #define BNXT_MAX_MC_ADDRS       16
 898
 899         u32             flags;
 900 #define BNXT_VNIC_RSS_FLAG      1
 901 #define BNXT_VNIC_RFS_FLAG      2
 902 #define BNXT_VNIC_MCAST_FLAG    4
 903 #define BNXT_VNIC_UCAST_FLAG    8
 904 #define BNXT_VNIC_RFS_NEW_RSS_FLAG      0x10
 905 };
 906
 907 struct bnxt_hw_resc {
 908         u16     min_rsscos_ctxs;
 909         u16     max_rsscos_ctxs;
 910         u16     min_cp_rings;
 911         u16     max_cp_rings;
 912         u16     resv_cp_rings;
 913         u16     min_tx_rings;
 914         u16     max_tx_rings;
 915         u16     resv_tx_rings;
 916         u16     max_tx_sch_inputs;
 917         u16     min_rx_rings;
 918         u16     max_rx_rings;
 919         u16     resv_rx_rings;
 920         u16     min_hw_ring_grps;
 921         u16     max_hw_ring_grps;
 922         u16     resv_hw_ring_grps;
 923         u16     min_l2_ctxs;
 924         u16     max_l2_ctxs;
 925         u16     min_vnics;
 926         u16     max_vnics;
 927         u16     resv_vnics;
 928         u16     min_stat_ctxs;
 929         u16     max_stat_ctxs;
 930         u16     max_irqs;
 931 };
 932
 933 #if defined(CONFIG_BNXT_SRIOV)
 934 struct bnxt_vf_info {
 935         u16     fw_fid;
 936         u8      mac_addr[ETH_ALEN];     /* PF assigned MAC Address */
 937         u8      vf_mac_addr[ETH_ALEN];  /* VF assigned MAC address, only
 938                                          * stored by PF.
 939                                          */
 940         u16     vlan;
 941         u32     flags;
 942 #define BNXT_VF_QOS             0x1
 943 #define BNXT_VF_SPOOFCHK        0x2
 944 #define BNXT_VF_LINK_FORCED     0x4
 945 #define BNXT_VF_LINK_UP         0x8
 946 #define BNXT_VF_TRUST           0x10
 947         u32     func_flags; /* func cfg flags */
 948         u32     min_tx_rate;
 949         u32     max_tx_rate;
 950         void    *hwrm_cmd_req_addr;
 951         dma_addr_t      hwrm_cmd_req_dma_addr;
 952 };
 953 #endif
 954
 955 struct bnxt_pf_info {
 956 #define BNXT_FIRST_PF_FID       1
 957 #define BNXT_FIRST_VF_FID       128
 958         u16     fw_fid;
 959         u16     port_id;
 960         u8      mac_addr[ETH_ALEN];
 961         u32     first_vf_id;
 962         u16     active_vfs;
 963         u16     max_vfs;
 964         u32     max_encap_records;
 965         u32     max_decap_records;
 966         u32     max_tx_em_flows;
 967         u32     max_tx_wm_flows;
 968         u32     max_rx_em_flows;
 969         u32     max_rx_wm_flows;
 970         unsigned long   *vf_event_bmap;
 971         u16     hwrm_cmd_req_pages;
 972         u8      vf_resv_strategy;
 973 #define BNXT_VF_RESV_STRATEGY_MAXIMAL   0
 974 #define BNXT_VF_RESV_STRATEGY_MINIMAL   1
 975 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC    2
 976         void                    *hwrm_cmd_req_addr[4];
 977         dma_addr_t              hwrm_cmd_req_dma_addr[4];
 978         struct bnxt_vf_info     *vf;
 979 };
 980
 981 struct bnxt_ntuple_filter {
 982         struct hlist_node       hash;
 983         u8                      dst_mac_addr[ETH_ALEN];
 984         u8                      src_mac_addr[ETH_ALEN];
 985         struct flow_keys        fkeys;
 986         __le64                  filter_id;
 987         u16                     sw_id;
 988         u8                      l2_fltr_idx;
 989         u16                     rxq;
 990         u32                     flow_id;
 991         unsigned long           state;
 992 #define BNXT_FLTR_VALID         0
 993 #define BNXT_FLTR_UPDATE        1
 994 };
 995
 996 struct bnxt_link_info {
 997         u8                      phy_type;
 998         u8                      media_type;
 999         u8                      transceiver;
1000         u8                      phy_addr;
1001         u8                      phy_link_status;
1002 #define BNXT_LINK_NO_LINK       PORT_PHY_QCFG_RESP_LINK_NO_LINK
1003 #define BNXT_LINK_SIGNAL        PORT_PHY_QCFG_RESP_LINK_SIGNAL
1004 #define BNXT_LINK_LINK          PORT_PHY_QCFG_RESP_LINK_LINK
1005         u8                      wire_speed;
1006         u8                      loop_back;
1007         u8                      link_up;
1008         u8                      duplex;
1009 #define BNXT_LINK_DUPLEX_HALF   PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1010 #define BNXT_LINK_DUPLEX_FULL   PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1011         u8                      pause;
1012 #define BNXT_LINK_PAUSE_TX      PORT_PHY_QCFG_RESP_PAUSE_TX
1013 #define BNXT_LINK_PAUSE_RX      PORT_PHY_QCFG_RESP_PAUSE_RX
1014 #define BNXT_LINK_PAUSE_BOTH    (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1015                                  PORT_PHY_QCFG_RESP_PAUSE_TX)
1016         u8                      lp_pause;
1017         u8                      auto_pause_setting;
1018         u8                      force_pause_setting;
1019         u8                      duplex_setting;
1020         u8                      auto_mode;
1021 #define BNXT_AUTO_MODE(mode)    ((mode) > BNXT_LINK_AUTO_NONE && \
1022                                  (mode) <= BNXT_LINK_AUTO_MSK)
1023 #define BNXT_LINK_AUTO_NONE     PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1024 #define BNXT_LINK_AUTO_ALLSPDS  PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1025 #define BNXT_LINK_AUTO_ONESPD   PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1026 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1027 #define BNXT_LINK_AUTO_MSK      PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1028 #define PHY_VER_LEN             3
1029         u8                      phy_ver[PHY_VER_LEN];
1030         u16                     link_speed;
1031 #define BNXT_LINK_SPEED_100MB   PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1032 #define BNXT_LINK_SPEED_1GB     PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1033 #define BNXT_LINK_SPEED_2GB     PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1034 #define BNXT_LINK_SPEED_2_5GB   PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1035 #define BNXT_LINK_SPEED_10GB    PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1036 #define BNXT_LINK_SPEED_20GB    PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1037 #define BNXT_LINK_SPEED_25GB    PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1038 #define BNXT_LINK_SPEED_40GB    PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1039 #define BNXT_LINK_SPEED_50GB    PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1040 #define BNXT_LINK_SPEED_100GB   PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1041         u16                     support_speeds;
1042         u16                     auto_link_speeds;       /* fw adv setting */
1043 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1044 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1045 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1046 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1047 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1048 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1049 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1050 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1051 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1052 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1053         u16                     support_auto_speeds;
1054         u16                     lp_auto_link_speeds;
1055         u16                     force_link_speed;
1056         u32                     preemphasis;
1057         u8                      module_status;
1058         u16                     fec_cfg;
1059 #define BNXT_FEC_AUTONEG        PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1060 #define BNXT_FEC_ENC_BASE_R     PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1061 #define BNXT_FEC_ENC_RS         PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED
1062
1063         /* copy of requested setting from ethtool cmd */
1064         u8                      autoneg;
1065 #define BNXT_AUTONEG_SPEED              1
1066 #define BNXT_AUTONEG_FLOW_CTRL          2
1067         u8                      req_duplex;
1068         u8                      req_flow_ctrl;
1069         u16                     req_link_speed;
1070         u16                     advertising;    /* user adv setting */
1071         bool                    force_link_chng;
1072
1073         bool                    phy_retry;
1074         unsigned long           phy_retry_expires;
1075
1076         /* a copy of phy_qcfg output used to report link
1077          * info to VF
1078          */
1079         struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1080 };
1081
1082 #define BNXT_MAX_QUEUE  8
1083
1084 struct bnxt_queue_info {
1085         u8      queue_id;
1086         u8      queue_profile;
1087 };
1088
1089 #define BNXT_MAX_LED                    4
1090
1091 struct bnxt_led_info {
1092         u8      led_id;
1093         u8      led_type;
1094         u8      led_group_id;
1095         u8      unused;
1096         __le16  led_state_caps;
1097 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
1098         cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1099
1100         __le16  led_color_caps;
1101 };
1102
1103 #define BNXT_MAX_TEST   8
1104
1105 struct bnxt_test_info {
1106         u8 offline_mask;
1107         u8 flags;
1108 #define BNXT_TEST_FL_EXT_LPBK   0x1
1109         u16 timeout;
1110         char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1111 };
1112
1113 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
1114 #define BNXT_CAG_REG_LEGACY_INT_STATUS  0x4014
1115 #define BNXT_CAG_REG_BASE               0x300000
1116
1117 struct bnxt_tc_flow_stats {
1118         u64             packets;
1119         u64             bytes;
1120 };
1121
1122 struct bnxt_tc_info {
1123         bool                            enabled;
1124
1125         /* hash table to store TC offloaded flows */
1126         struct rhashtable               flow_table;
1127         struct rhashtable_params        flow_ht_params;
1128
1129         /* hash table to store L2 keys of TC flows */
1130         struct rhashtable               l2_table;
1131         struct rhashtable_params        l2_ht_params;
1132         /* hash table to store L2 keys for TC tunnel decap */
1133         struct rhashtable               decap_l2_table;
1134         struct rhashtable_params        decap_l2_ht_params;
1135         /* hash table to store tunnel decap entries */
1136         struct rhashtable               decap_table;
1137         struct rhashtable_params        decap_ht_params;
1138         /* hash table to store tunnel encap entries */
1139         struct rhashtable               encap_table;
1140         struct rhashtable_params        encap_ht_params;
1141
1142         /* lock to atomically add/del an l2 node when a flow is
1143          * added or deleted.
1144          */
1145         struct mutex                    lock;
1146
1147         /* Fields used for batching stats query */
1148         struct rhashtable_iter          iter;
1149 #define BNXT_FLOW_STATS_BATCH_MAX       10
1150         struct bnxt_tc_stats_batch {
1151                 void                      *flow_node;
1152                 struct bnxt_tc_flow_stats hw_stats;
1153         } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1154
1155         /* Stat counter mask (width) */
1156         u64                             bytes_mask;
1157         u64                             packets_mask;
1158 };
1159
1160 struct bnxt_vf_rep_stats {
1161         u64                     packets;
1162         u64                     bytes;
1163         u64                     dropped;
1164 };
1165
1166 struct bnxt_vf_rep {
1167         struct bnxt                     *bp;
1168         struct net_device               *dev;
1169         struct metadata_dst             *dst;
1170         u16                             vf_idx;
1171         u16                             tx_cfa_action;
1172         u16                             rx_cfa_code;
1173
1174         struct bnxt_vf_rep_stats        rx_stats;
1175         struct bnxt_vf_rep_stats        tx_stats;
1176 };
1177
1178 #define PTU_PTE_VALID             0x1UL
1179 #define PTU_PTE_LAST              0x2UL
1180 #define PTU_PTE_NEXT_TO_LAST      0x4UL
1181
1182 #define MAX_CTX_PAGES   (BNXT_PAGE_SIZE / 8)
1183
1184 struct bnxt_ctx_pg_info {
1185         u32             entries;
1186         void            *ctx_pg_arr[MAX_CTX_PAGES];
1187         dma_addr_t      ctx_dma_arr[MAX_CTX_PAGES];
1188         struct bnxt_ring_mem_info ring_mem;
1189 };
1190
1191 struct bnxt_ctx_mem_info {
1192         u32     qp_max_entries;
1193         u16     qp_min_qp1_entries;
1194         u16     qp_max_l2_entries;
1195         u16     qp_entry_size;
1196         u16     srq_max_l2_entries;
1197         u32     srq_max_entries;
1198         u16     srq_entry_size;
1199         u16     cq_max_l2_entries;
1200         u32     cq_max_entries;
1201         u16     cq_entry_size;
1202         u16     vnic_max_vnic_entries;
1203         u16     vnic_max_ring_table_entries;
1204         u16     vnic_entry_size;
1205         u32     stat_max_entries;
1206         u16     stat_entry_size;
1207         u16     tqm_entry_size;
1208         u32     tqm_min_entries_per_ring;
1209         u32     tqm_max_entries_per_ring;
1210         u32     mrav_max_entries;
1211         u16     mrav_entry_size;
1212         u16     tim_entry_size;
1213         u32     tim_max_entries;
1214         u8      tqm_entries_multiple;
1215
1216         u32     flags;
1217         #define BNXT_CTX_FLAG_INITED    0x01
1218
1219         struct bnxt_ctx_pg_info qp_mem;
1220         struct bnxt_ctx_pg_info srq_mem;
1221         struct bnxt_ctx_pg_info cq_mem;
1222         struct bnxt_ctx_pg_info vnic_mem;
1223         struct bnxt_ctx_pg_info stat_mem;
1224         struct bnxt_ctx_pg_info *tqm_mem[9];
1225 };
1226
1227 struct bnxt {
1228         void __iomem            *bar0;
1229         void __iomem            *bar1;
1230         void __iomem            *bar2;
1231
1232         u32                     reg_base;
1233         u16                     chip_num;
1234 #define CHIP_NUM_57301          0x16c8
1235 #define CHIP_NUM_57302          0x16c9
1236 #define CHIP_NUM_57304          0x16ca
1237 #define CHIP_NUM_58700          0x16cd
1238 #define CHIP_NUM_57402          0x16d0
1239 #define CHIP_NUM_57404          0x16d1
1240 #define CHIP_NUM_57406          0x16d2
1241 #define CHIP_NUM_57407          0x16d5
1242
1243 #define CHIP_NUM_57311          0x16ce
1244 #define CHIP_NUM_57312          0x16cf
1245 #define CHIP_NUM_57314          0x16df
1246 #define CHIP_NUM_57317          0x16e0
1247 #define CHIP_NUM_57412          0x16d6
1248 #define CHIP_NUM_57414          0x16d7
1249 #define CHIP_NUM_57416          0x16d8
1250 #define CHIP_NUM_57417          0x16d9
1251 #define CHIP_NUM_57412L         0x16da
1252 #define CHIP_NUM_57414L         0x16db
1253
1254 #define CHIP_NUM_5745X          0xd730
1255
1256 #define CHIP_NUM_57500          0x1750
1257
1258 #define CHIP_NUM_58802          0xd802
1259 #define CHIP_NUM_58804          0xd804
1260 #define CHIP_NUM_58808          0xd808
1261
1262 #define BNXT_CHIP_NUM_5730X(chip_num)           \
1263         ((chip_num) >= CHIP_NUM_57301 &&        \
1264          (chip_num) <= CHIP_NUM_57304)
1265
1266 #define BNXT_CHIP_NUM_5740X(chip_num)           \
1267         (((chip_num) >= CHIP_NUM_57402 &&       \
1268           (chip_num) <= CHIP_NUM_57406) ||      \
1269          (chip_num) == CHIP_NUM_57407)
1270
1271 #define BNXT_CHIP_NUM_5731X(chip_num)           \
1272         ((chip_num) == CHIP_NUM_57311 ||        \
1273          (chip_num) == CHIP_NUM_57312 ||        \
1274          (chip_num) == CHIP_NUM_57314 ||        \
1275          (chip_num) == CHIP_NUM_57317)
1276
1277 #define BNXT_CHIP_NUM_5741X(chip_num)           \
1278         ((chip_num) >= CHIP_NUM_57412 &&        \
1279          (chip_num) <= CHIP_NUM_57414L)
1280
1281 #define BNXT_CHIP_NUM_58700(chip_num)           \
1282          ((chip_num) == CHIP_NUM_58700)
1283
1284 #define BNXT_CHIP_NUM_5745X(chip_num)           \
1285          ((chip_num) == CHIP_NUM_5745X)
1286
1287 #define BNXT_CHIP_NUM_57X0X(chip_num)           \
1288         (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1289
1290 #define BNXT_CHIP_NUM_57X1X(chip_num)           \
1291         (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1292
1293 #define BNXT_CHIP_NUM_588XX(chip_num)           \
1294         ((chip_num) == CHIP_NUM_58802 ||        \
1295          (chip_num) == CHIP_NUM_58804 ||        \
1296          (chip_num) == CHIP_NUM_58808)
1297
1298         struct net_device       *dev;
1299         struct pci_dev          *pdev;
1300
1301         atomic_t                intr_sem;
1302
1303         u32                     flags;
1304         #define BNXT_FLAG_CHIP_P5       0x1
1305         #define BNXT_FLAG_VF            0x2
1306         #define BNXT_FLAG_LRO           0x4
1307 #ifdef CONFIG_INET
1308         #define BNXT_FLAG_GRO           0x8
1309 #else
1310         /* Cannot support hardware GRO if CONFIG_INET is not set */
1311         #define BNXT_FLAG_GRO           0x0
1312 #endif
1313         #define BNXT_FLAG_TPA           (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1314         #define BNXT_FLAG_JUMBO         0x10
1315         #define BNXT_FLAG_STRIP_VLAN    0x20
1316         #define BNXT_FLAG_AGG_RINGS     (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1317                                          BNXT_FLAG_LRO)
1318         #define BNXT_FLAG_USING_MSIX    0x40
1319         #define BNXT_FLAG_MSIX_CAP      0x80
1320         #define BNXT_FLAG_RFS           0x100
1321         #define BNXT_FLAG_SHARED_RINGS  0x200
1322         #define BNXT_FLAG_PORT_STATS    0x400
1323         #define BNXT_FLAG_UDP_RSS_CAP   0x800
1324         #define BNXT_FLAG_EEE_CAP       0x1000
1325         #define BNXT_FLAG_NEW_RSS_CAP   0x2000
1326         #define BNXT_FLAG_WOL_CAP       0x4000
1327         #define BNXT_FLAG_ROCEV1_CAP    0x8000
1328         #define BNXT_FLAG_ROCEV2_CAP    0x10000
1329         #define BNXT_FLAG_ROCE_CAP      (BNXT_FLAG_ROCEV1_CAP | \
1330                                          BNXT_FLAG_ROCEV2_CAP)
1331         #define BNXT_FLAG_NO_AGG_RINGS  0x20000
1332         #define BNXT_FLAG_RX_PAGE_MODE  0x40000
1333         #define BNXT_FLAG_MULTI_HOST    0x100000
1334         #define BNXT_FLAG_DOUBLE_DB     0x400000
1335         #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1336         #define BNXT_FLAG_DIM           0x2000000
1337         #define BNXT_FLAG_ROCE_MIRROR_CAP       0x4000000
1338         #define BNXT_FLAG_PORT_STATS_EXT        0x10000000
1339
1340         #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA |             \
1341                                             BNXT_FLAG_RFS |             \
1342                                             BNXT_FLAG_STRIP_VLAN)
1343
1344 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
1345 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
1346 #define BNXT_NPAR(bp)           ((bp)->port_partition_type)
1347 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1348 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1349 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1350 #define BNXT_RX_PAGE_MODE(bp)   ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1351 #define BNXT_SUPPORTS_TPA(bp)   (!BNXT_CHIP_TYPE_NITRO_A0(bp) &&        \
1352                                  !(bp->flags & BNXT_FLAG_CHIP_P5))
1353
1354 /* Chip class phase 5 */
1355 #define BNXT_CHIP_P5(bp)                        \
1356         ((bp)->chip_num == CHIP_NUM_57500)
1357
1358 /* Chip class phase 4.x */
1359 #define BNXT_CHIP_P4(bp)                        \
1360         (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1361          BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1362          BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1363          (BNXT_CHIP_NUM_58700((bp)->chip_num) &&        \
1364           !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1365
1366 #define BNXT_CHIP_P4_PLUS(bp)                   \
1367         (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1368
1369         struct bnxt_en_dev      *edev;
1370         struct bnxt_en_dev *    (*ulp_probe)(struct net_device *);
1371
1372         struct bnxt_napi        **bnapi;
1373
1374         struct bnxt_rx_ring_info        *rx_ring;
1375         struct bnxt_tx_ring_info        *tx_ring;
1376         u16                     *tx_ring_map;
1377
1378         struct sk_buff *        (*gro_func)(struct bnxt_tpa_info *, int, int,
1379                                             struct sk_buff *);
1380
1381         struct sk_buff *        (*rx_skb_func)(struct bnxt *,
1382                                                struct bnxt_rx_ring_info *,
1383                                                u16, void *, u8 *, dma_addr_t,
1384                                                unsigned int);
1385
1386         u32                     rx_buf_size;
1387         u32                     rx_buf_use_size;        /* useable size */
1388         u16                     rx_offset;
1389         u16                     rx_dma_offset;
1390         enum dma_data_direction rx_dir;
1391         u32                     rx_ring_size;
1392         u32                     rx_agg_ring_size;
1393         u32                     rx_copy_thresh;
1394         u32                     rx_ring_mask;
1395         u32                     rx_agg_ring_mask;
1396         int                     rx_nr_pages;
1397         int                     rx_agg_nr_pages;
1398         int                     rx_nr_rings;
1399         int                     rsscos_nr_ctxs;
1400
1401         u32                     tx_ring_size;
1402         u32                     tx_ring_mask;
1403         int                     tx_nr_pages;
1404         int                     tx_nr_rings;
1405         int                     tx_nr_rings_per_tc;
1406         int                     tx_nr_rings_xdp;
1407
1408         int                     tx_wake_thresh;
1409         int                     tx_push_thresh;
1410         int                     tx_push_size;
1411
1412         u32                     cp_ring_size;
1413         u32                     cp_ring_mask;
1414         u32                     cp_bit;
1415         int                     cp_nr_pages;
1416         int                     cp_nr_rings;
1417
1418         int                     num_stat_ctxs;
1419
1420         /* grp_info indexed by completion ring index */
1421         struct bnxt_ring_grp_info       *grp_info;
1422         struct bnxt_vnic_info   *vnic_info;
1423         int                     nr_vnics;
1424         u32                     rss_hash_cfg;
1425
1426         u16                     max_mtu;
1427         u8                      max_tc;
1428         u8                      max_lltc;       /* lossless TCs */
1429         struct bnxt_queue_info  q_info[BNXT_MAX_QUEUE];
1430         u8                      tc_to_qidx[BNXT_MAX_QUEUE];
1431         u8                      q_ids[BNXT_MAX_QUEUE];
1432         u8                      max_q;
1433
1434         unsigned int            current_interval;
1435 #define BNXT_TIMER_INTERVAL     HZ
1436
1437         struct timer_list       timer;
1438
1439         unsigned long           state;
1440 #define BNXT_STATE_OPEN         0
1441 #define BNXT_STATE_IN_SP_TASK   1
1442 #define BNXT_STATE_READ_STATS   2
1443
1444         struct bnxt_irq *irq_tbl;
1445         int                     total_irqs;
1446         u8                      mac_addr[ETH_ALEN];
1447
1448 #ifdef CONFIG_BNXT_DCB
1449         struct ieee_pfc         *ieee_pfc;
1450         struct ieee_ets         *ieee_ets;
1451         u8                      dcbx_cap;
1452         u8                      default_pri;
1453         u8                      max_dscp_value;
1454 #endif /* CONFIG_BNXT_DCB */
1455
1456         u32                     msg_enable;
1457
1458         u32                     fw_cap;
1459         #define BNXT_FW_CAP_SHORT_CMD   0x00000001
1460         #define BNXT_FW_CAP_LLDP_AGENT  0x00000002
1461         #define BNXT_FW_CAP_DCBX_AGENT  0x00000004
1462         #define BNXT_FW_CAP_NEW_RM      0x00000008
1463         #define BNXT_FW_CAP_IF_CHANGE   0x00000010
1464
1465 #define BNXT_NEW_RM(bp)         ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1466         u32                     hwrm_spec_code;
1467         u16                     hwrm_cmd_seq;
1468         u32                     hwrm_intr_seq_id;
1469         void                    *hwrm_short_cmd_req_addr;
1470         dma_addr_t              hwrm_short_cmd_req_dma_addr;
1471         void                    *hwrm_cmd_resp_addr;
1472         dma_addr_t              hwrm_cmd_resp_dma_addr;
1473
1474         struct rx_port_stats    *hw_rx_port_stats;
1475         struct tx_port_stats    *hw_tx_port_stats;
1476         struct rx_port_stats_ext        *hw_rx_port_stats_ext;
1477         struct tx_port_stats_ext        *hw_tx_port_stats_ext;
1478         dma_addr_t              hw_rx_port_stats_map;
1479         dma_addr_t              hw_tx_port_stats_map;
1480         dma_addr_t              hw_rx_port_stats_ext_map;
1481         dma_addr_t              hw_tx_port_stats_ext_map;
1482         int                     hw_port_stats_size;
1483         u16                     fw_rx_stats_ext_size;
1484         u16                     fw_tx_stats_ext_size;
1485
1486         u16                     hwrm_max_req_len;
1487         u16                     hwrm_max_ext_req_len;
1488         int                     hwrm_cmd_timeout;
1489         struct mutex            hwrm_cmd_lock;  /* serialize hwrm messages */
1490         struct hwrm_ver_get_output      ver_resp;
1491 #define FW_VER_STR_LEN          32
1492 #define BC_HWRM_STR_LEN         21
1493 #define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1494         char                    fw_ver_str[FW_VER_STR_LEN];
1495         __be16                  vxlan_port;
1496         u8                      vxlan_port_cnt;
1497         __le16                  vxlan_fw_dst_port_id;
1498         __be16                  nge_port;
1499         u8                      nge_port_cnt;
1500         __le16                  nge_fw_dst_port_id;
1501         u8                      port_partition_type;
1502         u8                      port_count;
1503         u16                     br_mode;
1504
1505         struct bnxt_coal_cap    coal_cap;
1506         struct bnxt_coal        rx_coal;
1507         struct bnxt_coal        tx_coal;
1508
1509         u32                     stats_coal_ticks;
1510 #define BNXT_DEF_STATS_COAL_TICKS        1000000
1511 #define BNXT_MIN_STATS_COAL_TICKS         250000
1512 #define BNXT_MAX_STATS_COAL_TICKS        1000000
1513
1514         struct work_struct      sp_task;
1515         unsigned long           sp_event;
1516 #define BNXT_RX_MASK_SP_EVENT           0
1517 #define BNXT_RX_NTP_FLTR_SP_EVENT       1
1518 #define BNXT_LINK_CHNG_SP_EVENT         2
1519 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1520 #define BNXT_VXLAN_ADD_PORT_SP_EVENT    4
1521 #define BNXT_VXLAN_DEL_PORT_SP_EVENT    5
1522 #define BNXT_RESET_TASK_SP_EVENT        6
1523 #define BNXT_RST_RING_SP_EVENT          7
1524 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT    8
1525 #define BNXT_PERIODIC_STATS_SP_EVENT    9
1526 #define BNXT_HWRM_PORT_MODULE_SP_EVENT  10
1527 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1528 #define BNXT_GENEVE_ADD_PORT_SP_EVENT   12
1529 #define BNXT_GENEVE_DEL_PORT_SP_EVENT   13
1530 #define BNXT_LINK_SPEED_CHNG_SP_EVENT   14
1531 #define BNXT_FLOW_STATS_SP_EVENT        15
1532 #define BNXT_UPDATE_PHY_SP_EVENT        16
1533 #define BNXT_RING_COAL_NOW_SP_EVENT     17
1534
1535         struct bnxt_hw_resc     hw_resc;
1536         struct bnxt_pf_info     pf;
1537         struct bnxt_ctx_mem_info        *ctx;
1538 #ifdef CONFIG_BNXT_SRIOV
1539         int                     nr_vfs;
1540         struct bnxt_vf_info     vf;
1541         wait_queue_head_t       sriov_cfg_wait;
1542         bool                    sriov_cfg;
1543 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1544
1545         /* lock to protect VF-rep creation/cleanup via
1546          * multiple paths such as ->sriov_configure() and
1547          * devlink ->eswitch_mode_set()
1548          */
1549         struct mutex            sriov_lock;
1550 #endif
1551
1552 #if BITS_PER_LONG == 32
1553         /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
1554         spinlock_t              db_lock;
1555 #endif
1556
1557 #define BNXT_NTP_FLTR_MAX_FLTR  4096
1558 #define BNXT_NTP_FLTR_HASH_SIZE 512
1559 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1560         struct hlist_head       ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1561         spinlock_t              ntp_fltr_lock;  /* for hash table add, del */
1562
1563         unsigned long           *ntp_fltr_bmap;
1564         int                     ntp_fltr_count;
1565
1566         /* To protect link related settings during link changes and
1567          * ethtool settings changes.
1568          */
1569         struct mutex            link_lock;
1570         struct bnxt_link_info   link_info;
1571         struct ethtool_eee      eee;
1572         u32                     lpi_tmr_lo;
1573         u32                     lpi_tmr_hi;
1574
1575         u8                      num_tests;
1576         struct bnxt_test_info   *test_info;
1577
1578         u8                      wol_filter_id;
1579         u8                      wol;
1580
1581         u8                      num_leds;
1582         struct bnxt_led_info    leds[BNXT_MAX_LED];
1583
1584         struct bpf_prog         *xdp_prog;
1585
1586         /* devlink interface and vf-rep structs */
1587         struct devlink          *dl;
1588         enum devlink_eswitch_mode eswitch_mode;
1589         struct bnxt_vf_rep      **vf_reps; /* array of vf-rep ptrs */
1590         u16                     *cfa_code_map; /* cfa_code -> vf_idx map */
1591         u8                      switch_id[8];
1592         struct bnxt_tc_info     *tc_info;
1593         struct dentry           *debugfs_pdev;
1594         struct dentry           *debugfs_dim;
1595         struct device           *hwmon_dev;
1596 };
1597
1598 #define BNXT_RX_STATS_OFFSET(counter)                   \
1599         (offsetof(struct rx_port_stats, counter) / 8)
1600
1601 #define BNXT_TX_STATS_OFFSET(counter)                   \
1602         ((offsetof(struct tx_port_stats, counter) +     \
1603           sizeof(struct rx_port_stats) + 512) / 8)
1604
1605 #define BNXT_RX_STATS_EXT_OFFSET(counter)               \
1606         (offsetof(struct rx_port_stats_ext, counter) / 8)
1607
1608 #define BNXT_TX_STATS_EXT_OFFSET(counter)               \
1609         (offsetof(struct tx_port_stats_ext, counter) / 8)
1610
1611 #define I2C_DEV_ADDR_A0                         0xa0
1612 #define I2C_DEV_ADDR_A2                         0xa2
1613 #define SFF_DIAG_SUPPORT_OFFSET                 0x5c
1614 #define SFF_MODULE_ID_SFP                       0x3
1615 #define SFF_MODULE_ID_QSFP                      0xc
1616 #define SFF_MODULE_ID_QSFP_PLUS                 0xd
1617 #define SFF_MODULE_ID_QSFP28                    0x11
1618 #define BNXT_MAX_PHY_I2C_RESP_SIZE              64
1619
1620 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
1621 {
1622         /* Tell compiler to fetch tx indices from memory. */
1623         barrier();
1624
1625         return bp->tx_ring_size -
1626                 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
1627 }
1628
1629 #if BITS_PER_LONG == 32
1630 #define writeq(val64, db)                       \
1631 do {                                            \
1632         spin_lock(&bp->db_lock);                \
1633         writel((val64) & 0xffffffff, db);       \
1634         writel((val64) >> 32, (db) + 4);        \
1635         spin_unlock(&bp->db_lock);              \
1636 } while (0)
1637
1638 #define writeq_relaxed writeq
1639 #endif
1640
1641 /* For TX and RX ring doorbells with no ordering guarantee*/
1642 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
1643                                          struct bnxt_db_info *db, u32 idx)
1644 {
1645         if (bp->flags & BNXT_FLAG_CHIP_P5) {
1646                 writeq_relaxed(db->db_key64 | idx, db->doorbell);
1647         } else {
1648                 u32 db_val = db->db_key32 | idx;
1649
1650                 writel_relaxed(db_val, db->doorbell);
1651                 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1652                         writel_relaxed(db_val, db->doorbell);
1653         }
1654 }
1655
1656 /* For TX and RX ring doorbells */
1657 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
1658                                  u32 idx)
1659 {
1660         if (bp->flags & BNXT_FLAG_CHIP_P5) {
1661                 writeq(db->db_key64 | idx, db->doorbell);
1662         } else {
1663                 u32 db_val = db->db_key32 | idx;
1664
1665                 writel(db_val, db->doorbell);
1666                 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1667                         writel(db_val, db->doorbell);
1668         }
1669 }
1670
1671 extern const u16 bnxt_lhint_arr[];
1672
1673 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1674                        u16 prod, gfp_t gfp);
1675 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
1676 void bnxt_set_tpa_flags(struct bnxt *bp);
1677 void bnxt_set_ring_params(struct bnxt *);
1678 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
1679 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
1680 int _hwrm_send_message(struct bnxt *, void *, u32, int);
1681 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout);
1682 int hwrm_send_message(struct bnxt *, void *, u32, int);
1683 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
1684 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
1685                                      int bmap_size);
1686 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
1687 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
1688 int bnxt_hwrm_set_coal(struct bnxt *);
1689 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
1690 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max);
1691 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
1692 unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp);
1693 int bnxt_get_avail_msix(struct bnxt *bp, int num);
1694 int bnxt_reserve_rings(struct bnxt *bp);
1695 void bnxt_tx_disable(struct bnxt *bp);
1696 void bnxt_tx_enable(struct bnxt *bp);
1697 int bnxt_hwrm_set_pause(struct bnxt *);
1698 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
1699 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
1700 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
1701 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
1702 int bnxt_hwrm_fw_set_time(struct bnxt *);
1703 int bnxt_open_nic(struct bnxt *, bool, bool);
1704 int bnxt_half_open_nic(struct bnxt *bp);
1705 void bnxt_half_close_nic(struct bnxt *bp);
1706 int bnxt_close_nic(struct bnxt *, bool, bool);
1707 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
1708                      int tx_xdp);
1709 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
1710 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
1711 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
1712 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr);
1713 void bnxt_dim_work(struct work_struct *work);
1714 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
1715
1716 #endif