drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2012 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/ethtool.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/types.h>
  23 #include <linux/sched.h>
  24 #include <linux/crc32.h>
  25 #include "bnx2x.h"
  26 #include "bnx2x_cmn.h"
  27 #include "bnx2x_dump.h"
  28 #include "bnx2x_init.h"
  29
  30 /* Note: in the format strings below %s is replaced by the queue-name which is
  31  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  32  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  33  */
  34 #define MAX_QUEUE_NAME_LEN      4
  35 static const struct {
  36         long offset;
  37         int size;
  38         char string[ETH_GSTRING_LEN];
  39 } bnx2x_q_stats_arr[] = {
  40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  41         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  42                                                 8, "[%s]: rx_ucast_packets" },
  43         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  44                                                 8, "[%s]: rx_mcast_packets" },
  45         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  46                                                 8, "[%s]: rx_bcast_packets" },
  47         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  48         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  49                                          4, "[%s]: rx_phy_ip_err_discards"},
  50         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  51                                          4, "[%s]: rx_skb_alloc_discard" },
  52         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  53
  54         { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  56                                                 8, "[%s]: tx_ucast_packets" },
  57         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  58                                                 8, "[%s]: tx_mcast_packets" },
  59         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  60                                                 8, "[%s]: tx_bcast_packets" },
  61         { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  62                                                 8, "[%s]: tpa_aggregations" },
  63         { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  64                                         8, "[%s]: tpa_aggregated_frames"},
  65         { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
  66 };
  67
  68 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  69
  70 static const struct {
  71         long offset;
  72         int size;
  73         u32 flags;
  74 #define STATS_FLAGS_PORT                1
  75 #define STATS_FLAGS_FUNC                2
  76 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  77         char string[ETH_GSTRING_LEN];
  78 } bnx2x_stats_arr[] = {
  79 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  80                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  81         { STATS_OFFSET32(error_bytes_received_hi),
  82                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  83         { STATS_OFFSET32(total_unicast_packets_received_hi),
  84                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  85         { STATS_OFFSET32(total_multicast_packets_received_hi),
  86                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  87         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  88                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  89         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  90                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  91         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  92                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  93         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  94                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  95         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  96                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
  97 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
  98                                 8, STATS_FLAGS_PORT, "rx_fragments" },
  99         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
 100                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
 101         { STATS_OFFSET32(no_buff_discard_hi),
 102                                 8, STATS_FLAGS_BOTH, "rx_discards" },
 103         { STATS_OFFSET32(mac_filter_discard),
 104                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 105         { STATS_OFFSET32(mf_tag_discard),
 106                                 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
 107         { STATS_OFFSET32(pfc_frames_received_hi),
 108                                 8, STATS_FLAGS_PORT, "pfc_frames_received" },
 109         { STATS_OFFSET32(pfc_frames_sent_hi),
 110                                 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
 111         { STATS_OFFSET32(brb_drop_hi),
 112                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 113         { STATS_OFFSET32(brb_truncate_hi),
 114                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 115         { STATS_OFFSET32(pause_frames_received_hi),
 116                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 117         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 118                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 119         { STATS_OFFSET32(nig_timer_max),
 120                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 121 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 122                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 123         { STATS_OFFSET32(rx_skb_alloc_failed),
 124                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 125         { STATS_OFFSET32(hw_csum_err),
 126                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 127
 128         { STATS_OFFSET32(total_bytes_transmitted_hi),
 129                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 130         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 131                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 132         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 133                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 134         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 135                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 136         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 137                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 138         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 139                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 140         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 141                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 142 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 143                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 144         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 145                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 146         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 147                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 148         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 149                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 150         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 151                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 152         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 153                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 154         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 155                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 156         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 157                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 158         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 159                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 160         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 161                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 162 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 163                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 164         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 165                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 166         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 167                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 168         { STATS_OFFSET32(pause_frames_sent_hi),
 169                                 8, STATS_FLAGS_PORT, "tx_pause_frames" },
 170         { STATS_OFFSET32(total_tpa_aggregations_hi),
 171                         8, STATS_FLAGS_FUNC, "tpa_aggregations" },
 172         { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
 173                         8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
 174         { STATS_OFFSET32(total_tpa_bytes_hi),
 175                         8, STATS_FLAGS_FUNC, "tpa_bytes"},
 176         { STATS_OFFSET32(recoverable_error),
 177                         4, STATS_FLAGS_FUNC, "recoverable_errors" },
 178         { STATS_OFFSET32(unrecoverable_error),
 179                         4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
 180         { STATS_OFFSET32(eee_tx_lpi),
 181                         4, STATS_FLAGS_PORT, "Tx LPI entry count"}
 182 };
 183
 184 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 185 static int bnx2x_get_port_type(struct bnx2x *bp)
 186 {
 187         int port_type;
 188         u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 189         switch (bp->link_params.phy[phy_idx].media_type) {
 190         case ETH_PHY_SFPP_10G_FIBER:
 191         case ETH_PHY_SFP_1G_FIBER:
 192         case ETH_PHY_XFP_FIBER:
 193         case ETH_PHY_KR:
 194         case ETH_PHY_CX4:
 195                 port_type = PORT_FIBRE;
 196                 break;
 197         case ETH_PHY_DA_TWINAX:
 198                 port_type = PORT_DA;
 199                 break;
 200         case ETH_PHY_BASE_T:
 201                 port_type = PORT_TP;
 202                 break;
 203         case ETH_PHY_NOT_PRESENT:
 204                 port_type = PORT_NONE;
 205                 break;
 206         case ETH_PHY_UNSPECIFIED:
 207         default:
 208                 port_type = PORT_OTHER;
 209                 break;
 210         }
 211         return port_type;
 212 }
 213
 214 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 215 {
 216         struct bnx2x *bp = netdev_priv(dev);
 217         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 218
 219         /* Dual Media boards present all available port types */
 220         cmd->supported = bp->port.supported[cfg_idx] |
 221                 (bp->port.supported[cfg_idx ^ 1] &
 222                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 223         cmd->advertising = bp->port.advertising[cfg_idx];
 224         if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
 225             ETH_PHY_SFP_1G_FIBER) {
 226                 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
 227                 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
 228         }
 229
 230         if ((bp->state == BNX2X_STATE_OPEN) && (bp->link_vars.link_up)) {
 231                 if (!(bp->flags & MF_FUNC_DIS)) {
 232                         ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 233                         cmd->duplex = bp->link_vars.duplex;
 234                 } else {
 235                         ethtool_cmd_speed_set(
 236                                 cmd, bp->link_params.req_line_speed[cfg_idx]);
 237                         cmd->duplex = bp->link_params.req_duplex[cfg_idx];
 238                 }
 239
 240                 if (IS_MF(bp) && !BP_NOMCP(bp))
 241                         ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 242         } else {
 243                 cmd->duplex = DUPLEX_UNKNOWN;
 244                 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
 245         }
 246
 247         cmd->port = bnx2x_get_port_type(bp);
 248
 249         cmd->phy_address = bp->mdio.prtad;
 250         cmd->transceiver = XCVR_INTERNAL;
 251
 252         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 253                 cmd->autoneg = AUTONEG_ENABLE;
 254         else
 255                 cmd->autoneg = AUTONEG_DISABLE;
 256
 257         /* Publish LP advertised speeds and FC */
 258         if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
 259                 u32 status = bp->link_vars.link_status;
 260
 261                 cmd->lp_advertising |= ADVERTISED_Autoneg;
 262                 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
 263                         cmd->lp_advertising |= ADVERTISED_Pause;
 264                 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 265                         cmd->lp_advertising |= ADVERTISED_Asym_Pause;
 266
 267                 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
 268                         cmd->lp_advertising |= ADVERTISED_10baseT_Half;
 269                 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
 270                         cmd->lp_advertising |= ADVERTISED_10baseT_Full;
 271                 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
 272                         cmd->lp_advertising |= ADVERTISED_100baseT_Half;
 273                 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
 274                         cmd->lp_advertising |= ADVERTISED_100baseT_Full;
 275                 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
 276                         cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
 277                 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
 278                         cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
 279                 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
 280                         cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
 281                 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
 282                         cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
 283         }
 284
 285         cmd->maxtxpkt = 0;
 286         cmd->maxrxpkt = 0;
 287
 288         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 289            "  supported 0x%x  advertising 0x%x  speed %u\n"
 290            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 291            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 292            cmd->cmd, cmd->supported, cmd->advertising,
 293            ethtool_cmd_speed(cmd),
 294            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 295            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 296
 297         return 0;
 298 }
 299
 300 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 301 {
 302         struct bnx2x *bp = netdev_priv(dev);
 303         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 304         u32 speed, phy_idx;
 305
 306         if (IS_MF_SD(bp))
 307                 return 0;
 308
 309         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 310            "  supported 0x%x  advertising 0x%x  speed %u\n"
 311            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 312            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 313            cmd->cmd, cmd->supported, cmd->advertising,
 314            ethtool_cmd_speed(cmd),
 315            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 316            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 317
 318         speed = ethtool_cmd_speed(cmd);
 319
 320         /* If recieved a request for an unknown duplex, assume full*/
 321         if (cmd->duplex == DUPLEX_UNKNOWN)
 322                 cmd->duplex = DUPLEX_FULL;
 323
 324         if (IS_MF_SI(bp)) {
 325                 u32 part;
 326                 u32 line_speed = bp->link_vars.line_speed;
 327
 328                 /* use 10G if no link detected */
 329                 if (!line_speed)
 330                         line_speed = 10000;
 331
 332                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 333                         DP(BNX2X_MSG_ETHTOOL,
 334                            "To set speed BC %X or higher is required, please upgrade BC\n",
 335                            REQ_BC_VER_4_SET_MF_BW);
 336                         return -EINVAL;
 337                 }
 338
 339                 part = (speed * 100) / line_speed;
 340
 341                 if (line_speed < speed || !part) {
 342                         DP(BNX2X_MSG_ETHTOOL,
 343                            "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
 344                         return -EINVAL;
 345                 }
 346
 347                 if (bp->state != BNX2X_STATE_OPEN)
 348                         /* store value for following "load" */
 349                         bp->pending_max = part;
 350                 else
 351                         bnx2x_update_max_mf_config(bp, part);
 352
 353                 return 0;
 354         }
 355
 356         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 357         old_multi_phy_config = bp->link_params.multi_phy_config;
 358         switch (cmd->port) {
 359         case PORT_TP:
 360                 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 361                         break; /* no port change */
 362
 363                 if (!(bp->port.supported[0] & SUPPORTED_TP ||
 364                       bp->port.supported[1] & SUPPORTED_TP)) {
 365                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 366                         return -EINVAL;
 367                 }
 368                 bp->link_params.multi_phy_config &=
 369                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 370                 if (bp->link_params.multi_phy_config &
 371                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 372                         bp->link_params.multi_phy_config |=
 373                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 374                 else
 375                         bp->link_params.multi_phy_config |=
 376                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 377                 break;
 378         case PORT_FIBRE:
 379         case PORT_DA:
 380                 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 381                         break; /* no port change */
 382
 383                 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 384                       bp->port.supported[1] & SUPPORTED_FIBRE)) {
 385                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 386                         return -EINVAL;
 387                 }
 388                 bp->link_params.multi_phy_config &=
 389                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 390                 if (bp->link_params.multi_phy_config &
 391                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 392                         bp->link_params.multi_phy_config |=
 393                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 394                 else
 395                         bp->link_params.multi_phy_config |=
 396                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 397                 break;
 398         default:
 399                 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 400                 return -EINVAL;
 401         }
 402         /* Save new config in case command complete successully */
 403         new_multi_phy_config = bp->link_params.multi_phy_config;
 404         /* Get the new cfg_idx */
 405         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 406         /* Restore old config in case command failed */
 407         bp->link_params.multi_phy_config = old_multi_phy_config;
 408         DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
 409
 410         if (cmd->autoneg == AUTONEG_ENABLE) {
 411                 u32 an_supported_speed = bp->port.supported[cfg_idx];
 412                 if (bp->link_params.phy[EXT_PHY1].type ==
 413                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
 414                         an_supported_speed |= (SUPPORTED_100baseT_Half |
 415                                                SUPPORTED_100baseT_Full);
 416                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 417                         DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
 418                         return -EINVAL;
 419                 }
 420
 421                 /* advertise the requested speed and duplex if supported */
 422                 if (cmd->advertising & ~an_supported_speed) {
 423                         DP(BNX2X_MSG_ETHTOOL,
 424                            "Advertisement parameters are not supported\n");
 425                         return -EINVAL;
 426                 }
 427
 428                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 429                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 430                 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
 431                                          cmd->advertising);
 432                 if (cmd->advertising) {
 433
 434                         bp->link_params.speed_cap_mask[cfg_idx] = 0;
 435                         if (cmd->advertising & ADVERTISED_10baseT_Half) {
 436                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 437                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
 438                         }
 439                         if (cmd->advertising & ADVERTISED_10baseT_Full)
 440                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 441                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
 442
 443                         if (cmd->advertising & ADVERTISED_100baseT_Full)
 444                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 445                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
 446
 447                         if (cmd->advertising & ADVERTISED_100baseT_Half) {
 448                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 449                                      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
 450                         }
 451                         if (cmd->advertising & ADVERTISED_1000baseT_Half) {
 452                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 453                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 454                         }
 455                         if (cmd->advertising & (ADVERTISED_1000baseT_Full |
 456                                                 ADVERTISED_1000baseKX_Full))
 457                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 458                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 459
 460                         if (cmd->advertising & (ADVERTISED_10000baseT_Full |
 461                                                 ADVERTISED_10000baseKX4_Full |
 462                                                 ADVERTISED_10000baseKR_Full))
 463                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 464                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
 465                 }
 466         } else { /* forced speed */
 467                 /* advertise the requested speed and duplex if supported */
 468                 switch (speed) {
 469                 case SPEED_10:
 470                         if (cmd->duplex == DUPLEX_FULL) {
 471                                 if (!(bp->port.supported[cfg_idx] &
 472                                       SUPPORTED_10baseT_Full)) {
 473                                         DP(BNX2X_MSG_ETHTOOL,
 474                                            "10M full not supported\n");
 475                                         return -EINVAL;
 476                                 }
 477
 478                                 advertising = (ADVERTISED_10baseT_Full |
 479                                                ADVERTISED_TP);
 480                         } else {
 481                                 if (!(bp->port.supported[cfg_idx] &
 482                                       SUPPORTED_10baseT_Half)) {
 483                                         DP(BNX2X_MSG_ETHTOOL,
 484                                            "10M half not supported\n");
 485                                         return -EINVAL;
 486                                 }
 487
 488                                 advertising = (ADVERTISED_10baseT_Half |
 489                                                ADVERTISED_TP);
 490                         }
 491                         break;
 492
 493                 case SPEED_100:
 494                         if (cmd->duplex == DUPLEX_FULL) {
 495                                 if (!(bp->port.supported[cfg_idx] &
 496                                                 SUPPORTED_100baseT_Full)) {
 497                                         DP(BNX2X_MSG_ETHTOOL,
 498                                            "100M full not supported\n");
 499                                         return -EINVAL;
 500                                 }
 501
 502                                 advertising = (ADVERTISED_100baseT_Full |
 503                                                ADVERTISED_TP);
 504                         } else {
 505                                 if (!(bp->port.supported[cfg_idx] &
 506                                                 SUPPORTED_100baseT_Half)) {
 507                                         DP(BNX2X_MSG_ETHTOOL,
 508                                            "100M half not supported\n");
 509                                         return -EINVAL;
 510                                 }
 511
 512                                 advertising = (ADVERTISED_100baseT_Half |
 513                                                ADVERTISED_TP);
 514                         }
 515                         break;
 516
 517                 case SPEED_1000:
 518                         if (cmd->duplex != DUPLEX_FULL) {
 519                                 DP(BNX2X_MSG_ETHTOOL,
 520                                    "1G half not supported\n");
 521                                 return -EINVAL;
 522                         }
 523
 524                         if (!(bp->port.supported[cfg_idx] &
 525                               SUPPORTED_1000baseT_Full)) {
 526                                 DP(BNX2X_MSG_ETHTOOL,
 527                                    "1G full not supported\n");
 528                                 return -EINVAL;
 529                         }
 530
 531                         advertising = (ADVERTISED_1000baseT_Full |
 532                                        ADVERTISED_TP);
 533                         break;
 534
 535                 case SPEED_2500:
 536                         if (cmd->duplex != DUPLEX_FULL) {
 537                                 DP(BNX2X_MSG_ETHTOOL,
 538                                    "2.5G half not supported\n");
 539                                 return -EINVAL;
 540                         }
 541
 542                         if (!(bp->port.supported[cfg_idx]
 543                               & SUPPORTED_2500baseX_Full)) {
 544                                 DP(BNX2X_MSG_ETHTOOL,
 545                                    "2.5G full not supported\n");
 546                                 return -EINVAL;
 547                         }
 548
 549                         advertising = (ADVERTISED_2500baseX_Full |
 550                                        ADVERTISED_TP);
 551                         break;
 552
 553                 case SPEED_10000:
 554                         if (cmd->duplex != DUPLEX_FULL) {
 555                                 DP(BNX2X_MSG_ETHTOOL,
 556                                    "10G half not supported\n");
 557                                 return -EINVAL;
 558                         }
 559                         phy_idx = bnx2x_get_cur_phy_idx(bp);
 560                         if (!(bp->port.supported[cfg_idx]
 561                               & SUPPORTED_10000baseT_Full) ||
 562                             (bp->link_params.phy[phy_idx].media_type ==
 563                              ETH_PHY_SFP_1G_FIBER)) {
 564                                 DP(BNX2X_MSG_ETHTOOL,
 565                                    "10G full not supported\n");
 566                                 return -EINVAL;
 567                         }
 568
 569                         advertising = (ADVERTISED_10000baseT_Full |
 570                                        ADVERTISED_FIBRE);
 571                         break;
 572
 573                 default:
 574                         DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
 575                         return -EINVAL;
 576                 }
 577
 578                 bp->link_params.req_line_speed[cfg_idx] = speed;
 579                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 580                 bp->port.advertising[cfg_idx] = advertising;
 581         }
 582
 583         DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
 584            "  req_duplex %d  advertising 0x%x\n",
 585            bp->link_params.req_line_speed[cfg_idx],
 586            bp->link_params.req_duplex[cfg_idx],
 587            bp->port.advertising[cfg_idx]);
 588
 589         /* Set new config */
 590         bp->link_params.multi_phy_config = new_multi_phy_config;
 591         if (netif_running(dev)) {
 592                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 593                 bnx2x_link_set(bp);
 594         }
 595
 596         return 0;
 597 }
 598
 599 #define IS_E1_ONLINE(info)      (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
 600 #define IS_E1H_ONLINE(info)     (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
 601 #define IS_E2_ONLINE(info)      (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
 602 #define IS_E3_ONLINE(info)      (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
 603 #define IS_E3B0_ONLINE(info)    (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
 604
 605 static bool bnx2x_is_reg_online(struct bnx2x *bp,
 606                                 const struct reg_addr *reg_info)
 607 {
 608         if (CHIP_IS_E1(bp))
 609                 return IS_E1_ONLINE(reg_info->info);
 610         else if (CHIP_IS_E1H(bp))
 611                 return IS_E1H_ONLINE(reg_info->info);
 612         else if (CHIP_IS_E2(bp))
 613                 return IS_E2_ONLINE(reg_info->info);
 614         else if (CHIP_IS_E3A0(bp))
 615                 return IS_E3_ONLINE(reg_info->info);
 616         else if (CHIP_IS_E3B0(bp))
 617                 return IS_E3B0_ONLINE(reg_info->info);
 618         else
 619                 return false;
 620 }
 621
 622 /******* Paged registers info selectors ********/
 623 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 624 {
 625         if (CHIP_IS_E2(bp))
 626                 return page_vals_e2;
 627         else if (CHIP_IS_E3(bp))
 628                 return page_vals_e3;
 629         else
 630                 return NULL;
 631 }
 632
 633 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
 634 {
 635         if (CHIP_IS_E2(bp))
 636                 return PAGE_MODE_VALUES_E2;
 637         else if (CHIP_IS_E3(bp))
 638                 return PAGE_MODE_VALUES_E3;
 639         else
 640                 return 0;
 641 }
 642
 643 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 644 {
 645         if (CHIP_IS_E2(bp))
 646                 return page_write_regs_e2;
 647         else if (CHIP_IS_E3(bp))
 648                 return page_write_regs_e3;
 649         else
 650                 return NULL;
 651 }
 652
 653 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
 654 {
 655         if (CHIP_IS_E2(bp))
 656                 return PAGE_WRITE_REGS_E2;
 657         else if (CHIP_IS_E3(bp))
 658                 return PAGE_WRITE_REGS_E3;
 659         else
 660                 return 0;
 661 }
 662
 663 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
 664 {
 665         if (CHIP_IS_E2(bp))
 666                 return page_read_regs_e2;
 667         else if (CHIP_IS_E3(bp))
 668                 return page_read_regs_e3;
 669         else
 670                 return NULL;
 671 }
 672
 673 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
 674 {
 675         if (CHIP_IS_E2(bp))
 676                 return PAGE_READ_REGS_E2;
 677         else if (CHIP_IS_E3(bp))
 678                 return PAGE_READ_REGS_E3;
 679         else
 680                 return 0;
 681 }
 682
 683 static int __bnx2x_get_regs_len(struct bnx2x *bp)
 684 {
 685         int num_pages = __bnx2x_get_page_reg_num(bp);
 686         int page_write_num = __bnx2x_get_page_write_num(bp);
 687         const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
 688         int page_read_num = __bnx2x_get_page_read_num(bp);
 689         int regdump_len = 0;
 690         int i, j, k;
 691
 692         for (i = 0; i < REGS_COUNT; i++)
 693                 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
 694                         regdump_len += reg_addrs[i].size;
 695
 696         for (i = 0; i < num_pages; i++)
 697                 for (j = 0; j < page_write_num; j++)
 698                         for (k = 0; k < page_read_num; k++)
 699                                 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
 700                                         regdump_len += page_read_addr[k].size;
 701
 702         return regdump_len;
 703 }
 704
 705 static int bnx2x_get_regs_len(struct net_device *dev)
 706 {
 707         struct bnx2x *bp = netdev_priv(dev);
 708         int regdump_len = 0;
 709
 710         regdump_len = __bnx2x_get_regs_len(bp);
 711         regdump_len *= 4;
 712         regdump_len += sizeof(struct dump_hdr);
 713
 714         return regdump_len;
 715 }
 716
 717 /**
 718  * bnx2x_read_pages_regs - read "paged" registers
 719  *
 720  * @bp          device handle
 721  * @p           output buffer
 722  *
 723  * Reads "paged" memories: memories that may only be read by first writing to a
 724  * specific address ("write address") and then reading from a specific address
 725  * ("read address"). There may be more than one write address per "page" and
 726  * more than one read address per write address.
 727  */
 728 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
 729 {
 730         u32 i, j, k, n;
 731         /* addresses of the paged registers */
 732         const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
 733         /* number of paged registers */
 734         int num_pages = __bnx2x_get_page_reg_num(bp);
 735         /* write addresses */
 736         const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
 737         /* number of write addresses */
 738         int write_num = __bnx2x_get_page_write_num(bp);
 739         /* read addresses info */
 740         const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
 741         /* number of read addresses */
 742         int read_num = __bnx2x_get_page_read_num(bp);
 743
 744         for (i = 0; i < num_pages; i++) {
 745                 for (j = 0; j < write_num; j++) {
 746                         REG_WR(bp, write_addr[j], page_addr[i]);
 747                         for (k = 0; k < read_num; k++)
 748                                 if (bnx2x_is_reg_online(bp, &read_addr[k]))
 749                                         for (n = 0; n <
 750                                               read_addr[k].size; n++)
 751                                                 *p++ = REG_RD(bp,
 752                                                        read_addr[k].addr + n*4);
 753                 }
 754         }
 755 }
 756
 757 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 758 {
 759         u32 i, j;
 760
 761         /* Read the regular registers */
 762         for (i = 0; i < REGS_COUNT; i++)
 763                 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
 764                         for (j = 0; j < reg_addrs[i].size; j++)
 765                                 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
 766
 767         /* Read "paged" registes */
 768         bnx2x_read_pages_regs(bp, p);
 769 }
 770
 771 static void bnx2x_get_regs(struct net_device *dev,
 772                            struct ethtool_regs *regs, void *_p)
 773 {
 774         u32 *p = _p;
 775         struct bnx2x *bp = netdev_priv(dev);
 776         struct dump_hdr dump_hdr = {0};
 777
 778         regs->version = 1;
 779         memset(p, 0, regs->len);
 780
 781         if (!netif_running(bp->dev))
 782                 return;
 783
 784         /* Disable parity attentions as long as following dump may
 785          * cause false alarms by reading never written registers. We
 786          * will re-enable parity attentions right after the dump.
 787          */
 788         bnx2x_disable_blocks_parity(bp);
 789
 790         dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
 791         dump_hdr.dump_sign = dump_sign_all;
 792         dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
 793         dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
 794         dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
 795         dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
 796
 797         if (CHIP_IS_E1(bp))
 798                 dump_hdr.info = RI_E1_ONLINE;
 799         else if (CHIP_IS_E1H(bp))
 800                 dump_hdr.info = RI_E1H_ONLINE;
 801         else if (!CHIP_IS_E1x(bp))
 802                 dump_hdr.info = RI_E2_ONLINE |
 803                 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
 804
 805         memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
 806         p += dump_hdr.hdr_size + 1;
 807
 808         /* Actually read the registers */
 809         __bnx2x_get_regs(bp, p);
 810
 811         /* Re-enable parity attentions */
 812         bnx2x_clear_blocks_parity(bp);
 813         bnx2x_enable_blocks_parity(bp);
 814 }
 815
 816 static void bnx2x_get_drvinfo(struct net_device *dev,
 817                               struct ethtool_drvinfo *info)
 818 {
 819         struct bnx2x *bp = netdev_priv(dev);
 820         u8 phy_fw_ver[PHY_FW_VER_LEN];
 821
 822         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
 823         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
 824
 825         phy_fw_ver[0] = '\0';
 826         bnx2x_get_ext_phy_fw_version(&bp->link_params,
 827                                      phy_fw_ver, PHY_FW_VER_LEN);
 828         strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version));
 829         snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
 830                  "bc %d.%d.%d%s%s",
 831                  (bp->common.bc_ver & 0xff0000) >> 16,
 832                  (bp->common.bc_ver & 0xff00) >> 8,
 833                  (bp->common.bc_ver & 0xff),
 834                  ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
 835         strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
 836         info->n_stats = BNX2X_NUM_STATS;
 837         info->testinfo_len = BNX2X_NUM_TESTS(bp);
 838         info->eedump_len = bp->common.flash_size;
 839         info->regdump_len = bnx2x_get_regs_len(dev);
 840 }
 841
 842 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 843 {
 844         struct bnx2x *bp = netdev_priv(dev);
 845
 846         if (bp->flags & NO_WOL_FLAG) {
 847                 wol->supported = 0;
 848                 wol->wolopts = 0;
 849         } else {
 850                 wol->supported = WAKE_MAGIC;
 851                 if (bp->wol)
 852                         wol->wolopts = WAKE_MAGIC;
 853                 else
 854                         wol->wolopts = 0;
 855         }
 856         memset(&wol->sopass, 0, sizeof(wol->sopass));
 857 }
 858
 859 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 860 {
 861         struct bnx2x *bp = netdev_priv(dev);
 862
 863         if (wol->wolopts & ~WAKE_MAGIC) {
 864                 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
 865                 return -EINVAL;
 866         }
 867
 868         if (wol->wolopts & WAKE_MAGIC) {
 869                 if (bp->flags & NO_WOL_FLAG) {
 870                         DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
 871                         return -EINVAL;
 872                 }
 873                 bp->wol = 1;
 874         } else
 875                 bp->wol = 0;
 876
 877         return 0;
 878 }
 879
 880 static u32 bnx2x_get_msglevel(struct net_device *dev)
 881 {
 882         struct bnx2x *bp = netdev_priv(dev);
 883
 884         return bp->msg_enable;
 885 }
 886
 887 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
 888 {
 889         struct bnx2x *bp = netdev_priv(dev);
 890
 891         if (capable(CAP_NET_ADMIN)) {
 892                 /* dump MCP trace */
 893                 if (level & BNX2X_MSG_MCP)
 894                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
 895                 bp->msg_enable = level;
 896         }
 897 }
 898
 899 static int bnx2x_nway_reset(struct net_device *dev)
 900 {
 901         struct bnx2x *bp = netdev_priv(dev);
 902
 903         if (!bp->port.pmf)
 904                 return 0;
 905
 906         if (netif_running(dev)) {
 907                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 908                 bnx2x_force_link_reset(bp);
 909                 bnx2x_link_set(bp);
 910         }
 911
 912         return 0;
 913 }
 914
 915 static u32 bnx2x_get_link(struct net_device *dev)
 916 {
 917         struct bnx2x *bp = netdev_priv(dev);
 918
 919         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
 920                 return 0;
 921
 922         return bp->link_vars.link_up;
 923 }
 924
 925 static int bnx2x_get_eeprom_len(struct net_device *dev)
 926 {
 927         struct bnx2x *bp = netdev_priv(dev);
 928
 929         return bp->common.flash_size;
 930 }
 931
 932 /* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
 933  * we done things the other way around, if two pfs from the same port would
 934  * attempt to access nvram at the same time, we could run into a scenario such
 935  * as:
 936  * pf A takes the port lock.
 937  * pf B succeeds in taking the same lock since they are from the same port.
 938  * pf A takes the per pf misc lock. Performs eeprom access.
 939  * pf A finishes. Unlocks the per pf misc lock.
 940  * Pf B takes the lock and proceeds to perform it's own access.
 941  * pf A unlocks the per port lock, while pf B is still working (!).
 942  * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
 943  * acess corrupted by pf B).*
 944  */
 945 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
 946 {
 947         int port = BP_PORT(bp);
 948         int count, i;
 949         u32 val;
 950
 951         /* acquire HW lock: protect against other PFs in PF Direct Assignment */
 952         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
 953
 954         /* adjust timeout for emulation/FPGA */
 955         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 956         if (CHIP_REV_IS_SLOW(bp))
 957                 count *= 100;
 958
 959         /* request access to nvram interface */
 960         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 961                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
 962
 963         for (i = 0; i < count*10; i++) {
 964                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 965                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
 966                         break;
 967
 968                 udelay(5);
 969         }
 970
 971         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
 972                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
 973                    "cannot get access to nvram interface\n");
 974                 return -EBUSY;
 975         }
 976
 977         return 0;
 978 }
 979
 980 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
 981 {
 982         int port = BP_PORT(bp);
 983         int count, i;
 984         u32 val;
 985
 986         /* adjust timeout for emulation/FPGA */
 987         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 988         if (CHIP_REV_IS_SLOW(bp))
 989                 count *= 100;
 990
 991         /* relinquish nvram interface */
 992         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 993                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
 994
 995         for (i = 0; i < count*10; i++) {
 996                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 997                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
 998                         break;
 999
1000                 udelay(5);
1001         }
1002
1003         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1004                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1005                    "cannot free access to nvram interface\n");
1006                 return -EBUSY;
1007         }
1008
1009         /* release HW lock: protect against other PFs in PF Direct Assignment */
1010         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1011         return 0;
1012 }
1013
1014 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1015 {
1016         u32 val;
1017
1018         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1019
1020         /* enable both bits, even on read */
1021         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1022                (val | MCPR_NVM_ACCESS_ENABLE_EN |
1023                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
1024 }
1025
1026 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1027 {
1028         u32 val;
1029
1030         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1031
1032         /* disable both bits, even after read */
1033         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1034                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1035                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1036 }
1037
1038 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1039                                   u32 cmd_flags)
1040 {
1041         int count, i, rc;
1042         u32 val;
1043
1044         /* build the command word */
1045         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1046
1047         /* need to clear DONE bit separately */
1048         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1049
1050         /* address of the NVRAM to read from */
1051         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1052                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1053
1054         /* issue a read command */
1055         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1056
1057         /* adjust timeout for emulation/FPGA */
1058         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1059         if (CHIP_REV_IS_SLOW(bp))
1060                 count *= 100;
1061
1062         /* wait for completion */
1063         *ret_val = 0;
1064         rc = -EBUSY;
1065         for (i = 0; i < count; i++) {
1066                 udelay(5);
1067                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1068
1069                 if (val & MCPR_NVM_COMMAND_DONE) {
1070                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1071                         /* we read nvram data in cpu order
1072                          * but ethtool sees it as an array of bytes
1073                          * converting to big-endian will do the work */
1074                         *ret_val = cpu_to_be32(val);
1075                         rc = 0;
1076                         break;
1077                 }
1078         }
1079         if (rc == -EBUSY)
1080                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1081                    "nvram read timeout expired\n");
1082         return rc;
1083 }
1084
1085 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1086                             int buf_size)
1087 {
1088         int rc;
1089         u32 cmd_flags;
1090         __be32 val;
1091
1092         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1093                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1094                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1095                    offset, buf_size);
1096                 return -EINVAL;
1097         }
1098
1099         if (offset + buf_size > bp->common.flash_size) {
1100                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1101                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1102                    offset, buf_size, bp->common.flash_size);
1103                 return -EINVAL;
1104         }
1105
1106         /* request access to nvram interface */
1107         rc = bnx2x_acquire_nvram_lock(bp);
1108         if (rc)
1109                 return rc;
1110
1111         /* enable access to nvram interface */
1112         bnx2x_enable_nvram_access(bp);
1113
1114         /* read the first word(s) */
1115         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1116         while ((buf_size > sizeof(u32)) && (rc == 0)) {
1117                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1118                 memcpy(ret_buf, &val, 4);
1119
1120                 /* advance to the next dword */
1121                 offset += sizeof(u32);
1122                 ret_buf += sizeof(u32);
1123                 buf_size -= sizeof(u32);
1124                 cmd_flags = 0;
1125         }
1126
1127         if (rc == 0) {
1128                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1129                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1130                 memcpy(ret_buf, &val, 4);
1131         }
1132
1133         /* disable access to nvram interface */
1134         bnx2x_disable_nvram_access(bp);
1135         bnx2x_release_nvram_lock(bp);
1136
1137         return rc;
1138 }
1139
1140 static int bnx2x_get_eeprom(struct net_device *dev,
1141                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1142 {
1143         struct bnx2x *bp = netdev_priv(dev);
1144         int rc;
1145
1146         if (!netif_running(dev)) {
1147                 DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1148                    "cannot access eeprom when the interface is down\n");
1149                 return -EAGAIN;
1150         }
1151
1152         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1153            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1154            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1155            eeprom->len, eeprom->len);
1156
1157         /* parameters already validated in ethtool_get_eeprom */
1158
1159         rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1160
1161         return rc;
1162 }
1163
1164 static int bnx2x_get_module_eeprom(struct net_device *dev,
1165                                    struct ethtool_eeprom *ee,
1166                                    u8 *data)
1167 {
1168         struct bnx2x *bp = netdev_priv(dev);
1169         int rc = 0, phy_idx;
1170         u8 *user_data = data;
1171         int remaining_len = ee->len, xfer_size;
1172         unsigned int page_off = ee->offset;
1173
1174         if (!netif_running(dev)) {
1175                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1176                    "cannot access eeprom when the interface is down\n");
1177                 return -EAGAIN;
1178         }
1179
1180         phy_idx = bnx2x_get_cur_phy_idx(bp);
1181         bnx2x_acquire_phy_lock(bp);
1182         while (!rc && remaining_len > 0) {
1183                 xfer_size = (remaining_len > SFP_EEPROM_PAGE_SIZE) ?
1184                         SFP_EEPROM_PAGE_SIZE : remaining_len;
1185                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1186                                                   &bp->link_params,
1187                                                   page_off,
1188                                                   xfer_size,
1189                                                   user_data);
1190                 remaining_len -= xfer_size;
1191                 user_data += xfer_size;
1192                 page_off += xfer_size;
1193         }
1194
1195         bnx2x_release_phy_lock(bp);
1196         return rc;
1197 }
1198
1199 static int bnx2x_get_module_info(struct net_device *dev,
1200                                  struct ethtool_modinfo *modinfo)
1201 {
1202         struct bnx2x *bp = netdev_priv(dev);
1203         int phy_idx;
1204         if (!netif_running(dev)) {
1205                 DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1206                    "cannot access eeprom when the interface is down\n");
1207                 return -EAGAIN;
1208         }
1209
1210         phy_idx = bnx2x_get_cur_phy_idx(bp);
1211         switch (bp->link_params.phy[phy_idx].media_type) {
1212         case ETH_PHY_SFPP_10G_FIBER:
1213         case ETH_PHY_SFP_1G_FIBER:
1214         case ETH_PHY_DA_TWINAX:
1215                 modinfo->type = ETH_MODULE_SFF_8079;
1216                 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1217                 return 0;
1218         default:
1219                 return -EOPNOTSUPP;
1220         }
1221 }
1222
1223 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1224                                    u32 cmd_flags)
1225 {
1226         int count, i, rc;
1227
1228         /* build the command word */
1229         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1230
1231         /* need to clear DONE bit separately */
1232         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1233
1234         /* write the data */
1235         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1236
1237         /* address of the NVRAM to write to */
1238         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1239                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1240
1241         /* issue the write command */
1242         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1243
1244         /* adjust timeout for emulation/FPGA */
1245         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1246         if (CHIP_REV_IS_SLOW(bp))
1247                 count *= 100;
1248
1249         /* wait for completion */
1250         rc = -EBUSY;
1251         for (i = 0; i < count; i++) {
1252                 udelay(5);
1253                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1254                 if (val & MCPR_NVM_COMMAND_DONE) {
1255                         rc = 0;
1256                         break;
1257                 }
1258         }
1259
1260         if (rc == -EBUSY)
1261                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1262                    "nvram write timeout expired\n");
1263         return rc;
1264 }
1265
1266 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1267
1268 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1269                               int buf_size)
1270 {
1271         int rc;
1272         u32 cmd_flags;
1273         u32 align_offset;
1274         __be32 val;
1275
1276         if (offset + buf_size > bp->common.flash_size) {
1277                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1278                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1279                    offset, buf_size, bp->common.flash_size);
1280                 return -EINVAL;
1281         }
1282
1283         /* request access to nvram interface */
1284         rc = bnx2x_acquire_nvram_lock(bp);
1285         if (rc)
1286                 return rc;
1287
1288         /* enable access to nvram interface */
1289         bnx2x_enable_nvram_access(bp);
1290
1291         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1292         align_offset = (offset & ~0x03);
1293         rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1294
1295         if (rc == 0) {
1296                 val &= ~(0xff << BYTE_OFFSET(offset));
1297                 val |= (*data_buf << BYTE_OFFSET(offset));
1298
1299                 /* nvram data is returned as an array of bytes
1300                  * convert it back to cpu order */
1301                 val = be32_to_cpu(val);
1302
1303                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1304                                              cmd_flags);
1305         }
1306
1307         /* disable access to nvram interface */
1308         bnx2x_disable_nvram_access(bp);
1309         bnx2x_release_nvram_lock(bp);
1310
1311         return rc;
1312 }
1313
1314 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1315                              int buf_size)
1316 {
1317         int rc;
1318         u32 cmd_flags;
1319         u32 val;
1320         u32 written_so_far;
1321
1322         if (buf_size == 1)      /* ethtool */
1323                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1324
1325         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1326                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1327                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1328                    offset, buf_size);
1329                 return -EINVAL;
1330         }
1331
1332         if (offset + buf_size > bp->common.flash_size) {
1333                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1334                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1335                    offset, buf_size, bp->common.flash_size);
1336                 return -EINVAL;
1337         }
1338
1339         /* request access to nvram interface */
1340         rc = bnx2x_acquire_nvram_lock(bp);
1341         if (rc)
1342                 return rc;
1343
1344         /* enable access to nvram interface */
1345         bnx2x_enable_nvram_access(bp);
1346
1347         written_so_far = 0;
1348         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1349         while ((written_so_far < buf_size) && (rc == 0)) {
1350                 if (written_so_far == (buf_size - sizeof(u32)))
1351                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1352                 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1353                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1354                 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1355                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1356
1357                 memcpy(&val, data_buf, 4);
1358
1359                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1360
1361                 /* advance to the next dword */
1362                 offset += sizeof(u32);
1363                 data_buf += sizeof(u32);
1364                 written_so_far += sizeof(u32);
1365                 cmd_flags = 0;
1366         }
1367
1368         /* disable access to nvram interface */
1369         bnx2x_disable_nvram_access(bp);
1370         bnx2x_release_nvram_lock(bp);
1371
1372         return rc;
1373 }
1374
1375 static int bnx2x_set_eeprom(struct net_device *dev,
1376                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1377 {
1378         struct bnx2x *bp = netdev_priv(dev);
1379         int port = BP_PORT(bp);
1380         int rc = 0;
1381         u32 ext_phy_config;
1382         if (!netif_running(dev)) {
1383                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1384                    "cannot access eeprom when the interface is down\n");
1385                 return -EAGAIN;
1386         }
1387
1388         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1389            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1390            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1391            eeprom->len, eeprom->len);
1392
1393         /* parameters already validated in ethtool_set_eeprom */
1394
1395         /* PHY eeprom can be accessed only by the PMF */
1396         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1397             !bp->port.pmf) {
1398                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1399                    "wrong magic or interface is not pmf\n");
1400                 return -EINVAL;
1401         }
1402
1403         ext_phy_config =
1404                 SHMEM_RD(bp,
1405                          dev_info.port_hw_config[port].external_phy_config);
1406
1407         if (eeprom->magic == 0x50485950) {
1408                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1409                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1410
1411                 bnx2x_acquire_phy_lock(bp);
1412                 rc |= bnx2x_link_reset(&bp->link_params,
1413                                        &bp->link_vars, 0);
1414                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1415                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1416                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1417                                        MISC_REGISTERS_GPIO_HIGH, port);
1418                 bnx2x_release_phy_lock(bp);
1419                 bnx2x_link_report(bp);
1420
1421         } else if (eeprom->magic == 0x50485952) {
1422                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1423                 if (bp->state == BNX2X_STATE_OPEN) {
1424                         bnx2x_acquire_phy_lock(bp);
1425                         rc |= bnx2x_link_reset(&bp->link_params,
1426                                                &bp->link_vars, 1);
1427
1428                         rc |= bnx2x_phy_init(&bp->link_params,
1429                                              &bp->link_vars);
1430                         bnx2x_release_phy_lock(bp);
1431                         bnx2x_calc_fc_adv(bp);
1432                 }
1433         } else if (eeprom->magic == 0x53985943) {
1434                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1435                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1436                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1437
1438                         /* DSP Remove Download Mode */
1439                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1440                                        MISC_REGISTERS_GPIO_LOW, port);
1441
1442                         bnx2x_acquire_phy_lock(bp);
1443
1444                         bnx2x_sfx7101_sp_sw_reset(bp,
1445                                                 &bp->link_params.phy[EXT_PHY1]);
1446
1447                         /* wait 0.5 sec to allow it to run */
1448                         msleep(500);
1449                         bnx2x_ext_phy_hw_reset(bp, port);
1450                         msleep(500);
1451                         bnx2x_release_phy_lock(bp);
1452                 }
1453         } else
1454                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1455
1456         return rc;
1457 }
1458
1459 static int bnx2x_get_coalesce(struct net_device *dev,
1460                               struct ethtool_coalesce *coal)
1461 {
1462         struct bnx2x *bp = netdev_priv(dev);
1463
1464         memset(coal, 0, sizeof(struct ethtool_coalesce));
1465
1466         coal->rx_coalesce_usecs = bp->rx_ticks;
1467         coal->tx_coalesce_usecs = bp->tx_ticks;
1468
1469         return 0;
1470 }
1471
1472 static int bnx2x_set_coalesce(struct net_device *dev,
1473                               struct ethtool_coalesce *coal)
1474 {
1475         struct bnx2x *bp = netdev_priv(dev);
1476
1477         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1478         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1479                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1480
1481         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1482         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1483                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1484
1485         if (netif_running(dev))
1486                 bnx2x_update_coalesce(bp);
1487
1488         return 0;
1489 }
1490
1491 static void bnx2x_get_ringparam(struct net_device *dev,
1492                                 struct ethtool_ringparam *ering)
1493 {
1494         struct bnx2x *bp = netdev_priv(dev);
1495
1496         ering->rx_max_pending = MAX_RX_AVAIL;
1497
1498         if (bp->rx_ring_size)
1499                 ering->rx_pending = bp->rx_ring_size;
1500         else
1501                 ering->rx_pending = MAX_RX_AVAIL;
1502
1503         ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1504         ering->tx_pending = bp->tx_ring_size;
1505 }
1506
1507 static int bnx2x_set_ringparam(struct net_device *dev,
1508                                struct ethtool_ringparam *ering)
1509 {
1510         struct bnx2x *bp = netdev_priv(dev);
1511
1512         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1513                 DP(BNX2X_MSG_ETHTOOL,
1514                    "Handling parity error recovery. Try again later\n");
1515                 return -EAGAIN;
1516         }
1517
1518         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1519             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1520                                                     MIN_RX_SIZE_TPA)) ||
1521             (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
1522             (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1523                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1524                 return -EINVAL;
1525         }
1526
1527         bp->rx_ring_size = ering->rx_pending;
1528         bp->tx_ring_size = ering->tx_pending;
1529
1530         return bnx2x_reload_if_running(dev);
1531 }
1532
1533 static void bnx2x_get_pauseparam(struct net_device *dev,
1534                                  struct ethtool_pauseparam *epause)
1535 {
1536         struct bnx2x *bp = netdev_priv(dev);
1537         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1538         int cfg_reg;
1539
1540         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1541                            BNX2X_FLOW_CTRL_AUTO);
1542
1543         if (!epause->autoneg)
1544                 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1545         else
1546                 cfg_reg = bp->link_params.req_fc_auto_adv;
1547
1548         epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1549                             BNX2X_FLOW_CTRL_RX);
1550         epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1551                             BNX2X_FLOW_CTRL_TX);
1552
1553         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1554            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1555            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1556 }
1557
1558 static int bnx2x_set_pauseparam(struct net_device *dev,
1559                                 struct ethtool_pauseparam *epause)
1560 {
1561         struct bnx2x *bp = netdev_priv(dev);
1562         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1563         if (IS_MF(bp))
1564                 return 0;
1565
1566         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1567            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1568            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1569
1570         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1571
1572         if (epause->rx_pause)
1573                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1574
1575         if (epause->tx_pause)
1576                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1577
1578         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1579                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1580
1581         if (epause->autoneg) {
1582                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1583                         DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1584                         return -EINVAL;
1585                 }
1586
1587                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1588                         bp->link_params.req_flow_ctrl[cfg_idx] =
1589                                 BNX2X_FLOW_CTRL_AUTO;
1590                 }
1591                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_NONE;
1592                 if (epause->rx_pause)
1593                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1594
1595                 if (epause->tx_pause)
1596                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1597         }
1598
1599         DP(BNX2X_MSG_ETHTOOL,
1600            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1601
1602         if (netif_running(dev)) {
1603                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1604                 bnx2x_link_set(bp);
1605         }
1606
1607         return 0;
1608 }
1609
1610 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
1611         "register_test (offline)    ",
1612         "memory_test (offline)      ",
1613         "int_loopback_test (offline)",
1614         "ext_loopback_test (offline)",
1615         "nvram_test (online)        ",
1616         "interrupt_test (online)    ",
1617         "link_test (online)         "
1618 };
1619
1620 static u32 bnx2x_eee_to_adv(u32 eee_adv)
1621 {
1622         u32 modes = 0;
1623
1624         if (eee_adv & SHMEM_EEE_100M_ADV)
1625                 modes |= ADVERTISED_100baseT_Full;
1626         if (eee_adv & SHMEM_EEE_1G_ADV)
1627                 modes |= ADVERTISED_1000baseT_Full;
1628         if (eee_adv & SHMEM_EEE_10G_ADV)
1629                 modes |= ADVERTISED_10000baseT_Full;
1630
1631         return modes;
1632 }
1633
1634 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1635 {
1636         u32 eee_adv = 0;
1637         if (modes & ADVERTISED_100baseT_Full)
1638                 eee_adv |= SHMEM_EEE_100M_ADV;
1639         if (modes & ADVERTISED_1000baseT_Full)
1640                 eee_adv |= SHMEM_EEE_1G_ADV;
1641         if (modes & ADVERTISED_10000baseT_Full)
1642                 eee_adv |= SHMEM_EEE_10G_ADV;
1643
1644         return eee_adv << shift;
1645 }
1646
1647 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1648 {
1649         struct bnx2x *bp = netdev_priv(dev);
1650         u32 eee_cfg;
1651
1652         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1653                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1654                 return -EOPNOTSUPP;
1655         }
1656
1657         eee_cfg = bp->link_vars.eee_status;
1658
1659         edata->supported =
1660                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1661                                  SHMEM_EEE_SUPPORTED_SHIFT);
1662
1663         edata->advertised =
1664                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1665                                  SHMEM_EEE_ADV_STATUS_SHIFT);
1666         edata->lp_advertised =
1667                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1668                                  SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1669
1670         /* SHMEM value is in 16u units --> Convert to 1u units. */
1671         edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1672
1673         edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)     ? 1 : 0;
1674         edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)        ? 1 : 0;
1675         edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1676
1677         return 0;
1678 }
1679
1680 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1681 {
1682         struct bnx2x *bp = netdev_priv(dev);
1683         u32 eee_cfg;
1684         u32 advertised;
1685
1686         if (IS_MF(bp))
1687                 return 0;
1688
1689         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1690                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1691                 return -EOPNOTSUPP;
1692         }
1693
1694         eee_cfg = bp->link_vars.eee_status;
1695
1696         if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
1697                 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
1698                 return -EOPNOTSUPP;
1699         }
1700
1701         advertised = bnx2x_adv_to_eee(edata->advertised,
1702                                       SHMEM_EEE_ADV_STATUS_SHIFT);
1703         if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
1704                 DP(BNX2X_MSG_ETHTOOL,
1705                    "Direct manipulation of EEE advertisement is not supported\n");
1706                 return -EINVAL;
1707         }
1708
1709         if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
1710                 DP(BNX2X_MSG_ETHTOOL,
1711                    "Maximal Tx Lpi timer supported is %x(u)\n",
1712                    EEE_MODE_TIMER_MASK);
1713                 return -EINVAL;
1714         }
1715         if (edata->tx_lpi_enabled &&
1716             (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
1717                 DP(BNX2X_MSG_ETHTOOL,
1718                    "Minimal Tx Lpi timer supported is %d(u)\n",
1719                    EEE_MODE_NVRAM_AGGRESSIVE_TIME);
1720                 return -EINVAL;
1721         }
1722
1723         /* All is well; Apply changes*/
1724         if (edata->eee_enabled)
1725                 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
1726         else
1727                 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
1728
1729         if (edata->tx_lpi_enabled)
1730                 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
1731         else
1732                 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
1733
1734         bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
1735         bp->link_params.eee_mode |= (edata->tx_lpi_timer &
1736                                     EEE_MODE_TIMER_MASK) |
1737                                     EEE_MODE_OVERRIDE_NVRAM |
1738                                     EEE_MODE_OUTPUT_TIME;
1739
1740         /* Restart link to propogate changes */
1741         if (netif_running(dev)) {
1742                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1743                 bnx2x_force_link_reset(bp);
1744                 bnx2x_link_set(bp);
1745         }
1746
1747         return 0;
1748 }
1749
1750
1751 enum {
1752         BNX2X_CHIP_E1_OFST = 0,
1753         BNX2X_CHIP_E1H_OFST,
1754         BNX2X_CHIP_E2_OFST,
1755         BNX2X_CHIP_E3_OFST,
1756         BNX2X_CHIP_E3B0_OFST,
1757         BNX2X_CHIP_MAX_OFST
1758 };
1759
1760 #define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
1761 #define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
1762 #define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
1763 #define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
1764 #define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
1765
1766 #define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1767 #define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1768
1769 static int bnx2x_test_registers(struct bnx2x *bp)
1770 {
1771         int idx, i, rc = -ENODEV;
1772         u32 wr_val = 0, hw;
1773         int port = BP_PORT(bp);
1774         static const struct {
1775                 u32 hw;
1776                 u32 offset0;
1777                 u32 offset1;
1778                 u32 mask;
1779         } reg_tbl[] = {
1780 /* 0 */         { BNX2X_CHIP_MASK_ALL,
1781                         BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1782                 { BNX2X_CHIP_MASK_ALL,
1783                         DORQ_REG_DB_ADDR0,              4, 0xffffffff },
1784                 { BNX2X_CHIP_MASK_E1X,
1785                         HC_REG_AGG_INT_0,               4, 0x000003ff },
1786                 { BNX2X_CHIP_MASK_ALL,
1787                         PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
1788                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1789                         PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
1790                 { BNX2X_CHIP_MASK_E3B0,
1791                         PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
1792                 { BNX2X_CHIP_MASK_ALL,
1793                         PRS_REG_CID_PORT_0,             4, 0x00ffffff },
1794                 { BNX2X_CHIP_MASK_ALL,
1795                         PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
1796                 { BNX2X_CHIP_MASK_ALL,
1797                         PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1798                 { BNX2X_CHIP_MASK_ALL,
1799                         PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
1800 /* 10 */        { BNX2X_CHIP_MASK_ALL,
1801                         PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1802                 { BNX2X_CHIP_MASK_ALL,
1803                         PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
1804                 { BNX2X_CHIP_MASK_ALL,
1805                         QM_REG_CONNNUM_0,               4, 0x000fffff },
1806                 { BNX2X_CHIP_MASK_ALL,
1807                         TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
1808                 { BNX2X_CHIP_MASK_ALL,
1809                         SRC_REG_KEYRSS0_0,              40, 0xffffffff },
1810                 { BNX2X_CHIP_MASK_ALL,
1811                         SRC_REG_KEYRSS0_7,              40, 0xffffffff },
1812                 { BNX2X_CHIP_MASK_ALL,
1813                         XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1814                 { BNX2X_CHIP_MASK_ALL,
1815                         XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
1816                 { BNX2X_CHIP_MASK_ALL,
1817                         XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
1818                 { BNX2X_CHIP_MASK_ALL,
1819                         NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
1820 /* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1821                         NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
1822                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1823                         NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
1824                 { BNX2X_CHIP_MASK_ALL,
1825                         NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
1826                 { BNX2X_CHIP_MASK_ALL,
1827                         NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
1828                 { BNX2X_CHIP_MASK_ALL,
1829                         NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
1830                 { BNX2X_CHIP_MASK_ALL,
1831                         NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
1832                 { BNX2X_CHIP_MASK_ALL,
1833                         NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
1834                 { BNX2X_CHIP_MASK_ALL,
1835                         NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
1836                 { BNX2X_CHIP_MASK_ALL,
1837                         NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
1838                 { BNX2X_CHIP_MASK_ALL,
1839                         NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
1840 /* 30 */        { BNX2X_CHIP_MASK_ALL,
1841                         NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
1842                 { BNX2X_CHIP_MASK_ALL,
1843                         NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
1844                 { BNX2X_CHIP_MASK_ALL,
1845                         NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1846                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1847                         NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
1848                 { BNX2X_CHIP_MASK_ALL,
1849                         NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1850                 { BNX2X_CHIP_MASK_ALL,
1851                         NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1852                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1853                         NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1854                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1855                         NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
1856
1857                 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
1858         };
1859
1860         if (!netif_running(bp->dev)) {
1861                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1862                    "cannot access eeprom when the interface is down\n");
1863                 return rc;
1864         }
1865
1866         if (CHIP_IS_E1(bp))
1867                 hw = BNX2X_CHIP_MASK_E1;
1868         else if (CHIP_IS_E1H(bp))
1869                 hw = BNX2X_CHIP_MASK_E1H;
1870         else if (CHIP_IS_E2(bp))
1871                 hw = BNX2X_CHIP_MASK_E2;
1872         else if (CHIP_IS_E3B0(bp))
1873                 hw = BNX2X_CHIP_MASK_E3B0;
1874         else /* e3 A0 */
1875                 hw = BNX2X_CHIP_MASK_E3;
1876
1877         /* Repeat the test twice:
1878            First by writing 0x00000000, second by writing 0xffffffff */
1879         for (idx = 0; idx < 2; idx++) {
1880
1881                 switch (idx) {
1882                 case 0:
1883                         wr_val = 0;
1884                         break;
1885                 case 1:
1886                         wr_val = 0xffffffff;
1887                         break;
1888                 }
1889
1890                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1891                         u32 offset, mask, save_val, val;
1892                         if (!(hw & reg_tbl[i].hw))
1893                                 continue;
1894
1895                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1896                         mask = reg_tbl[i].mask;
1897
1898                         save_val = REG_RD(bp, offset);
1899
1900                         REG_WR(bp, offset, wr_val & mask);
1901
1902                         val = REG_RD(bp, offset);
1903
1904                         /* Restore the original register's value */
1905                         REG_WR(bp, offset, save_val);
1906
1907                         /* verify value is as expected */
1908                         if ((val & mask) != (wr_val & mask)) {
1909                                 DP(BNX2X_MSG_ETHTOOL,
1910                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1911                                    offset, val, wr_val, mask);
1912                                 goto test_reg_exit;
1913                         }
1914                 }
1915         }
1916
1917         rc = 0;
1918
1919 test_reg_exit:
1920         return rc;
1921 }
1922
1923 static int bnx2x_test_memory(struct bnx2x *bp)
1924 {
1925         int i, j, rc = -ENODEV;
1926         u32 val, index;
1927         static const struct {
1928                 u32 offset;
1929                 int size;
1930         } mem_tbl[] = {
1931                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
1932                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1933                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
1934                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
1935                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
1936                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
1937                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
1938
1939                 { 0xffffffff, 0 }
1940         };
1941
1942         static const struct {
1943                 char *name;
1944                 u32 offset;
1945                 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
1946         } prty_tbl[] = {
1947                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
1948                         {0x3ffc0, 0,   0, 0} },
1949                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
1950                         {0x2,     0x2, 0, 0} },
1951                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1952                         {0,       0,   0, 0} },
1953                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
1954                         {0x3ffc0, 0,   0, 0} },
1955                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
1956                         {0x3ffc0, 0,   0, 0} },
1957                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
1958                         {0x3ffc1, 0,   0, 0} },
1959
1960                 { NULL, 0xffffffff, {0, 0, 0, 0} }
1961         };
1962
1963         if (!netif_running(bp->dev)) {
1964                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1965                    "cannot access eeprom when the interface is down\n");
1966                 return rc;
1967         }
1968
1969         if (CHIP_IS_E1(bp))
1970                 index = BNX2X_CHIP_E1_OFST;
1971         else if (CHIP_IS_E1H(bp))
1972                 index = BNX2X_CHIP_E1H_OFST;
1973         else if (CHIP_IS_E2(bp))
1974                 index = BNX2X_CHIP_E2_OFST;
1975         else /* e3 */
1976                 index = BNX2X_CHIP_E3_OFST;
1977
1978         /* pre-Check the parity status */
1979         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1980                 val = REG_RD(bp, prty_tbl[i].offset);
1981                 if (val & ~(prty_tbl[i].hw_mask[index])) {
1982                         DP(BNX2X_MSG_ETHTOOL,
1983                            "%s is 0x%x\n", prty_tbl[i].name, val);
1984                         goto test_mem_exit;
1985                 }
1986         }
1987
1988         /* Go through all the memories */
1989         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1990                 for (j = 0; j < mem_tbl[i].size; j++)
1991                         REG_RD(bp, mem_tbl[i].offset + j*4);
1992
1993         /* Check the parity status */
1994         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1995                 val = REG_RD(bp, prty_tbl[i].offset);
1996                 if (val & ~(prty_tbl[i].hw_mask[index])) {
1997                         DP(BNX2X_MSG_ETHTOOL,
1998                            "%s is 0x%x\n", prty_tbl[i].name, val);
1999                         goto test_mem_exit;
2000                 }
2001         }
2002
2003         rc = 0;
2004
2005 test_mem_exit:
2006         return rc;
2007 }
2008
2009 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2010 {
2011         int cnt = 1400;
2012
2013         if (link_up) {
2014                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2015                         msleep(20);
2016
2017                 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2018                         DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2019
2020                 cnt = 1400;
2021                 while (!bp->link_vars.link_up && cnt--)
2022                         msleep(20);
2023
2024                 if (cnt <= 0 && !bp->link_vars.link_up)
2025                         DP(BNX2X_MSG_ETHTOOL,
2026                            "Timeout waiting for link init\n");
2027         }
2028 }
2029
2030 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2031 {
2032         unsigned int pkt_size, num_pkts, i;
2033         struct sk_buff *skb;
2034         unsigned char *packet;
2035         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2036         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2037         struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2038         u16 tx_start_idx, tx_idx;
2039         u16 rx_start_idx, rx_idx;
2040         u16 pkt_prod, bd_prod;
2041         struct sw_tx_bd *tx_buf;
2042         struct eth_tx_start_bd *tx_start_bd;
2043         dma_addr_t mapping;
2044         union eth_rx_cqe *cqe;
2045         u8 cqe_fp_flags, cqe_fp_type;
2046         struct sw_rx_bd *rx_buf;
2047         u16 len;
2048         int rc = -ENODEV;
2049         u8 *data;
2050         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2051                                                        txdata->txq_index);
2052
2053         /* check the loopback mode */
2054         switch (loopback_mode) {
2055         case BNX2X_PHY_LOOPBACK:
2056                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2057                         DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2058                         return -EINVAL;
2059                 }
2060                 break;
2061         case BNX2X_MAC_LOOPBACK:
2062                 if (CHIP_IS_E3(bp)) {
2063                         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2064                         if (bp->port.supported[cfg_idx] &
2065                             (SUPPORTED_10000baseT_Full |
2066                              SUPPORTED_20000baseMLD2_Full |
2067                              SUPPORTED_20000baseKR2_Full))
2068                                 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2069                         else
2070                                 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2071                 } else
2072                         bp->link_params.loopback_mode = LOOPBACK_BMAC;
2073
2074                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2075                 break;
2076         case BNX2X_EXT_LOOPBACK:
2077                 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2078                         DP(BNX2X_MSG_ETHTOOL,
2079                            "Can't configure external loopback\n");
2080                         return -EINVAL;
2081                 }
2082                 break;
2083         default:
2084                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2085                 return -EINVAL;
2086         }
2087
2088         /* prepare the loopback packet */
2089         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2090                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2091         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2092         if (!skb) {
2093                 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2094                 rc = -ENOMEM;
2095                 goto test_loopback_exit;
2096         }
2097         packet = skb_put(skb, pkt_size);
2098         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2099         memset(packet + ETH_ALEN, 0, ETH_ALEN);
2100         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2101         for (i = ETH_HLEN; i < pkt_size; i++)
2102                 packet[i] = (unsigned char) (i & 0xff);
2103         mapping = dma_map_single(&bp->pdev->dev, skb->data,
2104                                  skb_headlen(skb), DMA_TO_DEVICE);
2105         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2106                 rc = -ENOMEM;
2107                 dev_kfree_skb(skb);
2108                 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2109                 goto test_loopback_exit;
2110         }
2111
2112         /* send the loopback packet */
2113         num_pkts = 0;
2114         tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2115         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2116
2117         netdev_tx_sent_queue(txq, skb->len);
2118
2119         pkt_prod = txdata->tx_pkt_prod++;
2120         tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2121         tx_buf->first_bd = txdata->tx_bd_prod;
2122         tx_buf->skb = skb;
2123         tx_buf->flags = 0;
2124
2125         bd_prod = TX_BD(txdata->tx_bd_prod);
2126         tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2127         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2128         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2129         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2130         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2131         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2132         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2133         SET_FLAG(tx_start_bd->general_data,
2134                  ETH_TX_START_BD_HDR_NBDS,
2135                  1);
2136         SET_FLAG(tx_start_bd->general_data,
2137                  ETH_TX_START_BD_PARSE_NBDS,
2138                  0);
2139
2140         /* turn on parsing and get a BD */
2141         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2142
2143         if (CHIP_IS_E1x(bp)) {
2144                 u16 global_data = 0;
2145                 struct eth_tx_parse_bd_e1x  *pbd_e1x =
2146                         &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2147                 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2148                 SET_FLAG(global_data,
2149                          ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2150                 pbd_e1x->global_data = cpu_to_le16(global_data);
2151         } else {
2152                 u32 parsing_data = 0;
2153                 struct eth_tx_parse_bd_e2  *pbd_e2 =
2154                         &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2155                 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2156                 SET_FLAG(parsing_data,
2157                          ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2158                 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2159         }
2160         wmb();
2161
2162         txdata->tx_db.data.prod += 2;
2163         barrier();
2164         DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2165
2166         mmiowb();
2167         barrier();
2168
2169         num_pkts++;
2170         txdata->tx_bd_prod += 2; /* start + pbd */
2171
2172         udelay(100);
2173
2174         tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2175         if (tx_idx != tx_start_idx + num_pkts)
2176                 goto test_loopback_exit;
2177
2178         /* Unlike HC IGU won't generate an interrupt for status block
2179          * updates that have been performed while interrupts were
2180          * disabled.
2181          */
2182         if (bp->common.int_block == INT_BLOCK_IGU) {
2183                 /* Disable local BHes to prevent a dead-lock situation between
2184                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
2185                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
2186                  */
2187                 local_bh_disable();
2188                 bnx2x_tx_int(bp, txdata);
2189                 local_bh_enable();
2190         }
2191
2192         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2193         if (rx_idx != rx_start_idx + num_pkts)
2194                 goto test_loopback_exit;
2195
2196         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2197         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2198         cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2199         if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2200                 goto test_loopback_rx_exit;
2201
2202         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2203         if (len != pkt_size)
2204                 goto test_loopback_rx_exit;
2205
2206         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2207         dma_sync_single_for_cpu(&bp->pdev->dev,
2208                                    dma_unmap_addr(rx_buf, mapping),
2209                                    fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2210         data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2211         for (i = ETH_HLEN; i < pkt_size; i++)
2212                 if (*(data + i) != (unsigned char) (i & 0xff))
2213                         goto test_loopback_rx_exit;
2214
2215         rc = 0;
2216
2217 test_loopback_rx_exit:
2218
2219         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2220         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2221         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2222         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2223
2224         /* Update producers */
2225         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2226                              fp_rx->rx_sge_prod);
2227
2228 test_loopback_exit:
2229         bp->link_params.loopback_mode = LOOPBACK_NONE;
2230
2231         return rc;
2232 }
2233
2234 static int bnx2x_test_loopback(struct bnx2x *bp)
2235 {
2236         int rc = 0, res;
2237
2238         if (BP_NOMCP(bp))
2239                 return rc;
2240
2241         if (!netif_running(bp->dev))
2242                 return BNX2X_LOOPBACK_FAILED;
2243
2244         bnx2x_netif_stop(bp, 1);
2245         bnx2x_acquire_phy_lock(bp);
2246
2247         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2248         if (res) {
2249                 DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2250                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2251         }
2252
2253         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2254         if (res) {
2255                 DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2256                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2257         }
2258
2259         bnx2x_release_phy_lock(bp);
2260         bnx2x_netif_start(bp);
2261
2262         return rc;
2263 }
2264
2265 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2266 {
2267         int rc;
2268         u8 is_serdes =
2269                 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2270
2271         if (BP_NOMCP(bp))
2272                 return -ENODEV;
2273
2274         if (!netif_running(bp->dev))
2275                 return BNX2X_EXT_LOOPBACK_FAILED;
2276
2277         bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2278         rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2279         if (rc) {
2280                 DP(BNX2X_MSG_ETHTOOL,
2281                    "Can't perform self-test, nic_load (for external lb) failed\n");
2282                 return -ENODEV;
2283         }
2284         bnx2x_wait_for_link(bp, 1, is_serdes);
2285
2286         bnx2x_netif_stop(bp, 1);
2287
2288         rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2289         if (rc)
2290                 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2291
2292         bnx2x_netif_start(bp);
2293
2294         return rc;
2295 }
2296
2297 #define CRC32_RESIDUAL                  0xdebb20e3
2298
2299 static int bnx2x_test_nvram(struct bnx2x *bp)
2300 {
2301         static const struct {
2302                 int offset;
2303                 int size;
2304         } nvram_tbl[] = {
2305                 {     0,  0x14 }, /* bootstrap */
2306                 {  0x14,  0xec }, /* dir */
2307                 { 0x100, 0x350 }, /* manuf_info */
2308                 { 0x450,  0xf0 }, /* feature_info */
2309                 { 0x640,  0x64 }, /* upgrade_key_info */
2310                 { 0x708,  0x70 }, /* manuf_key_info */
2311                 {     0,     0 }
2312         };
2313         __be32 *buf;
2314         u8 *data;
2315         int i, rc;
2316         u32 magic, crc;
2317
2318         if (BP_NOMCP(bp))
2319                 return 0;
2320
2321         buf = kmalloc(0x350, GFP_KERNEL);
2322         if (!buf) {
2323                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2324                 rc = -ENOMEM;
2325                 goto test_nvram_exit;
2326         }
2327         data = (u8 *)buf;
2328
2329         rc = bnx2x_nvram_read(bp, 0, data, 4);
2330         if (rc) {
2331                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2332                    "magic value read (rc %d)\n", rc);
2333                 goto test_nvram_exit;
2334         }
2335
2336         magic = be32_to_cpu(buf[0]);
2337         if (magic != 0x669955aa) {
2338                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2339                    "wrong magic value (0x%08x)\n", magic);
2340                 rc = -ENODEV;
2341                 goto test_nvram_exit;
2342         }
2343
2344         for (i = 0; nvram_tbl[i].size; i++) {
2345
2346                 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2347                                       nvram_tbl[i].size);
2348                 if (rc) {
2349                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2350                            "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2351                         goto test_nvram_exit;
2352                 }
2353
2354                 crc = ether_crc_le(nvram_tbl[i].size, data);
2355                 if (crc != CRC32_RESIDUAL) {
2356                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2357                            "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
2358                         rc = -ENODEV;
2359                         goto test_nvram_exit;
2360                 }
2361         }
2362
2363 test_nvram_exit:
2364         kfree(buf);
2365         return rc;
2366 }
2367
2368 /* Send an EMPTY ramrod on the first queue */
2369 static int bnx2x_test_intr(struct bnx2x *bp)
2370 {
2371         struct bnx2x_queue_state_params params = {NULL};
2372
2373         if (!netif_running(bp->dev)) {
2374                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2375                    "cannot access eeprom when the interface is down\n");
2376                 return -ENODEV;
2377         }
2378
2379         params.q_obj = &bp->sp_objs->q_obj;
2380         params.cmd = BNX2X_Q_CMD_EMPTY;
2381
2382         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2383
2384         return bnx2x_queue_state_change(bp, &params);
2385 }
2386
2387 static void bnx2x_self_test(struct net_device *dev,
2388                             struct ethtool_test *etest, u64 *buf)
2389 {
2390         struct bnx2x *bp = netdev_priv(dev);
2391         u8 is_serdes;
2392         int rc;
2393
2394         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2395                 netdev_err(bp->dev,
2396                            "Handling parity error recovery. Try again later\n");
2397                 etest->flags |= ETH_TEST_FL_FAILED;
2398                 return;
2399         }
2400         DP(BNX2X_MSG_ETHTOOL,
2401            "Self-test command parameters: offline = %d, external_lb = %d\n",
2402            (etest->flags & ETH_TEST_FL_OFFLINE),
2403            (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2404
2405         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2406
2407         if (!netif_running(dev)) {
2408                 DP(BNX2X_MSG_ETHTOOL,
2409                    "Can't perform self-test when interface is down\n");
2410                 return;
2411         }
2412
2413         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2414
2415         /* offline tests are not supported in MF mode */
2416         if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2417                 int port = BP_PORT(bp);
2418                 u32 val;
2419                 u8 link_up;
2420
2421                 /* save current value of input enable for TX port IF */
2422                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2423                 /* disable input for TX port IF */
2424                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2425
2426                 link_up = bp->link_vars.link_up;
2427
2428                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2429                 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2430                 if (rc) {
2431                         etest->flags |= ETH_TEST_FL_FAILED;
2432                         DP(BNX2X_MSG_ETHTOOL,
2433                            "Can't perform self-test, nic_load (for offline) failed\n");
2434                         return;
2435                 }
2436
2437                 /* wait until link state is restored */
2438                 bnx2x_wait_for_link(bp, 1, is_serdes);
2439
2440                 if (bnx2x_test_registers(bp) != 0) {
2441                         buf[0] = 1;
2442                         etest->flags |= ETH_TEST_FL_FAILED;
2443                 }
2444                 if (bnx2x_test_memory(bp) != 0) {
2445                         buf[1] = 1;
2446                         etest->flags |= ETH_TEST_FL_FAILED;
2447                 }
2448
2449                 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
2450                 if (buf[2] != 0)
2451                         etest->flags |= ETH_TEST_FL_FAILED;
2452
2453                 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2454                         buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2455                         if (buf[3] != 0)
2456                                 etest->flags |= ETH_TEST_FL_FAILED;
2457                         etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2458                 }
2459
2460                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2461
2462                 /* restore input for TX port IF */
2463                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2464                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2465                 if (rc) {
2466                         etest->flags |= ETH_TEST_FL_FAILED;
2467                         DP(BNX2X_MSG_ETHTOOL,
2468                            "Can't perform self-test, nic_load (for online) failed\n");
2469                         return;
2470                 }
2471                 /* wait until link state is restored */
2472                 bnx2x_wait_for_link(bp, link_up, is_serdes);
2473         }
2474         if (bnx2x_test_nvram(bp) != 0) {
2475                 if (!IS_MF(bp))
2476                         buf[4] = 1;
2477                 else
2478                         buf[0] = 1;
2479                 etest->flags |= ETH_TEST_FL_FAILED;
2480         }
2481         if (bnx2x_test_intr(bp) != 0) {
2482                 if (!IS_MF(bp))
2483                         buf[5] = 1;
2484                 else
2485                         buf[1] = 1;
2486                 etest->flags |= ETH_TEST_FL_FAILED;
2487         }
2488
2489         if (bnx2x_link_test(bp, is_serdes) != 0) {
2490                 if (!IS_MF(bp))
2491                         buf[6] = 1;
2492                 else
2493                         buf[2] = 1;
2494                 etest->flags |= ETH_TEST_FL_FAILED;
2495         }
2496
2497 #ifdef BNX2X_EXTRA_DEBUG
2498         bnx2x_panic_dump(bp);
2499 #endif
2500 }
2501
2502 #define IS_PORT_STAT(i) \
2503         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2504 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
2505 #define IS_MF_MODE_STAT(bp) \
2506                         (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
2507
2508 /* ethtool statistics are displayed for all regular ethernet queues and the
2509  * fcoe L2 queue if not disabled
2510  */
2511 static int bnx2x_num_stat_queues(struct bnx2x *bp)
2512 {
2513         return BNX2X_NUM_ETH_QUEUES(bp);
2514 }
2515
2516 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2517 {
2518         struct bnx2x *bp = netdev_priv(dev);
2519         int i, num_stats;
2520
2521         switch (stringset) {
2522         case ETH_SS_STATS:
2523                 if (is_multi(bp)) {
2524                         num_stats = bnx2x_num_stat_queues(bp) *
2525                                                 BNX2X_NUM_Q_STATS;
2526                 } else
2527                         num_stats = 0;
2528                 if (IS_MF_MODE_STAT(bp)) {
2529                         for (i = 0; i < BNX2X_NUM_STATS; i++)
2530                                 if (IS_FUNC_STAT(i))
2531                                         num_stats++;
2532                 } else
2533                         num_stats += BNX2X_NUM_STATS;
2534
2535                 return num_stats;
2536
2537         case ETH_SS_TEST:
2538                 return BNX2X_NUM_TESTS(bp);
2539
2540         default:
2541                 return -EINVAL;
2542         }
2543 }
2544
2545 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2546 {
2547         struct bnx2x *bp = netdev_priv(dev);
2548         int i, j, k, start;
2549         char queue_name[MAX_QUEUE_NAME_LEN+1];
2550
2551         switch (stringset) {
2552         case ETH_SS_STATS:
2553                 k = 0;
2554                 if (is_multi(bp)) {
2555                         for_each_eth_queue(bp, i) {
2556                                 memset(queue_name, 0, sizeof(queue_name));
2557                                 sprintf(queue_name, "%d", i);
2558                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
2559                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2560                                                 ETH_GSTRING_LEN,
2561                                                 bnx2x_q_stats_arr[j].string,
2562                                                 queue_name);
2563                                 k += BNX2X_NUM_Q_STATS;
2564                         }
2565                 }
2566
2567
2568                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2569                         if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2570                                 continue;
2571                         strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2572                                    bnx2x_stats_arr[i].string);
2573                         j++;
2574                 }
2575
2576                 break;
2577
2578         case ETH_SS_TEST:
2579                 /* First 4 tests cannot be done in MF mode */
2580                 if (!IS_MF(bp))
2581                         start = 0;
2582                 else
2583                         start = 4;
2584                 memcpy(buf, bnx2x_tests_str_arr + start,
2585                        ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
2586         }
2587 }
2588
2589 static void bnx2x_get_ethtool_stats(struct net_device *dev,
2590                                     struct ethtool_stats *stats, u64 *buf)
2591 {
2592         struct bnx2x *bp = netdev_priv(dev);
2593         u32 *hw_stats, *offset;
2594         int i, j, k = 0;
2595
2596         if (is_multi(bp)) {
2597                 for_each_eth_queue(bp, i) {
2598                         hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
2599                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2600                                 if (bnx2x_q_stats_arr[j].size == 0) {
2601                                         /* skip this counter */
2602                                         buf[k + j] = 0;
2603                                         continue;
2604                                 }
2605                                 offset = (hw_stats +
2606                                           bnx2x_q_stats_arr[j].offset);
2607                                 if (bnx2x_q_stats_arr[j].size == 4) {
2608                                         /* 4-byte counter */
2609                                         buf[k + j] = (u64) *offset;
2610                                         continue;
2611                                 }
2612                                 /* 8-byte counter */
2613                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2614                         }
2615                         k += BNX2X_NUM_Q_STATS;
2616                 }
2617         }
2618
2619         hw_stats = (u32 *)&bp->eth_stats;
2620         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2621                 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2622                         continue;
2623                 if (bnx2x_stats_arr[i].size == 0) {
2624                         /* skip this counter */
2625                         buf[k + j] = 0;
2626                         j++;
2627                         continue;
2628                 }
2629                 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2630                 if (bnx2x_stats_arr[i].size == 4) {
2631                         /* 4-byte counter */
2632                         buf[k + j] = (u64) *offset;
2633                         j++;
2634                         continue;
2635                 }
2636                 /* 8-byte counter */
2637                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2638                 j++;
2639         }
2640 }
2641
2642 static int bnx2x_set_phys_id(struct net_device *dev,
2643                              enum ethtool_phys_id_state state)
2644 {
2645         struct bnx2x *bp = netdev_priv(dev);
2646
2647         if (!netif_running(dev)) {
2648                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2649                    "cannot access eeprom when the interface is down\n");
2650                 return -EAGAIN;
2651         }
2652
2653         if (!bp->port.pmf) {
2654                 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
2655                 return -EOPNOTSUPP;
2656         }
2657
2658         switch (state) {
2659         case ETHTOOL_ID_ACTIVE:
2660                 return 1;       /* cycle on/off once per second */
2661
2662         case ETHTOOL_ID_ON:
2663                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2664                               LED_MODE_ON, SPEED_1000);
2665                 break;
2666
2667         case ETHTOOL_ID_OFF:
2668                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2669                               LED_MODE_FRONT_PANEL_OFF, 0);
2670
2671                 break;
2672
2673         case ETHTOOL_ID_INACTIVE:
2674                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2675                               LED_MODE_OPER,
2676                               bp->link_vars.line_speed);
2677         }
2678
2679         return 0;
2680 }
2681
2682 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2683 {
2684
2685         switch (info->flow_type) {
2686         case TCP_V4_FLOW:
2687         case TCP_V6_FLOW:
2688                 info->data = RXH_IP_SRC | RXH_IP_DST |
2689                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2690                 break;
2691         case UDP_V4_FLOW:
2692                 if (bp->rss_conf_obj.udp_rss_v4)
2693                         info->data = RXH_IP_SRC | RXH_IP_DST |
2694                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
2695                 else
2696                         info->data = RXH_IP_SRC | RXH_IP_DST;
2697                 break;
2698         case UDP_V6_FLOW:
2699                 if (bp->rss_conf_obj.udp_rss_v6)
2700                         info->data = RXH_IP_SRC | RXH_IP_DST |
2701                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
2702                 else
2703                         info->data = RXH_IP_SRC | RXH_IP_DST;
2704                 break;
2705         case IPV4_FLOW:
2706         case IPV6_FLOW:
2707                 info->data = RXH_IP_SRC | RXH_IP_DST;
2708                 break;
2709         default:
2710                 info->data = 0;
2711                 break;
2712         }
2713
2714         return 0;
2715 }
2716
2717 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2718                            u32 *rules __always_unused)
2719 {
2720         struct bnx2x *bp = netdev_priv(dev);
2721
2722         switch (info->cmd) {
2723         case ETHTOOL_GRXRINGS:
2724                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2725                 return 0;
2726         case ETHTOOL_GRXFH:
2727                 return bnx2x_get_rss_flags(bp, info);
2728         default:
2729                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2730                 return -EOPNOTSUPP;
2731         }
2732 }
2733
2734 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2735 {
2736         int udp_rss_requested;
2737
2738         DP(BNX2X_MSG_ETHTOOL,
2739            "Set rss flags command parameters: flow type = %d, data = %llu\n",
2740            info->flow_type, info->data);
2741
2742         switch (info->flow_type) {
2743         case TCP_V4_FLOW:
2744         case TCP_V6_FLOW:
2745                 /* For TCP only 4-tupple hash is supported */
2746                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
2747                                   RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2748                         DP(BNX2X_MSG_ETHTOOL,
2749                            "Command parameters not supported\n");
2750                         return -EINVAL;
2751                 } else {
2752                         return 0;
2753                 }
2754
2755         case UDP_V4_FLOW:
2756         case UDP_V6_FLOW:
2757                 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
2758                 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
2759                                  RXH_L4_B_0_1 | RXH_L4_B_2_3))
2760                         udp_rss_requested = 1;
2761                 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
2762                         udp_rss_requested = 0;
2763                 else
2764                         return -EINVAL;
2765                 if ((info->flow_type == UDP_V4_FLOW) &&
2766                     (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
2767                         bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
2768                         DP(BNX2X_MSG_ETHTOOL,
2769                            "rss re-configured, UDP 4-tupple %s\n",
2770                            udp_rss_requested ? "enabled" : "disabled");
2771                         return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
2772                 } else if ((info->flow_type == UDP_V6_FLOW) &&
2773                            (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
2774                         bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
2775                         return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
2776                         DP(BNX2X_MSG_ETHTOOL,
2777                            "rss re-configured, UDP 4-tupple %s\n",
2778                            udp_rss_requested ? "enabled" : "disabled");
2779                 } else {
2780                         return 0;
2781                 }
2782         case IPV4_FLOW:
2783         case IPV6_FLOW:
2784                 /* For IP only 2-tupple hash is supported */
2785                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
2786                         DP(BNX2X_MSG_ETHTOOL,
2787                            "Command parameters not supported\n");
2788                         return -EINVAL;
2789                 } else {
2790                         return 0;
2791                 }
2792         case SCTP_V4_FLOW:
2793         case AH_ESP_V4_FLOW:
2794         case AH_V4_FLOW:
2795         case ESP_V4_FLOW:
2796         case SCTP_V6_FLOW:
2797         case AH_ESP_V6_FLOW:
2798         case AH_V6_FLOW:
2799         case ESP_V6_FLOW:
2800         case IP_USER_FLOW:
2801         case ETHER_FLOW:
2802                 /* RSS is not supported for these protocols */
2803                 if (info->data) {
2804                         DP(BNX2X_MSG_ETHTOOL,
2805                            "Command parameters not supported\n");
2806                         return -EINVAL;
2807                 } else {
2808                         return 0;
2809                 }
2810         default:
2811                 return -EINVAL;
2812         }
2813 }
2814
2815 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
2816 {
2817         struct bnx2x *bp = netdev_priv(dev);
2818
2819         switch (info->cmd) {
2820         case ETHTOOL_SRXFH:
2821                 return bnx2x_set_rss_flags(bp, info);
2822         default:
2823                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2824                 return -EOPNOTSUPP;
2825         }
2826 }
2827
2828 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
2829 {
2830         return T_ETH_INDIRECTION_TABLE_SIZE;
2831 }
2832
2833 static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
2834 {
2835         struct bnx2x *bp = netdev_priv(dev);
2836         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2837         size_t i;
2838
2839         /* Get the current configuration of the RSS indirection table */
2840         bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2841
2842         /*
2843          * We can't use a memcpy() as an internal storage of an
2844          * indirection table is a u8 array while indir->ring_index
2845          * points to an array of u32.
2846          *
2847          * Indirection table contains the FW Client IDs, so we need to
2848          * align the returned table to the Client ID of the leading RSS
2849          * queue.
2850          */
2851         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
2852                 indir[i] = ind_table[i] - bp->fp->cl_id;
2853
2854         return 0;
2855 }
2856
2857 static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
2858 {
2859         struct bnx2x *bp = netdev_priv(dev);
2860         size_t i;
2861
2862         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
2863                 /*
2864                  * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2865                  * as an internal storage of an indirection table is a u8 array
2866                  * while indir->ring_index points to an array of u32.
2867                  *
2868                  * Indirection table contains the FW Client IDs, so we need to
2869                  * align the received table to the Client ID of the leading RSS
2870                  * queue
2871                  */
2872                 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
2873         }
2874
2875         return bnx2x_config_rss_eth(bp, false);
2876 }
2877
2878 /**
2879  * bnx2x_get_channels - gets the number of RSS queues.
2880  *
2881  * @dev:                net device
2882  * @channels:           returns the number of max / current queues
2883  */
2884 static void bnx2x_get_channels(struct net_device *dev,
2885                                struct ethtool_channels *channels)
2886 {
2887         struct bnx2x *bp = netdev_priv(dev);
2888
2889         channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
2890         channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
2891 }
2892
2893 /**
2894  * bnx2x_change_num_queues - change the number of RSS queues.
2895  *
2896  * @bp:                 bnx2x private structure
2897  *
2898  * Re-configure interrupt mode to get the new number of MSI-X
2899  * vectors and re-add NAPI objects.
2900  */
2901 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
2902 {
2903         bnx2x_disable_msi(bp);
2904         BNX2X_NUM_QUEUES(bp) = num_rss + NON_ETH_CONTEXT_USE;
2905         bnx2x_set_int_mode(bp);
2906 }
2907
2908 /**
2909  * bnx2x_set_channels - sets the number of RSS queues.
2910  *
2911  * @dev:                net device
2912  * @channels:           includes the number of queues requested
2913  */
2914 static int bnx2x_set_channels(struct net_device *dev,
2915                               struct ethtool_channels *channels)
2916 {
2917         struct bnx2x *bp = netdev_priv(dev);
2918
2919
2920         DP(BNX2X_MSG_ETHTOOL,
2921            "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
2922            channels->rx_count, channels->tx_count, channels->other_count,
2923            channels->combined_count);
2924
2925         /* We don't support separate rx / tx channels.
2926          * We don't allow setting 'other' channels.
2927          */
2928         if (channels->rx_count || channels->tx_count || channels->other_count
2929             || (channels->combined_count == 0) ||
2930             (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
2931                 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
2932                 return -EINVAL;
2933         }
2934
2935         /* Check if there was a change in the active parameters */
2936         if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
2937                 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
2938                 return 0;
2939         }
2940
2941         /* Set the requested number of queues in bp context.
2942          * Note that the actual number of queues created during load may be
2943          * less than requested if memory is low.
2944          */
2945         if (unlikely(!netif_running(dev))) {
2946                 bnx2x_change_num_queues(bp, channels->combined_count);
2947                 return 0;
2948         }
2949         bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
2950         bnx2x_change_num_queues(bp, channels->combined_count);
2951         return bnx2x_nic_load(bp, LOAD_NORMAL);
2952 }
2953
2954 static const struct ethtool_ops bnx2x_ethtool_ops = {
2955         .get_settings           = bnx2x_get_settings,
2956         .set_settings           = bnx2x_set_settings,
2957         .get_drvinfo            = bnx2x_get_drvinfo,
2958         .get_regs_len           = bnx2x_get_regs_len,
2959         .get_regs               = bnx2x_get_regs,
2960         .get_wol                = bnx2x_get_wol,
2961         .set_wol                = bnx2x_set_wol,
2962         .get_msglevel           = bnx2x_get_msglevel,
2963         .set_msglevel           = bnx2x_set_msglevel,
2964         .nway_reset             = bnx2x_nway_reset,
2965         .get_link               = bnx2x_get_link,
2966         .get_eeprom_len         = bnx2x_get_eeprom_len,
2967         .get_eeprom             = bnx2x_get_eeprom,
2968         .set_eeprom             = bnx2x_set_eeprom,
2969         .get_coalesce           = bnx2x_get_coalesce,
2970         .set_coalesce           = bnx2x_set_coalesce,
2971         .get_ringparam          = bnx2x_get_ringparam,
2972         .set_ringparam          = bnx2x_set_ringparam,
2973         .get_pauseparam         = bnx2x_get_pauseparam,
2974         .set_pauseparam         = bnx2x_set_pauseparam,
2975         .self_test              = bnx2x_self_test,
2976         .get_sset_count         = bnx2x_get_sset_count,
2977         .get_strings            = bnx2x_get_strings,
2978         .set_phys_id            = bnx2x_set_phys_id,
2979         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
2980         .get_rxnfc              = bnx2x_get_rxnfc,
2981         .set_rxnfc              = bnx2x_set_rxnfc,
2982         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
2983         .get_rxfh_indir         = bnx2x_get_rxfh_indir,
2984         .set_rxfh_indir         = bnx2x_set_rxfh_indir,
2985         .get_channels           = bnx2x_get_channels,
2986         .set_channels           = bnx2x_set_channels,
2987         .get_module_info        = bnx2x_get_module_info,
2988         .get_module_eeprom      = bnx2x_get_module_eeprom,
2989         .get_eee                = bnx2x_get_eee,
2990         .set_eee                = bnx2x_set_eee,
2991         .get_ts_info            = ethtool_op_get_ts_info,
2992 };
2993
2994 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2995 {
2996         SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2997 }