drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/ethtool.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/types.h>
  23 #include <linux/sched.h>
  24 #include <linux/crc32.h>
  25 #include "bnx2x.h"
  26 #include "bnx2x_cmn.h"
  27 #include "bnx2x_dump.h"
  28 #include "bnx2x_init.h"
  29
  30 /* Note: in the format strings below %s is replaced by the queue-name which is
  31  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  32  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  33  */
  34 #define MAX_QUEUE_NAME_LEN      4
  35 static const struct {
  36         long offset;
  37         int size;
  38         char string[ETH_GSTRING_LEN];
  39 } bnx2x_q_stats_arr[] = {
  40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  41         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  42                                                 8, "[%s]: rx_ucast_packets" },
  43         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  44                                                 8, "[%s]: rx_mcast_packets" },
  45         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  46                                                 8, "[%s]: rx_bcast_packets" },
  47         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  48         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  49                                          4, "[%s]: rx_phy_ip_err_discards"},
  50         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  51                                          4, "[%s]: rx_skb_alloc_discard" },
  52         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  53
  54         { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  56                                                 8, "[%s]: tx_ucast_packets" },
  57         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  58                                                 8, "[%s]: tx_mcast_packets" },
  59         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  60                                                 8, "[%s]: tx_bcast_packets" },
  61         { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  62                                                 8, "[%s]: tpa_aggregations" },
  63         { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  64                                         8, "[%s]: tpa_aggregated_frames"},
  65         { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
  66         { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
  67                                         4, "[%s]: driver_filtered_tx_pkt" }
  68 };
  69
  70 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  71
  72 static const struct {
  73         long offset;
  74         int size;
  75         u32 flags;
  76 #define STATS_FLAGS_PORT                1
  77 #define STATS_FLAGS_FUNC                2
  78 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  79         char string[ETH_GSTRING_LEN];
  80 } bnx2x_stats_arr[] = {
  81 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  82                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  83         { STATS_OFFSET32(error_bytes_received_hi),
  84                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  85         { STATS_OFFSET32(total_unicast_packets_received_hi),
  86                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  87         { STATS_OFFSET32(total_multicast_packets_received_hi),
  88                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  89         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  90                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  91         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  92                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  93         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  94                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  95         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  96                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  97         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  98                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
  99 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
 100                                 8, STATS_FLAGS_PORT, "rx_fragments" },
 101         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
 102                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
 103         { STATS_OFFSET32(no_buff_discard_hi),
 104                                 8, STATS_FLAGS_BOTH, "rx_discards" },
 105         { STATS_OFFSET32(mac_filter_discard),
 106                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 107         { STATS_OFFSET32(mf_tag_discard),
 108                                 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
 109         { STATS_OFFSET32(pfc_frames_received_hi),
 110                                 8, STATS_FLAGS_PORT, "pfc_frames_received" },
 111         { STATS_OFFSET32(pfc_frames_sent_hi),
 112                                 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
 113         { STATS_OFFSET32(brb_drop_hi),
 114                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 115         { STATS_OFFSET32(brb_truncate_hi),
 116                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 117         { STATS_OFFSET32(pause_frames_received_hi),
 118                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 119         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 120                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 121         { STATS_OFFSET32(nig_timer_max),
 122                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 123 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 124                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 125         { STATS_OFFSET32(rx_skb_alloc_failed),
 126                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 127         { STATS_OFFSET32(hw_csum_err),
 128                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 129
 130         { STATS_OFFSET32(total_bytes_transmitted_hi),
 131                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 132         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 133                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 134         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 135                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 136         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 137                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 138         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 139                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 140         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 141                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 142         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 143                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 145                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 146         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 147                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 148         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 149                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 150         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 151                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 152         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 153                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 154         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 155                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 156         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 157                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 158         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 159                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 160         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 161                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 162         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 163                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 165                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 166         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 167                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 168         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 169                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 170         { STATS_OFFSET32(pause_frames_sent_hi),
 171                                 8, STATS_FLAGS_PORT, "tx_pause_frames" },
 172         { STATS_OFFSET32(total_tpa_aggregations_hi),
 173                         8, STATS_FLAGS_FUNC, "tpa_aggregations" },
 174         { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
 175                         8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
 176         { STATS_OFFSET32(total_tpa_bytes_hi),
 177                         8, STATS_FLAGS_FUNC, "tpa_bytes"},
 178         { STATS_OFFSET32(recoverable_error),
 179                         4, STATS_FLAGS_FUNC, "recoverable_errors" },
 180         { STATS_OFFSET32(unrecoverable_error),
 181                         4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
 182         { STATS_OFFSET32(driver_filtered_tx_pkt),
 183                         4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
 184         { STATS_OFFSET32(eee_tx_lpi),
 185                         4, STATS_FLAGS_PORT, "Tx LPI entry count"}
 186 };
 187
 188 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 189
 190 static int bnx2x_get_port_type(struct bnx2x *bp)
 191 {
 192         int port_type;
 193         u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 194         switch (bp->link_params.phy[phy_idx].media_type) {
 195         case ETH_PHY_SFPP_10G_FIBER:
 196         case ETH_PHY_SFP_1G_FIBER:
 197         case ETH_PHY_XFP_FIBER:
 198         case ETH_PHY_KR:
 199         case ETH_PHY_CX4:
 200                 port_type = PORT_FIBRE;
 201                 break;
 202         case ETH_PHY_DA_TWINAX:
 203                 port_type = PORT_DA;
 204                 break;
 205         case ETH_PHY_BASE_T:
 206                 port_type = PORT_TP;
 207                 break;
 208         case ETH_PHY_NOT_PRESENT:
 209                 port_type = PORT_NONE;
 210                 break;
 211         case ETH_PHY_UNSPECIFIED:
 212         default:
 213                 port_type = PORT_OTHER;
 214                 break;
 215         }
 216         return port_type;
 217 }
 218
 219 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 220 {
 221         struct bnx2x *bp = netdev_priv(dev);
 222         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 223
 224         /* Dual Media boards present all available port types */
 225         cmd->supported = bp->port.supported[cfg_idx] |
 226                 (bp->port.supported[cfg_idx ^ 1] &
 227                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 228         cmd->advertising = bp->port.advertising[cfg_idx];
 229         if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
 230             ETH_PHY_SFP_1G_FIBER) {
 231                 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
 232                 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
 233         }
 234
 235         if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
 236             !(bp->flags & MF_FUNC_DIS)) {
 237                 cmd->duplex = bp->link_vars.duplex;
 238
 239                 if (IS_MF(bp) && !BP_NOMCP(bp))
 240                         ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 241                 else
 242                         ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 243         } else {
 244                 cmd->duplex = DUPLEX_UNKNOWN;
 245                 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
 246         }
 247
 248         cmd->port = bnx2x_get_port_type(bp);
 249
 250         cmd->phy_address = bp->mdio.prtad;
 251         cmd->transceiver = XCVR_INTERNAL;
 252
 253         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 254                 cmd->autoneg = AUTONEG_ENABLE;
 255         else
 256                 cmd->autoneg = AUTONEG_DISABLE;
 257
 258         /* Publish LP advertised speeds and FC */
 259         if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
 260                 u32 status = bp->link_vars.link_status;
 261
 262                 cmd->lp_advertising |= ADVERTISED_Autoneg;
 263                 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
 264                         cmd->lp_advertising |= ADVERTISED_Pause;
 265                 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 266                         cmd->lp_advertising |= ADVERTISED_Asym_Pause;
 267
 268                 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
 269                         cmd->lp_advertising |= ADVERTISED_10baseT_Half;
 270                 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
 271                         cmd->lp_advertising |= ADVERTISED_10baseT_Full;
 272                 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
 273                         cmd->lp_advertising |= ADVERTISED_100baseT_Half;
 274                 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
 275                         cmd->lp_advertising |= ADVERTISED_100baseT_Full;
 276                 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
 277                         cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
 278                 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
 279                         cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
 280                 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
 281                         cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
 282                 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
 283                         cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
 284                 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
 285                         cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
 286         }
 287
 288         cmd->maxtxpkt = 0;
 289         cmd->maxrxpkt = 0;
 290
 291         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 292            "  supported 0x%x  advertising 0x%x  speed %u\n"
 293            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 294            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 295            cmd->cmd, cmd->supported, cmd->advertising,
 296            ethtool_cmd_speed(cmd),
 297            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 298            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 299
 300         return 0;
 301 }
 302
 303 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 304 {
 305         struct bnx2x *bp = netdev_priv(dev);
 306         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 307         u32 speed, phy_idx;
 308
 309         if (IS_MF_SD(bp))
 310                 return 0;
 311
 312         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 313            "  supported 0x%x  advertising 0x%x  speed %u\n"
 314            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 315            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 316            cmd->cmd, cmd->supported, cmd->advertising,
 317            ethtool_cmd_speed(cmd),
 318            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 319            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 320
 321         speed = ethtool_cmd_speed(cmd);
 322
 323         /* If received a request for an unknown duplex, assume full*/
 324         if (cmd->duplex == DUPLEX_UNKNOWN)
 325                 cmd->duplex = DUPLEX_FULL;
 326
 327         if (IS_MF_SI(bp)) {
 328                 u32 part;
 329                 u32 line_speed = bp->link_vars.line_speed;
 330
 331                 /* use 10G if no link detected */
 332                 if (!line_speed)
 333                         line_speed = 10000;
 334
 335                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 336                         DP(BNX2X_MSG_ETHTOOL,
 337                            "To set speed BC %X or higher is required, please upgrade BC\n",
 338                            REQ_BC_VER_4_SET_MF_BW);
 339                         return -EINVAL;
 340                 }
 341
 342                 part = (speed * 100) / line_speed;
 343
 344                 if (line_speed < speed || !part) {
 345                         DP(BNX2X_MSG_ETHTOOL,
 346                            "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
 347                         return -EINVAL;
 348                 }
 349
 350                 if (bp->state != BNX2X_STATE_OPEN)
 351                         /* store value for following "load" */
 352                         bp->pending_max = part;
 353                 else
 354                         bnx2x_update_max_mf_config(bp, part);
 355
 356                 return 0;
 357         }
 358
 359         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 360         old_multi_phy_config = bp->link_params.multi_phy_config;
 361         if (cmd->port != bnx2x_get_port_type(bp)) {
 362                 switch (cmd->port) {
 363                 case PORT_TP:
 364                         if (!(bp->port.supported[0] & SUPPORTED_TP ||
 365                               bp->port.supported[1] & SUPPORTED_TP)) {
 366                                 DP(BNX2X_MSG_ETHTOOL,
 367                                    "Unsupported port type\n");
 368                                 return -EINVAL;
 369                         }
 370                         bp->link_params.multi_phy_config &=
 371                                 ~PORT_HW_CFG_PHY_SELECTION_MASK;
 372                         if (bp->link_params.multi_phy_config &
 373                             PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 374                                 bp->link_params.multi_phy_config |=
 375                                 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 376                         else
 377                                 bp->link_params.multi_phy_config |=
 378                                 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 379                         break;
 380                 case PORT_FIBRE:
 381                 case PORT_DA:
 382                 case PORT_NONE:
 383                         if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 384                               bp->port.supported[1] & SUPPORTED_FIBRE)) {
 385                                 DP(BNX2X_MSG_ETHTOOL,
 386                                    "Unsupported port type\n");
 387                                 return -EINVAL;
 388                         }
 389                         bp->link_params.multi_phy_config &=
 390                                 ~PORT_HW_CFG_PHY_SELECTION_MASK;
 391                         if (bp->link_params.multi_phy_config &
 392                             PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 393                                 bp->link_params.multi_phy_config |=
 394                                 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 395                         else
 396                                 bp->link_params.multi_phy_config |=
 397                                 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 398                         break;
 399                 default:
 400                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 401                         return -EINVAL;
 402                 }
 403         }
 404         /* Save new config in case command complete successfully */
 405         new_multi_phy_config = bp->link_params.multi_phy_config;
 406         /* Get the new cfg_idx */
 407         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 408         /* Restore old config in case command failed */
 409         bp->link_params.multi_phy_config = old_multi_phy_config;
 410         DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
 411
 412         if (cmd->autoneg == AUTONEG_ENABLE) {
 413                 u32 an_supported_speed = bp->port.supported[cfg_idx];
 414                 if (bp->link_params.phy[EXT_PHY1].type ==
 415                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
 416                         an_supported_speed |= (SUPPORTED_100baseT_Half |
 417                                                SUPPORTED_100baseT_Full);
 418                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 419                         DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
 420                         return -EINVAL;
 421                 }
 422
 423                 /* advertise the requested speed and duplex if supported */
 424                 if (cmd->advertising & ~an_supported_speed) {
 425                         DP(BNX2X_MSG_ETHTOOL,
 426                            "Advertisement parameters are not supported\n");
 427                         return -EINVAL;
 428                 }
 429
 430                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 431                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 432                 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
 433                                          cmd->advertising);
 434                 if (cmd->advertising) {
 435
 436                         bp->link_params.speed_cap_mask[cfg_idx] = 0;
 437                         if (cmd->advertising & ADVERTISED_10baseT_Half) {
 438                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 439                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
 440                         }
 441                         if (cmd->advertising & ADVERTISED_10baseT_Full)
 442                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 443                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
 444
 445                         if (cmd->advertising & ADVERTISED_100baseT_Full)
 446                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 447                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
 448
 449                         if (cmd->advertising & ADVERTISED_100baseT_Half) {
 450                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 451                                      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
 452                         }
 453                         if (cmd->advertising & ADVERTISED_1000baseT_Half) {
 454                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 455                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 456                         }
 457                         if (cmd->advertising & (ADVERTISED_1000baseT_Full |
 458                                                 ADVERTISED_1000baseKX_Full))
 459                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 460                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 461
 462                         if (cmd->advertising & (ADVERTISED_10000baseT_Full |
 463                                                 ADVERTISED_10000baseKX4_Full |
 464                                                 ADVERTISED_10000baseKR_Full))
 465                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 466                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
 467
 468                         if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
 469                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 470                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
 471                 }
 472         } else { /* forced speed */
 473                 /* advertise the requested speed and duplex if supported */
 474                 switch (speed) {
 475                 case SPEED_10:
 476                         if (cmd->duplex == DUPLEX_FULL) {
 477                                 if (!(bp->port.supported[cfg_idx] &
 478                                       SUPPORTED_10baseT_Full)) {
 479                                         DP(BNX2X_MSG_ETHTOOL,
 480                                            "10M full not supported\n");
 481                                         return -EINVAL;
 482                                 }
 483
 484                                 advertising = (ADVERTISED_10baseT_Full |
 485                                                ADVERTISED_TP);
 486                         } else {
 487                                 if (!(bp->port.supported[cfg_idx] &
 488                                       SUPPORTED_10baseT_Half)) {
 489                                         DP(BNX2X_MSG_ETHTOOL,
 490                                            "10M half not supported\n");
 491                                         return -EINVAL;
 492                                 }
 493
 494                                 advertising = (ADVERTISED_10baseT_Half |
 495                                                ADVERTISED_TP);
 496                         }
 497                         break;
 498
 499                 case SPEED_100:
 500                         if (cmd->duplex == DUPLEX_FULL) {
 501                                 if (!(bp->port.supported[cfg_idx] &
 502                                                 SUPPORTED_100baseT_Full)) {
 503                                         DP(BNX2X_MSG_ETHTOOL,
 504                                            "100M full not supported\n");
 505                                         return -EINVAL;
 506                                 }
 507
 508                                 advertising = (ADVERTISED_100baseT_Full |
 509                                                ADVERTISED_TP);
 510                         } else {
 511                                 if (!(bp->port.supported[cfg_idx] &
 512                                                 SUPPORTED_100baseT_Half)) {
 513                                         DP(BNX2X_MSG_ETHTOOL,
 514                                            "100M half not supported\n");
 515                                         return -EINVAL;
 516                                 }
 517
 518                                 advertising = (ADVERTISED_100baseT_Half |
 519                                                ADVERTISED_TP);
 520                         }
 521                         break;
 522
 523                 case SPEED_1000:
 524                         if (cmd->duplex != DUPLEX_FULL) {
 525                                 DP(BNX2X_MSG_ETHTOOL,
 526                                    "1G half not supported\n");
 527                                 return -EINVAL;
 528                         }
 529
 530                         if (!(bp->port.supported[cfg_idx] &
 531                               SUPPORTED_1000baseT_Full)) {
 532                                 DP(BNX2X_MSG_ETHTOOL,
 533                                    "1G full not supported\n");
 534                                 return -EINVAL;
 535                         }
 536
 537                         advertising = (ADVERTISED_1000baseT_Full |
 538                                        ADVERTISED_TP);
 539                         break;
 540
 541                 case SPEED_2500:
 542                         if (cmd->duplex != DUPLEX_FULL) {
 543                                 DP(BNX2X_MSG_ETHTOOL,
 544                                    "2.5G half not supported\n");
 545                                 return -EINVAL;
 546                         }
 547
 548                         if (!(bp->port.supported[cfg_idx]
 549                               & SUPPORTED_2500baseX_Full)) {
 550                                 DP(BNX2X_MSG_ETHTOOL,
 551                                    "2.5G full not supported\n");
 552                                 return -EINVAL;
 553                         }
 554
 555                         advertising = (ADVERTISED_2500baseX_Full |
 556                                        ADVERTISED_TP);
 557                         break;
 558
 559                 case SPEED_10000:
 560                         if (cmd->duplex != DUPLEX_FULL) {
 561                                 DP(BNX2X_MSG_ETHTOOL,
 562                                    "10G half not supported\n");
 563                                 return -EINVAL;
 564                         }
 565                         phy_idx = bnx2x_get_cur_phy_idx(bp);
 566                         if (!(bp->port.supported[cfg_idx]
 567                               & SUPPORTED_10000baseT_Full) ||
 568                             (bp->link_params.phy[phy_idx].media_type ==
 569                              ETH_PHY_SFP_1G_FIBER)) {
 570                                 DP(BNX2X_MSG_ETHTOOL,
 571                                    "10G full not supported\n");
 572                                 return -EINVAL;
 573                         }
 574
 575                         advertising = (ADVERTISED_10000baseT_Full |
 576                                        ADVERTISED_FIBRE);
 577                         break;
 578
 579                 default:
 580                         DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
 581                         return -EINVAL;
 582                 }
 583
 584                 bp->link_params.req_line_speed[cfg_idx] = speed;
 585                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 586                 bp->port.advertising[cfg_idx] = advertising;
 587         }
 588
 589         DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
 590            "  req_duplex %d  advertising 0x%x\n",
 591            bp->link_params.req_line_speed[cfg_idx],
 592            bp->link_params.req_duplex[cfg_idx],
 593            bp->port.advertising[cfg_idx]);
 594
 595         /* Set new config */
 596         bp->link_params.multi_phy_config = new_multi_phy_config;
 597         if (netif_running(dev)) {
 598                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 599                 bnx2x_link_set(bp);
 600         }
 601
 602         return 0;
 603 }
 604
 605 #define DUMP_ALL_PRESETS                0x1FFF
 606 #define DUMP_MAX_PRESETS                13
 607
 608 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
 609 {
 610         if (CHIP_IS_E1(bp))
 611                 return dump_num_registers[0][preset-1];
 612         else if (CHIP_IS_E1H(bp))
 613                 return dump_num_registers[1][preset-1];
 614         else if (CHIP_IS_E2(bp))
 615                 return dump_num_registers[2][preset-1];
 616         else if (CHIP_IS_E3A0(bp))
 617                 return dump_num_registers[3][preset-1];
 618         else if (CHIP_IS_E3B0(bp))
 619                 return dump_num_registers[4][preset-1];
 620         else
 621                 return 0;
 622 }
 623
 624 static int __bnx2x_get_regs_len(struct bnx2x *bp)
 625 {
 626         u32 preset_idx;
 627         int regdump_len = 0;
 628
 629         /* Calculate the total preset regs length */
 630         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
 631                 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
 632
 633         return regdump_len;
 634 }
 635
 636 static int bnx2x_get_regs_len(struct net_device *dev)
 637 {
 638         struct bnx2x *bp = netdev_priv(dev);
 639         int regdump_len = 0;
 640
 641         if (IS_VF(bp))
 642                 return 0;
 643
 644         regdump_len = __bnx2x_get_regs_len(bp);
 645         regdump_len *= 4;
 646         regdump_len += sizeof(struct dump_header);
 647
 648         return regdump_len;
 649 }
 650
 651 #define IS_E1_REG(chips)        ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
 652 #define IS_E1H_REG(chips)       ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
 653 #define IS_E2_REG(chips)        ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
 654 #define IS_E3A0_REG(chips)      ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
 655 #define IS_E3B0_REG(chips)      ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
 656
 657 #define IS_REG_IN_PRESET(presets, idx)  \
 658                 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
 659
 660 /******* Paged registers info selectors ********/
 661 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 662 {
 663         if (CHIP_IS_E2(bp))
 664                 return page_vals_e2;
 665         else if (CHIP_IS_E3(bp))
 666                 return page_vals_e3;
 667         else
 668                 return NULL;
 669 }
 670
 671 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
 672 {
 673         if (CHIP_IS_E2(bp))
 674                 return PAGE_MODE_VALUES_E2;
 675         else if (CHIP_IS_E3(bp))
 676                 return PAGE_MODE_VALUES_E3;
 677         else
 678                 return 0;
 679 }
 680
 681 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 682 {
 683         if (CHIP_IS_E2(bp))
 684                 return page_write_regs_e2;
 685         else if (CHIP_IS_E3(bp))
 686                 return page_write_regs_e3;
 687         else
 688                 return NULL;
 689 }
 690
 691 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
 692 {
 693         if (CHIP_IS_E2(bp))
 694                 return PAGE_WRITE_REGS_E2;
 695         else if (CHIP_IS_E3(bp))
 696                 return PAGE_WRITE_REGS_E3;
 697         else
 698                 return 0;
 699 }
 700
 701 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
 702 {
 703         if (CHIP_IS_E2(bp))
 704                 return page_read_regs_e2;
 705         else if (CHIP_IS_E3(bp))
 706                 return page_read_regs_e3;
 707         else
 708                 return NULL;
 709 }
 710
 711 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
 712 {
 713         if (CHIP_IS_E2(bp))
 714                 return PAGE_READ_REGS_E2;
 715         else if (CHIP_IS_E3(bp))
 716                 return PAGE_READ_REGS_E3;
 717         else
 718                 return 0;
 719 }
 720
 721 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
 722                                        const struct reg_addr *reg_info)
 723 {
 724         if (CHIP_IS_E1(bp))
 725                 return IS_E1_REG(reg_info->chips);
 726         else if (CHIP_IS_E1H(bp))
 727                 return IS_E1H_REG(reg_info->chips);
 728         else if (CHIP_IS_E2(bp))
 729                 return IS_E2_REG(reg_info->chips);
 730         else if (CHIP_IS_E3A0(bp))
 731                 return IS_E3A0_REG(reg_info->chips);
 732         else if (CHIP_IS_E3B0(bp))
 733                 return IS_E3B0_REG(reg_info->chips);
 734         else
 735                 return false;
 736 }
 737
 738 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
 739         const struct wreg_addr *wreg_info)
 740 {
 741         if (CHIP_IS_E1(bp))
 742                 return IS_E1_REG(wreg_info->chips);
 743         else if (CHIP_IS_E1H(bp))
 744                 return IS_E1H_REG(wreg_info->chips);
 745         else if (CHIP_IS_E2(bp))
 746                 return IS_E2_REG(wreg_info->chips);
 747         else if (CHIP_IS_E3A0(bp))
 748                 return IS_E3A0_REG(wreg_info->chips);
 749         else if (CHIP_IS_E3B0(bp))
 750                 return IS_E3B0_REG(wreg_info->chips);
 751         else
 752                 return false;
 753 }
 754
 755 /**
 756  * bnx2x_read_pages_regs - read "paged" registers
 757  *
 758  * @bp          device handle
 759  * @p           output buffer
 760  *
 761  * Reads "paged" memories: memories that may only be read by first writing to a
 762  * specific address ("write address") and then reading from a specific address
 763  * ("read address"). There may be more than one write address per "page" and
 764  * more than one read address per write address.
 765  */
 766 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
 767 {
 768         u32 i, j, k, n;
 769
 770         /* addresses of the paged registers */
 771         const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
 772         /* number of paged registers */
 773         int num_pages = __bnx2x_get_page_reg_num(bp);
 774         /* write addresses */
 775         const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
 776         /* number of write addresses */
 777         int write_num = __bnx2x_get_page_write_num(bp);
 778         /* read addresses info */
 779         const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
 780         /* number of read addresses */
 781         int read_num = __bnx2x_get_page_read_num(bp);
 782         u32 addr, size;
 783
 784         for (i = 0; i < num_pages; i++) {
 785                 for (j = 0; j < write_num; j++) {
 786                         REG_WR(bp, write_addr[j], page_addr[i]);
 787
 788                         for (k = 0; k < read_num; k++) {
 789                                 if (IS_REG_IN_PRESET(read_addr[k].presets,
 790                                                      preset)) {
 791                                         size = read_addr[k].size;
 792                                         for (n = 0; n < size; n++) {
 793                                                 addr = read_addr[k].addr + n*4;
 794                                                 *p++ = REG_RD(bp, addr);
 795                                         }
 796                                 }
 797                         }
 798                 }
 799         }
 800 }
 801
 802 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
 803 {
 804         u32 i, j, addr;
 805         const struct wreg_addr *wreg_addr_p = NULL;
 806
 807         if (CHIP_IS_E1(bp))
 808                 wreg_addr_p = &wreg_addr_e1;
 809         else if (CHIP_IS_E1H(bp))
 810                 wreg_addr_p = &wreg_addr_e1h;
 811         else if (CHIP_IS_E2(bp))
 812                 wreg_addr_p = &wreg_addr_e2;
 813         else if (CHIP_IS_E3A0(bp))
 814                 wreg_addr_p = &wreg_addr_e3;
 815         else if (CHIP_IS_E3B0(bp))
 816                 wreg_addr_p = &wreg_addr_e3b0;
 817
 818         /* Read the idle_chk registers */
 819         for (i = 0; i < IDLE_REGS_COUNT; i++) {
 820                 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
 821                     IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
 822                         for (j = 0; j < idle_reg_addrs[i].size; j++)
 823                                 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
 824                 }
 825         }
 826
 827         /* Read the regular registers */
 828         for (i = 0; i < REGS_COUNT; i++) {
 829                 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
 830                     IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
 831                         for (j = 0; j < reg_addrs[i].size; j++)
 832                                 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
 833                 }
 834         }
 835
 836         /* Read the CAM registers */
 837         if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
 838             IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
 839                 for (i = 0; i < wreg_addr_p->size; i++) {
 840                         *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
 841
 842                         /* In case of wreg_addr register, read additional
 843                            registers from read_regs array
 844                         */
 845                         for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
 846                                 addr = *(wreg_addr_p->read_regs);
 847                                 *p++ = REG_RD(bp, addr + j*4);
 848                         }
 849                 }
 850         }
 851
 852         /* Paged registers are supported in E2 & E3 only */
 853         if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
 854                 /* Read "paged" registers */
 855                 bnx2x_read_pages_regs(bp, p, preset);
 856         }
 857
 858         return 0;
 859 }
 860
 861 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 862 {
 863         u32 preset_idx;
 864
 865         /* Read all registers, by reading all preset registers */
 866         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
 867                 /* Skip presets with IOR */
 868                 if ((preset_idx == 2) ||
 869                     (preset_idx == 5) ||
 870                     (preset_idx == 8) ||
 871                     (preset_idx == 11))
 872                         continue;
 873                 __bnx2x_get_preset_regs(bp, p, preset_idx);
 874                 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
 875         }
 876 }
 877
 878 static void bnx2x_get_regs(struct net_device *dev,
 879                            struct ethtool_regs *regs, void *_p)
 880 {
 881         u32 *p = _p;
 882         struct bnx2x *bp = netdev_priv(dev);
 883         struct dump_header dump_hdr = {0};
 884
 885         regs->version = 2;
 886         memset(p, 0, regs->len);
 887
 888         if (!netif_running(bp->dev))
 889                 return;
 890
 891         /* Disable parity attentions as long as following dump may
 892          * cause false alarms by reading never written registers. We
 893          * will re-enable parity attentions right after the dump.
 894          */
 895
 896         bnx2x_disable_blocks_parity(bp);
 897
 898         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
 899         dump_hdr.preset = DUMP_ALL_PRESETS;
 900         dump_hdr.version = BNX2X_DUMP_VERSION;
 901
 902         /* dump_meta_data presents OR of CHIP and PATH. */
 903         if (CHIP_IS_E1(bp)) {
 904                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
 905         } else if (CHIP_IS_E1H(bp)) {
 906                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
 907         } else if (CHIP_IS_E2(bp)) {
 908                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
 909                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 910         } else if (CHIP_IS_E3A0(bp)) {
 911                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
 912                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 913         } else if (CHIP_IS_E3B0(bp)) {
 914                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
 915                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 916         }
 917
 918         memcpy(p, &dump_hdr, sizeof(struct dump_header));
 919         p += dump_hdr.header_size + 1;
 920
 921         /* Actually read the registers */
 922         __bnx2x_get_regs(bp, p);
 923
 924         /* Re-enable parity attentions */
 925         bnx2x_clear_blocks_parity(bp);
 926         bnx2x_enable_blocks_parity(bp);
 927 }
 928
 929 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
 930 {
 931         struct bnx2x *bp = netdev_priv(dev);
 932         int regdump_len = 0;
 933
 934         regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
 935         regdump_len *= 4;
 936         regdump_len += sizeof(struct dump_header);
 937
 938         return regdump_len;
 939 }
 940
 941 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
 942 {
 943         struct bnx2x *bp = netdev_priv(dev);
 944
 945         /* Use the ethtool_dump "flag" field as the dump preset index */
 946         if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
 947                 return -EINVAL;
 948
 949         bp->dump_preset_idx = val->flag;
 950         return 0;
 951 }
 952
 953 static int bnx2x_get_dump_flag(struct net_device *dev,
 954                                struct ethtool_dump *dump)
 955 {
 956         struct bnx2x *bp = netdev_priv(dev);
 957
 958         dump->version = BNX2X_DUMP_VERSION;
 959         dump->flag = bp->dump_preset_idx;
 960         /* Calculate the requested preset idx length */
 961         dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
 962         DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
 963            bp->dump_preset_idx, dump->len);
 964         return 0;
 965 }
 966
 967 static int bnx2x_get_dump_data(struct net_device *dev,
 968                                struct ethtool_dump *dump,
 969                                void *buffer)
 970 {
 971         u32 *p = buffer;
 972         struct bnx2x *bp = netdev_priv(dev);
 973         struct dump_header dump_hdr = {0};
 974
 975         /* Disable parity attentions as long as following dump may
 976          * cause false alarms by reading never written registers. We
 977          * will re-enable parity attentions right after the dump.
 978          */
 979
 980         bnx2x_disable_blocks_parity(bp);
 981
 982         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
 983         dump_hdr.preset = bp->dump_preset_idx;
 984         dump_hdr.version = BNX2X_DUMP_VERSION;
 985
 986         DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
 987
 988         /* dump_meta_data presents OR of CHIP and PATH. */
 989         if (CHIP_IS_E1(bp)) {
 990                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
 991         } else if (CHIP_IS_E1H(bp)) {
 992                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
 993         } else if (CHIP_IS_E2(bp)) {
 994                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
 995                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 996         } else if (CHIP_IS_E3A0(bp)) {
 997                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
 998                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 999         } else if (CHIP_IS_E3B0(bp)) {
1000                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1001                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1002         }
1003
1004         memcpy(p, &dump_hdr, sizeof(struct dump_header));
1005         p += dump_hdr.header_size + 1;
1006
1007         /* Actually read the registers */
1008         __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1009
1010         /* Re-enable parity attentions */
1011         bnx2x_clear_blocks_parity(bp);
1012         bnx2x_enable_blocks_parity(bp);
1013
1014         return 0;
1015 }
1016
1017 static void bnx2x_get_drvinfo(struct net_device *dev,
1018                               struct ethtool_drvinfo *info)
1019 {
1020         struct bnx2x *bp = netdev_priv(dev);
1021
1022         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1023         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1024
1025         bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1026
1027         strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1028         info->n_stats = BNX2X_NUM_STATS;
1029         info->testinfo_len = BNX2X_NUM_TESTS(bp);
1030         info->eedump_len = bp->common.flash_size;
1031         info->regdump_len = bnx2x_get_regs_len(dev);
1032 }
1033
1034 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1035 {
1036         struct bnx2x *bp = netdev_priv(dev);
1037
1038         if (bp->flags & NO_WOL_FLAG) {
1039                 wol->supported = 0;
1040                 wol->wolopts = 0;
1041         } else {
1042                 wol->supported = WAKE_MAGIC;
1043                 if (bp->wol)
1044                         wol->wolopts = WAKE_MAGIC;
1045                 else
1046                         wol->wolopts = 0;
1047         }
1048         memset(&wol->sopass, 0, sizeof(wol->sopass));
1049 }
1050
1051 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1052 {
1053         struct bnx2x *bp = netdev_priv(dev);
1054
1055         if (wol->wolopts & ~WAKE_MAGIC) {
1056                 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1057                 return -EINVAL;
1058         }
1059
1060         if (wol->wolopts & WAKE_MAGIC) {
1061                 if (bp->flags & NO_WOL_FLAG) {
1062                         DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1063                         return -EINVAL;
1064                 }
1065                 bp->wol = 1;
1066         } else
1067                 bp->wol = 0;
1068
1069         return 0;
1070 }
1071
1072 static u32 bnx2x_get_msglevel(struct net_device *dev)
1073 {
1074         struct bnx2x *bp = netdev_priv(dev);
1075
1076         return bp->msg_enable;
1077 }
1078
1079 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1080 {
1081         struct bnx2x *bp = netdev_priv(dev);
1082
1083         if (capable(CAP_NET_ADMIN)) {
1084                 /* dump MCP trace */
1085                 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1086                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
1087                 bp->msg_enable = level;
1088         }
1089 }
1090
1091 static int bnx2x_nway_reset(struct net_device *dev)
1092 {
1093         struct bnx2x *bp = netdev_priv(dev);
1094
1095         if (!bp->port.pmf)
1096                 return 0;
1097
1098         if (netif_running(dev)) {
1099                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1100                 bnx2x_force_link_reset(bp);
1101                 bnx2x_link_set(bp);
1102         }
1103
1104         return 0;
1105 }
1106
1107 static u32 bnx2x_get_link(struct net_device *dev)
1108 {
1109         struct bnx2x *bp = netdev_priv(dev);
1110
1111         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1112                 return 0;
1113
1114         return bp->link_vars.link_up;
1115 }
1116
1117 static int bnx2x_get_eeprom_len(struct net_device *dev)
1118 {
1119         struct bnx2x *bp = netdev_priv(dev);
1120
1121         return bp->common.flash_size;
1122 }
1123
1124 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1125  * had we done things the other way around, if two pfs from the same port would
1126  * attempt to access nvram at the same time, we could run into a scenario such
1127  * as:
1128  * pf A takes the port lock.
1129  * pf B succeeds in taking the same lock since they are from the same port.
1130  * pf A takes the per pf misc lock. Performs eeprom access.
1131  * pf A finishes. Unlocks the per pf misc lock.
1132  * Pf B takes the lock and proceeds to perform it's own access.
1133  * pf A unlocks the per port lock, while pf B is still working (!).
1134  * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1135  * access corrupted by pf B)
1136  */
1137 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1138 {
1139         int port = BP_PORT(bp);
1140         int count, i;
1141         u32 val;
1142
1143         /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1144         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1145
1146         /* adjust timeout for emulation/FPGA */
1147         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1148         if (CHIP_REV_IS_SLOW(bp))
1149                 count *= 100;
1150
1151         /* request access to nvram interface */
1152         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1153                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1154
1155         for (i = 0; i < count*10; i++) {
1156                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1157                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1158                         break;
1159
1160                 udelay(5);
1161         }
1162
1163         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1164                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1165                    "cannot get access to nvram interface\n");
1166                 return -EBUSY;
1167         }
1168
1169         return 0;
1170 }
1171
1172 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1173 {
1174         int port = BP_PORT(bp);
1175         int count, i;
1176         u32 val;
1177
1178         /* adjust timeout for emulation/FPGA */
1179         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1180         if (CHIP_REV_IS_SLOW(bp))
1181                 count *= 100;
1182
1183         /* relinquish nvram interface */
1184         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1185                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1186
1187         for (i = 0; i < count*10; i++) {
1188                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1189                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1190                         break;
1191
1192                 udelay(5);
1193         }
1194
1195         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1196                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1197                    "cannot free access to nvram interface\n");
1198                 return -EBUSY;
1199         }
1200
1201         /* release HW lock: protect against other PFs in PF Direct Assignment */
1202         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1203         return 0;
1204 }
1205
1206 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1207 {
1208         u32 val;
1209
1210         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1211
1212         /* enable both bits, even on read */
1213         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1214                (val | MCPR_NVM_ACCESS_ENABLE_EN |
1215                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
1216 }
1217
1218 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1219 {
1220         u32 val;
1221
1222         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1223
1224         /* disable both bits, even after read */
1225         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1226                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1227                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1228 }
1229
1230 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1231                                   u32 cmd_flags)
1232 {
1233         int count, i, rc;
1234         u32 val;
1235
1236         /* build the command word */
1237         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1238
1239         /* need to clear DONE bit separately */
1240         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1241
1242         /* address of the NVRAM to read from */
1243         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1244                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1245
1246         /* issue a read command */
1247         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1248
1249         /* adjust timeout for emulation/FPGA */
1250         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1251         if (CHIP_REV_IS_SLOW(bp))
1252                 count *= 100;
1253
1254         /* wait for completion */
1255         *ret_val = 0;
1256         rc = -EBUSY;
1257         for (i = 0; i < count; i++) {
1258                 udelay(5);
1259                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1260
1261                 if (val & MCPR_NVM_COMMAND_DONE) {
1262                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1263                         /* we read nvram data in cpu order
1264                          * but ethtool sees it as an array of bytes
1265                          * converting to big-endian will do the work
1266                          */
1267                         *ret_val = cpu_to_be32(val);
1268                         rc = 0;
1269                         break;
1270                 }
1271         }
1272         if (rc == -EBUSY)
1273                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1274                    "nvram read timeout expired\n");
1275         return rc;
1276 }
1277
1278 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1279                             int buf_size)
1280 {
1281         int rc;
1282         u32 cmd_flags;
1283         __be32 val;
1284
1285         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1286                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1287                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1288                    offset, buf_size);
1289                 return -EINVAL;
1290         }
1291
1292         if (offset + buf_size > bp->common.flash_size) {
1293                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1294                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1295                    offset, buf_size, bp->common.flash_size);
1296                 return -EINVAL;
1297         }
1298
1299         /* request access to nvram interface */
1300         rc = bnx2x_acquire_nvram_lock(bp);
1301         if (rc)
1302                 return rc;
1303
1304         /* enable access to nvram interface */
1305         bnx2x_enable_nvram_access(bp);
1306
1307         /* read the first word(s) */
1308         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1309         while ((buf_size > sizeof(u32)) && (rc == 0)) {
1310                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1311                 memcpy(ret_buf, &val, 4);
1312
1313                 /* advance to the next dword */
1314                 offset += sizeof(u32);
1315                 ret_buf += sizeof(u32);
1316                 buf_size -= sizeof(u32);
1317                 cmd_flags = 0;
1318         }
1319
1320         if (rc == 0) {
1321                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1322                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1323                 memcpy(ret_buf, &val, 4);
1324         }
1325
1326         /* disable access to nvram interface */
1327         bnx2x_disable_nvram_access(bp);
1328         bnx2x_release_nvram_lock(bp);
1329
1330         return rc;
1331 }
1332
1333 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1334                               int buf_size)
1335 {
1336         int rc;
1337
1338         rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1339
1340         if (!rc) {
1341                 __be32 *be = (__be32 *)buf;
1342
1343                 while ((buf_size -= 4) >= 0)
1344                         *buf++ = be32_to_cpu(*be++);
1345         }
1346
1347         return rc;
1348 }
1349
1350 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1351 {
1352         int rc = 1;
1353         u16 pm = 0;
1354         struct net_device *dev = pci_get_drvdata(bp->pdev);
1355
1356         if (bp->pdev->pm_cap)
1357                 rc = pci_read_config_word(bp->pdev,
1358                                           bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1359
1360         if ((rc && !netif_running(dev)) ||
1361             (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
1362                 return false;
1363
1364         return true;
1365 }
1366
1367 static int bnx2x_get_eeprom(struct net_device *dev,
1368                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1369 {
1370         struct bnx2x *bp = netdev_priv(dev);
1371
1372         if (!bnx2x_is_nvm_accessible(bp)) {
1373                 DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1374                    "cannot access eeprom when the interface is down\n");
1375                 return -EAGAIN;
1376         }
1377
1378         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1379            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1380            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1381            eeprom->len, eeprom->len);
1382
1383         /* parameters already validated in ethtool_get_eeprom */
1384
1385         return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1386 }
1387
1388 static int bnx2x_get_module_eeprom(struct net_device *dev,
1389                                    struct ethtool_eeprom *ee,
1390                                    u8 *data)
1391 {
1392         struct bnx2x *bp = netdev_priv(dev);
1393         int rc = -EINVAL, phy_idx;
1394         u8 *user_data = data;
1395         unsigned int start_addr = ee->offset, xfer_size = 0;
1396
1397         if (!bnx2x_is_nvm_accessible(bp)) {
1398                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1399                    "cannot access eeprom when the interface is down\n");
1400                 return -EAGAIN;
1401         }
1402
1403         phy_idx = bnx2x_get_cur_phy_idx(bp);
1404
1405         /* Read A0 section */
1406         if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1407                 /* Limit transfer size to the A0 section boundary */
1408                 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1409                         xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1410                 else
1411                         xfer_size = ee->len;
1412                 bnx2x_acquire_phy_lock(bp);
1413                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1414                                                   &bp->link_params,
1415                                                   I2C_DEV_ADDR_A0,
1416                                                   start_addr,
1417                                                   xfer_size,
1418                                                   user_data);
1419                 bnx2x_release_phy_lock(bp);
1420                 if (rc) {
1421                         DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1422
1423                         return -EINVAL;
1424                 }
1425                 user_data += xfer_size;
1426                 start_addr += xfer_size;
1427         }
1428
1429         /* Read A2 section */
1430         if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1431             (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1432                 xfer_size = ee->len - xfer_size;
1433                 /* Limit transfer size to the A2 section boundary */
1434                 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1435                         xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1436                 start_addr -= ETH_MODULE_SFF_8079_LEN;
1437                 bnx2x_acquire_phy_lock(bp);
1438                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1439                                                   &bp->link_params,
1440                                                   I2C_DEV_ADDR_A2,
1441                                                   start_addr,
1442                                                   xfer_size,
1443                                                   user_data);
1444                 bnx2x_release_phy_lock(bp);
1445                 if (rc) {
1446                         DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1447                         return -EINVAL;
1448                 }
1449         }
1450         return rc;
1451 }
1452
1453 static int bnx2x_get_module_info(struct net_device *dev,
1454                                  struct ethtool_modinfo *modinfo)
1455 {
1456         struct bnx2x *bp = netdev_priv(dev);
1457         int phy_idx, rc;
1458         u8 sff8472_comp, diag_type;
1459
1460         if (!bnx2x_is_nvm_accessible(bp)) {
1461                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1462                    "cannot access eeprom when the interface is down\n");
1463                 return -EAGAIN;
1464         }
1465         phy_idx = bnx2x_get_cur_phy_idx(bp);
1466         bnx2x_acquire_phy_lock(bp);
1467         rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1468                                           &bp->link_params,
1469                                           I2C_DEV_ADDR_A0,
1470                                           SFP_EEPROM_SFF_8472_COMP_ADDR,
1471                                           SFP_EEPROM_SFF_8472_COMP_SIZE,
1472                                           &sff8472_comp);
1473         bnx2x_release_phy_lock(bp);
1474         if (rc) {
1475                 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1476                 return -EINVAL;
1477         }
1478
1479         bnx2x_acquire_phy_lock(bp);
1480         rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1481                                           &bp->link_params,
1482                                           I2C_DEV_ADDR_A0,
1483                                           SFP_EEPROM_DIAG_TYPE_ADDR,
1484                                           SFP_EEPROM_DIAG_TYPE_SIZE,
1485                                           &diag_type);
1486         bnx2x_release_phy_lock(bp);
1487         if (rc) {
1488                 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1489                 return -EINVAL;
1490         }
1491
1492         if (!sff8472_comp ||
1493             (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) {
1494                 modinfo->type = ETH_MODULE_SFF_8079;
1495                 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1496         } else {
1497                 modinfo->type = ETH_MODULE_SFF_8472;
1498                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1499         }
1500         return 0;
1501 }
1502
1503 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1504                                    u32 cmd_flags)
1505 {
1506         int count, i, rc;
1507
1508         /* build the command word */
1509         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1510
1511         /* need to clear DONE bit separately */
1512         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1513
1514         /* write the data */
1515         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1516
1517         /* address of the NVRAM to write to */
1518         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1519                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1520
1521         /* issue the write command */
1522         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1523
1524         /* adjust timeout for emulation/FPGA */
1525         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1526         if (CHIP_REV_IS_SLOW(bp))
1527                 count *= 100;
1528
1529         /* wait for completion */
1530         rc = -EBUSY;
1531         for (i = 0; i < count; i++) {
1532                 udelay(5);
1533                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1534                 if (val & MCPR_NVM_COMMAND_DONE) {
1535                         rc = 0;
1536                         break;
1537                 }
1538         }
1539
1540         if (rc == -EBUSY)
1541                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1542                    "nvram write timeout expired\n");
1543         return rc;
1544 }
1545
1546 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1547
1548 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1549                               int buf_size)
1550 {
1551         int rc;
1552         u32 cmd_flags, align_offset, val;
1553         __be32 val_be;
1554
1555         if (offset + buf_size > bp->common.flash_size) {
1556                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1557                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1558                    offset, buf_size, bp->common.flash_size);
1559                 return -EINVAL;
1560         }
1561
1562         /* request access to nvram interface */
1563         rc = bnx2x_acquire_nvram_lock(bp);
1564         if (rc)
1565                 return rc;
1566
1567         /* enable access to nvram interface */
1568         bnx2x_enable_nvram_access(bp);
1569
1570         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1571         align_offset = (offset & ~0x03);
1572         rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1573
1574         if (rc == 0) {
1575                 /* nvram data is returned as an array of bytes
1576                  * convert it back to cpu order
1577                  */
1578                 val = be32_to_cpu(val_be);
1579
1580                 val &= ~le32_to_cpu((__force __le32)
1581                                     (0xff << BYTE_OFFSET(offset)));
1582                 val |= le32_to_cpu((__force __le32)
1583                                    (*data_buf << BYTE_OFFSET(offset)));
1584
1585                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1586                                              cmd_flags);
1587         }
1588
1589         /* disable access to nvram interface */
1590         bnx2x_disable_nvram_access(bp);
1591         bnx2x_release_nvram_lock(bp);
1592
1593         return rc;
1594 }
1595
1596 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1597                              int buf_size)
1598 {
1599         int rc;
1600         u32 cmd_flags;
1601         u32 val;
1602         u32 written_so_far;
1603
1604         if (buf_size == 1)      /* ethtool */
1605                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1606
1607         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1608                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1609                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1610                    offset, buf_size);
1611                 return -EINVAL;
1612         }
1613
1614         if (offset + buf_size > bp->common.flash_size) {
1615                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1616                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1617                    offset, buf_size, bp->common.flash_size);
1618                 return -EINVAL;
1619         }
1620
1621         /* request access to nvram interface */
1622         rc = bnx2x_acquire_nvram_lock(bp);
1623         if (rc)
1624                 return rc;
1625
1626         /* enable access to nvram interface */
1627         bnx2x_enable_nvram_access(bp);
1628
1629         written_so_far = 0;
1630         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1631         while ((written_so_far < buf_size) && (rc == 0)) {
1632                 if (written_so_far == (buf_size - sizeof(u32)))
1633                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1634                 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1635                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1636                 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1637                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1638
1639                 memcpy(&val, data_buf, 4);
1640
1641                 /* Notice unlike bnx2x_nvram_read_dword() this will not
1642                  * change val using be32_to_cpu(), which causes data to flip
1643                  * if the eeprom is read and then written back. This is due
1644                  * to tools utilizing this functionality that would break
1645                  * if this would be resolved.
1646                  */
1647                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1648
1649                 /* advance to the next dword */
1650                 offset += sizeof(u32);
1651                 data_buf += sizeof(u32);
1652                 written_so_far += sizeof(u32);
1653                 cmd_flags = 0;
1654         }
1655
1656         /* disable access to nvram interface */
1657         bnx2x_disable_nvram_access(bp);
1658         bnx2x_release_nvram_lock(bp);
1659
1660         return rc;
1661 }
1662
1663 static int bnx2x_set_eeprom(struct net_device *dev,
1664                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1665 {
1666         struct bnx2x *bp = netdev_priv(dev);
1667         int port = BP_PORT(bp);
1668         int rc = 0;
1669         u32 ext_phy_config;
1670
1671         if (!bnx2x_is_nvm_accessible(bp)) {
1672                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1673                    "cannot access eeprom when the interface is down\n");
1674                 return -EAGAIN;
1675         }
1676
1677         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1678            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1679            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1680            eeprom->len, eeprom->len);
1681
1682         /* parameters already validated in ethtool_set_eeprom */
1683
1684         /* PHY eeprom can be accessed only by the PMF */
1685         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1686             !bp->port.pmf) {
1687                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1688                    "wrong magic or interface is not pmf\n");
1689                 return -EINVAL;
1690         }
1691
1692         ext_phy_config =
1693                 SHMEM_RD(bp,
1694                          dev_info.port_hw_config[port].external_phy_config);
1695
1696         if (eeprom->magic == 0x50485950) {
1697                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1698                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1699
1700                 bnx2x_acquire_phy_lock(bp);
1701                 rc |= bnx2x_link_reset(&bp->link_params,
1702                                        &bp->link_vars, 0);
1703                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1704                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1705                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1706                                        MISC_REGISTERS_GPIO_HIGH, port);
1707                 bnx2x_release_phy_lock(bp);
1708                 bnx2x_link_report(bp);
1709
1710         } else if (eeprom->magic == 0x50485952) {
1711                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1712                 if (bp->state == BNX2X_STATE_OPEN) {
1713                         bnx2x_acquire_phy_lock(bp);
1714                         rc |= bnx2x_link_reset(&bp->link_params,
1715                                                &bp->link_vars, 1);
1716
1717                         rc |= bnx2x_phy_init(&bp->link_params,
1718                                              &bp->link_vars);
1719                         bnx2x_release_phy_lock(bp);
1720                         bnx2x_calc_fc_adv(bp);
1721                 }
1722         } else if (eeprom->magic == 0x53985943) {
1723                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1724                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1725                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1726
1727                         /* DSP Remove Download Mode */
1728                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1729                                        MISC_REGISTERS_GPIO_LOW, port);
1730
1731                         bnx2x_acquire_phy_lock(bp);
1732
1733                         bnx2x_sfx7101_sp_sw_reset(bp,
1734                                                 &bp->link_params.phy[EXT_PHY1]);
1735
1736                         /* wait 0.5 sec to allow it to run */
1737                         msleep(500);
1738                         bnx2x_ext_phy_hw_reset(bp, port);
1739                         msleep(500);
1740                         bnx2x_release_phy_lock(bp);
1741                 }
1742         } else
1743                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1744
1745         return rc;
1746 }
1747
1748 static int bnx2x_get_coalesce(struct net_device *dev,
1749                               struct ethtool_coalesce *coal)
1750 {
1751         struct bnx2x *bp = netdev_priv(dev);
1752
1753         memset(coal, 0, sizeof(struct ethtool_coalesce));
1754
1755         coal->rx_coalesce_usecs = bp->rx_ticks;
1756         coal->tx_coalesce_usecs = bp->tx_ticks;
1757
1758         return 0;
1759 }
1760
1761 static int bnx2x_set_coalesce(struct net_device *dev,
1762                               struct ethtool_coalesce *coal)
1763 {
1764         struct bnx2x *bp = netdev_priv(dev);
1765
1766         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1767         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1768                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1769
1770         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1771         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1772                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1773
1774         if (netif_running(dev))
1775                 bnx2x_update_coalesce(bp);
1776
1777         return 0;
1778 }
1779
1780 static void bnx2x_get_ringparam(struct net_device *dev,
1781                                 struct ethtool_ringparam *ering)
1782 {
1783         struct bnx2x *bp = netdev_priv(dev);
1784
1785         ering->rx_max_pending = MAX_RX_AVAIL;
1786
1787         if (bp->rx_ring_size)
1788                 ering->rx_pending = bp->rx_ring_size;
1789         else
1790                 ering->rx_pending = MAX_RX_AVAIL;
1791
1792         ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1793         ering->tx_pending = bp->tx_ring_size;
1794 }
1795
1796 static int bnx2x_set_ringparam(struct net_device *dev,
1797                                struct ethtool_ringparam *ering)
1798 {
1799         struct bnx2x *bp = netdev_priv(dev);
1800
1801         DP(BNX2X_MSG_ETHTOOL,
1802            "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1803            ering->rx_pending, ering->tx_pending);
1804
1805         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1806                 DP(BNX2X_MSG_ETHTOOL,
1807                    "Handling parity error recovery. Try again later\n");
1808                 return -EAGAIN;
1809         }
1810
1811         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1812             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1813                                                     MIN_RX_SIZE_TPA)) ||
1814             (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
1815             (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1816                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1817                 return -EINVAL;
1818         }
1819
1820         bp->rx_ring_size = ering->rx_pending;
1821         bp->tx_ring_size = ering->tx_pending;
1822
1823         return bnx2x_reload_if_running(dev);
1824 }
1825
1826 static void bnx2x_get_pauseparam(struct net_device *dev,
1827                                  struct ethtool_pauseparam *epause)
1828 {
1829         struct bnx2x *bp = netdev_priv(dev);
1830         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1831         int cfg_reg;
1832
1833         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1834                            BNX2X_FLOW_CTRL_AUTO);
1835
1836         if (!epause->autoneg)
1837                 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1838         else
1839                 cfg_reg = bp->link_params.req_fc_auto_adv;
1840
1841         epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1842                             BNX2X_FLOW_CTRL_RX);
1843         epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1844                             BNX2X_FLOW_CTRL_TX);
1845
1846         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1847            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1848            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1849 }
1850
1851 static int bnx2x_set_pauseparam(struct net_device *dev,
1852                                 struct ethtool_pauseparam *epause)
1853 {
1854         struct bnx2x *bp = netdev_priv(dev);
1855         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1856         if (IS_MF(bp))
1857                 return 0;
1858
1859         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1860            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1861            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1862
1863         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1864
1865         if (epause->rx_pause)
1866                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1867
1868         if (epause->tx_pause)
1869                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1870
1871         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1872                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1873
1874         if (epause->autoneg) {
1875                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1876                         DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1877                         return -EINVAL;
1878                 }
1879
1880                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1881                         bp->link_params.req_flow_ctrl[cfg_idx] =
1882                                 BNX2X_FLOW_CTRL_AUTO;
1883                 }
1884                 bp->link_params.req_fc_auto_adv = 0;
1885                 if (epause->rx_pause)
1886                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1887
1888                 if (epause->tx_pause)
1889                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1890
1891                 if (!bp->link_params.req_fc_auto_adv)
1892                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
1893         }
1894
1895         DP(BNX2X_MSG_ETHTOOL,
1896            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1897
1898         if (netif_running(dev)) {
1899                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1900                 bnx2x_link_set(bp);
1901         }
1902
1903         return 0;
1904 }
1905
1906 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
1907         "register_test (offline)    ",
1908         "memory_test (offline)      ",
1909         "int_loopback_test (offline)",
1910         "ext_loopback_test (offline)",
1911         "nvram_test (online)        ",
1912         "interrupt_test (online)    ",
1913         "link_test (online)         "
1914 };
1915
1916 enum {
1917         BNX2X_PRI_FLAG_ISCSI,
1918         BNX2X_PRI_FLAG_FCOE,
1919         BNX2X_PRI_FLAG_STORAGE,
1920         BNX2X_PRI_FLAG_LEN,
1921 };
1922
1923 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
1924         "iSCSI offload support",
1925         "FCoE offload support",
1926         "Storage only interface"
1927 };
1928
1929 static u32 bnx2x_eee_to_adv(u32 eee_adv)
1930 {
1931         u32 modes = 0;
1932
1933         if (eee_adv & SHMEM_EEE_100M_ADV)
1934                 modes |= ADVERTISED_100baseT_Full;
1935         if (eee_adv & SHMEM_EEE_1G_ADV)
1936                 modes |= ADVERTISED_1000baseT_Full;
1937         if (eee_adv & SHMEM_EEE_10G_ADV)
1938                 modes |= ADVERTISED_10000baseT_Full;
1939
1940         return modes;
1941 }
1942
1943 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1944 {
1945         u32 eee_adv = 0;
1946         if (modes & ADVERTISED_100baseT_Full)
1947                 eee_adv |= SHMEM_EEE_100M_ADV;
1948         if (modes & ADVERTISED_1000baseT_Full)
1949                 eee_adv |= SHMEM_EEE_1G_ADV;
1950         if (modes & ADVERTISED_10000baseT_Full)
1951                 eee_adv |= SHMEM_EEE_10G_ADV;
1952
1953         return eee_adv << shift;
1954 }
1955
1956 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1957 {
1958         struct bnx2x *bp = netdev_priv(dev);
1959         u32 eee_cfg;
1960
1961         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1962                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1963                 return -EOPNOTSUPP;
1964         }
1965
1966         eee_cfg = bp->link_vars.eee_status;
1967
1968         edata->supported =
1969                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1970                                  SHMEM_EEE_SUPPORTED_SHIFT);
1971
1972         edata->advertised =
1973                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1974                                  SHMEM_EEE_ADV_STATUS_SHIFT);
1975         edata->lp_advertised =
1976                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1977                                  SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1978
1979         /* SHMEM value is in 16u units --> Convert to 1u units. */
1980         edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1981
1982         edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)     ? 1 : 0;
1983         edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)        ? 1 : 0;
1984         edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1985
1986         return 0;
1987 }
1988
1989 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1990 {
1991         struct bnx2x *bp = netdev_priv(dev);
1992         u32 eee_cfg;
1993         u32 advertised;
1994
1995         if (IS_MF(bp))
1996                 return 0;
1997
1998         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1999                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2000                 return -EOPNOTSUPP;
2001         }
2002
2003         eee_cfg = bp->link_vars.eee_status;
2004
2005         if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2006                 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2007                 return -EOPNOTSUPP;
2008         }
2009
2010         advertised = bnx2x_adv_to_eee(edata->advertised,
2011                                       SHMEM_EEE_ADV_STATUS_SHIFT);
2012         if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2013                 DP(BNX2X_MSG_ETHTOOL,
2014                    "Direct manipulation of EEE advertisement is not supported\n");
2015                 return -EINVAL;
2016         }
2017
2018         if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2019                 DP(BNX2X_MSG_ETHTOOL,
2020                    "Maximal Tx Lpi timer supported is %x(u)\n",
2021                    EEE_MODE_TIMER_MASK);
2022                 return -EINVAL;
2023         }
2024         if (edata->tx_lpi_enabled &&
2025             (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2026                 DP(BNX2X_MSG_ETHTOOL,
2027                    "Minimal Tx Lpi timer supported is %d(u)\n",
2028                    EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2029                 return -EINVAL;
2030         }
2031
2032         /* All is well; Apply changes*/
2033         if (edata->eee_enabled)
2034                 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2035         else
2036                 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2037
2038         if (edata->tx_lpi_enabled)
2039                 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2040         else
2041                 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2042
2043         bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2044         bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2045                                     EEE_MODE_TIMER_MASK) |
2046                                     EEE_MODE_OVERRIDE_NVRAM |
2047                                     EEE_MODE_OUTPUT_TIME;
2048
2049         /* Restart link to propagate changes */
2050         if (netif_running(dev)) {
2051                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2052                 bnx2x_force_link_reset(bp);
2053                 bnx2x_link_set(bp);
2054         }
2055
2056         return 0;
2057 }
2058
2059 enum {
2060         BNX2X_CHIP_E1_OFST = 0,
2061         BNX2X_CHIP_E1H_OFST,
2062         BNX2X_CHIP_E2_OFST,
2063         BNX2X_CHIP_E3_OFST,
2064         BNX2X_CHIP_E3B0_OFST,
2065         BNX2X_CHIP_MAX_OFST
2066 };
2067
2068 #define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
2069 #define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
2070 #define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
2071 #define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
2072 #define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
2073
2074 #define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2075 #define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2076
2077 static int bnx2x_test_registers(struct bnx2x *bp)
2078 {
2079         int idx, i, rc = -ENODEV;
2080         u32 wr_val = 0, hw;
2081         int port = BP_PORT(bp);
2082         static const struct {
2083                 u32 hw;
2084                 u32 offset0;
2085                 u32 offset1;
2086                 u32 mask;
2087         } reg_tbl[] = {
2088 /* 0 */         { BNX2X_CHIP_MASK_ALL,
2089                         BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2090                 { BNX2X_CHIP_MASK_ALL,
2091                         DORQ_REG_DB_ADDR0,              4, 0xffffffff },
2092                 { BNX2X_CHIP_MASK_E1X,
2093                         HC_REG_AGG_INT_0,               4, 0x000003ff },
2094                 { BNX2X_CHIP_MASK_ALL,
2095                         PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
2096                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2097                         PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
2098                 { BNX2X_CHIP_MASK_E3B0,
2099                         PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
2100                 { BNX2X_CHIP_MASK_ALL,
2101                         PRS_REG_CID_PORT_0,             4, 0x00ffffff },
2102                 { BNX2X_CHIP_MASK_ALL,
2103                         PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
2104                 { BNX2X_CHIP_MASK_ALL,
2105                         PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2106                 { BNX2X_CHIP_MASK_ALL,
2107                         PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
2108 /* 10 */        { BNX2X_CHIP_MASK_ALL,
2109                         PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2110                 { BNX2X_CHIP_MASK_ALL,
2111                         PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
2112                 { BNX2X_CHIP_MASK_ALL,
2113                         QM_REG_CONNNUM_0,               4, 0x000fffff },
2114                 { BNX2X_CHIP_MASK_ALL,
2115                         TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
2116                 { BNX2X_CHIP_MASK_ALL,
2117                         SRC_REG_KEYRSS0_0,              40, 0xffffffff },
2118                 { BNX2X_CHIP_MASK_ALL,
2119                         SRC_REG_KEYRSS0_7,              40, 0xffffffff },
2120                 { BNX2X_CHIP_MASK_ALL,
2121                         XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2122                 { BNX2X_CHIP_MASK_ALL,
2123                         XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
2124                 { BNX2X_CHIP_MASK_ALL,
2125                         XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
2126                 { BNX2X_CHIP_MASK_ALL,
2127                         NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
2128 /* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2129                         NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
2130                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2131                         NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
2132                 { BNX2X_CHIP_MASK_ALL,
2133                         NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
2134                 { BNX2X_CHIP_MASK_ALL,
2135                         NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
2136                 { BNX2X_CHIP_MASK_ALL,
2137                         NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
2138                 { BNX2X_CHIP_MASK_ALL,
2139                         NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
2140                 { BNX2X_CHIP_MASK_ALL,
2141                         NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
2142                 { BNX2X_CHIP_MASK_ALL,
2143                         NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
2144                 { BNX2X_CHIP_MASK_ALL,
2145                         NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
2146                 { BNX2X_CHIP_MASK_ALL,
2147                         NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
2148 /* 30 */        { BNX2X_CHIP_MASK_ALL,
2149                         NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
2150                 { BNX2X_CHIP_MASK_ALL,
2151                         NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
2152                 { BNX2X_CHIP_MASK_ALL,
2153                         NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2154                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2155                         NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
2156                 { BNX2X_CHIP_MASK_ALL,
2157                         NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2158                 { BNX2X_CHIP_MASK_ALL,
2159                         NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2160                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2161                         NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2162                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2163                         NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
2164
2165                 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2166         };
2167
2168         if (!bnx2x_is_nvm_accessible(bp)) {
2169                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2170                    "cannot access eeprom when the interface is down\n");
2171                 return rc;
2172         }
2173
2174         if (CHIP_IS_E1(bp))
2175                 hw = BNX2X_CHIP_MASK_E1;
2176         else if (CHIP_IS_E1H(bp))
2177                 hw = BNX2X_CHIP_MASK_E1H;
2178         else if (CHIP_IS_E2(bp))
2179                 hw = BNX2X_CHIP_MASK_E2;
2180         else if (CHIP_IS_E3B0(bp))
2181                 hw = BNX2X_CHIP_MASK_E3B0;
2182         else /* e3 A0 */
2183                 hw = BNX2X_CHIP_MASK_E3;
2184
2185         /* Repeat the test twice:
2186          * First by writing 0x00000000, second by writing 0xffffffff
2187          */
2188         for (idx = 0; idx < 2; idx++) {
2189
2190                 switch (idx) {
2191                 case 0:
2192                         wr_val = 0;
2193                         break;
2194                 case 1:
2195                         wr_val = 0xffffffff;
2196                         break;
2197                 }
2198
2199                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2200                         u32 offset, mask, save_val, val;
2201                         if (!(hw & reg_tbl[i].hw))
2202                                 continue;
2203
2204                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2205                         mask = reg_tbl[i].mask;
2206
2207                         save_val = REG_RD(bp, offset);
2208
2209                         REG_WR(bp, offset, wr_val & mask);
2210
2211                         val = REG_RD(bp, offset);
2212
2213                         /* Restore the original register's value */
2214                         REG_WR(bp, offset, save_val);
2215
2216                         /* verify value is as expected */
2217                         if ((val & mask) != (wr_val & mask)) {
2218                                 DP(BNX2X_MSG_ETHTOOL,
2219                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2220                                    offset, val, wr_val, mask);
2221                                 goto test_reg_exit;
2222                         }
2223                 }
2224         }
2225
2226         rc = 0;
2227
2228 test_reg_exit:
2229         return rc;
2230 }
2231
2232 static int bnx2x_test_memory(struct bnx2x *bp)
2233 {
2234         int i, j, rc = -ENODEV;
2235         u32 val, index;
2236         static const struct {
2237                 u32 offset;
2238                 int size;
2239         } mem_tbl[] = {
2240                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
2241                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2242                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
2243                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
2244                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
2245                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
2246                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
2247
2248                 { 0xffffffff, 0 }
2249         };
2250
2251         static const struct {
2252                 char *name;
2253                 u32 offset;
2254                 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2255         } prty_tbl[] = {
2256                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
2257                         {0x3ffc0, 0,   0, 0} },
2258                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
2259                         {0x2,     0x2, 0, 0} },
2260                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2261                         {0,       0,   0, 0} },
2262                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
2263                         {0x3ffc0, 0,   0, 0} },
2264                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
2265                         {0x3ffc0, 0,   0, 0} },
2266                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
2267                         {0x3ffc1, 0,   0, 0} },
2268
2269                 { NULL, 0xffffffff, {0, 0, 0, 0} }
2270         };
2271
2272         if (!bnx2x_is_nvm_accessible(bp)) {
2273                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2274                    "cannot access eeprom when the interface is down\n");
2275                 return rc;
2276         }
2277
2278         if (CHIP_IS_E1(bp))
2279                 index = BNX2X_CHIP_E1_OFST;
2280         else if (CHIP_IS_E1H(bp))
2281                 index = BNX2X_CHIP_E1H_OFST;
2282         else if (CHIP_IS_E2(bp))
2283                 index = BNX2X_CHIP_E2_OFST;
2284         else /* e3 */
2285                 index = BNX2X_CHIP_E3_OFST;
2286
2287         /* pre-Check the parity status */
2288         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2289                 val = REG_RD(bp, prty_tbl[i].offset);
2290                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2291                         DP(BNX2X_MSG_ETHTOOL,
2292                            "%s is 0x%x\n", prty_tbl[i].name, val);
2293                         goto test_mem_exit;
2294                 }
2295         }
2296
2297         /* Go through all the memories */
2298         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2299                 for (j = 0; j < mem_tbl[i].size; j++)
2300                         REG_RD(bp, mem_tbl[i].offset + j*4);
2301
2302         /* Check the parity status */
2303         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2304                 val = REG_RD(bp, prty_tbl[i].offset);
2305                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2306                         DP(BNX2X_MSG_ETHTOOL,
2307                            "%s is 0x%x\n", prty_tbl[i].name, val);
2308                         goto test_mem_exit;
2309                 }
2310         }
2311
2312         rc = 0;
2313
2314 test_mem_exit:
2315         return rc;
2316 }
2317
2318 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2319 {
2320         int cnt = 1400;
2321
2322         if (link_up) {
2323                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2324                         msleep(20);
2325
2326                 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2327                         DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2328
2329                 cnt = 1400;
2330                 while (!bp->link_vars.link_up && cnt--)
2331                         msleep(20);
2332
2333                 if (cnt <= 0 && !bp->link_vars.link_up)
2334                         DP(BNX2X_MSG_ETHTOOL,
2335                            "Timeout waiting for link init\n");
2336         }
2337 }
2338
2339 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2340 {
2341         unsigned int pkt_size, num_pkts, i;
2342         struct sk_buff *skb;
2343         unsigned char *packet;
2344         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2345         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2346         struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2347         u16 tx_start_idx, tx_idx;
2348         u16 rx_start_idx, rx_idx;
2349         u16 pkt_prod, bd_prod;
2350         struct sw_tx_bd *tx_buf;
2351         struct eth_tx_start_bd *tx_start_bd;
2352         dma_addr_t mapping;
2353         union eth_rx_cqe *cqe;
2354         u8 cqe_fp_flags, cqe_fp_type;
2355         struct sw_rx_bd *rx_buf;
2356         u16 len;
2357         int rc = -ENODEV;
2358         u8 *data;
2359         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2360                                                        txdata->txq_index);
2361
2362         /* check the loopback mode */
2363         switch (loopback_mode) {
2364         case BNX2X_PHY_LOOPBACK:
2365                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2366                         DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2367                         return -EINVAL;
2368                 }
2369                 break;
2370         case BNX2X_MAC_LOOPBACK:
2371                 if (CHIP_IS_E3(bp)) {
2372                         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2373                         if (bp->port.supported[cfg_idx] &
2374                             (SUPPORTED_10000baseT_Full |
2375                              SUPPORTED_20000baseMLD2_Full |
2376                              SUPPORTED_20000baseKR2_Full))
2377                                 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2378                         else
2379                                 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2380                 } else
2381                         bp->link_params.loopback_mode = LOOPBACK_BMAC;
2382
2383                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2384                 break;
2385         case BNX2X_EXT_LOOPBACK:
2386                 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2387                         DP(BNX2X_MSG_ETHTOOL,
2388                            "Can't configure external loopback\n");
2389                         return -EINVAL;
2390                 }
2391                 break;
2392         default:
2393                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2394                 return -EINVAL;
2395         }
2396
2397         /* prepare the loopback packet */
2398         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2399                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2400         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2401         if (!skb) {
2402                 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2403                 rc = -ENOMEM;
2404                 goto test_loopback_exit;
2405         }
2406         packet = skb_put(skb, pkt_size);
2407         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2408         memset(packet + ETH_ALEN, 0, ETH_ALEN);
2409         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2410         for (i = ETH_HLEN; i < pkt_size; i++)
2411                 packet[i] = (unsigned char) (i & 0xff);
2412         mapping = dma_map_single(&bp->pdev->dev, skb->data,
2413                                  skb_headlen(skb), DMA_TO_DEVICE);
2414         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2415                 rc = -ENOMEM;
2416                 dev_kfree_skb(skb);
2417                 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2418                 goto test_loopback_exit;
2419         }
2420
2421         /* send the loopback packet */
2422         num_pkts = 0;
2423         tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2424         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2425
2426         netdev_tx_sent_queue(txq, skb->len);
2427
2428         pkt_prod = txdata->tx_pkt_prod++;
2429         tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2430         tx_buf->first_bd = txdata->tx_bd_prod;
2431         tx_buf->skb = skb;
2432         tx_buf->flags = 0;
2433
2434         bd_prod = TX_BD(txdata->tx_bd_prod);
2435         tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2436         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2437         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2438         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2439         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2440         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2441         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2442         SET_FLAG(tx_start_bd->general_data,
2443                  ETH_TX_START_BD_HDR_NBDS,
2444                  1);
2445         SET_FLAG(tx_start_bd->general_data,
2446                  ETH_TX_START_BD_PARSE_NBDS,
2447                  0);
2448
2449         /* turn on parsing and get a BD */
2450         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2451
2452         if (CHIP_IS_E1x(bp)) {
2453                 u16 global_data = 0;
2454                 struct eth_tx_parse_bd_e1x  *pbd_e1x =
2455                         &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2456                 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2457                 SET_FLAG(global_data,
2458                          ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2459                 pbd_e1x->global_data = cpu_to_le16(global_data);
2460         } else {
2461                 u32 parsing_data = 0;
2462                 struct eth_tx_parse_bd_e2  *pbd_e2 =
2463                         &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2464                 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2465                 SET_FLAG(parsing_data,
2466                          ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2467                 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2468         }
2469         wmb();
2470
2471         txdata->tx_db.data.prod += 2;
2472         barrier();
2473         DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2474
2475         mmiowb();
2476         barrier();
2477
2478         num_pkts++;
2479         txdata->tx_bd_prod += 2; /* start + pbd */
2480
2481         udelay(100);
2482
2483         tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2484         if (tx_idx != tx_start_idx + num_pkts)
2485                 goto test_loopback_exit;
2486
2487         /* Unlike HC IGU won't generate an interrupt for status block
2488          * updates that have been performed while interrupts were
2489          * disabled.
2490          */
2491         if (bp->common.int_block == INT_BLOCK_IGU) {
2492                 /* Disable local BHes to prevent a dead-lock situation between
2493                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
2494                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
2495                  */
2496                 local_bh_disable();
2497                 bnx2x_tx_int(bp, txdata);
2498                 local_bh_enable();
2499         }
2500
2501         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2502         if (rx_idx != rx_start_idx + num_pkts)
2503                 goto test_loopback_exit;
2504
2505         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2506         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2507         cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2508         if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2509                 goto test_loopback_rx_exit;
2510
2511         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2512         if (len != pkt_size)
2513                 goto test_loopback_rx_exit;
2514
2515         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2516         dma_sync_single_for_cpu(&bp->pdev->dev,
2517                                    dma_unmap_addr(rx_buf, mapping),
2518                                    fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2519         data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2520         for (i = ETH_HLEN; i < pkt_size; i++)
2521                 if (*(data + i) != (unsigned char) (i & 0xff))
2522                         goto test_loopback_rx_exit;
2523
2524         rc = 0;
2525
2526 test_loopback_rx_exit:
2527
2528         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2529         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2530         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2531         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2532
2533         /* Update producers */
2534         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2535                              fp_rx->rx_sge_prod);
2536
2537 test_loopback_exit:
2538         bp->link_params.loopback_mode = LOOPBACK_NONE;
2539
2540         return rc;
2541 }
2542
2543 static int bnx2x_test_loopback(struct bnx2x *bp)
2544 {
2545         int rc = 0, res;
2546
2547         if (BP_NOMCP(bp))
2548                 return rc;
2549
2550         if (!netif_running(bp->dev))
2551                 return BNX2X_LOOPBACK_FAILED;
2552
2553         bnx2x_netif_stop(bp, 1);
2554         bnx2x_acquire_phy_lock(bp);
2555
2556         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2557         if (res) {
2558                 DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2559                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2560         }
2561
2562         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2563         if (res) {
2564                 DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2565                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2566         }
2567
2568         bnx2x_release_phy_lock(bp);
2569         bnx2x_netif_start(bp);
2570
2571         return rc;
2572 }
2573
2574 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2575 {
2576         int rc;
2577         u8 is_serdes =
2578                 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2579
2580         if (BP_NOMCP(bp))
2581                 return -ENODEV;
2582
2583         if (!netif_running(bp->dev))
2584                 return BNX2X_EXT_LOOPBACK_FAILED;
2585
2586         bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2587         rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2588         if (rc) {
2589                 DP(BNX2X_MSG_ETHTOOL,
2590                    "Can't perform self-test, nic_load (for external lb) failed\n");
2591                 return -ENODEV;
2592         }
2593         bnx2x_wait_for_link(bp, 1, is_serdes);
2594
2595         bnx2x_netif_stop(bp, 1);
2596
2597         rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2598         if (rc)
2599                 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2600
2601         bnx2x_netif_start(bp);
2602
2603         return rc;
2604 }
2605
2606 struct code_entry {
2607         u32 sram_start_addr;
2608         u32 code_attribute;
2609 #define CODE_IMAGE_TYPE_MASK                    0xf0800003
2610 #define CODE_IMAGE_VNTAG_PROFILES_DATA          0xd0000003
2611 #define CODE_IMAGE_LENGTH_MASK                  0x007ffffc
2612 #define CODE_IMAGE_TYPE_EXTENDED_DIR            0xe0000000
2613         u32 nvm_start_addr;
2614 };
2615
2616 #define CODE_ENTRY_MAX                  16
2617 #define CODE_ENTRY_EXTENDED_DIR_IDX     15
2618 #define MAX_IMAGES_IN_EXTENDED_DIR      64
2619 #define NVRAM_DIR_OFFSET                0x14
2620
2621 #define EXTENDED_DIR_EXISTS(code)                                         \
2622         ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2623          (code & CODE_IMAGE_LENGTH_MASK) != 0)
2624
2625 #define CRC32_RESIDUAL                  0xdebb20e3
2626 #define CRC_BUFF_SIZE                   256
2627
2628 static int bnx2x_nvram_crc(struct bnx2x *bp,
2629                            int offset,
2630                            int size,
2631                            u8 *buff)
2632 {
2633         u32 crc = ~0;
2634         int rc = 0, done = 0;
2635
2636         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2637            "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2638
2639         while (done < size) {
2640                 int count = min_t(int, size - done, CRC_BUFF_SIZE);
2641
2642                 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2643
2644                 if (rc)
2645                         return rc;
2646
2647                 crc = crc32_le(crc, buff, count);
2648                 done += count;
2649         }
2650
2651         if (crc != CRC32_RESIDUAL)
2652                 rc = -EINVAL;
2653
2654         return rc;
2655 }
2656
2657 static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2658                                 struct code_entry *entry,
2659                                 u8 *buff)
2660 {
2661         size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2662         u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2663         int rc;
2664
2665         /* Zero-length images and AFEX profiles do not have CRC */
2666         if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2667                 return 0;
2668
2669         rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2670         if (rc)
2671                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2672                    "image %x has failed crc test (rc %d)\n", type, rc);
2673
2674         return rc;
2675 }
2676
2677 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2678 {
2679         int rc;
2680         struct code_entry entry;
2681
2682         rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2683         if (rc)
2684                 return rc;
2685
2686         return bnx2x_test_nvram_dir(bp, &entry, buff);
2687 }
2688
2689 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2690 {
2691         u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2692         struct code_entry entry;
2693         int i;
2694
2695         rc = bnx2x_nvram_read32(bp,
2696                                 dir_offset +
2697                                 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2698                                 (u32 *)&entry, sizeof(entry));
2699         if (rc)
2700                 return rc;
2701
2702         if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2703                 return 0;
2704
2705         rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2706                                 &cnt, sizeof(u32));
2707         if (rc)
2708                 return rc;
2709
2710         dir_offset = entry.nvm_start_addr + 8;
2711
2712         for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2713                 rc = bnx2x_test_dir_entry(bp, dir_offset +
2714                                               sizeof(struct code_entry) * i,
2715                                           buff);
2716                 if (rc)
2717                         return rc;
2718         }
2719
2720         return 0;
2721 }
2722
2723 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2724 {
2725         u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2726         int i;
2727
2728         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2729
2730         for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2731                 rc = bnx2x_test_dir_entry(bp, dir_offset +
2732                                               sizeof(struct code_entry) * i,
2733                                           buff);
2734                 if (rc)
2735                         return rc;
2736         }
2737
2738         return bnx2x_test_nvram_ext_dirs(bp, buff);
2739 }
2740
2741 struct crc_pair {
2742         int offset;
2743         int size;
2744 };
2745
2746 static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2747                                 const struct crc_pair *nvram_tbl, u8 *buf)
2748 {
2749         int i;
2750
2751         for (i = 0; nvram_tbl[i].size; i++) {
2752                 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2753                                          nvram_tbl[i].size, buf);
2754                 if (rc) {
2755                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2756                            "nvram_tbl[%d] has failed crc test (rc %d)\n",
2757                            i, rc);
2758                         return rc;
2759                 }
2760         }
2761
2762         return 0;
2763 }
2764
2765 static int bnx2x_test_nvram(struct bnx2x *bp)
2766 {
2767         const struct crc_pair nvram_tbl[] = {
2768                 {     0,  0x14 }, /* bootstrap */
2769                 {  0x14,  0xec }, /* dir */
2770                 { 0x100, 0x350 }, /* manuf_info */
2771                 { 0x450,  0xf0 }, /* feature_info */
2772                 { 0x640,  0x64 }, /* upgrade_key_info */
2773                 { 0x708,  0x70 }, /* manuf_key_info */
2774                 {     0,     0 }
2775         };
2776         const struct crc_pair nvram_tbl2[] = {
2777                 { 0x7e8, 0x350 }, /* manuf_info2 */
2778                 { 0xb38,  0xf0 }, /* feature_info */
2779                 {     0,     0 }
2780         };
2781
2782         u8 *buf;
2783         int rc;
2784         u32 magic;
2785
2786         if (BP_NOMCP(bp))
2787                 return 0;
2788
2789         buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2790         if (!buf) {
2791                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2792                 rc = -ENOMEM;
2793                 goto test_nvram_exit;
2794         }
2795
2796         rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2797         if (rc) {
2798                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2799                    "magic value read (rc %d)\n", rc);
2800                 goto test_nvram_exit;
2801         }
2802
2803         if (magic != 0x669955aa) {
2804                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2805                    "wrong magic value (0x%08x)\n", magic);
2806                 rc = -ENODEV;
2807                 goto test_nvram_exit;
2808         }
2809
2810         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2811         rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2812         if (rc)
2813                 goto test_nvram_exit;
2814
2815         if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2816                 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2817                            SHARED_HW_CFG_HIDE_PORT1;
2818
2819                 if (!hide) {
2820                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2821                            "Port 1 CRC test-set\n");
2822                         rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2823                         if (rc)
2824                                 goto test_nvram_exit;
2825                 }
2826         }
2827
2828         rc = bnx2x_test_nvram_dirs(bp, buf);
2829
2830 test_nvram_exit:
2831         kfree(buf);
2832         return rc;
2833 }
2834
2835 /* Send an EMPTY ramrod on the first queue */
2836 static int bnx2x_test_intr(struct bnx2x *bp)
2837 {
2838         struct bnx2x_queue_state_params params = {NULL};
2839
2840         if (!netif_running(bp->dev)) {
2841                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2842                    "cannot access eeprom when the interface is down\n");
2843                 return -ENODEV;
2844         }
2845
2846         params.q_obj = &bp->sp_objs->q_obj;
2847         params.cmd = BNX2X_Q_CMD_EMPTY;
2848
2849         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2850
2851         return bnx2x_queue_state_change(bp, &params);
2852 }
2853
2854 static void bnx2x_self_test(struct net_device *dev,
2855                             struct ethtool_test *etest, u64 *buf)
2856 {
2857         struct bnx2x *bp = netdev_priv(dev);
2858         u8 is_serdes, link_up;
2859         int rc, cnt = 0;
2860
2861         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2862                 netdev_err(bp->dev,
2863                            "Handling parity error recovery. Try again later\n");
2864                 etest->flags |= ETH_TEST_FL_FAILED;
2865                 return;
2866         }
2867
2868         DP(BNX2X_MSG_ETHTOOL,
2869            "Self-test command parameters: offline = %d, external_lb = %d\n",
2870            (etest->flags & ETH_TEST_FL_OFFLINE),
2871            (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2872
2873         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2874
2875         if (bnx2x_test_nvram(bp) != 0) {
2876                 if (!IS_MF(bp))
2877                         buf[4] = 1;
2878                 else
2879                         buf[0] = 1;
2880                 etest->flags |= ETH_TEST_FL_FAILED;
2881         }
2882
2883         if (!netif_running(dev)) {
2884                 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
2885                 return;
2886         }
2887
2888         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2889         link_up = bp->link_vars.link_up;
2890         /* offline tests are not supported in MF mode */
2891         if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2892                 int port = BP_PORT(bp);
2893                 u32 val;
2894
2895                 /* save current value of input enable for TX port IF */
2896                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2897                 /* disable input for TX port IF */
2898                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2899
2900                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2901                 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2902                 if (rc) {
2903                         etest->flags |= ETH_TEST_FL_FAILED;
2904                         DP(BNX2X_MSG_ETHTOOL,
2905                            "Can't perform self-test, nic_load (for offline) failed\n");
2906                         return;
2907                 }
2908
2909                 /* wait until link state is restored */
2910                 bnx2x_wait_for_link(bp, 1, is_serdes);
2911
2912                 if (bnx2x_test_registers(bp) != 0) {
2913                         buf[0] = 1;
2914                         etest->flags |= ETH_TEST_FL_FAILED;
2915                 }
2916                 if (bnx2x_test_memory(bp) != 0) {
2917                         buf[1] = 1;
2918                         etest->flags |= ETH_TEST_FL_FAILED;
2919                 }
2920
2921                 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
2922                 if (buf[2] != 0)
2923                         etest->flags |= ETH_TEST_FL_FAILED;
2924
2925                 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2926                         buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2927                         if (buf[3] != 0)
2928                                 etest->flags |= ETH_TEST_FL_FAILED;
2929                         etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2930                 }
2931
2932                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2933
2934                 /* restore input for TX port IF */
2935                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2936                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2937                 if (rc) {
2938                         etest->flags |= ETH_TEST_FL_FAILED;
2939                         DP(BNX2X_MSG_ETHTOOL,
2940                            "Can't perform self-test, nic_load (for online) failed\n");
2941                         return;
2942                 }
2943                 /* wait until link state is restored */
2944                 bnx2x_wait_for_link(bp, link_up, is_serdes);
2945         }
2946
2947         if (bnx2x_test_intr(bp) != 0) {
2948                 if (!IS_MF(bp))
2949                         buf[5] = 1;
2950                 else
2951                         buf[1] = 1;
2952                 etest->flags |= ETH_TEST_FL_FAILED;
2953         }
2954
2955         if (link_up) {
2956                 cnt = 100;
2957                 while (bnx2x_link_test(bp, is_serdes) && --cnt)
2958                         msleep(20);
2959         }
2960
2961         if (!cnt) {
2962                 if (!IS_MF(bp))
2963                         buf[6] = 1;
2964                 else
2965                         buf[2] = 1;
2966                 etest->flags |= ETH_TEST_FL_FAILED;
2967         }
2968 }
2969
2970 #define IS_PORT_STAT(i) \
2971         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2972 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
2973 #define HIDE_PORT_STAT(bp) \
2974                 ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \
2975                  IS_VF(bp))
2976
2977 /* ethtool statistics are displayed for all regular ethernet queues and the
2978  * fcoe L2 queue if not disabled
2979  */
2980 static int bnx2x_num_stat_queues(struct bnx2x *bp)
2981 {
2982         return BNX2X_NUM_ETH_QUEUES(bp);
2983 }
2984
2985 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2986 {
2987         struct bnx2x *bp = netdev_priv(dev);
2988         int i, num_strings = 0;
2989
2990         switch (stringset) {
2991         case ETH_SS_STATS:
2992                 if (is_multi(bp)) {
2993                         num_strings = bnx2x_num_stat_queues(bp) *
2994                                       BNX2X_NUM_Q_STATS;
2995                 } else
2996                         num_strings = 0;
2997                 if (HIDE_PORT_STAT(bp)) {
2998                         for (i = 0; i < BNX2X_NUM_STATS; i++)
2999                                 if (IS_FUNC_STAT(i))
3000                                         num_strings++;
3001                 } else
3002                         num_strings += BNX2X_NUM_STATS;
3003
3004                 return num_strings;
3005
3006         case ETH_SS_TEST:
3007                 return BNX2X_NUM_TESTS(bp);
3008
3009         case ETH_SS_PRIV_FLAGS:
3010                 return BNX2X_PRI_FLAG_LEN;
3011
3012         default:
3013                 return -EINVAL;
3014         }
3015 }
3016
3017 static u32 bnx2x_get_private_flags(struct net_device *dev)
3018 {
3019         struct bnx2x *bp = netdev_priv(dev);
3020         u32 flags = 0;
3021
3022         flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3023         flags |= (!(bp->flags & NO_FCOE_FLAG)  ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3024         flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3025
3026         return flags;
3027 }
3028
3029 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3030 {
3031         struct bnx2x *bp = netdev_priv(dev);
3032         int i, j, k, start;
3033         char queue_name[MAX_QUEUE_NAME_LEN+1];
3034
3035         switch (stringset) {
3036         case ETH_SS_STATS:
3037                 k = 0;
3038                 if (is_multi(bp)) {
3039                         for_each_eth_queue(bp, i) {
3040                                 memset(queue_name, 0, sizeof(queue_name));
3041                                 sprintf(queue_name, "%d", i);
3042                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3043                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3044                                                 ETH_GSTRING_LEN,
3045                                                 bnx2x_q_stats_arr[j].string,
3046                                                 queue_name);
3047                                 k += BNX2X_NUM_Q_STATS;
3048                         }
3049                 }
3050
3051                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3052                         if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3053                                 continue;
3054                         strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3055                                    bnx2x_stats_arr[i].string);
3056                         j++;
3057                 }
3058
3059                 break;
3060
3061         case ETH_SS_TEST:
3062                 /* First 4 tests cannot be done in MF mode */
3063                 if (!IS_MF(bp))
3064                         start = 0;
3065                 else
3066                         start = 4;
3067                 memcpy(buf, bnx2x_tests_str_arr + start,
3068                        ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3069                 break;
3070
3071         case ETH_SS_PRIV_FLAGS:
3072                 memcpy(buf, bnx2x_private_arr,
3073                        ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3074                 break;
3075         }
3076 }
3077
3078 static void bnx2x_get_ethtool_stats(struct net_device *dev,
3079                                     struct ethtool_stats *stats, u64 *buf)
3080 {
3081         struct bnx2x *bp = netdev_priv(dev);
3082         u32 *hw_stats, *offset;
3083         int i, j, k = 0;
3084
3085         if (is_multi(bp)) {
3086                 for_each_eth_queue(bp, i) {
3087                         hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3088                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3089                                 if (bnx2x_q_stats_arr[j].size == 0) {
3090                                         /* skip this counter */
3091                                         buf[k + j] = 0;
3092                                         continue;
3093                                 }
3094                                 offset = (hw_stats +
3095                                           bnx2x_q_stats_arr[j].offset);
3096                                 if (bnx2x_q_stats_arr[j].size == 4) {
3097                                         /* 4-byte counter */
3098                                         buf[k + j] = (u64) *offset;
3099                                         continue;
3100                                 }
3101                                 /* 8-byte counter */
3102                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3103                         }
3104                         k += BNX2X_NUM_Q_STATS;
3105                 }
3106         }
3107
3108         hw_stats = (u32 *)&bp->eth_stats;
3109         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3110                 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3111                         continue;
3112                 if (bnx2x_stats_arr[i].size == 0) {
3113                         /* skip this counter */
3114                         buf[k + j] = 0;
3115                         j++;
3116                         continue;
3117                 }
3118                 offset = (hw_stats + bnx2x_stats_arr[i].offset);
3119                 if (bnx2x_stats_arr[i].size == 4) {
3120                         /* 4-byte counter */
3121                         buf[k + j] = (u64) *offset;
3122                         j++;
3123                         continue;
3124                 }
3125                 /* 8-byte counter */
3126                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3127                 j++;
3128         }
3129 }
3130
3131 static int bnx2x_set_phys_id(struct net_device *dev,
3132                              enum ethtool_phys_id_state state)
3133 {
3134         struct bnx2x *bp = netdev_priv(dev);
3135
3136         if (!bnx2x_is_nvm_accessible(bp)) {
3137                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3138                    "cannot access eeprom when the interface is down\n");
3139                 return -EAGAIN;
3140         }
3141
3142         switch (state) {
3143         case ETHTOOL_ID_ACTIVE:
3144                 return 1;       /* cycle on/off once per second */
3145
3146         case ETHTOOL_ID_ON:
3147                 bnx2x_acquire_phy_lock(bp);
3148                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3149                               LED_MODE_ON, SPEED_1000);
3150                 bnx2x_release_phy_lock(bp);
3151                 break;
3152
3153         case ETHTOOL_ID_OFF:
3154                 bnx2x_acquire_phy_lock(bp);
3155                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3156                               LED_MODE_FRONT_PANEL_OFF, 0);
3157                 bnx2x_release_phy_lock(bp);
3158                 break;
3159
3160         case ETHTOOL_ID_INACTIVE:
3161                 bnx2x_acquire_phy_lock(bp);
3162                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3163                               LED_MODE_OPER,
3164                               bp->link_vars.line_speed);
3165                 bnx2x_release_phy_lock(bp);
3166         }
3167
3168         return 0;
3169 }
3170
3171 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3172 {
3173         switch (info->flow_type) {
3174         case TCP_V4_FLOW:
3175         case TCP_V6_FLOW:
3176                 info->data = RXH_IP_SRC | RXH_IP_DST |
3177                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3178                 break;
3179         case UDP_V4_FLOW:
3180                 if (bp->rss_conf_obj.udp_rss_v4)
3181                         info->data = RXH_IP_SRC | RXH_IP_DST |
3182                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
3183                 else
3184                         info->data = RXH_IP_SRC | RXH_IP_DST;
3185                 break;
3186         case UDP_V6_FLOW:
3187                 if (bp->rss_conf_obj.udp_rss_v6)
3188                         info->data = RXH_IP_SRC | RXH_IP_DST |
3189                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
3190                 else
3191                         info->data = RXH_IP_SRC | RXH_IP_DST;
3192                 break;
3193         case IPV4_FLOW:
3194         case IPV6_FLOW:
3195                 info->data = RXH_IP_SRC | RXH_IP_DST;
3196                 break;
3197         default:
3198                 info->data = 0;
3199                 break;
3200         }
3201
3202         return 0;
3203 }
3204
3205 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3206                            u32 *rules __always_unused)
3207 {
3208         struct bnx2x *bp = netdev_priv(dev);
3209
3210         switch (info->cmd) {
3211         case ETHTOOL_GRXRINGS:
3212                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3213                 return 0;
3214         case ETHTOOL_GRXFH:
3215                 return bnx2x_get_rss_flags(bp, info);
3216         default:
3217                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3218                 return -EOPNOTSUPP;
3219         }
3220 }
3221
3222 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3223 {
3224         int udp_rss_requested;
3225
3226         DP(BNX2X_MSG_ETHTOOL,
3227            "Set rss flags command parameters: flow type = %d, data = %llu\n",
3228            info->flow_type, info->data);
3229
3230         switch (info->flow_type) {
3231         case TCP_V4_FLOW:
3232         case TCP_V6_FLOW:
3233                 /* For TCP only 4-tupple hash is supported */
3234                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3235                                   RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3236                         DP(BNX2X_MSG_ETHTOOL,
3237                            "Command parameters not supported\n");
3238                         return -EINVAL;
3239                 }
3240                 return 0;
3241
3242         case UDP_V4_FLOW:
3243         case UDP_V6_FLOW:
3244                 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3245                 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3246                                    RXH_L4_B_0_1 | RXH_L4_B_2_3))
3247                         udp_rss_requested = 1;
3248                 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3249                         udp_rss_requested = 0;
3250                 else
3251                         return -EINVAL;
3252                 if ((info->flow_type == UDP_V4_FLOW) &&
3253                     (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3254                         bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3255                         DP(BNX2X_MSG_ETHTOOL,
3256                            "rss re-configured, UDP 4-tupple %s\n",
3257                            udp_rss_requested ? "enabled" : "disabled");
3258                         return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3259                 } else if ((info->flow_type == UDP_V6_FLOW) &&
3260                            (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3261                         bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3262                         DP(BNX2X_MSG_ETHTOOL,
3263                            "rss re-configured, UDP 4-tupple %s\n",
3264                            udp_rss_requested ? "enabled" : "disabled");
3265                         return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3266                 }
3267                 return 0;
3268
3269         case IPV4_FLOW:
3270         case IPV6_FLOW:
3271                 /* For IP only 2-tupple hash is supported */
3272                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3273                         DP(BNX2X_MSG_ETHTOOL,
3274                            "Command parameters not supported\n");
3275                         return -EINVAL;
3276                 }
3277                 return 0;
3278
3279         case SCTP_V4_FLOW:
3280         case AH_ESP_V4_FLOW:
3281         case AH_V4_FLOW:
3282         case ESP_V4_FLOW:
3283         case SCTP_V6_FLOW:
3284         case AH_ESP_V6_FLOW:
3285         case AH_V6_FLOW:
3286         case ESP_V6_FLOW:
3287         case IP_USER_FLOW:
3288         case ETHER_FLOW:
3289                 /* RSS is not supported for these protocols */
3290                 if (info->data) {
3291                         DP(BNX2X_MSG_ETHTOOL,
3292                            "Command parameters not supported\n");
3293                         return -EINVAL;
3294                 }
3295                 return 0;
3296
3297         default:
3298                 return -EINVAL;
3299         }
3300 }
3301
3302 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3303 {
3304         struct bnx2x *bp = netdev_priv(dev);
3305
3306         switch (info->cmd) {
3307         case ETHTOOL_SRXFH:
3308                 return bnx2x_set_rss_flags(bp, info);
3309         default:
3310                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3311                 return -EOPNOTSUPP;
3312         }
3313 }
3314
3315 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3316 {
3317         return T_ETH_INDIRECTION_TABLE_SIZE;
3318 }
3319
3320 static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key)
3321 {
3322         struct bnx2x *bp = netdev_priv(dev);
3323         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3324         size_t i;
3325
3326         /* Get the current configuration of the RSS indirection table */
3327         bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3328
3329         /*
3330          * We can't use a memcpy() as an internal storage of an
3331          * indirection table is a u8 array while indir->ring_index
3332          * points to an array of u32.
3333          *
3334          * Indirection table contains the FW Client IDs, so we need to
3335          * align the returned table to the Client ID of the leading RSS
3336          * queue.
3337          */
3338         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3339                 indir[i] = ind_table[i] - bp->fp->cl_id;
3340
3341         return 0;
3342 }
3343
3344 static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
3345                           const u8 *key)
3346 {
3347         struct bnx2x *bp = netdev_priv(dev);
3348         size_t i;
3349
3350         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3351                 /*
3352                  * The same as in bnx2x_get_rxfh: we can't use a memcpy()
3353                  * as an internal storage of an indirection table is a u8 array
3354                  * while indir->ring_index points to an array of u32.
3355                  *
3356                  * Indirection table contains the FW Client IDs, so we need to
3357                  * align the received table to the Client ID of the leading RSS
3358                  * queue
3359                  */
3360                 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3361         }
3362
3363         return bnx2x_config_rss_eth(bp, false);
3364 }
3365
3366 /**
3367  * bnx2x_get_channels - gets the number of RSS queues.
3368  *
3369  * @dev:                net device
3370  * @channels:           returns the number of max / current queues
3371  */
3372 static void bnx2x_get_channels(struct net_device *dev,
3373                                struct ethtool_channels *channels)
3374 {
3375         struct bnx2x *bp = netdev_priv(dev);
3376
3377         channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3378         channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3379 }
3380
3381 /**
3382  * bnx2x_change_num_queues - change the number of RSS queues.
3383  *
3384  * @bp:                 bnx2x private structure
3385  *
3386  * Re-configure interrupt mode to get the new number of MSI-X
3387  * vectors and re-add NAPI objects.
3388  */
3389 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3390 {
3391         bnx2x_disable_msi(bp);
3392         bp->num_ethernet_queues = num_rss;
3393         bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3394         BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3395         bnx2x_set_int_mode(bp);
3396 }
3397
3398 /**
3399  * bnx2x_set_channels - sets the number of RSS queues.
3400  *
3401  * @dev:                net device
3402  * @channels:           includes the number of queues requested
3403  */
3404 static int bnx2x_set_channels(struct net_device *dev,
3405                               struct ethtool_channels *channels)
3406 {
3407         struct bnx2x *bp = netdev_priv(dev);
3408
3409         DP(BNX2X_MSG_ETHTOOL,
3410            "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3411            channels->rx_count, channels->tx_count, channels->other_count,
3412            channels->combined_count);
3413
3414         /* We don't support separate rx / tx channels.
3415          * We don't allow setting 'other' channels.
3416          */
3417         if (channels->rx_count || channels->tx_count || channels->other_count
3418             || (channels->combined_count == 0) ||
3419             (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3420                 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3421                 return -EINVAL;
3422         }
3423
3424         /* Check if there was a change in the active parameters */
3425         if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3426                 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3427                 return 0;
3428         }
3429
3430         /* Set the requested number of queues in bp context.
3431          * Note that the actual number of queues created during load may be
3432          * less than requested if memory is low.
3433          */
3434         if (unlikely(!netif_running(dev))) {
3435                 bnx2x_change_num_queues(bp, channels->combined_count);
3436                 return 0;
3437         }
3438         bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3439         bnx2x_change_num_queues(bp, channels->combined_count);
3440         return bnx2x_nic_load(bp, LOAD_NORMAL);
3441 }
3442
3443 static const struct ethtool_ops bnx2x_ethtool_ops = {
3444         .get_settings           = bnx2x_get_settings,
3445         .set_settings           = bnx2x_set_settings,
3446         .get_drvinfo            = bnx2x_get_drvinfo,
3447         .get_regs_len           = bnx2x_get_regs_len,
3448         .get_regs               = bnx2x_get_regs,
3449         .get_dump_flag          = bnx2x_get_dump_flag,
3450         .get_dump_data          = bnx2x_get_dump_data,
3451         .set_dump               = bnx2x_set_dump,
3452         .get_wol                = bnx2x_get_wol,
3453         .set_wol                = bnx2x_set_wol,
3454         .get_msglevel           = bnx2x_get_msglevel,
3455         .set_msglevel           = bnx2x_set_msglevel,
3456         .nway_reset             = bnx2x_nway_reset,
3457         .get_link               = bnx2x_get_link,
3458         .get_eeprom_len         = bnx2x_get_eeprom_len,
3459         .get_eeprom             = bnx2x_get_eeprom,
3460         .set_eeprom             = bnx2x_set_eeprom,
3461         .get_coalesce           = bnx2x_get_coalesce,
3462         .set_coalesce           = bnx2x_set_coalesce,
3463         .get_ringparam          = bnx2x_get_ringparam,
3464         .set_ringparam          = bnx2x_set_ringparam,
3465         .get_pauseparam         = bnx2x_get_pauseparam,
3466         .set_pauseparam         = bnx2x_set_pauseparam,
3467         .self_test              = bnx2x_self_test,
3468         .get_sset_count         = bnx2x_get_sset_count,
3469         .get_priv_flags         = bnx2x_get_private_flags,
3470         .get_strings            = bnx2x_get_strings,
3471         .set_phys_id            = bnx2x_set_phys_id,
3472         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
3473         .get_rxnfc              = bnx2x_get_rxnfc,
3474         .set_rxnfc              = bnx2x_set_rxnfc,
3475         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
3476         .get_rxfh               = bnx2x_get_rxfh,
3477         .set_rxfh               = bnx2x_set_rxfh,
3478         .get_channels           = bnx2x_get_channels,
3479         .set_channels           = bnx2x_set_channels,
3480         .get_module_info        = bnx2x_get_module_info,
3481         .get_module_eeprom      = bnx2x_get_module_eeprom,
3482         .get_eee                = bnx2x_get_eee,
3483         .set_eee                = bnx2x_set_eee,
3484         .get_ts_info            = ethtool_op_get_ts_info,
3485 };
3486
3487 static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3488         .get_settings           = bnx2x_get_settings,
3489         .set_settings           = bnx2x_set_settings,
3490         .get_drvinfo            = bnx2x_get_drvinfo,
3491         .get_msglevel           = bnx2x_get_msglevel,
3492         .set_msglevel           = bnx2x_set_msglevel,
3493         .get_link               = bnx2x_get_link,
3494         .get_coalesce           = bnx2x_get_coalesce,
3495         .get_ringparam          = bnx2x_get_ringparam,
3496         .set_ringparam          = bnx2x_set_ringparam,
3497         .get_sset_count         = bnx2x_get_sset_count,
3498         .get_strings            = bnx2x_get_strings,
3499         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
3500         .get_rxnfc              = bnx2x_get_rxnfc,
3501         .set_rxnfc              = bnx2x_set_rxnfc,
3502         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
3503         .get_rxfh               = bnx2x_get_rxfh,
3504         .set_rxfh               = bnx2x_set_rxfh,
3505         .get_channels           = bnx2x_get_channels,
3506         .set_channels           = bnx2x_set_channels,
3507 };
3508
3509 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3510 {
3511         netdev->ethtool_ops = (IS_PF(bp)) ?
3512                 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;
3513 }