drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c

   1 /*
   2  * aQuantia Corporation Network Driver
   3  * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  */
   9
  10 /* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */
  11
  12 #include "../aq_hw.h"
  13 #include "../aq_hw_utils.h"
  14 #include "../aq_ring.h"
  15 #include "../aq_nic.h"
  16 #include "hw_atl_b0.h"
  17 #include "hw_atl_utils.h"
  18 #include "hw_atl_llh.h"
  19 #include "hw_atl_b0_internal.h"
  20 #include "hw_atl_llh_internal.h"
  21
  22 #define DEFAULT_B0_BOARD_BASIC_CAPABILITIES \
  23         .is_64_dma = true,                \
  24         .msix_irqs = 4U,                  \
  25         .irq_mask = ~0U,                  \
  26         .vecs = HW_ATL_B0_RSS_MAX,        \
  27         .tcs = HW_ATL_B0_TC_MAX,          \
  28         .rxd_alignment = 1U,              \
  29         .rxd_size = HW_ATL_B0_RXD_SIZE,   \
  30         .rxds_max = HW_ATL_B0_MAX_RXD,    \
  31         .rxds_min = HW_ATL_B0_MIN_RXD,    \
  32         .txd_alignment = 1U,              \
  33         .txd_size = HW_ATL_B0_TXD_SIZE,   \
  34         .txds_max = HW_ATL_B0_MAX_TXD,    \
  35         .txds_min = HW_ATL_B0_MIN_TXD,    \
  36         .txhwb_alignment = 4096U,         \
  37         .tx_rings = HW_ATL_B0_TX_RINGS,   \
  38         .rx_rings = HW_ATL_B0_RX_RINGS,   \
  39         .hw_features = NETIF_F_HW_CSUM |  \
  40                         NETIF_F_RXCSUM |  \
  41                         NETIF_F_RXHASH |  \
  42                         NETIF_F_SG |      \
  43                         NETIF_F_TSO |     \
  44                         NETIF_F_LRO,      \
  45         .hw_priv_flags = IFF_UNICAST_FLT, \
  46         .flow_control = true,             \
  47         .mtu = HW_ATL_B0_MTU_JUMBO,       \
  48         .mac_regs_count = 88,             \
  49         .hw_alive_check_addr = 0x10U
  50
  51 const struct aq_hw_caps_s hw_atl_b0_caps_aqc100 = {
  52         DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
  53         .media_type = AQ_HW_MEDIA_TYPE_FIBRE,
  54         .link_speed_msk = AQ_NIC_RATE_10G |
  55                           AQ_NIC_RATE_5G |
  56                           AQ_NIC_RATE_2GS |
  57                           AQ_NIC_RATE_1G |
  58                           AQ_NIC_RATE_100M,
  59 };
  60
  61 const struct aq_hw_caps_s hw_atl_b0_caps_aqc107 = {
  62         DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
  63         .media_type = AQ_HW_MEDIA_TYPE_TP,
  64         .link_speed_msk = AQ_NIC_RATE_10G |
  65                           AQ_NIC_RATE_5G |
  66                           AQ_NIC_RATE_2GS |
  67                           AQ_NIC_RATE_1G |
  68                           AQ_NIC_RATE_100M,
  69 };
  70
  71 const struct aq_hw_caps_s hw_atl_b0_caps_aqc108 = {
  72         DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
  73         .media_type = AQ_HW_MEDIA_TYPE_TP,
  74         .link_speed_msk = AQ_NIC_RATE_5G |
  75                           AQ_NIC_RATE_2GS |
  76                           AQ_NIC_RATE_1G |
  77                           AQ_NIC_RATE_100M,
  78 };
  79
  80 const struct aq_hw_caps_s hw_atl_b0_caps_aqc109 = {
  81         DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
  82         .media_type = AQ_HW_MEDIA_TYPE_TP,
  83         .link_speed_msk = AQ_NIC_RATE_2GS |
  84                           AQ_NIC_RATE_1G |
  85                           AQ_NIC_RATE_100M,
  86 };
  87
  88 static int hw_atl_b0_hw_reset(struct aq_hw_s *self)
  89 {
  90         int err = 0;
  91
  92         err = hw_atl_utils_soft_reset(self);
  93         if (err)
  94                 return err;
  95
  96         self->aq_fw_ops->set_state(self, MPI_RESET);
  97
  98         err = aq_hw_err_from_flags(self);
  99
 100         return err;
 101 }
 102
 103 static int hw_atl_b0_set_fc(struct aq_hw_s *self, u32 fc, u32 tc)
 104 {
 105         hw_atl_rpb_rx_xoff_en_per_tc_set(self, !!(fc & AQ_NIC_FC_RX), tc);
 106         return 0;
 107 }
 108
 109 static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
 110 {
 111         u32 tc = 0U;
 112         u32 buff_size = 0U;
 113         unsigned int i_priority = 0U;
 114
 115         /* TPS Descriptor rate init */
 116         hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
 117         hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
 118
 119         /* TPS VM init */
 120         hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
 121
 122         /* TPS TC credits init */
 123         hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
 124         hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
 125
 126         hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
 127         hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
 128         hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
 129         hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
 130
 131         /* Tx buf size */
 132         buff_size = HW_ATL_B0_TXBUF_MAX;
 133
 134         hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
 135         hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self,
 136                                                    (buff_size *
 137                                                    (1024 / 32U) * 66U) /
 138                                                    100U, tc);
 139         hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self,
 140                                                    (buff_size *
 141                                                    (1024 / 32U) * 50U) /
 142                                                    100U, tc);
 143
 144         /* QoS Rx buf size per TC */
 145         tc = 0;
 146         buff_size = HW_ATL_B0_RXBUF_MAX;
 147
 148         hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
 149         hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self,
 150                                                    (buff_size *
 151                                                    (1024U / 32U) * 66U) /
 152                                                    100U, tc);
 153         hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self,
 154                                                    (buff_size *
 155                                                    (1024U / 32U) * 50U) /
 156                                                    100U, tc);
 157
 158         hw_atl_b0_set_fc(self, self->aq_nic_cfg->flow_control, tc);
 159
 160         /* QoS 802.1p priority -> TC mapping */
 161         for (i_priority = 8U; i_priority--;)
 162                 hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
 163
 164         return aq_hw_err_from_flags(self);
 165 }
 166
 167 static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
 168                                      struct aq_rss_parameters *rss_params)
 169 {
 170         struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
 171         int err = 0;
 172         unsigned int i = 0U;
 173         unsigned int addr = 0U;
 174
 175         for (i = 10, addr = 0U; i--; ++addr) {
 176                 u32 key_data = cfg->is_rss ?
 177                         __swab32(rss_params->hash_secret_key[i]) : 0U;
 178                 hw_atl_rpf_rss_key_wr_data_set(self, key_data);
 179                 hw_atl_rpf_rss_key_addr_set(self, addr);
 180                 hw_atl_rpf_rss_key_wr_en_set(self, 1U);
 181                 AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,
 182                                1000U, 10U);
 183                 if (err < 0)
 184                         goto err_exit;
 185         }
 186
 187         err = aq_hw_err_from_flags(self);
 188
 189 err_exit:
 190         return err;
 191 }
 192
 193 static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,
 194                                 struct aq_rss_parameters *rss_params)
 195 {
 196         u8 *indirection_table = rss_params->indirection_table;
 197         u32 i = 0U;
 198         u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
 199         int err = 0;
 200         u16 bitary[(HW_ATL_B0_RSS_REDIRECTION_MAX *
 201                                         HW_ATL_B0_RSS_REDIRECTION_BITS / 16U)];
 202
 203         memset(bitary, 0, sizeof(bitary));
 204
 205         for (i = HW_ATL_B0_RSS_REDIRECTION_MAX; i--;) {
 206                 (*(u32 *)(bitary + ((i * 3U) / 16U))) |=
 207                         ((indirection_table[i] % num_rss_queues) <<
 208                         ((i * 3U) & 0xFU));
 209         }
 210
 211         for (i = ARRAY_SIZE(bitary); i--;) {
 212                 hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
 213                 hw_atl_rpf_rss_redir_tbl_addr_set(self, i);
 214                 hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
 215                 AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,
 216                                1000U, 10U);
 217                 if (err < 0)
 218                         goto err_exit;
 219         }
 220
 221         err = aq_hw_err_from_flags(self);
 222
 223 err_exit:
 224         return err;
 225 }
 226
 227 static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self,
 228                                     struct aq_nic_cfg_s *aq_nic_cfg)
 229 {
 230         unsigned int i;
 231
 232         /* TX checksums offloads*/
 233         hw_atl_tpo_ipv4header_crc_offload_en_set(self, 1);
 234         hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1);
 235
 236         /* RX checksums offloads*/
 237         hw_atl_rpo_ipv4header_crc_offload_en_set(self, !!(aq_nic_cfg->features &
 238                                                  NETIF_F_RXCSUM));
 239         hw_atl_rpo_tcp_udp_crc_offload_en_set(self, !!(aq_nic_cfg->features &
 240                                               NETIF_F_RXCSUM));
 241
 242         /* LSO offloads*/
 243         hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
 244
 245 /* LRO offloads */
 246         {
 247                 unsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U :
 248                         ((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U :
 249                         ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0));
 250
 251                 for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++)
 252                         hw_atl_rpo_lro_max_num_of_descriptors_set(self, val, i);
 253
 254                 hw_atl_rpo_lro_time_base_divider_set(self, 0x61AU);
 255                 hw_atl_rpo_lro_inactive_interval_set(self, 0);
 256                 hw_atl_rpo_lro_max_coalescing_interval_set(self, 2);
 257
 258                 hw_atl_rpo_lro_qsessions_lim_set(self, 1U);
 259
 260                 hw_atl_rpo_lro_total_desc_lim_set(self, 2U);
 261
 262                 hw_atl_rpo_lro_patch_optimization_en_set(self, 0U);
 263
 264                 hw_atl_rpo_lro_min_pay_of_first_pkt_set(self, 10U);
 265
 266                 hw_atl_rpo_lro_pkt_lim_set(self, 1U);
 267
 268                 hw_atl_rpo_lro_en_set(self,
 269                                       aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U);
 270         }
 271         return aq_hw_err_from_flags(self);
 272 }
 273
 274 static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self)
 275 {
 276         hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
 277         hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
 278         hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
 279
 280         /* Tx interrupts */
 281         hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
 282
 283         /* misc */
 284         aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
 285                         0x00010000U : 0x00000000U);
 286         hw_atl_tdm_tx_dca_en_set(self, 0U);
 287         hw_atl_tdm_tx_dca_mode_set(self, 0U);
 288
 289         hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U);
 290
 291         return aq_hw_err_from_flags(self);
 292 }
 293
 294 static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self)
 295 {
 296         struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
 297         int i;
 298
 299         /* Rx TC/RSS number config */
 300         hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U);
 301
 302         /* Rx flow control */
 303         hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);
 304
 305         /* RSS Ring selection */
 306         hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?
 307                                         0xB3333333U : 0x00000000U);
 308
 309         /* Multicast filters */
 310         for (i = HW_ATL_B0_MAC_MAX; i--;) {
 311                 hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
 312                 hw_atl_rpfl2unicast_flr_act_set(self, 1U, i);
 313         }
 314
 315         hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
 316         hw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
 317
 318         /* Vlan filters */
 319         hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U);
 320         hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U);
 321
 322         if (cfg->vlan_id) {
 323                 hw_atl_rpf_vlan_flr_act_set(self, 1U, 0U);
 324                 hw_atl_rpf_vlan_id_flr_set(self, 0U, 0U);
 325                 hw_atl_rpf_vlan_flr_en_set(self, 0U, 0U);
 326
 327                 hw_atl_rpf_vlan_accept_untagged_packets_set(self, 1U);
 328                 hw_atl_rpf_vlan_untagged_act_set(self, 1U);
 329
 330                 hw_atl_rpf_vlan_flr_act_set(self, 1U, 1U);
 331                 hw_atl_rpf_vlan_id_flr_set(self, cfg->vlan_id, 0U);
 332                 hw_atl_rpf_vlan_flr_en_set(self, 1U, 1U);
 333         } else {
 334                 hw_atl_rpf_vlan_prom_mode_en_set(self, 1);
 335         }
 336
 337         /* Rx Interrupts */
 338         hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
 339
 340         /* misc */
 341         aq_hw_write_reg(self, 0x00005040U,
 342                         IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U);
 343
 344         hw_atl_rpfl2broadcast_flr_act_set(self, 1U);
 345         hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
 346
 347         hw_atl_rdm_rx_dca_en_set(self, 0U);
 348         hw_atl_rdm_rx_dca_mode_set(self, 0U);
 349
 350         return aq_hw_err_from_flags(self);
 351 }
 352
 353 static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
 354 {
 355         int err = 0;
 356         unsigned int h = 0U;
 357         unsigned int l = 0U;
 358
 359         if (!mac_addr) {
 360                 err = -EINVAL;
 361                 goto err_exit;
 362         }
 363         h = (mac_addr[0] << 8) | (mac_addr[1]);
 364         l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
 365                 (mac_addr[4] << 8) | mac_addr[5];
 366
 367         hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC);
 368         hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC);
 369         hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC);
 370         hw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC);
 371
 372         err = aq_hw_err_from_flags(self);
 373
 374 err_exit:
 375         return err;
 376 }
 377
 378 static int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
 379 {
 380         static u32 aq_hw_atl_igcr_table_[4][2] = {
 381                 { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */
 382                 { 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */
 383                 { 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */
 384                 { 0x20000022U, 0x20000026U }  /* AQ_IRQ_MSIX */
 385         };
 386
 387         int err = 0;
 388         u32 val;
 389
 390         struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg;
 391
 392         hw_atl_b0_hw_init_tx_path(self);
 393         hw_atl_b0_hw_init_rx_path(self);
 394
 395         hw_atl_b0_hw_mac_addr_set(self, mac_addr);
 396
 397         self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk);
 398         self->aq_fw_ops->set_state(self, MPI_INIT);
 399
 400         hw_atl_b0_hw_qos_set(self);
 401         hw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
 402         hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
 403
 404         /* Force limit MRRS on RDM/TDM to 2K */
 405         val = aq_hw_read_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR);
 406         aq_hw_write_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR,
 407                         (val & ~0x707) | 0x404);
 408
 409         /* TX DMA total request limit. B0 hardware is not capable to
 410          * handle more than (8K-MRRS) incoming DMA data.
 411          * Value 24 in 256byte units
 412          */
 413         aq_hw_write_reg(self, HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR, 24);
 414
 415         /* Reset link status and read out initial hardware counters */
 416         self->aq_link_status.mbps = 0;
 417         self->aq_fw_ops->update_stats(self);
 418
 419         err = aq_hw_err_from_flags(self);
 420         if (err < 0)
 421                 goto err_exit;
 422
 423         /* Interrupts */
 424         hw_atl_reg_irq_glb_ctl_set(self,
 425                                    aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
 426                                                  [(aq_nic_cfg->vecs > 1U) ?
 427                                                  1 : 0]);
 428
 429         hw_atl_itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
 430
 431         /* Interrupts */
 432         hw_atl_reg_gen_irq_map_set(self,
 433                                    ((HW_ATL_B0_ERR_INT << 0x18) | (1U << 0x1F)) |
 434                             ((HW_ATL_B0_ERR_INT << 0x10) | (1U << 0x17)), 0U);
 435
 436         hw_atl_b0_hw_offload_set(self, aq_nic_cfg);
 437
 438 err_exit:
 439         return err;
 440 }
 441
 442 static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self,
 443                                       struct aq_ring_s *ring)
 444 {
 445         hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx);
 446         return aq_hw_err_from_flags(self);
 447 }
 448
 449 static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self,
 450                                       struct aq_ring_s *ring)
 451 {
 452         hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx);
 453         return aq_hw_err_from_flags(self);
 454 }
 455
 456 static int hw_atl_b0_hw_start(struct aq_hw_s *self)
 457 {
 458         hw_atl_tpb_tx_buff_en_set(self, 1);
 459         hw_atl_rpb_rx_buff_en_set(self, 1);
 460         return aq_hw_err_from_flags(self);
 461 }
 462
 463 static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self,
 464                                             struct aq_ring_s *ring)
 465 {
 466         hw_atl_reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
 467         return 0;
 468 }
 469
 470 static int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self,
 471                                      struct aq_ring_s *ring,
 472                                      unsigned int frags)
 473 {
 474         struct aq_ring_buff_s *buff = NULL;
 475         struct hw_atl_txd_s *txd = NULL;
 476         unsigned int buff_pa_len = 0U;
 477         unsigned int pkt_len = 0U;
 478         unsigned int frag_count = 0U;
 479         bool is_gso = false;
 480
 481         buff = &ring->buff_ring[ring->sw_tail];
 482         pkt_len = (buff->is_eop && buff->is_sop) ? buff->len : buff->len_pkt;
 483
 484         for (frag_count = 0; frag_count < frags; frag_count++) {
 485                 txd = (struct hw_atl_txd_s *)&ring->dx_ring[ring->sw_tail *
 486                                                 HW_ATL_B0_TXD_SIZE];
 487                 txd->ctl = 0;
 488                 txd->ctl2 = 0;
 489                 txd->buf_addr = 0;
 490
 491                 buff = &ring->buff_ring[ring->sw_tail];
 492
 493                 if (buff->is_txc) {
 494                         txd->ctl |= (buff->len_l3 << 31) |
 495                                 (buff->len_l2 << 24) |
 496                                 HW_ATL_B0_TXD_CTL_CMD_TCP |
 497                                 HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC;
 498                         txd->ctl2 |= (buff->mss << 16) |
 499                                 (buff->len_l4 << 8) |
 500                                 (buff->len_l3 >> 1);
 501
 502                         pkt_len -= (buff->len_l4 +
 503                                     buff->len_l3 +
 504                                     buff->len_l2);
 505                         is_gso = true;
 506
 507                         if (buff->is_ipv6)
 508                                 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPV6;
 509                 } else {
 510                         buff_pa_len = buff->len;
 511
 512                         txd->buf_addr = buff->pa;
 513                         txd->ctl |= (HW_ATL_B0_TXD_CTL_BLEN &
 514                                                 ((u32)buff_pa_len << 4));
 515                         txd->ctl |= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD;
 516                         /* PAY_LEN */
 517                         txd->ctl2 |= HW_ATL_B0_TXD_CTL2_LEN & (pkt_len << 14);
 518
 519                         if (is_gso) {
 520                                 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_LSO;
 521                                 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_CTX_EN;
 522                         }
 523
 524                         /* Tx checksum offloads */
 525                         if (buff->is_ip_cso)
 526                                 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPCSO;
 527
 528                         if (buff->is_udp_cso || buff->is_tcp_cso)
 529                                 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_TUCSO;
 530
 531                         if (unlikely(buff->is_eop)) {
 532                                 txd->ctl |= HW_ATL_B0_TXD_CTL_EOP;
 533                                 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_WB;
 534                                 is_gso = false;
 535                         }
 536                 }
 537
 538                 ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail);
 539         }
 540
 541         hw_atl_b0_hw_tx_ring_tail_update(self, ring);
 542         return aq_hw_err_from_flags(self);
 543 }
 544
 545 static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self,
 546                                      struct aq_ring_s *aq_ring,
 547                                      struct aq_ring_param_s *aq_ring_param)
 548 {
 549         u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
 550         u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
 551
 552         hw_atl_rdm_rx_desc_en_set(self, false, aq_ring->idx);
 553
 554         hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
 555
 556         hw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
 557                                                   aq_ring->idx);
 558
 559         hw_atl_reg_rx_dma_desc_base_addressmswset(self,
 560                                                   dma_desc_addr_msw, aq_ring->idx);
 561
 562         hw_atl_rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
 563
 564         hw_atl_rdm_rx_desc_data_buff_size_set(self,
 565                                               AQ_CFG_RX_FRAME_MAX / 1024U,
 566                                        aq_ring->idx);
 567
 568         hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
 569         hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
 570         hw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
 571
 572         /* Rx ring set mode */
 573
 574         /* Mapping interrupt vector */
 575         hw_atl_itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
 576         hw_atl_itr_irq_map_en_rx_set(self, true, aq_ring->idx);
 577
 578         hw_atl_rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
 579         hw_atl_rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
 580         hw_atl_rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
 581         hw_atl_rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
 582
 583         return aq_hw_err_from_flags(self);
 584 }
 585
 586 static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self,
 587                                      struct aq_ring_s *aq_ring,
 588                                      struct aq_ring_param_s *aq_ring_param)
 589 {
 590         u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
 591         u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
 592
 593         hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
 594                                                   aq_ring->idx);
 595
 596         hw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
 597                                                   aq_ring->idx);
 598
 599         hw_atl_tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
 600
 601         hw_atl_b0_hw_tx_ring_tail_update(self, aq_ring);
 602
 603         /* Set Tx threshold */
 604         hw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
 605
 606         /* Mapping interrupt vector */
 607         hw_atl_itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
 608         hw_atl_itr_irq_map_en_tx_set(self, true, aq_ring->idx);
 609
 610         hw_atl_tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
 611         hw_atl_tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
 612
 613         return aq_hw_err_from_flags(self);
 614 }
 615
 616 static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self,
 617                                      struct aq_ring_s *ring,
 618                                      unsigned int sw_tail_old)
 619 {
 620         for (; sw_tail_old != ring->sw_tail;
 621                 sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) {
 622                 struct hw_atl_rxd_s *rxd =
 623                         (struct hw_atl_rxd_s *)&ring->dx_ring[sw_tail_old *
 624                                                         HW_ATL_B0_RXD_SIZE];
 625
 626                 struct aq_ring_buff_s *buff = &ring->buff_ring[sw_tail_old];
 627
 628                 rxd->buf_addr = buff->pa;
 629                 rxd->hdr_addr = 0U;
 630         }
 631
 632         hw_atl_reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
 633
 634         return aq_hw_err_from_flags(self);
 635 }
 636
 637 static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self,
 638                                             struct aq_ring_s *ring)
 639 {
 640         int err = 0;
 641         unsigned int hw_head_ = hw_atl_tdm_tx_desc_head_ptr_get(self, ring->idx);
 642
 643         if (aq_utils_obj_test(&self->flags, AQ_HW_FLAG_ERR_UNPLUG)) {
 644                 err = -ENXIO;
 645                 goto err_exit;
 646         }
 647         ring->hw_head = hw_head_;
 648         err = aq_hw_err_from_flags(self);
 649
 650 err_exit:
 651         return err;
 652 }
 653
 654 static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self,
 655                                         struct aq_ring_s *ring)
 656 {
 657         struct device *ndev = aq_nic_get_dev(ring->aq_nic);
 658
 659         for (; ring->hw_head != ring->sw_tail;
 660                 ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) {
 661                 struct aq_ring_buff_s *buff = NULL;
 662                 struct hw_atl_rxd_wb_s *rxd_wb = (struct hw_atl_rxd_wb_s *)
 663                         &ring->dx_ring[ring->hw_head * HW_ATL_B0_RXD_SIZE];
 664
 665                 unsigned int is_rx_check_sum_enabled = 0U;
 666                 unsigned int pkt_type = 0U;
 667                 u8 rx_stat = 0U;
 668
 669                 if (!(rxd_wb->status & 0x1U)) { /* RxD is not done */
 670                         break;
 671                 }
 672
 673                 buff = &ring->buff_ring[ring->hw_head];
 674
 675                 rx_stat = (0x0000003CU & rxd_wb->status) >> 2;
 676
 677                 is_rx_check_sum_enabled = (rxd_wb->type) & (0x3U << 19);
 678
 679                 pkt_type = 0xFFU & (rxd_wb->type >> 4);
 680
 681                 if (is_rx_check_sum_enabled & BIT(0) &&
 682                     (0x0U == (pkt_type & 0x3U)))
 683                         buff->is_ip_cso = (rx_stat & BIT(1)) ? 0U : 1U;
 684
 685                 if (is_rx_check_sum_enabled & BIT(1)) {
 686                         if (0x4U == (pkt_type & 0x1CU))
 687                                 buff->is_udp_cso = (rx_stat & BIT(2)) ? 0U :
 688                                                    !!(rx_stat & BIT(3));
 689                         else if (0x0U == (pkt_type & 0x1CU))
 690                                 buff->is_tcp_cso = (rx_stat & BIT(2)) ? 0U :
 691                                                    !!(rx_stat & BIT(3));
 692                 }
 693                 buff->is_cso_err = !!(rx_stat & 0x6);
 694                 /* Checksum offload workaround for small packets */
 695                 if (unlikely(rxd_wb->pkt_len <= 60)) {
 696                         buff->is_ip_cso = 0U;
 697                         buff->is_cso_err = 0U;
 698                 }
 699
 700                 dma_unmap_page(ndev, buff->pa, buff->len, DMA_FROM_DEVICE);
 701
 702                 if ((rx_stat & BIT(0)) || rxd_wb->type & 0x1000U) {
 703                         /* MAC error or DMA error */
 704                         buff->is_error = 1U;
 705                 } else {
 706                         if (self->aq_nic_cfg->is_rss) {
 707                                 /* last 4 byte */
 708                                 u16 rss_type = rxd_wb->type & 0xFU;
 709
 710                                 if (rss_type && rss_type < 0x8U) {
 711                                         buff->is_hash_l4 = (rss_type == 0x4 ||
 712                                         rss_type == 0x5);
 713                                         buff->rss_hash = rxd_wb->rss_hash;
 714                                 }
 715                         }
 716
 717                         if (HW_ATL_B0_RXD_WB_STAT2_EOP & rxd_wb->status) {
 718                                 buff->len = rxd_wb->pkt_len %
 719                                         AQ_CFG_RX_FRAME_MAX;
 720                                 buff->len = buff->len ?
 721                                         buff->len : AQ_CFG_RX_FRAME_MAX;
 722                                 buff->next = 0U;
 723                                 buff->is_eop = 1U;
 724                         } else {
 725                                 if (HW_ATL_B0_RXD_WB_STAT2_RSCCNT &
 726                                         rxd_wb->status) {
 727                                         /* LRO */
 728                                         buff->next = rxd_wb->next_desc_ptr;
 729                                         ++ring->stats.rx.lro_packets;
 730                                 } else {
 731                                         /* jumbo */
 732                                         buff->next =
 733                                                 aq_ring_next_dx(ring,
 734                                                                 ring->hw_head);
 735                                         ++ring->stats.rx.jumbo_packets;
 736                                 }
 737                         }
 738                 }
 739         }
 740
 741         return aq_hw_err_from_flags(self);
 742 }
 743
 744 static int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
 745 {
 746         hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask));
 747         return aq_hw_err_from_flags(self);
 748 }
 749
 750 static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
 751 {
 752         hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask));
 753         hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask));
 754
 755         atomic_inc(&self->dpc);
 756         return aq_hw_err_from_flags(self);
 757 }
 758
 759 static int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
 760 {
 761         *mask = hw_atl_itr_irq_statuslsw_get(self);
 762         return aq_hw_err_from_flags(self);
 763 }
 764
 765 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
 766
 767 static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self,
 768                                           unsigned int packet_filter)
 769 {
 770         unsigned int i = 0U;
 771
 772         hw_atl_rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
 773         hw_atl_rpfl2multicast_flr_en_set(self,
 774                                          IS_FILTER_ENABLED(IFF_ALLMULTI), 0);
 775
 776         hw_atl_rpfl2_accept_all_mc_packets_set(self,
 777                                                IS_FILTER_ENABLED(IFF_ALLMULTI));
 778
 779         hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
 780
 781         self->aq_nic_cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST);
 782
 783         for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i)
 784                 hw_atl_rpfl2_uc_flr_en_set(self,
 785                                            (self->aq_nic_cfg->is_mc_list_enabled &&
 786                                     (i <= self->aq_nic_cfg->mc_list_count)) ?
 787                                     1U : 0U, i);
 788
 789         return aq_hw_err_from_flags(self);
 790 }
 791
 792 #undef IS_FILTER_ENABLED
 793
 794 static int hw_atl_b0_hw_multicast_list_set(struct aq_hw_s *self,
 795                                            u8 ar_mac
 796                                            [AQ_HW_MULTICAST_ADDRESS_MAX]
 797                                            [ETH_ALEN],
 798                                            u32 count)
 799 {
 800         int err = 0;
 801
 802         if (count > (HW_ATL_B0_MAC_MAX - HW_ATL_B0_MAC_MIN)) {
 803                 err = -EBADRQC;
 804                 goto err_exit;
 805         }
 806         for (self->aq_nic_cfg->mc_list_count = 0U;
 807                         self->aq_nic_cfg->mc_list_count < count;
 808                         ++self->aq_nic_cfg->mc_list_count) {
 809                 u32 i = self->aq_nic_cfg->mc_list_count;
 810                 u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]);
 811                 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
 812                                         (ar_mac[i][4] << 8) | ar_mac[i][5];
 813
 814                 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC_MIN + i);
 815
 816                 hw_atl_rpfl2unicast_dest_addresslsw_set(self,
 817                                                         l, HW_ATL_B0_MAC_MIN + i);
 818
 819                 hw_atl_rpfl2unicast_dest_addressmsw_set(self,
 820                                                         h, HW_ATL_B0_MAC_MIN + i);
 821
 822                 hw_atl_rpfl2_uc_flr_en_set(self,
 823                                            (self->aq_nic_cfg->is_mc_list_enabled),
 824                                            HW_ATL_B0_MAC_MIN + i);
 825         }
 826
 827         err = aq_hw_err_from_flags(self);
 828
 829 err_exit:
 830         return err;
 831 }
 832
 833 static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self)
 834 {
 835         unsigned int i = 0U;
 836         u32 itr_tx = 2U;
 837         u32 itr_rx = 2U;
 838
 839         switch (self->aq_nic_cfg->itr) {
 840         case  AQ_CFG_INTERRUPT_MODERATION_ON:
 841         case  AQ_CFG_INTERRUPT_MODERATION_AUTO:
 842                 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U);
 843                 hw_atl_tdm_tdm_intr_moder_en_set(self, 1U);
 844                 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U);
 845                 hw_atl_rdm_rdm_intr_moder_en_set(self, 1U);
 846
 847                 if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) {
 848                         /* HW timers are in 2us units */
 849                         int tx_max_timer = self->aq_nic_cfg->tx_itr / 2;
 850                         int tx_min_timer = tx_max_timer / 2;
 851
 852                         int rx_max_timer = self->aq_nic_cfg->rx_itr / 2;
 853                         int rx_min_timer = rx_max_timer / 2;
 854
 855                         tx_max_timer = min(HW_ATL_INTR_MODER_MAX, tx_max_timer);
 856                         tx_min_timer = min(HW_ATL_INTR_MODER_MIN, tx_min_timer);
 857                         rx_max_timer = min(HW_ATL_INTR_MODER_MAX, rx_max_timer);
 858                         rx_min_timer = min(HW_ATL_INTR_MODER_MIN, rx_min_timer);
 859
 860                         itr_tx |= tx_min_timer << 0x8U;
 861                         itr_tx |= tx_max_timer << 0x10U;
 862                         itr_rx |= rx_min_timer << 0x8U;
 863                         itr_rx |= rx_max_timer << 0x10U;
 864                 } else {
 865                         static unsigned int hw_atl_b0_timers_table_tx_[][2] = {
 866                                 {0xfU, 0xffU}, /* 10Gbit */
 867                                 {0xfU, 0x1ffU}, /* 5Gbit */
 868                                 {0xfU, 0x1ffU}, /* 5Gbit 5GS */
 869                                 {0xfU, 0x1ffU}, /* 2.5Gbit */
 870                                 {0xfU, 0x1ffU}, /* 1Gbit */
 871                                 {0xfU, 0x1ffU}, /* 100Mbit */
 872                         };
 873
 874                         static unsigned int hw_atl_b0_timers_table_rx_[][2] = {
 875                                 {0x6U, 0x38U},/* 10Gbit */
 876                                 {0xCU, 0x70U},/* 5Gbit */
 877                                 {0xCU, 0x70U},/* 5Gbit 5GS */
 878                                 {0x18U, 0xE0U},/* 2.5Gbit */
 879                                 {0x30U, 0x80U},/* 1Gbit */
 880                                 {0x4U, 0x50U},/* 100Mbit */
 881                         };
 882
 883                         unsigned int speed_index =
 884                                         hw_atl_utils_mbps_2_speed_index(
 885                                                 self->aq_link_status.mbps);
 886
 887                         /* Update user visible ITR settings */
 888                         self->aq_nic_cfg->tx_itr = hw_atl_b0_timers_table_tx_
 889                                                         [speed_index][1] * 2;
 890                         self->aq_nic_cfg->rx_itr = hw_atl_b0_timers_table_rx_
 891                                                         [speed_index][1] * 2;
 892
 893                         itr_tx |= hw_atl_b0_timers_table_tx_
 894                                                 [speed_index][0] << 0x8U;
 895                         itr_tx |= hw_atl_b0_timers_table_tx_
 896                                                 [speed_index][1] << 0x10U;
 897
 898                         itr_rx |= hw_atl_b0_timers_table_rx_
 899                                                 [speed_index][0] << 0x8U;
 900                         itr_rx |= hw_atl_b0_timers_table_rx_
 901                                                 [speed_index][1] << 0x10U;
 902                 }
 903                 break;
 904         case AQ_CFG_INTERRUPT_MODERATION_OFF:
 905                 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
 906                 hw_atl_tdm_tdm_intr_moder_en_set(self, 0U);
 907                 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
 908                 hw_atl_rdm_rdm_intr_moder_en_set(self, 0U);
 909                 itr_tx = 0U;
 910                 itr_rx = 0U;
 911                 break;
 912         }
 913
 914         for (i = HW_ATL_B0_RINGS_MAX; i--;) {
 915                 hw_atl_reg_tx_intr_moder_ctrl_set(self, itr_tx, i);
 916                 hw_atl_reg_rx_intr_moder_ctrl_set(self, itr_rx, i);
 917         }
 918
 919         return aq_hw_err_from_flags(self);
 920 }
 921
 922 static int hw_atl_b0_hw_stop(struct aq_hw_s *self)
 923 {
 924         hw_atl_b0_hw_irq_disable(self, HW_ATL_B0_INT_MASK);
 925
 926         /* Invalidate Descriptor Cache to prevent writing to the cached
 927          * descriptors and to the data pointer of those descriptors
 928          */
 929         hw_atl_rdm_rx_dma_desc_cache_init_set(self, 1);
 930
 931         return aq_hw_err_from_flags(self);
 932 }
 933
 934 static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self,
 935                                      struct aq_ring_s *ring)
 936 {
 937         hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx);
 938         return aq_hw_err_from_flags(self);
 939 }
 940
 941 static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self,
 942                                      struct aq_ring_s *ring)
 943 {
 944         hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx);
 945         return aq_hw_err_from_flags(self);
 946 }
 947
 948 const struct aq_hw_ops hw_atl_ops_b0 = {
 949         .hw_set_mac_address   = hw_atl_b0_hw_mac_addr_set,
 950         .hw_init              = hw_atl_b0_hw_init,
 951         .hw_reset             = hw_atl_b0_hw_reset,
 952         .hw_start             = hw_atl_b0_hw_start,
 953         .hw_ring_tx_start     = hw_atl_b0_hw_ring_tx_start,
 954         .hw_ring_tx_stop      = hw_atl_b0_hw_ring_tx_stop,
 955         .hw_ring_rx_start     = hw_atl_b0_hw_ring_rx_start,
 956         .hw_ring_rx_stop      = hw_atl_b0_hw_ring_rx_stop,
 957         .hw_stop              = hw_atl_b0_hw_stop,
 958
 959         .hw_ring_tx_xmit         = hw_atl_b0_hw_ring_tx_xmit,
 960         .hw_ring_tx_head_update  = hw_atl_b0_hw_ring_tx_head_update,
 961
 962         .hw_ring_rx_receive      = hw_atl_b0_hw_ring_rx_receive,
 963         .hw_ring_rx_fill         = hw_atl_b0_hw_ring_rx_fill,
 964
 965         .hw_irq_enable           = hw_atl_b0_hw_irq_enable,
 966         .hw_irq_disable          = hw_atl_b0_hw_irq_disable,
 967         .hw_irq_read             = hw_atl_b0_hw_irq_read,
 968
 969         .hw_ring_rx_init             = hw_atl_b0_hw_ring_rx_init,
 970         .hw_ring_tx_init             = hw_atl_b0_hw_ring_tx_init,
 971         .hw_packet_filter_set        = hw_atl_b0_hw_packet_filter_set,
 972         .hw_multicast_list_set       = hw_atl_b0_hw_multicast_list_set,
 973         .hw_interrupt_moderation_set = hw_atl_b0_hw_interrupt_moderation_set,
 974         .hw_rss_set                  = hw_atl_b0_hw_rss_set,
 975         .hw_rss_hash_set             = hw_atl_b0_hw_rss_hash_set,
 976         .hw_get_regs                 = hw_atl_utils_hw_get_regs,
 977         .hw_get_hw_stats             = hw_atl_utils_get_hw_stats,
 978         .hw_get_fw_version           = hw_atl_utils_get_fw_version,
 979         .hw_set_offload              = hw_atl_b0_hw_offload_set,
 980         .hw_set_fc                   = hw_atl_b0_set_fc,
 981 };