2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
10 /* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */
13 #include "../aq_hw_utils.h"
14 #include "../aq_ring.h"
15 #include "hw_atl_b0.h"
16 #include "hw_atl_utils.h"
17 #include "hw_atl_llh.h"
18 #include "hw_atl_b0_internal.h"
19 #include "hw_atl_llh_internal.h"
21 static int hw_atl_b0_get_hw_caps(struct aq_hw_s *self,
22 struct aq_hw_caps_s *aq_hw_caps,
23 unsigned short device,
24 unsigned short subsystem_device)
26 memcpy(aq_hw_caps, &hw_atl_b0_hw_caps_, sizeof(*aq_hw_caps));
28 if (device == HW_ATL_DEVICE_ID_D108 && subsystem_device == 0x0001)
29 aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_10G;
31 if (device == HW_ATL_DEVICE_ID_D109 && subsystem_device == 0x0001) {
32 aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_10G;
33 aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_5G;
39 static struct aq_hw_s *hw_atl_b0_create(struct aq_pci_func_s *aq_pci_func,
41 struct aq_hw_ops *ops)
43 struct hw_atl_s *self = NULL;
45 self = kzalloc(sizeof(*self), GFP_KERNEL);
49 self->base.aq_pci_func = aq_pci_func;
51 self->base.not_ff_addr = 0x10U;
54 return (struct aq_hw_s *)self;
57 static void hw_atl_b0_destroy(struct aq_hw_s *self)
62 static int hw_atl_b0_hw_reset(struct aq_hw_s *self)
66 glb_glb_reg_res_dis_set(self, 1U);
67 pci_pci_reg_res_dis_set(self, 0U);
68 rx_rx_reg_res_dis_set(self, 0U);
69 tx_tx_reg_res_dis_set(self, 0U);
72 glb_soft_res_set(self, 1);
74 /* check 10 times by 1ms */
75 AQ_HW_WAIT_FOR(glb_soft_res_get(self) == 0, 1000U, 10U);
79 itr_irq_reg_res_dis_set(self, 0U);
80 itr_res_irq_set(self, 1U);
82 /* check 10 times by 1ms */
83 AQ_HW_WAIT_FOR(itr_res_irq_get(self) == 0, 1000U, 10U);
87 hw_atl_utils_mpi_set(self, MPI_RESET, 0x0U);
89 err = aq_hw_err_from_flags(self);
95 static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
99 unsigned int i_priority = 0U;
100 bool is_rx_flow_control = false;
102 /* TPS Descriptor rate init */
103 tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
104 tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
107 tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
109 /* TPS TC credits init */
110 tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
111 tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
113 tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
114 tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
115 tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
116 tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
119 buff_size = HW_ATL_B0_TXBUF_MAX;
121 tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
122 tpb_tx_buff_hi_threshold_per_tc_set(self,
123 (buff_size * (1024 / 32U) * 66U) /
125 tpb_tx_buff_lo_threshold_per_tc_set(self,
126 (buff_size * (1024 / 32U) * 50U) /
129 /* QoS Rx buf size per TC */
131 is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);
132 buff_size = HW_ATL_B0_RXBUF_MAX;
134 rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
135 rpb_rx_buff_hi_threshold_per_tc_set(self,
137 (1024U / 32U) * 66U) /
139 rpb_rx_buff_lo_threshold_per_tc_set(self,
141 (1024U / 32U) * 50U) /
143 rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
145 /* QoS 802.1p priority -> TC mapping */
146 for (i_priority = 8U; i_priority--;)
147 rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
149 return aq_hw_err_from_flags(self);
152 static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
153 struct aq_rss_parameters *rss_params)
155 struct aq_nic_cfg_s *cfg = NULL;
158 unsigned int addr = 0U;
160 cfg = self->aq_nic_cfg;
162 for (i = 10, addr = 0U; i--; ++addr) {
163 u32 key_data = cfg->is_rss ?
164 __swab32(rss_params->hash_secret_key[i]) : 0U;
165 rpf_rss_key_wr_data_set(self, key_data);
166 rpf_rss_key_addr_set(self, addr);
167 rpf_rss_key_wr_en_set(self, 1U);
168 AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self) == 0, 1000U, 10U);
173 err = aq_hw_err_from_flags(self);
179 static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,
180 struct aq_rss_parameters *rss_params)
182 u8 *indirection_table = rss_params->indirection_table;
184 u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
186 u16 bitary[(HW_ATL_B0_RSS_REDIRECTION_MAX *
187 HW_ATL_B0_RSS_REDIRECTION_BITS / 16U)];
189 memset(bitary, 0, sizeof(bitary));
191 for (i = HW_ATL_B0_RSS_REDIRECTION_MAX; i--;) {
192 (*(u32 *)(bitary + ((i * 3U) / 16U))) |=
193 ((indirection_table[i] % num_rss_queues) <<
197 for (i = AQ_DIMOF(bitary); i--;) {
198 rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
199 rpf_rss_redir_tbl_addr_set(self, i);
200 rpf_rss_redir_wr_en_set(self, 1U);
201 AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self) == 0, 1000U, 10U);
206 err = aq_hw_err_from_flags(self);
212 static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self,
213 struct aq_nic_cfg_s *aq_nic_cfg)
217 /* TX checksums offloads*/
218 tpo_ipv4header_crc_offload_en_set(self, 1);
219 tpo_tcp_udp_crc_offload_en_set(self, 1);
221 /* RX checksums offloads*/
222 rpo_ipv4header_crc_offload_en_set(self, 1);
223 rpo_tcp_udp_crc_offload_en_set(self, 1);
226 tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
230 unsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U :
231 ((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U :
232 ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0));
234 for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++)
235 rpo_lro_max_num_of_descriptors_set(self, val, i);
237 rpo_lro_time_base_divider_set(self, 0x61AU);
238 rpo_lro_inactive_interval_set(self, 0);
239 rpo_lro_max_coalescing_interval_set(self, 2);
241 rpo_lro_qsessions_lim_set(self, 1U);
243 rpo_lro_total_desc_lim_set(self, 2U);
245 rpo_lro_patch_optimization_en_set(self, 0U);
247 rpo_lro_min_pay_of_first_pkt_set(self, 10U);
249 rpo_lro_pkt_lim_set(self, 1U);
251 rpo_lro_en_set(self, aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U);
253 return aq_hw_err_from_flags(self);
256 static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self)
258 thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
259 thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
260 thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
263 tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
266 aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
267 0x00010000U : 0x00000000U);
268 tdm_tx_dca_en_set(self, 0U);
269 tdm_tx_dca_mode_set(self, 0U);
271 tpb_tx_path_scp_ins_en_set(self, 1U);
273 return aq_hw_err_from_flags(self);
276 static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self)
278 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
281 /* Rx TC/RSS number config */
282 rpb_rpf_rx_traf_class_mode_set(self, 1U);
284 /* Rx flow control */
285 rpb_rx_flow_ctl_mode_set(self, 1U);
287 /* RSS Ring selection */
288 reg_rx_flr_rss_control1set(self, cfg->is_rss ?
289 0xB3333333U : 0x00000000U);
291 /* Multicast filters */
292 for (i = HW_ATL_B0_MAC_MAX; i--;) {
293 rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
294 rpfl2unicast_flr_act_set(self, 1U, i);
297 reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
298 reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
301 rpf_vlan_outer_etht_set(self, 0x88A8U);
302 rpf_vlan_inner_etht_set(self, 0x8100U);
305 rpf_vlan_flr_act_set(self, 1U, 0U);
306 rpf_vlan_id_flr_set(self, 0U, 0U);
307 rpf_vlan_flr_en_set(self, 0U, 0U);
309 rpf_vlan_accept_untagged_packets_set(self, 1U);
310 rpf_vlan_untagged_act_set(self, 1U);
312 rpf_vlan_flr_act_set(self, 1U, 1U);
313 rpf_vlan_id_flr_set(self, cfg->vlan_id, 0U);
314 rpf_vlan_flr_en_set(self, 1U, 1U);
316 rpf_vlan_prom_mode_en_set(self, 1);
320 rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
323 aq_hw_write_reg(self, 0x00005040U,
324 IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U);
326 rpfl2broadcast_flr_act_set(self, 1U);
327 rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
329 rdm_rx_dca_en_set(self, 0U);
330 rdm_rx_dca_mode_set(self, 0U);
332 return aq_hw_err_from_flags(self);
335 static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
345 h = (mac_addr[0] << 8) | (mac_addr[1]);
346 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
347 (mac_addr[4] << 8) | mac_addr[5];
349 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC);
350 rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC);
351 rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC);
352 rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC);
354 err = aq_hw_err_from_flags(self);
360 static int hw_atl_b0_hw_init(struct aq_hw_s *self,
361 struct aq_nic_cfg_s *aq_nic_cfg,
364 static u32 aq_hw_atl_igcr_table_[4][2] = {
365 { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */
366 { 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */
367 { 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */
368 { 0x20000022U, 0x20000026U } /* AQ_IRQ_MSIX */
374 self->aq_nic_cfg = aq_nic_cfg;
376 hw_atl_utils_hw_chip_features_init(self,
377 &PHAL_ATLANTIC_B0->chip_features);
379 hw_atl_b0_hw_init_tx_path(self);
380 hw_atl_b0_hw_init_rx_path(self);
382 hw_atl_b0_hw_mac_addr_set(self, mac_addr);
384 hw_atl_utils_mpi_set(self, MPI_INIT, aq_nic_cfg->link_speed_msk);
386 hw_atl_b0_hw_qos_set(self);
387 hw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
388 hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
390 /* Force limit MRRS on RDM/TDM to 2K */
391 val = aq_hw_read_reg(self, pci_reg_control6_adr);
392 aq_hw_write_reg(self, pci_reg_control6_adr, (val & ~0x707) | 0x404);
394 /* TX DMA total request limit. B0 hardware is not capable to
395 * handle more than (8K-MRRS) incoming DMA data.
396 * Value 24 in 256byte units
398 aq_hw_write_reg(self, tx_dma_total_req_limit_adr, 24);
400 /* Reset link status and read out initial hardware counters */
401 self->aq_link_status.mbps = 0;
402 hw_atl_utils_update_stats(self);
404 err = aq_hw_err_from_flags(self);
409 reg_irq_glb_ctl_set(self,
410 aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
411 [(aq_nic_cfg->vecs > 1U) ?
414 itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
417 reg_gen_irq_map_set(self,
418 ((HW_ATL_B0_ERR_INT << 0x18) | (1U << 0x1F)) |
419 ((HW_ATL_B0_ERR_INT << 0x10) | (1U << 0x17)), 0U);
421 hw_atl_b0_hw_offload_set(self, aq_nic_cfg);
427 static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self,
428 struct aq_ring_s *ring)
430 tdm_tx_desc_en_set(self, 1, ring->idx);
431 return aq_hw_err_from_flags(self);
434 static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self,
435 struct aq_ring_s *ring)
437 rdm_rx_desc_en_set(self, 1, ring->idx);
438 return aq_hw_err_from_flags(self);
441 static int hw_atl_b0_hw_start(struct aq_hw_s *self)
443 tpb_tx_buff_en_set(self, 1);
444 rpb_rx_buff_en_set(self, 1);
445 return aq_hw_err_from_flags(self);
448 static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self,
449 struct aq_ring_s *ring)
451 reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
455 static int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self,
456 struct aq_ring_s *ring,
459 struct aq_ring_buff_s *buff = NULL;
460 struct hw_atl_txd_s *txd = NULL;
461 unsigned int buff_pa_len = 0U;
462 unsigned int pkt_len = 0U;
463 unsigned int frag_count = 0U;
466 buff = &ring->buff_ring[ring->sw_tail];
467 pkt_len = (buff->is_eop && buff->is_sop) ? buff->len : buff->len_pkt;
469 for (frag_count = 0; frag_count < frags; frag_count++) {
470 txd = (struct hw_atl_txd_s *)&ring->dx_ring[ring->sw_tail *
476 buff = &ring->buff_ring[ring->sw_tail];
479 txd->ctl |= (buff->len_l3 << 31) |
480 (buff->len_l2 << 24) |
481 HW_ATL_B0_TXD_CTL_CMD_TCP |
482 HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC;
483 txd->ctl2 |= (buff->mss << 16) |
484 (buff->len_l4 << 8) |
487 pkt_len -= (buff->len_l4 +
493 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPV6;
495 buff_pa_len = buff->len;
497 txd->buf_addr = buff->pa;
498 txd->ctl |= (HW_ATL_B0_TXD_CTL_BLEN &
499 ((u32)buff_pa_len << 4));
500 txd->ctl |= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD;
502 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_LEN & (pkt_len << 14);
505 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_LSO;
506 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_CTX_EN;
509 /* Tx checksum offloads */
511 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPCSO;
513 if (buff->is_udp_cso || buff->is_tcp_cso)
514 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_TUCSO;
516 if (unlikely(buff->is_eop)) {
517 txd->ctl |= HW_ATL_B0_TXD_CTL_EOP;
518 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_WB;
523 ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail);
526 hw_atl_b0_hw_tx_ring_tail_update(self, ring);
527 return aq_hw_err_from_flags(self);
530 static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self,
531 struct aq_ring_s *aq_ring,
532 struct aq_ring_param_s *aq_ring_param)
534 u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
535 u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
537 rdm_rx_desc_en_set(self, false, aq_ring->idx);
539 rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
541 reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
544 reg_rx_dma_desc_base_addressmswset(self,
545 dma_desc_addr_msw, aq_ring->idx);
547 rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
549 rdm_rx_desc_data_buff_size_set(self,
550 AQ_CFG_RX_FRAME_MAX / 1024U,
553 rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
554 rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
555 rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
557 /* Rx ring set mode */
559 /* Mapping interrupt vector */
560 itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
561 itr_irq_map_en_rx_set(self, true, aq_ring->idx);
563 rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
564 rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
565 rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
566 rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
568 return aq_hw_err_from_flags(self);
571 static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self,
572 struct aq_ring_s *aq_ring,
573 struct aq_ring_param_s *aq_ring_param)
575 u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
576 u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
578 reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
581 reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
584 tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
586 hw_atl_b0_hw_tx_ring_tail_update(self, aq_ring);
588 /* Set Tx threshold */
589 tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
591 /* Mapping interrupt vector */
592 itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
593 itr_irq_map_en_tx_set(self, true, aq_ring->idx);
595 tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
596 tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
598 return aq_hw_err_from_flags(self);
601 static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self,
602 struct aq_ring_s *ring,
603 unsigned int sw_tail_old)
605 for (; sw_tail_old != ring->sw_tail;
606 sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) {
607 struct hw_atl_rxd_s *rxd =
608 (struct hw_atl_rxd_s *)&ring->dx_ring[sw_tail_old *
611 struct aq_ring_buff_s *buff = &ring->buff_ring[sw_tail_old];
613 rxd->buf_addr = buff->pa;
617 reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
619 return aq_hw_err_from_flags(self);
622 static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self,
623 struct aq_ring_s *ring)
626 unsigned int hw_head_ = tdm_tx_desc_head_ptr_get(self, ring->idx);
628 if (aq_utils_obj_test(&self->header.flags, AQ_HW_FLAG_ERR_UNPLUG)) {
632 ring->hw_head = hw_head_;
633 err = aq_hw_err_from_flags(self);
639 static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self,
640 struct aq_ring_s *ring)
642 struct device *ndev = aq_nic_get_dev(ring->aq_nic);
644 for (; ring->hw_head != ring->sw_tail;
645 ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) {
646 struct aq_ring_buff_s *buff = NULL;
647 struct hw_atl_rxd_wb_s *rxd_wb = (struct hw_atl_rxd_wb_s *)
648 &ring->dx_ring[ring->hw_head * HW_ATL_B0_RXD_SIZE];
650 unsigned int is_err = 1U;
651 unsigned int is_rx_check_sum_enabled = 0U;
652 unsigned int pkt_type = 0U;
654 if (!(rxd_wb->status & 0x1U)) { /* RxD is not done */
658 buff = &ring->buff_ring[ring->hw_head];
660 is_err = (0x0000003CU & rxd_wb->status);
662 is_rx_check_sum_enabled = (rxd_wb->type) & (0x3U << 19);
663 is_err &= ~0x20U; /* exclude validity bit */
665 pkt_type = 0xFFU & (rxd_wb->type >> 4);
667 if (is_rx_check_sum_enabled) {
668 if (0x0U == (pkt_type & 0x3U))
669 buff->is_ip_cso = (is_err & 0x08U) ? 0U : 1U;
671 if (0x4U == (pkt_type & 0x1CU))
672 buff->is_udp_cso = buff->is_cso_err ? 0U : 1U;
673 else if (0x0U == (pkt_type & 0x1CU))
674 buff->is_tcp_cso = buff->is_cso_err ? 0U : 1U;
676 /* Checksum offload workaround for small packets */
677 if (rxd_wb->pkt_len <= 60) {
678 buff->is_ip_cso = 0U;
679 buff->is_cso_err = 0U;
685 dma_unmap_page(ndev, buff->pa, buff->len, DMA_FROM_DEVICE);
687 if (is_err || rxd_wb->type & 0x1000U) {
688 /* status error or DMA error */
691 if (self->aq_nic_cfg->is_rss) {
693 u16 rss_type = rxd_wb->type & 0xFU;
695 if (rss_type && rss_type < 0x8U) {
696 buff->is_hash_l4 = (rss_type == 0x4 ||
698 buff->rss_hash = rxd_wb->rss_hash;
702 if (HW_ATL_B0_RXD_WB_STAT2_EOP & rxd_wb->status) {
703 buff->len = rxd_wb->pkt_len %
705 buff->len = buff->len ?
706 buff->len : AQ_CFG_RX_FRAME_MAX;
710 if (HW_ATL_B0_RXD_WB_STAT2_RSCCNT &
713 buff->next = rxd_wb->next_desc_ptr;
714 ++ring->stats.rx.lro_packets;
718 aq_ring_next_dx(ring,
720 ++ring->stats.rx.jumbo_packets;
726 return aq_hw_err_from_flags(self);
729 static int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
731 itr_irq_msk_setlsw_set(self, LODWORD(mask));
732 return aq_hw_err_from_flags(self);
735 static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
737 itr_irq_msk_clearlsw_set(self, LODWORD(mask));
738 itr_irq_status_clearlsw_set(self, LODWORD(mask));
740 atomic_inc(&PHAL_ATLANTIC_B0->dpc);
741 return aq_hw_err_from_flags(self);
744 static int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
746 *mask = itr_irq_statuslsw_get(self);
747 return aq_hw_err_from_flags(self);
750 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
752 static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self,
753 unsigned int packet_filter)
757 rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
758 rpfl2multicast_flr_en_set(self,
759 IS_FILTER_ENABLED(IFF_MULTICAST), 0);
761 rpfl2_accept_all_mc_packets_set(self,
762 IS_FILTER_ENABLED(IFF_ALLMULTI));
764 rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
766 self->aq_nic_cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST);
768 for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i)
769 rpfl2_uc_flr_en_set(self,
770 (self->aq_nic_cfg->is_mc_list_enabled &&
771 (i <= self->aq_nic_cfg->mc_list_count)) ?
774 return aq_hw_err_from_flags(self);
777 #undef IS_FILTER_ENABLED
779 static int hw_atl_b0_hw_multicast_list_set(struct aq_hw_s *self,
781 [AQ_CFG_MULTICAST_ADDRESS_MAX]
787 if (count > (HW_ATL_B0_MAC_MAX - HW_ATL_B0_MAC_MIN)) {
791 for (self->aq_nic_cfg->mc_list_count = 0U;
792 self->aq_nic_cfg->mc_list_count < count;
793 ++self->aq_nic_cfg->mc_list_count) {
794 u32 i = self->aq_nic_cfg->mc_list_count;
795 u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]);
796 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
797 (ar_mac[i][4] << 8) | ar_mac[i][5];
799 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC_MIN + i);
801 rpfl2unicast_dest_addresslsw_set(self,
802 l, HW_ATL_B0_MAC_MIN + i);
804 rpfl2unicast_dest_addressmsw_set(self,
805 h, HW_ATL_B0_MAC_MIN + i);
807 rpfl2_uc_flr_en_set(self,
808 (self->aq_nic_cfg->is_mc_list_enabled),
809 HW_ATL_B0_MAC_MIN + i);
812 err = aq_hw_err_from_flags(self);
818 static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self)
824 switch (self->aq_nic_cfg->itr) {
825 case AQ_CFG_INTERRUPT_MODERATION_ON:
826 case AQ_CFG_INTERRUPT_MODERATION_AUTO:
827 tdm_tx_desc_wr_wb_irq_en_set(self, 0U);
828 tdm_tdm_intr_moder_en_set(self, 1U);
829 rdm_rx_desc_wr_wb_irq_en_set(self, 0U);
830 rdm_rdm_intr_moder_en_set(self, 1U);
832 if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) {
833 /* HW timers are in 2us units */
834 int tx_max_timer = self->aq_nic_cfg->tx_itr / 2;
835 int tx_min_timer = tx_max_timer / 2;
837 int rx_max_timer = self->aq_nic_cfg->rx_itr / 2;
838 int rx_min_timer = rx_max_timer / 2;
840 tx_max_timer = min(HW_ATL_INTR_MODER_MAX, tx_max_timer);
841 tx_min_timer = min(HW_ATL_INTR_MODER_MIN, tx_min_timer);
842 rx_max_timer = min(HW_ATL_INTR_MODER_MAX, rx_max_timer);
843 rx_min_timer = min(HW_ATL_INTR_MODER_MIN, rx_min_timer);
845 itr_tx |= tx_min_timer << 0x8U;
846 itr_tx |= tx_max_timer << 0x10U;
847 itr_rx |= rx_min_timer << 0x8U;
848 itr_rx |= rx_max_timer << 0x10U;
850 static unsigned int hw_atl_b0_timers_table_tx_[][2] = {
851 {0xfU, 0xffU}, /* 10Gbit */
852 {0xfU, 0x1ffU}, /* 5Gbit */
853 {0xfU, 0x1ffU}, /* 5Gbit 5GS */
854 {0xfU, 0x1ffU}, /* 2.5Gbit */
855 {0xfU, 0x1ffU}, /* 1Gbit */
856 {0xfU, 0x1ffU}, /* 100Mbit */
859 static unsigned int hw_atl_b0_timers_table_rx_[][2] = {
860 {0x6U, 0x38U},/* 10Gbit */
861 {0xCU, 0x70U},/* 5Gbit */
862 {0xCU, 0x70U},/* 5Gbit 5GS */
863 {0x18U, 0xE0U},/* 2.5Gbit */
864 {0x30U, 0x80U},/* 1Gbit */
865 {0x4U, 0x50U},/* 100Mbit */
868 unsigned int speed_index =
869 hw_atl_utils_mbps_2_speed_index(
870 self->aq_link_status.mbps);
872 /* Update user visible ITR settings */
873 self->aq_nic_cfg->tx_itr = hw_atl_b0_timers_table_tx_
874 [speed_index][1] * 2;
875 self->aq_nic_cfg->rx_itr = hw_atl_b0_timers_table_rx_
876 [speed_index][1] * 2;
878 itr_tx |= hw_atl_b0_timers_table_tx_
879 [speed_index][0] << 0x8U;
880 itr_tx |= hw_atl_b0_timers_table_tx_
881 [speed_index][1] << 0x10U;
883 itr_rx |= hw_atl_b0_timers_table_rx_
884 [speed_index][0] << 0x8U;
885 itr_rx |= hw_atl_b0_timers_table_rx_
886 [speed_index][1] << 0x10U;
889 case AQ_CFG_INTERRUPT_MODERATION_OFF:
890 tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
891 tdm_tdm_intr_moder_en_set(self, 0U);
892 rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
893 rdm_rdm_intr_moder_en_set(self, 0U);
899 for (i = HW_ATL_B0_RINGS_MAX; i--;) {
900 reg_tx_intr_moder_ctrl_set(self, itr_tx, i);
901 reg_rx_intr_moder_ctrl_set(self, itr_rx, i);
904 return aq_hw_err_from_flags(self);
907 static int hw_atl_b0_hw_stop(struct aq_hw_s *self)
909 hw_atl_b0_hw_irq_disable(self, HW_ATL_B0_INT_MASK);
910 return aq_hw_err_from_flags(self);
913 static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self,
914 struct aq_ring_s *ring)
916 tdm_tx_desc_en_set(self, 0U, ring->idx);
917 return aq_hw_err_from_flags(self);
920 static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self,
921 struct aq_ring_s *ring)
923 rdm_rx_desc_en_set(self, 0U, ring->idx);
924 return aq_hw_err_from_flags(self);
927 static int hw_atl_b0_hw_set_speed(struct aq_hw_s *self, u32 speed)
931 err = hw_atl_utils_mpi_set_speed(self, speed, MPI_INIT);
939 static struct aq_hw_ops hw_atl_ops_ = {
940 .create = hw_atl_b0_create,
941 .destroy = hw_atl_b0_destroy,
942 .get_hw_caps = hw_atl_b0_get_hw_caps,
944 .hw_get_mac_permanent = hw_atl_utils_get_mac_permanent,
945 .hw_set_mac_address = hw_atl_b0_hw_mac_addr_set,
946 .hw_get_link_status = hw_atl_utils_mpi_get_link_status,
947 .hw_set_link_speed = hw_atl_b0_hw_set_speed,
948 .hw_init = hw_atl_b0_hw_init,
949 .hw_deinit = hw_atl_utils_hw_deinit,
950 .hw_set_power = hw_atl_utils_hw_set_power,
951 .hw_reset = hw_atl_b0_hw_reset,
952 .hw_start = hw_atl_b0_hw_start,
953 .hw_ring_tx_start = hw_atl_b0_hw_ring_tx_start,
954 .hw_ring_tx_stop = hw_atl_b0_hw_ring_tx_stop,
955 .hw_ring_rx_start = hw_atl_b0_hw_ring_rx_start,
956 .hw_ring_rx_stop = hw_atl_b0_hw_ring_rx_stop,
957 .hw_stop = hw_atl_b0_hw_stop,
959 .hw_ring_tx_xmit = hw_atl_b0_hw_ring_tx_xmit,
960 .hw_ring_tx_head_update = hw_atl_b0_hw_ring_tx_head_update,
962 .hw_ring_rx_receive = hw_atl_b0_hw_ring_rx_receive,
963 .hw_ring_rx_fill = hw_atl_b0_hw_ring_rx_fill,
965 .hw_irq_enable = hw_atl_b0_hw_irq_enable,
966 .hw_irq_disable = hw_atl_b0_hw_irq_disable,
967 .hw_irq_read = hw_atl_b0_hw_irq_read,
969 .hw_ring_rx_init = hw_atl_b0_hw_ring_rx_init,
970 .hw_ring_tx_init = hw_atl_b0_hw_ring_tx_init,
971 .hw_packet_filter_set = hw_atl_b0_hw_packet_filter_set,
972 .hw_multicast_list_set = hw_atl_b0_hw_multicast_list_set,
973 .hw_interrupt_moderation_set = hw_atl_b0_hw_interrupt_moderation_set,
974 .hw_rss_set = hw_atl_b0_hw_rss_set,
975 .hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set,
976 .hw_get_regs = hw_atl_utils_hw_get_regs,
977 .hw_update_stats = hw_atl_utils_update_stats,
978 .hw_get_hw_stats = hw_atl_utils_get_hw_stats,
979 .hw_get_fw_version = hw_atl_utils_get_fw_version,
982 struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev)
984 bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA);
985 bool is_did_ok = ((pdev->device == HW_ATL_DEVICE_ID_0001) ||
986 (pdev->device == HW_ATL_DEVICE_ID_D100) ||
987 (pdev->device == HW_ATL_DEVICE_ID_D107) ||
988 (pdev->device == HW_ATL_DEVICE_ID_D108) ||
989 (pdev->device == HW_ATL_DEVICE_ID_D109));
991 bool is_rev_ok = (pdev->revision == 2U);
993 return (is_vid_ok && is_did_ok && is_rev_ok) ? &hw_atl_ops_ : NULL;