drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c

   1 /*
   2  * aQuantia Corporation Network Driver
   3  * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  */
   9
  10 /* File hw_atl_a0.c: Definition of Atlantic hardware specific functions. */
  11
  12 #include "../aq_hw.h"
  13 #include "../aq_hw_utils.h"
  14 #include "../aq_ring.h"
  15 #include "hw_atl_a0.h"
  16 #include "hw_atl_utils.h"
  17 #include "hw_atl_llh.h"
  18 #include "hw_atl_a0_internal.h"
  19
  20 static int hw_atl_a0_get_hw_caps(struct aq_hw_s *self,
  21                                  struct aq_hw_caps_s *aq_hw_caps)
  22 {
  23         memcpy(aq_hw_caps, &hw_atl_a0_hw_caps_, sizeof(*aq_hw_caps));
  24         return 0;
  25 }
  26
  27 static struct aq_hw_s *hw_atl_a0_create(struct aq_pci_func_s *aq_pci_func,
  28                                         unsigned int port,
  29                                         struct aq_hw_ops *ops)
  30 {
  31         struct hw_atl_s *self = NULL;
  32
  33         self = kzalloc(sizeof(*self), GFP_KERNEL);
  34         if (!self)
  35                 goto err_exit;
  36
  37         self->base.aq_pci_func = aq_pci_func;
  38
  39         self->base.not_ff_addr = 0x10U;
  40
  41 err_exit:
  42         return (struct aq_hw_s *)self;
  43 }
  44
  45 static void hw_atl_a0_destroy(struct aq_hw_s *self)
  46 {
  47         kfree(self);
  48 }
  49
  50 static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
  51 {
  52         int err = 0;
  53
  54         glb_glb_reg_res_dis_set(self, 1U);
  55         pci_pci_reg_res_dis_set(self, 0U);
  56         rx_rx_reg_res_dis_set(self, 0U);
  57         tx_tx_reg_res_dis_set(self, 0U);
  58
  59         HW_ATL_FLUSH();
  60         glb_soft_res_set(self, 1);
  61
  62         /* check 10 times by 1ms */
  63         AQ_HW_WAIT_FOR(glb_soft_res_get(self) == 0, 1000U, 10U);
  64         if (err < 0)
  65                 goto err_exit;
  66
  67         itr_irq_reg_res_dis_set(self, 0U);
  68         itr_res_irq_set(self, 1U);
  69
  70         /* check 10 times by 1ms */
  71         AQ_HW_WAIT_FOR(itr_res_irq_get(self) == 0, 1000U, 10U);
  72         if (err < 0)
  73                 goto err_exit;
  74
  75         hw_atl_utils_mpi_set(self, MPI_RESET, 0x0U);
  76
  77         err = aq_hw_err_from_flags(self);
  78
  79 err_exit:
  80         return err;
  81 }
  82
  83 static int hw_atl_a0_hw_qos_set(struct aq_hw_s *self)
  84 {
  85         u32 tc = 0U;
  86         u32 buff_size = 0U;
  87         unsigned int i_priority = 0U;
  88         bool is_rx_flow_control = false;
  89
  90         /* TPS Descriptor rate init */
  91         tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
  92         tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
  93
  94         /* TPS VM init */
  95         tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
  96
  97         /* TPS TC credits init */
  98         tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
  99         tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
 100
 101         tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
 102         tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
 103         tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
 104         tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
 105
 106         /* Tx buf size */
 107         buff_size = HW_ATL_A0_TXBUF_MAX;
 108
 109         tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
 110         tpb_tx_buff_hi_threshold_per_tc_set(self,
 111                                             (buff_size * (1024 / 32U) * 66U) /
 112                                             100U, tc);
 113         tpb_tx_buff_lo_threshold_per_tc_set(self,
 114                                             (buff_size * (1024 / 32U) * 50U) /
 115                                             100U, tc);
 116
 117         /* QoS Rx buf size per TC */
 118         tc = 0;
 119         is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);
 120         buff_size = HW_ATL_A0_RXBUF_MAX;
 121
 122         rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
 123         rpb_rx_buff_hi_threshold_per_tc_set(self,
 124                                             (buff_size *
 125                                             (1024U / 32U) * 66U) /
 126                                             100U, tc);
 127         rpb_rx_buff_lo_threshold_per_tc_set(self,
 128                                             (buff_size *
 129                                             (1024U / 32U) * 50U) /
 130                                             100U, tc);
 131         rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
 132
 133         /* QoS 802.1p priority -> TC mapping */
 134         for (i_priority = 8U; i_priority--;)
 135                 rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
 136
 137         return aq_hw_err_from_flags(self);
 138 }
 139
 140 static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s *self,
 141                                      struct aq_rss_parameters *rss_params)
 142 {
 143         struct aq_nic_cfg_s *cfg = NULL;
 144         int err = 0;
 145         unsigned int i = 0U;
 146         unsigned int addr = 0U;
 147
 148         cfg = self->aq_nic_cfg;
 149
 150         for (i = 10, addr = 0U; i--; ++addr) {
 151                 u32 key_data = cfg->is_rss ?
 152                         __swab32(rss_params->hash_secret_key[i]) : 0U;
 153                 rpf_rss_key_wr_data_set(self, key_data);
 154                 rpf_rss_key_addr_set(self, addr);
 155                 rpf_rss_key_wr_en_set(self, 1U);
 156                 AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self) == 0, 1000U, 10U);
 157                 if (err < 0)
 158                         goto err_exit;
 159         }
 160
 161         err = aq_hw_err_from_flags(self);
 162
 163 err_exit:
 164         return err;
 165 }
 166
 167 static int hw_atl_a0_hw_rss_set(struct aq_hw_s *self,
 168                                 struct aq_rss_parameters *rss_params)
 169 {
 170         u8 *indirection_table = rss_params->indirection_table;
 171         u32 i = 0U;
 172         u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
 173         int err = 0;
 174         u16 bitary[(HW_ATL_A0_RSS_REDIRECTION_MAX *
 175                                         HW_ATL_A0_RSS_REDIRECTION_BITS / 16U)];
 176
 177         memset(bitary, 0, sizeof(bitary));
 178
 179         for (i = HW_ATL_A0_RSS_REDIRECTION_MAX; i--; ) {
 180                 (*(u32 *)(bitary + ((i * 3U) / 16U))) |=
 181                         ((indirection_table[i] % num_rss_queues) <<
 182                         ((i * 3U) & 0xFU));
 183         }
 184
 185         for (i = AQ_DIMOF(bitary); i--;) {
 186                 rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
 187                 rpf_rss_redir_tbl_addr_set(self, i);
 188                 rpf_rss_redir_wr_en_set(self, 1U);
 189                 AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self) == 0, 1000U, 10U);
 190                 if (err < 0)
 191                         goto err_exit;
 192         }
 193
 194         err = aq_hw_err_from_flags(self);
 195
 196 err_exit:
 197         return err;
 198 }
 199
 200 static int hw_atl_a0_hw_offload_set(struct aq_hw_s *self,
 201                                     struct aq_nic_cfg_s *aq_nic_cfg)
 202 {
 203         /* TX checksums offloads*/
 204         tpo_ipv4header_crc_offload_en_set(self, 1);
 205         tpo_tcp_udp_crc_offload_en_set(self, 1);
 206
 207         /* RX checksums offloads*/
 208         rpo_ipv4header_crc_offload_en_set(self, 1);
 209         rpo_tcp_udp_crc_offload_en_set(self, 1);
 210
 211         /* LSO offloads*/
 212         tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
 213
 214         return aq_hw_err_from_flags(self);
 215 }
 216
 217 static int hw_atl_a0_hw_init_tx_path(struct aq_hw_s *self)
 218 {
 219         thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
 220         thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
 221         thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
 222
 223         /* Tx interrupts */
 224         tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
 225
 226         /* misc */
 227         aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
 228                         0x00010000U : 0x00000000U);
 229         tdm_tx_dca_en_set(self, 0U);
 230         tdm_tx_dca_mode_set(self, 0U);
 231
 232         tpb_tx_path_scp_ins_en_set(self, 1U);
 233
 234         return aq_hw_err_from_flags(self);
 235 }
 236
 237 static int hw_atl_a0_hw_init_rx_path(struct aq_hw_s *self)
 238 {
 239         struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
 240         int i;
 241
 242         /* Rx TC/RSS number config */
 243         rpb_rpf_rx_traf_class_mode_set(self, 1U);
 244
 245         /* Rx flow control */
 246         rpb_rx_flow_ctl_mode_set(self, 1U);
 247
 248         /* RSS Ring selection */
 249         reg_rx_flr_rss_control1set(self, cfg->is_rss ?
 250                                         0xB3333333U : 0x00000000U);
 251
 252         /* Multicast filters */
 253         for (i = HW_ATL_A0_MAC_MAX; i--;) {
 254                 rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
 255                 rpfl2unicast_flr_act_set(self, 1U, i);
 256         }
 257
 258         reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
 259         reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
 260
 261         /* Vlan filters */
 262         rpf_vlan_outer_etht_set(self, 0x88A8U);
 263         rpf_vlan_inner_etht_set(self, 0x8100U);
 264         rpf_vlan_prom_mode_en_set(self, 1);
 265
 266         /* Rx Interrupts */
 267         rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
 268
 269         /* misc */
 270         rpfl2broadcast_flr_act_set(self, 1U);
 271         rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
 272
 273         rdm_rx_dca_en_set(self, 0U);
 274         rdm_rx_dca_mode_set(self, 0U);
 275
 276         return aq_hw_err_from_flags(self);
 277 }
 278
 279 static int hw_atl_a0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
 280 {
 281         int err = 0;
 282         unsigned int h = 0U;
 283         unsigned int l = 0U;
 284
 285         if (!mac_addr) {
 286                 err = -EINVAL;
 287                 goto err_exit;
 288         }
 289         h = (mac_addr[0] << 8) | (mac_addr[1]);
 290         l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
 291                 (mac_addr[4] << 8) | mac_addr[5];
 292
 293         rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC);
 294         rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_A0_MAC);
 295         rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_A0_MAC);
 296         rpfl2_uc_flr_en_set(self, 1U, HW_ATL_A0_MAC);
 297
 298         err = aq_hw_err_from_flags(self);
 299
 300 err_exit:
 301         return err;
 302 }
 303
 304 static int hw_atl_a0_hw_init(struct aq_hw_s *self,
 305                              struct aq_nic_cfg_s *aq_nic_cfg,
 306                              u8 *mac_addr)
 307 {
 308         static u32 aq_hw_atl_igcr_table_[4][2] = {
 309                 { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */
 310                 { 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */
 311                 { 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */
 312                 { 0x20000022U, 0x20000026U }  /* AQ_IRQ_MSIX */
 313         };
 314
 315         int err = 0;
 316
 317         self->aq_nic_cfg = aq_nic_cfg;
 318
 319         hw_atl_utils_hw_chip_features_init(self,
 320                                            &PHAL_ATLANTIC_A0->chip_features);
 321
 322         hw_atl_a0_hw_init_tx_path(self);
 323         hw_atl_a0_hw_init_rx_path(self);
 324
 325         hw_atl_a0_hw_mac_addr_set(self, mac_addr);
 326
 327         hw_atl_utils_mpi_set(self, MPI_INIT, aq_nic_cfg->link_speed_msk);
 328
 329         reg_tx_dma_debug_ctl_set(self, 0x800000b8U);
 330         reg_tx_dma_debug_ctl_set(self, 0x000000b8U);
 331
 332         hw_atl_a0_hw_qos_set(self);
 333         hw_atl_a0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
 334         hw_atl_a0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
 335
 336         err = aq_hw_err_from_flags(self);
 337         if (err < 0)
 338                 goto err_exit;
 339
 340         /* Interrupts */
 341         reg_irq_glb_ctl_set(self,
 342                             aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
 343                                                  [(aq_nic_cfg->vecs > 1U) ?
 344                                                  1 : 0]);
 345
 346         itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
 347
 348         /* Interrupts */
 349         reg_gen_irq_map_set(self,
 350                             ((HW_ATL_A0_ERR_INT << 0x18) | (1U << 0x1F)) |
 351                             ((HW_ATL_A0_ERR_INT << 0x10) | (1U << 0x17)) |
 352                             ((HW_ATL_A0_ERR_INT << 8) | (1U << 0xF)) |
 353                             ((HW_ATL_A0_ERR_INT) | (1U << 0x7)), 0U);
 354
 355         hw_atl_a0_hw_offload_set(self, aq_nic_cfg);
 356
 357 err_exit:
 358         return err;
 359 }
 360
 361 static int hw_atl_a0_hw_ring_tx_start(struct aq_hw_s *self,
 362                                       struct aq_ring_s *ring)
 363 {
 364         tdm_tx_desc_en_set(self, 1, ring->idx);
 365         return aq_hw_err_from_flags(self);
 366 }
 367
 368 static int hw_atl_a0_hw_ring_rx_start(struct aq_hw_s *self,
 369                                       struct aq_ring_s *ring)
 370 {
 371         rdm_rx_desc_en_set(self, 1, ring->idx);
 372         return aq_hw_err_from_flags(self);
 373 }
 374
 375 static int hw_atl_a0_hw_start(struct aq_hw_s *self)
 376 {
 377         tpb_tx_buff_en_set(self, 1);
 378         rpb_rx_buff_en_set(self, 1);
 379         return aq_hw_err_from_flags(self);
 380 }
 381
 382 static int hw_atl_a0_hw_tx_ring_tail_update(struct aq_hw_s *self,
 383                                             struct aq_ring_s *ring)
 384 {
 385         reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
 386         return 0;
 387 }
 388
 389 static int hw_atl_a0_hw_ring_tx_xmit(struct aq_hw_s *self,
 390                                      struct aq_ring_s *ring,
 391                                      unsigned int frags)
 392 {
 393         struct aq_ring_buff_s *buff = NULL;
 394         struct hw_atl_txd_s *txd = NULL;
 395         unsigned int buff_pa_len = 0U;
 396         unsigned int pkt_len = 0U;
 397         unsigned int frag_count = 0U;
 398         bool is_gso = false;
 399
 400         buff = &ring->buff_ring[ring->sw_tail];
 401         pkt_len = (buff->is_eop && buff->is_sop) ? buff->len : buff->len_pkt;
 402
 403         for (frag_count = 0; frag_count < frags; frag_count++) {
 404                 txd = (struct hw_atl_txd_s *)&ring->dx_ring[ring->sw_tail *
 405                                                 HW_ATL_A0_TXD_SIZE];
 406                 txd->ctl = 0;
 407                 txd->ctl2 = 0;
 408                 txd->buf_addr = 0;
 409
 410                 buff = &ring->buff_ring[ring->sw_tail];
 411
 412                 if (buff->is_txc) {
 413                         txd->ctl |= (buff->len_l3 << 31) |
 414                                 (buff->len_l2 << 24) |
 415                                 HW_ATL_A0_TXD_CTL_CMD_TCP |
 416                                 HW_ATL_A0_TXD_CTL_DESC_TYPE_TXC;
 417                         txd->ctl2 |= (buff->mss << 16) |
 418                                 (buff->len_l4 << 8) |
 419                                 (buff->len_l3 >> 1);
 420
 421                         pkt_len -= (buff->len_l4 +
 422                                     buff->len_l3 +
 423                                     buff->len_l2);
 424                         is_gso = true;
 425
 426                         if (buff->is_ipv6)
 427                                 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_IPV6;
 428                 } else {
 429                         buff_pa_len = buff->len;
 430
 431                         txd->buf_addr = buff->pa;
 432                         txd->ctl |= (HW_ATL_A0_TXD_CTL_BLEN &
 433                                                 ((u32)buff_pa_len << 4));
 434                         txd->ctl |= HW_ATL_A0_TXD_CTL_DESC_TYPE_TXD;
 435                         /* PAY_LEN */
 436                         txd->ctl2 |= HW_ATL_A0_TXD_CTL2_LEN & (pkt_len << 14);
 437
 438                         if (is_gso) {
 439                                 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_LSO;
 440                                 txd->ctl2 |= HW_ATL_A0_TXD_CTL2_CTX_EN;
 441                         }
 442
 443                         /* Tx checksum offloads */
 444                         if (buff->is_ip_cso)
 445                                 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_IPCSO;
 446
 447                         if (buff->is_udp_cso || buff->is_tcp_cso)
 448                                 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_TUCSO;
 449
 450                         if (unlikely(buff->is_eop)) {
 451                                 txd->ctl |= HW_ATL_A0_TXD_CTL_EOP;
 452                                 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_WB;
 453                                 is_gso = false;
 454                         }
 455                 }
 456
 457                 ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail);
 458         }
 459
 460         hw_atl_a0_hw_tx_ring_tail_update(self, ring);
 461         return aq_hw_err_from_flags(self);
 462 }
 463
 464 static int hw_atl_a0_hw_ring_rx_init(struct aq_hw_s *self,
 465                                      struct aq_ring_s *aq_ring,
 466                                      struct aq_ring_param_s *aq_ring_param)
 467 {
 468         u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
 469         u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
 470
 471         rdm_rx_desc_en_set(self, false, aq_ring->idx);
 472
 473         rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
 474
 475         reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
 476                                            aq_ring->idx);
 477
 478         reg_rx_dma_desc_base_addressmswset(self,
 479                                            dma_desc_addr_msw, aq_ring->idx);
 480
 481         rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
 482
 483         rdm_rx_desc_data_buff_size_set(self,
 484                                        AQ_CFG_RX_FRAME_MAX / 1024U,
 485                                        aq_ring->idx);
 486
 487         rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
 488         rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
 489         rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
 490
 491         /* Rx ring set mode */
 492
 493         /* Mapping interrupt vector */
 494         itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
 495         itr_irq_map_en_rx_set(self, true, aq_ring->idx);
 496
 497         rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
 498         rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
 499         rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
 500         rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
 501
 502         return aq_hw_err_from_flags(self);
 503 }
 504
 505 static int hw_atl_a0_hw_ring_tx_init(struct aq_hw_s *self,
 506                                      struct aq_ring_s *aq_ring,
 507                                      struct aq_ring_param_s *aq_ring_param)
 508 {
 509         u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
 510         u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
 511
 512         reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
 513                                            aq_ring->idx);
 514
 515         reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
 516                                            aq_ring->idx);
 517
 518         tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
 519
 520         hw_atl_a0_hw_tx_ring_tail_update(self, aq_ring);
 521
 522         /* Set Tx threshold */
 523         tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
 524
 525         /* Mapping interrupt vector */
 526         itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
 527         itr_irq_map_en_tx_set(self, true, aq_ring->idx);
 528
 529         tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
 530         tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
 531
 532         return aq_hw_err_from_flags(self);
 533 }
 534
 535 static int hw_atl_a0_hw_ring_rx_fill(struct aq_hw_s *self,
 536                                      struct aq_ring_s *ring,
 537                                      unsigned int sw_tail_old)
 538 {
 539         for (; sw_tail_old != ring->sw_tail;
 540                 sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) {
 541                 struct hw_atl_rxd_s *rxd =
 542                         (struct hw_atl_rxd_s *)&ring->dx_ring[sw_tail_old *
 543                                                         HW_ATL_A0_RXD_SIZE];
 544
 545                 struct aq_ring_buff_s *buff = &ring->buff_ring[sw_tail_old];
 546
 547                 rxd->buf_addr = buff->pa;
 548                 rxd->hdr_addr = 0U;
 549         }
 550
 551         reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
 552
 553         return aq_hw_err_from_flags(self);
 554 }
 555
 556 static int hw_atl_a0_hw_ring_tx_head_update(struct aq_hw_s *self,
 557                                             struct aq_ring_s *ring)
 558 {
 559         int err = 0;
 560         unsigned int hw_head_ = tdm_tx_desc_head_ptr_get(self, ring->idx);
 561
 562         if (aq_utils_obj_test(&self->header.flags, AQ_HW_FLAG_ERR_UNPLUG)) {
 563                 err = -ENXIO;
 564                 goto err_exit;
 565         }
 566         ring->hw_head = hw_head_;
 567         err = aq_hw_err_from_flags(self);
 568
 569 err_exit:
 570         return err;
 571 }
 572
 573 static int hw_atl_a0_hw_ring_rx_receive(struct aq_hw_s *self,
 574                                         struct aq_ring_s *ring)
 575 {
 576         struct device *ndev = aq_nic_get_dev(ring->aq_nic);
 577
 578         for (; ring->hw_head != ring->sw_tail;
 579                 ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) {
 580                 struct aq_ring_buff_s *buff = NULL;
 581                 struct hw_atl_rxd_wb_s *rxd_wb = (struct hw_atl_rxd_wb_s *)
 582                         &ring->dx_ring[ring->hw_head * HW_ATL_A0_RXD_SIZE];
 583
 584                 unsigned int is_err = 1U;
 585                 unsigned int is_rx_check_sum_enabled = 0U;
 586                 unsigned int pkt_type = 0U;
 587
 588                 if (!(rxd_wb->status & 0x5U)) { /* RxD is not done */
 589                         if ((1U << 4) &
 590                                 reg_rx_dma_desc_status_get(self, ring->idx)) {
 591                         rdm_rx_desc_en_set(self, false, ring->idx);
 592                         rdm_rx_desc_res_set(self, true, ring->idx);
 593                         rdm_rx_desc_res_set(self, false, ring->idx);
 594                         rdm_rx_desc_en_set(self, true, ring->idx);
 595                         }
 596
 597                         if (ring->hw_head ||
 598                             (rdm_rx_desc_head_ptr_get(self, ring->idx) < 2U)) {
 599                                 break;
 600                         } else if (!(rxd_wb->status & 0x1U)) {
 601                                 struct hw_atl_rxd_wb_s *rxd_wb1 =
 602                                         (struct hw_atl_rxd_wb_s *)
 603                                         (&ring->dx_ring[(1U) *
 604                                                 HW_ATL_A0_RXD_SIZE]);
 605
 606                                 if ((rxd_wb1->status & 0x1U)) {
 607                                         rxd_wb->pkt_len = 1514U;
 608                                         rxd_wb->status = 3U;
 609                                 } else {
 610                                         break;
 611                                 }
 612                         }
 613                 }
 614
 615                 buff = &ring->buff_ring[ring->hw_head];
 616
 617                 if (0x3U != (rxd_wb->status & 0x3U))
 618                         rxd_wb->status |= 4;
 619
 620                 is_err = (0x0000001CU & rxd_wb->status);
 621                 is_rx_check_sum_enabled = (rxd_wb->type) & (0x3U << 19);
 622                 pkt_type = 0xFFU & (rxd_wb->type >> 4);
 623
 624                 if (is_rx_check_sum_enabled) {
 625                         if (0x0U == (pkt_type & 0x3U))
 626                                 buff->is_ip_cso = (is_err & 0x08U) ? 0 : 1;
 627
 628                         if (0x4U == (pkt_type & 0x1CU))
 629                                 buff->is_udp_cso = (is_err & 0x10U) ? 0 : 1;
 630                         else if (0x0U == (pkt_type & 0x1CU))
 631                                 buff->is_tcp_cso = (is_err & 0x10U) ? 0 : 1;
 632                 }
 633
 634                 is_err &= ~0x18U;
 635                 is_err &= ~0x04U;
 636
 637                 dma_unmap_page(ndev, buff->pa, buff->len, DMA_FROM_DEVICE);
 638
 639                 if (is_err || rxd_wb->type & 0x1000U) {
 640                         /* status error or DMA error */
 641                         buff->is_error = 1U;
 642                 } else {
 643                         if (self->aq_nic_cfg->is_rss) {
 644                                 /* last 4 byte */
 645                                 u16 rss_type = rxd_wb->type & 0xFU;
 646
 647                                 if (rss_type && rss_type < 0x8U) {
 648                                         buff->is_hash_l4 = (rss_type == 0x4 ||
 649                                                         rss_type == 0x5);
 650                                         buff->rss_hash = rxd_wb->rss_hash;
 651                                 }
 652                         }
 653
 654                         if (HW_ATL_A0_RXD_WB_STAT2_EOP & rxd_wb->status) {
 655                                 buff->len = rxd_wb->pkt_len %
 656                                         AQ_CFG_RX_FRAME_MAX;
 657                                 buff->len = buff->len ?
 658                                         buff->len : AQ_CFG_RX_FRAME_MAX;
 659                                 buff->next = 0U;
 660                                 buff->is_eop = 1U;
 661                         } else {
 662                                 /* jumbo */
 663                                 buff->next = aq_ring_next_dx(ring,
 664                                                              ring->hw_head);
 665                                 ++ring->stats.rx.jumbo_packets;
 666                         }
 667                 }
 668         }
 669
 670         return aq_hw_err_from_flags(self);
 671 }
 672
 673 static int hw_atl_a0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
 674 {
 675         itr_irq_msk_setlsw_set(self, LODWORD(mask) |
 676                                (1U << HW_ATL_A0_ERR_INT));
 677         return aq_hw_err_from_flags(self);
 678 }
 679
 680 static int hw_atl_a0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
 681 {
 682         itr_irq_msk_clearlsw_set(self, LODWORD(mask));
 683         itr_irq_status_clearlsw_set(self, LODWORD(mask));
 684
 685         if ((1U << 16) & reg_gen_irq_status_get(self))
 686
 687                 atomic_inc(&PHAL_ATLANTIC_A0->dpc);
 688
 689         return aq_hw_err_from_flags(self);
 690 }
 691
 692 static int hw_atl_a0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
 693 {
 694         *mask = itr_irq_statuslsw_get(self);
 695         return aq_hw_err_from_flags(self);
 696 }
 697
 698 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
 699
 700 static int hw_atl_a0_hw_packet_filter_set(struct aq_hw_s *self,
 701                                           unsigned int packet_filter)
 702 {
 703         unsigned int i = 0U;
 704
 705         rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
 706         rpfl2multicast_flr_en_set(self, IS_FILTER_ENABLED(IFF_MULTICAST), 0);
 707         rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
 708
 709         self->aq_nic_cfg->is_mc_list_enabled =
 710                         IS_FILTER_ENABLED(IFF_MULTICAST);
 711
 712         for (i = HW_ATL_A0_MAC_MIN; i < HW_ATL_A0_MAC_MAX; ++i)
 713                 rpfl2_uc_flr_en_set(self,
 714                                     (self->aq_nic_cfg->is_mc_list_enabled &&
 715                                     (i <= self->aq_nic_cfg->mc_list_count)) ?
 716                                     1U : 0U, i);
 717
 718         return aq_hw_err_from_flags(self);
 719 }
 720
 721 #undef IS_FILTER_ENABLED
 722
 723 static int hw_atl_a0_hw_multicast_list_set(struct aq_hw_s *self,
 724                                            u8 ar_mac
 725                                            [AQ_CFG_MULTICAST_ADDRESS_MAX]
 726                                            [ETH_ALEN],
 727                                            u32 count)
 728 {
 729         int err = 0;
 730
 731         if (count > (HW_ATL_A0_MAC_MAX - HW_ATL_A0_MAC_MIN)) {
 732                 err = EBADRQC;
 733                 goto err_exit;
 734         }
 735         for (self->aq_nic_cfg->mc_list_count = 0U;
 736                         self->aq_nic_cfg->mc_list_count < count;
 737                         ++self->aq_nic_cfg->mc_list_count) {
 738                 u32 i = self->aq_nic_cfg->mc_list_count;
 739                 u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]);
 740                 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
 741                                         (ar_mac[i][4] << 8) | ar_mac[i][5];
 742
 743                 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC_MIN + i);
 744
 745                 rpfl2unicast_dest_addresslsw_set(self,
 746                                                  l, HW_ATL_A0_MAC_MIN + i);
 747
 748                 rpfl2unicast_dest_addressmsw_set(self,
 749                                                  h, HW_ATL_A0_MAC_MIN + i);
 750
 751                 rpfl2_uc_flr_en_set(self,
 752                                     (self->aq_nic_cfg->is_mc_list_enabled),
 753                                     HW_ATL_A0_MAC_MIN + i);
 754         }
 755
 756         err = aq_hw_err_from_flags(self);
 757
 758 err_exit:
 759         return err;
 760 }
 761
 762 static int hw_atl_a0_hw_interrupt_moderation_set(struct aq_hw_s *self,
 763                                                  bool itr_enabled)
 764 {
 765         unsigned int i = 0U;
 766
 767         if (itr_enabled && self->aq_nic_cfg->itr) {
 768                 if (self->aq_nic_cfg->itr != 0xFFFFU) {
 769                         u32 itr_ = (self->aq_nic_cfg->itr >> 1);
 770
 771                         itr_ = min(AQ_CFG_IRQ_MASK, itr_);
 772
 773                         PHAL_ATLANTIC_A0->itr_rx = 0x80000000U |
 774                                         (itr_ << 0x10);
 775                 } else  {
 776                         u32 n = 0xFFFFU & aq_hw_read_reg(self, 0x00002A00U);
 777
 778                         if (n < self->aq_link_status.mbps) {
 779                                 PHAL_ATLANTIC_A0->itr_rx = 0U;
 780                         } else {
 781                                 static unsigned int hw_timers_tbl_[] = {
 782                                         0x01CU, /* 10Gbit */
 783                                         0x039U, /* 5Gbit */
 784                                         0x039U, /* 5Gbit 5GS */
 785                                         0x073U, /* 2.5Gbit */
 786                                         0x120U, /* 1Gbit */
 787                                         0x1FFU, /* 100Mbit */
 788                                 };
 789
 790                                 unsigned int speed_index =
 791                                         hw_atl_utils_mbps_2_speed_index(
 792                                                 self->aq_link_status.mbps);
 793
 794                                 PHAL_ATLANTIC_A0->itr_rx =
 795                                         0x80000000U |
 796                                         (hw_timers_tbl_[speed_index] << 0x10U);
 797                         }
 798
 799                         aq_hw_write_reg(self, 0x00002A00U, 0x40000000U);
 800                         aq_hw_write_reg(self, 0x00002A00U, 0x8D000000U);
 801                 }
 802         } else {
 803                 PHAL_ATLANTIC_A0->itr_rx = 0U;
 804         }
 805
 806         for (i = HW_ATL_A0_RINGS_MAX; i--;)
 807                 reg_irq_thr_set(self, PHAL_ATLANTIC_A0->itr_rx, i);
 808
 809         return aq_hw_err_from_flags(self);
 810 }
 811
 812 static int hw_atl_a0_hw_stop(struct aq_hw_s *self)
 813 {
 814         hw_atl_a0_hw_irq_disable(self, HW_ATL_A0_INT_MASK);
 815         return aq_hw_err_from_flags(self);
 816 }
 817
 818 static int hw_atl_a0_hw_ring_tx_stop(struct aq_hw_s *self,
 819                                      struct aq_ring_s *ring)
 820 {
 821         tdm_tx_desc_en_set(self, 0U, ring->idx);
 822         return aq_hw_err_from_flags(self);
 823 }
 824
 825 static int hw_atl_a0_hw_ring_rx_stop(struct aq_hw_s *self,
 826                                      struct aq_ring_s *ring)
 827 {
 828         rdm_rx_desc_en_set(self, 0U, ring->idx);
 829         return aq_hw_err_from_flags(self);
 830 }
 831
 832 static int hw_atl_a0_hw_set_speed(struct aq_hw_s *self, u32 speed)
 833 {
 834         int err = 0;
 835
 836         err = hw_atl_utils_mpi_set_speed(self, speed, MPI_INIT);
 837         if (err < 0)
 838                 goto err_exit;
 839
 840 err_exit:
 841         return err;
 842 }
 843
 844 static struct aq_hw_ops hw_atl_ops_ = {
 845         .create               = hw_atl_a0_create,
 846         .destroy              = hw_atl_a0_destroy,
 847         .get_hw_caps          = hw_atl_a0_get_hw_caps,
 848
 849         .hw_get_mac_permanent = hw_atl_utils_get_mac_permanent,
 850         .hw_set_mac_address   = hw_atl_a0_hw_mac_addr_set,
 851         .hw_get_link_status   = hw_atl_utils_mpi_get_link_status,
 852         .hw_set_link_speed    = hw_atl_a0_hw_set_speed,
 853         .hw_init              = hw_atl_a0_hw_init,
 854         .hw_deinit            = hw_atl_utils_hw_deinit,
 855         .hw_set_power         = hw_atl_utils_hw_set_power,
 856         .hw_reset             = hw_atl_a0_hw_reset,
 857         .hw_start             = hw_atl_a0_hw_start,
 858         .hw_ring_tx_start     = hw_atl_a0_hw_ring_tx_start,
 859         .hw_ring_tx_stop      = hw_atl_a0_hw_ring_tx_stop,
 860         .hw_ring_rx_start     = hw_atl_a0_hw_ring_rx_start,
 861         .hw_ring_rx_stop      = hw_atl_a0_hw_ring_rx_stop,
 862         .hw_stop              = hw_atl_a0_hw_stop,
 863
 864         .hw_ring_tx_xmit         = hw_atl_a0_hw_ring_tx_xmit,
 865         .hw_ring_tx_head_update  = hw_atl_a0_hw_ring_tx_head_update,
 866
 867         .hw_ring_rx_receive      = hw_atl_a0_hw_ring_rx_receive,
 868         .hw_ring_rx_fill         = hw_atl_a0_hw_ring_rx_fill,
 869
 870         .hw_irq_enable           = hw_atl_a0_hw_irq_enable,
 871         .hw_irq_disable          = hw_atl_a0_hw_irq_disable,
 872         .hw_irq_read             = hw_atl_a0_hw_irq_read,
 873
 874         .hw_ring_rx_init             = hw_atl_a0_hw_ring_rx_init,
 875         .hw_ring_tx_init             = hw_atl_a0_hw_ring_tx_init,
 876         .hw_packet_filter_set        = hw_atl_a0_hw_packet_filter_set,
 877         .hw_multicast_list_set       = hw_atl_a0_hw_multicast_list_set,
 878         .hw_interrupt_moderation_set = hw_atl_a0_hw_interrupt_moderation_set,
 879         .hw_rss_set                  = hw_atl_a0_hw_rss_set,
 880         .hw_rss_hash_set             = hw_atl_a0_hw_rss_hash_set,
 881         .hw_get_regs                 = hw_atl_utils_hw_get_regs,
 882         .hw_get_hw_stats             = hw_atl_utils_get_hw_stats,
 883         .hw_get_fw_version           = hw_atl_utils_get_fw_version,
 884 };
 885
 886 struct aq_hw_ops *hw_atl_a0_get_ops_by_id(struct pci_dev *pdev)
 887 {
 888         bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA);
 889         bool is_did_ok = ((pdev->device == HW_ATL_DEVICE_ID_0001) ||
 890                         (pdev->device == HW_ATL_DEVICE_ID_D100) ||
 891                         (pdev->device == HW_ATL_DEVICE_ID_D107) ||
 892                         (pdev->device == HW_ATL_DEVICE_ID_D108) ||
 893                         (pdev->device == HW_ATL_DEVICE_ID_D109));
 894
 895         bool is_rev_ok = (pdev->revision == 1U);
 896
 897         return (is_vid_ok && is_did_ok && is_rev_ok) ? &hw_atl_ops_ : NULL;
 898 }