net: ena: Add a driver for Amazon Elastic Network Adapters (ENA)
[sfrench/cifs-2.6.git] / drivers / net / ethernet / amazon / ena / ena_regs_defs.h
1 /*
2  * Copyright 2015 - 2016 Amazon.com, Inc. or its affiliates.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 #ifndef _ENA_REGS_H_
33 #define _ENA_REGS_H_
34
35 /* ena_registers offsets */
36 #define ENA_REGS_VERSION_OFF            0x0
37 #define ENA_REGS_CONTROLLER_VERSION_OFF         0x4
38 #define ENA_REGS_CAPS_OFF               0x8
39 #define ENA_REGS_CAPS_EXT_OFF           0xc
40 #define ENA_REGS_AQ_BASE_LO_OFF         0x10
41 #define ENA_REGS_AQ_BASE_HI_OFF         0x14
42 #define ENA_REGS_AQ_CAPS_OFF            0x18
43 #define ENA_REGS_ACQ_BASE_LO_OFF                0x20
44 #define ENA_REGS_ACQ_BASE_HI_OFF                0x24
45 #define ENA_REGS_ACQ_CAPS_OFF           0x28
46 #define ENA_REGS_AQ_DB_OFF              0x2c
47 #define ENA_REGS_ACQ_TAIL_OFF           0x30
48 #define ENA_REGS_AENQ_CAPS_OFF          0x34
49 #define ENA_REGS_AENQ_BASE_LO_OFF               0x38
50 #define ENA_REGS_AENQ_BASE_HI_OFF               0x3c
51 #define ENA_REGS_AENQ_HEAD_DB_OFF               0x40
52 #define ENA_REGS_AENQ_TAIL_OFF          0x44
53 #define ENA_REGS_INTR_MASK_OFF          0x4c
54 #define ENA_REGS_DEV_CTL_OFF            0x54
55 #define ENA_REGS_DEV_STS_OFF            0x58
56 #define ENA_REGS_MMIO_REG_READ_OFF              0x5c
57 #define ENA_REGS_MMIO_RESP_LO_OFF               0x60
58 #define ENA_REGS_MMIO_RESP_HI_OFF               0x64
59 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF               0x68
60
61 /* version register */
62 #define ENA_REGS_VERSION_MINOR_VERSION_MASK             0xff
63 #define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT            8
64 #define ENA_REGS_VERSION_MAJOR_VERSION_MASK             0xff00
65
66 /* controller_version register */
67 #define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK               0xff
68 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT         8
69 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK          0xff00
70 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT         16
71 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK          0xff0000
72 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT               24
73 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK                0xff000000
74
75 /* caps register */
76 #define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK            0x1
77 #define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT               1
78 #define ENA_REGS_CAPS_RESET_TIMEOUT_MASK                0x3e
79 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT              8
80 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK               0xff00
81
82 /* aq_caps register */
83 #define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK          0xffff
84 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT            16
85 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK             0xffff0000
86
87 /* acq_caps register */
88 #define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK                0xffff
89 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT          16
90 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK           0xffff0000
91
92 /* aenq_caps register */
93 #define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK              0xffff
94 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT                16
95 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK         0xffff0000
96
97 /* dev_ctl register */
98 #define ENA_REGS_DEV_CTL_DEV_RESET_MASK         0x1
99 #define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT               1
100 #define ENA_REGS_DEV_CTL_AQ_RESTART_MASK                0x2
101 #define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT                2
102 #define ENA_REGS_DEV_CTL_QUIESCENT_MASK         0x4
103 #define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT                3
104 #define ENA_REGS_DEV_CTL_IO_RESUME_MASK         0x8
105
106 /* dev_sts register */
107 #define ENA_REGS_DEV_STS_READY_MASK             0x1
108 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT           1
109 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK            0x2
110 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT              2
111 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK               0x4
112 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT                3
113 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK         0x8
114 #define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT           4
115 #define ENA_REGS_DEV_STS_RESET_FINISHED_MASK            0x10
116 #define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT              5
117 #define ENA_REGS_DEV_STS_FATAL_ERROR_MASK               0x20
118 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT              6
119 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK               0x40
120 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT         7
121 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK          0x80
122
123 /* mmio_reg_read register */
124 #define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK              0xffff
125 #define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT            16
126 #define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK             0xffff0000
127
128 /* rss_ind_entry_update register */
129 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK                0xffff
130 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT              16
131 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK               0xffff0000
132
133 #endif /*_ENA_REGS_H_ */