[PATCH] uintptr_t is unsigned long, not u32
[sfrench/cifs-2.6.git] / drivers / net / defxx.h
1 /*
2  * File Name:
3  *   defxx.h
4  *
5  * Copyright Information:
6  *   Copyright Digital Equipment Corporation 1996.
7  *
8  *   This software may be used and distributed according to the terms of
9  *   the GNU General Public License, incorporated herein by reference.
10  *
11  * Abstract:
12  *   Contains all definitions specified by port specification and required
13  *   by the defxx.c driver.
14  *
15  * The original author:
16  *   LVS        Lawrence V. Stefani <lstefani@yahoo.com>
17  *
18  * Maintainers:
19  *   macro      Maciej W. Rozycki <macro@linux-mips.org>
20  *
21  * Modification History:
22  *              Date            Name    Description
23  *              16-Aug-96       LVS             Created.
24  *              09-Sep-96       LVS             Added group_prom field.  Moved read/write I/O
25  *                                                      macros to DEFXX.C.
26  *              12-Sep-96       LVS             Removed packet request header pointers.
27  *              04 Aug 2003     macro           Converted to the DMA API.
28  *              23 Oct 2006     macro           Big-endian host support.
29  */
30
31 #ifndef _DEFXX_H_
32 #define _DEFXX_H_
33
34 /* Define basic types for unsigned chars, shorts, longs */
35
36 typedef u8      PI_UINT8;
37 typedef u16     PI_UINT16;
38 typedef u32     PI_UINT32;
39
40 /* Define general structures */
41
42 typedef struct                                                  /* 64-bit counter */
43         {
44         PI_UINT32  ms;
45         PI_UINT32  ls;
46         } PI_CNTR;
47
48 typedef struct                                                  /* LAN address */
49         {
50         PI_UINT32  lwrd_0;
51         PI_UINT32  lwrd_1;
52         } PI_LAN_ADDR;
53
54 typedef struct                                                  /* Station ID address */
55         {
56         PI_UINT32  octet_7_4;
57         PI_UINT32  octet_3_0;
58         } PI_STATION_ID;
59
60
61 /* Define general constants */
62
63 #define PI_ALIGN_K_DESC_BLK                             8192    /* Descriptor block boundary            */
64 #define PI_ALIGN_K_CONS_BLK                             64              /* Consumer block boundary                      */
65 #define PI_ALIGN_K_CMD_REQ_BUFF                 128             /* Xmt Command que buffer alignment */
66 #define PI_ALIGN_K_CMD_RSP_BUFF                 128             /* Rcv Command que buffer alignment */
67 #define PI_ALIGN_K_UNSOL_BUFF                   128             /* Unsol que buffer alignment           */
68 #define PI_ALIGN_K_XMT_DATA_BUFF                0               /* Xmt data que buffer alignment        */
69 #define PI_ALIGN_K_RCV_DATA_BUFF                128             /* Rcv que buffer alignment                     */
70
71 /* Define PHY index values */
72
73 #define PI_PHY_K_S                                              0               /* Index to S phy */
74 #define PI_PHY_K_A                                              0               /* Index to A phy */
75 #define PI_PHY_K_B                                              1               /* Index to B phy */
76 #define PI_PHY_K_MAX                                    2               /* Max number of phys */
77
78 /* Define FMC descriptor fields */
79
80 #define PI_FMC_DESCR_V_SOP                              31
81 #define PI_FMC_DESCR_V_EOP                              30
82 #define PI_FMC_DESCR_V_FSC                              27
83 #define PI_FMC_DESCR_V_FSB_ERROR                26
84 #define PI_FMC_DESCR_V_FSB_ADDR_RECOG   25
85 #define PI_FMC_DESCR_V_FSB_ADDR_COPIED  24
86 #define PI_FMC_DESCR_V_FSB                              22
87 #define PI_FMC_DESCR_V_RCC_FLUSH                21
88 #define PI_FMC_DESCR_V_RCC_CRC                  20
89 #define PI_FMC_DESCR_V_RCC_RRR                  17
90 #define PI_FMC_DESCR_V_RCC_DD                   15
91 #define PI_FMC_DESCR_V_RCC_SS                   13
92 #define PI_FMC_DESCR_V_RCC                              13
93 #define PI_FMC_DESCR_V_LEN                              0
94
95 #define PI_FMC_DESCR_M_SOP                              0x80000000
96 #define PI_FMC_DESCR_M_EOP                              0x40000000
97 #define PI_FMC_DESCR_M_FSC                              0x38000000
98 #define PI_FMC_DESCR_M_FSB_ERROR                0x04000000
99 #define PI_FMC_DESCR_M_FSB_ADDR_RECOG   0x02000000
100 #define PI_FMC_DESCR_M_FSB_ADDR_COPIED  0x01000000
101 #define PI_FMC_DESCR_M_FSB                              0x07C00000
102 #define PI_FMC_DESCR_M_RCC_FLUSH                0x00200000
103 #define PI_FMC_DESCR_M_RCC_CRC                  0x00100000
104 #define PI_FMC_DESCR_M_RCC_RRR                  0x000E0000
105 #define PI_FMC_DESCR_M_RCC_DD                   0x00018000
106 #define PI_FMC_DESCR_M_RCC_SS                   0x00006000
107 #define PI_FMC_DESCR_M_RCC                              0x003FE000
108 #define PI_FMC_DESCR_M_LEN                              0x00001FFF
109
110 #define PI_FMC_DESCR_K_RCC_FMC_INT_ERR  0x01AA
111
112 #define PI_FMC_DESCR_K_RRR_SUCCESS              0x00
113 #define PI_FMC_DESCR_K_RRR_SA_MATCH             0x01
114 #define PI_FMC_DESCR_K_RRR_DA_MATCH             0x02
115 #define PI_FMC_DESCR_K_RRR_FMC_ABORT    0x03
116 #define PI_FMC_DESCR_K_RRR_LENGTH_BAD   0x04
117 #define PI_FMC_DESCR_K_RRR_FRAGMENT             0x05
118 #define PI_FMC_DESCR_K_RRR_FORMAT_ERR   0x06
119 #define PI_FMC_DESCR_K_RRR_MAC_RESET    0x07
120
121 #define PI_FMC_DESCR_K_DD_NO_MATCH              0x0
122 #define PI_FMC_DESCR_K_DD_PROMISCUOUS   0x1
123 #define PI_FMC_DESCR_K_DD_CAM_MATCH             0x2
124 #define PI_FMC_DESCR_K_DD_LOCAL_MATCH   0x3
125
126 #define PI_FMC_DESCR_K_SS_NO_MATCH              0x0
127 #define PI_FMC_DESCR_K_SS_BRIDGE_MATCH  0x1
128 #define PI_FMC_DESCR_K_SS_NOT_POSSIBLE  0x2
129 #define PI_FMC_DESCR_K_SS_LOCAL_MATCH   0x3
130
131 /* Define some max buffer sizes */
132
133 #define PI_CMD_REQ_K_SIZE_MAX                   512
134 #define PI_CMD_RSP_K_SIZE_MAX                   512
135 #define PI_UNSOL_K_SIZE_MAX                             512
136 #define PI_SMT_HOST_K_SIZE_MAX                  4608            /* 4 1/2 K */
137 #define PI_RCV_DATA_K_SIZE_MAX                  4608            /* 4 1/2 K */
138 #define PI_XMT_DATA_K_SIZE_MAX                  4608            /* 4 1/2 K */
139
140 /* Define adapter states */
141
142 #define PI_STATE_K_RESET                                0
143 #define PI_STATE_K_UPGRADE                              1
144 #define PI_STATE_K_DMA_UNAVAIL                  2
145 #define PI_STATE_K_DMA_AVAIL                    3
146 #define PI_STATE_K_LINK_AVAIL                   4
147 #define PI_STATE_K_LINK_UNAVAIL                 5
148 #define PI_STATE_K_HALTED                               6
149 #define PI_STATE_K_RING_MEMBER                  7
150 #define PI_STATE_K_NUMBER                               8
151
152 /* Define codes for command type */
153
154 #define PI_CMD_K_START                                  0x00
155 #define PI_CMD_K_FILTERS_SET                    0x01
156 #define PI_CMD_K_FILTERS_GET                    0x02
157 #define PI_CMD_K_CHARS_SET                              0x03
158 #define PI_CMD_K_STATUS_CHARS_GET               0x04
159 #define PI_CMD_K_CNTRS_GET                              0x05
160 #define PI_CMD_K_CNTRS_SET                              0x06
161 #define PI_CMD_K_ADDR_FILTER_SET                0x07
162 #define PI_CMD_K_ADDR_FILTER_GET                0x08
163 #define PI_CMD_K_ERROR_LOG_CLEAR                0x09
164 #define PI_CMD_K_ERROR_LOG_GET                  0x0A
165 #define PI_CMD_K_FDDI_MIB_GET                   0x0B
166 #define PI_CMD_K_DEC_EXT_MIB_GET                0x0C
167 #define PI_CMD_K_DEVICE_SPECIFIC_GET    0x0D
168 #define PI_CMD_K_SNMP_SET                               0x0E
169 #define PI_CMD_K_UNSOL_TEST                             0x0F
170 #define PI_CMD_K_SMT_MIB_GET                    0x10
171 #define PI_CMD_K_SMT_MIB_SET                    0x11
172 #define PI_CMD_K_MAX                                    0x11    /* Must match last */
173
174 /* Define item codes for Chars_Set and Filters_Set commands */
175
176 #define PI_ITEM_K_EOL                                   0x00    /* End-of-Item list               */
177 #define PI_ITEM_K_T_REQ                                 0x01    /* DECnet T_REQ                           */
178 #define PI_ITEM_K_TVX                                   0x02    /* DECnet TVX                             */
179 #define PI_ITEM_K_RESTRICTED_TOKEN              0x03    /* DECnet Restricted Token        */
180 #define PI_ITEM_K_LEM_THRESHOLD                 0x04    /* DECnet LEM Threshold           */
181 #define PI_ITEM_K_RING_PURGER                   0x05    /* DECnet Ring Purger Enable  */
182 #define PI_ITEM_K_CNTR_INTERVAL                 0x06    /* Chars_Set                              */
183 #define PI_ITEM_K_IND_GROUP_PROM                0x07    /* Filters_Set                            */
184 #define PI_ITEM_K_GROUP_PROM                    0x08    /* Filters_Set                            */
185 #define PI_ITEM_K_BROADCAST                             0x09    /* Filters_Set                            */
186 #define PI_ITEM_K_SMT_PROM                              0x0A    /* Filters_Set                            */
187 #define PI_ITEM_K_SMT_USER                              0x0B    /* Filters_Set                            */
188 #define PI_ITEM_K_RESERVED                              0x0C    /* Filters_Set                            */
189 #define PI_ITEM_K_IMPLEMENTOR                   0x0D    /* Filters_Set                            */
190 #define PI_ITEM_K_LOOPBACK_MODE                 0x0E    /* Chars_Set                              */
191 #define PI_ITEM_K_CONFIG_POLICY                 0x10    /* SMTConfigPolicy                        */
192 #define PI_ITEM_K_CON_POLICY                    0x11    /* SMTConnectionPolicy            */
193 #define PI_ITEM_K_T_NOTIFY                              0x12    /* SMTTNotify                             */
194 #define PI_ITEM_K_STATION_ACTION                0x13    /* SMTStationAction                       */
195 #define PI_ITEM_K_MAC_PATHS_REQ                 0x15    /* MACPathsRequested              */
196 #define PI_ITEM_K_MAC_ACTION                    0x17    /* MACAction                              */
197 #define PI_ITEM_K_CON_POLICIES                  0x18    /* PORTConnectionPolicies         */
198 #define PI_ITEM_K_PORT_PATHS_REQ                0x19    /* PORTPathsRequested             */
199 #define PI_ITEM_K_MAC_LOOP_TIME                 0x1A    /* PORTMACLoopTime                        */
200 #define PI_ITEM_K_TB_MAX                                0x1B    /* PORTTBMax                              */
201 #define PI_ITEM_K_LER_CUTOFF                    0x1C    /* PORTLerCutoff                          */
202 #define PI_ITEM_K_LER_ALARM                             0x1D    /* PORTLerAlarm                           */
203 #define PI_ITEM_K_PORT_ACTION                   0x1E    /* PORTAction                             */
204 #define PI_ITEM_K_FLUSH_TIME                    0x20    /* Chars_Set                              */
205 #define PI_ITEM_K_MAC_T_REQ                             0x29    /* MACTReq                                        */
206 #define PI_ITEM_K_EMAC_RING_PURGER              0x2A    /* eMACRingPurgerEnable           */
207 #define PI_ITEM_K_EMAC_RTOKEN_TIMEOUT   0x2B    /* eMACRestrictedTokenTimeout */
208 #define PI_ITEM_K_FDX_ENB_DIS                   0x2C    /* eFDXEnable                             */
209 #define PI_ITEM_K_MAX                                   0x2C    /* Must equal high item           */
210
211 /* Values for some of the items */
212
213 #define PI_K_FALSE                                              0          /* Generic false */
214 #define PI_K_TRUE                                               1          /* Generic true  */
215
216 #define PI_SNMP_K_TRUE                                  1          /* SNMP true/false values */
217 #define PI_SNMP_K_FALSE                                 2
218
219 #define PI_FSTATE_K_BLOCK                               0          /* Filter State */
220 #define PI_FSTATE_K_PASS                                1
221
222 /* Define command return codes */
223
224 #define PI_RSP_K_SUCCESS                                0x00
225 #define PI_RSP_K_FAILURE                                0x01
226 #define PI_RSP_K_WARNING                                0x02
227 #define PI_RSP_K_LOOP_MODE_BAD                  0x03
228 #define PI_RSP_K_ITEM_CODE_BAD                  0x04
229 #define PI_RSP_K_TVX_BAD                                0x05
230 #define PI_RSP_K_TREQ_BAD                               0x06
231 #define PI_RSP_K_TOKEN_BAD                              0x07
232 #define PI_RSP_K_NO_EOL                                 0x0C
233 #define PI_RSP_K_FILTER_STATE_BAD               0x0D
234 #define PI_RSP_K_CMD_TYPE_BAD                   0x0E
235 #define PI_RSP_K_ADAPTER_STATE_BAD              0x0F
236 #define PI_RSP_K_RING_PURGER_BAD                0x10
237 #define PI_RSP_K_LEM_THRESHOLD_BAD              0x11
238 #define PI_RSP_K_LOOP_NOT_SUPPORTED             0x12
239 #define PI_RSP_K_FLUSH_TIME_BAD                 0x13
240 #define PI_RSP_K_NOT_IMPLEMENTED                0x14
241 #define PI_RSP_K_CONFIG_POLICY_BAD              0x15
242 #define PI_RSP_K_STATION_ACTION_BAD             0x16
243 #define PI_RSP_K_MAC_ACTION_BAD                 0x17
244 #define PI_RSP_K_CON_POLICIES_BAD               0x18
245 #define PI_RSP_K_MAC_LOOP_TIME_BAD              0x19
246 #define PI_RSP_K_TB_MAX_BAD                             0x1A
247 #define PI_RSP_K_LER_CUTOFF_BAD                 0x1B
248 #define PI_RSP_K_LER_ALARM_BAD                  0x1C
249 #define PI_RSP_K_MAC_PATHS_REQ_BAD              0x1D
250 #define PI_RSP_K_MAC_T_REQ_BAD                  0x1E
251 #define PI_RSP_K_EMAC_RING_PURGER_BAD   0x1F
252 #define PI_RSP_K_EMAC_RTOKEN_TIME_BAD   0x20
253 #define PI_RSP_K_NO_SUCH_ENTRY                  0x21
254 #define PI_RSP_K_T_NOTIFY_BAD                   0x22
255 #define PI_RSP_K_TR_MAX_EXP_BAD                 0x23
256 #define PI_RSP_K_MAC_FRM_ERR_THR_BAD    0x24
257 #define PI_RSP_K_MAX_T_REQ_BAD                  0x25
258 #define PI_RSP_K_FDX_ENB_DIS_BAD                0x26
259 #define PI_RSP_K_ITEM_INDEX_BAD                 0x27
260 #define PI_RSP_K_PORT_ACTION_BAD                0x28
261
262 /* Commonly used structures */
263
264 typedef struct                                                                  /* Item list */
265         {
266         PI_UINT32  item_code;
267         PI_UINT32  value;
268         } PI_ITEM_LIST;
269
270 typedef struct                                                                  /* Response header */
271         {
272         PI_UINT32  reserved;
273         PI_UINT32  cmd_type;
274         PI_UINT32  status;
275         } PI_RSP_HEADER;
276
277
278 /* Start Command */
279
280 typedef struct
281         {
282         PI_UINT32  cmd_type;
283         } PI_CMD_START_REQ;
284
285 /* Start Response */
286
287 typedef struct
288         {
289         PI_RSP_HEADER   header;
290         } PI_CMD_START_RSP;
291
292 /* Filters_Set Request */
293
294 #define PI_CMD_FILTERS_SET_K_ITEMS_MAX  63              /* Fits in a 512 byte buffer */
295
296 typedef struct
297         {
298         PI_UINT32               cmd_type;
299         PI_ITEM_LIST    item[PI_CMD_FILTERS_SET_K_ITEMS_MAX];
300         } PI_CMD_FILTERS_SET_REQ;
301
302 /* Filters_Set Response */
303
304 typedef struct
305         {
306         PI_RSP_HEADER   header;
307         } PI_CMD_FILTERS_SET_RSP;
308
309 /* Filters_Get Request */
310
311 typedef struct
312         {
313         PI_UINT32               cmd_type;
314         } PI_CMD_FILTERS_GET_REQ;
315
316 /* Filters_Get Response */
317
318 typedef struct
319         {
320         PI_RSP_HEADER   header;
321         PI_UINT32               ind_group_prom;
322         PI_UINT32               group_prom;
323         PI_UINT32               broadcast_all;
324         PI_UINT32               smt_all;
325         PI_UINT32               smt_user;
326         PI_UINT32               reserved_all;
327         PI_UINT32               implementor_all;
328         } PI_CMD_FILTERS_GET_RSP;
329
330
331 /* Chars_Set Request */
332
333 #define PI_CMD_CHARS_SET_K_ITEMS_MAX 42         /* Fits in a 512 byte buffer */
334
335 typedef struct
336         {
337         PI_UINT32               cmd_type;
338         struct                                                                  /* Item list */
339                 {
340                 PI_UINT32       item_code;
341                 PI_UINT32       value;
342                 PI_UINT32       item_index;
343                 } item[PI_CMD_CHARS_SET_K_ITEMS_MAX];
344         } PI_CMD_CHARS_SET_REQ;
345
346 /* Chars_Set Response */
347
348 typedef struct
349         {
350         PI_RSP_HEADER   header;
351         } PI_CMD_CHARS_SET_RSP;
352
353
354 /* SNMP_Set Request */
355
356 #define PI_CMD_SNMP_SET_K_ITEMS_MAX 42          /* Fits in a 512 byte buffer */
357
358 typedef struct
359         {
360         PI_UINT32               cmd_type;
361         struct                                                                  /* Item list */
362                 {
363                 PI_UINT32       item_code;
364                 PI_UINT32       value;
365                 PI_UINT32       item_index;
366                 } item[PI_CMD_SNMP_SET_K_ITEMS_MAX];
367         } PI_CMD_SNMP_SET_REQ;
368
369 /* SNMP_Set Response */
370
371 typedef struct
372         {
373         PI_RSP_HEADER   header;
374         } PI_CMD_SNMP_SET_RSP;
375
376
377 /* SMT_MIB_Set Request */
378
379 #define PI_CMD_SMT_MIB_SET_K_ITEMS_MAX 42       /* Max number of items */
380
381 typedef struct
382         {
383         PI_UINT32       cmd_type;
384         struct
385                 {
386                 PI_UINT32       item_code;
387                 PI_UINT32       value;
388                 PI_UINT32       item_index;
389                 } item[PI_CMD_SMT_MIB_SET_K_ITEMS_MAX];
390         } PI_CMD_SMT_MIB_SET_REQ;
391
392 /* SMT_MIB_Set Response */
393
394 typedef struct
395         {
396         PI_RSP_HEADER   header;
397         } PI_CMD_SMT_MIB_SET_RSP;
398
399 /* SMT_MIB_Get Request */
400
401 typedef struct
402         {
403         PI_UINT32  cmd_type;
404         } PI_CMD_SMT_MIB_GET_REQ;
405
406 /* SMT_MIB_Get Response */
407
408 typedef struct                                            /* Refer to ANSI FDDI SMT Rev. 7.3 */
409         {
410         PI_RSP_HEADER  header;
411
412         /* SMT GROUP */
413
414         PI_STATION_ID   smt_station_id;
415         PI_UINT32               smt_op_version_id;
416         PI_UINT32               smt_hi_version_id;
417         PI_UINT32               smt_lo_version_id;
418         PI_UINT32               smt_user_data[8];
419         PI_UINT32               smt_mib_version_id;
420         PI_UINT32               smt_mac_ct;
421         PI_UINT32               smt_non_master_ct;
422         PI_UINT32               smt_master_ct;
423         PI_UINT32               smt_available_paths;
424         PI_UINT32               smt_config_capabilities;
425         PI_UINT32               smt_config_policy;
426         PI_UINT32               smt_connection_policy;
427         PI_UINT32               smt_t_notify;
428         PI_UINT32               smt_stat_rpt_policy;
429         PI_UINT32               smt_trace_max_expiration;
430         PI_UINT32               smt_bypass_present;
431         PI_UINT32               smt_ecm_state;
432         PI_UINT32               smt_cf_state;
433         PI_UINT32               smt_remote_disconnect_flag;
434         PI_UINT32               smt_station_status;
435         PI_UINT32               smt_peer_wrap_flag;
436         PI_CNTR                 smt_msg_time_stamp;
437         PI_CNTR                 smt_transition_time_stamp;
438
439         /* MAC GROUP */
440
441         PI_UINT32               mac_frame_status_functions;
442         PI_UINT32               mac_t_max_capability;
443         PI_UINT32               mac_tvx_capability;
444         PI_UINT32               mac_available_paths;
445         PI_UINT32               mac_current_path;
446         PI_LAN_ADDR             mac_upstream_nbr;
447         PI_LAN_ADDR             mac_downstream_nbr;
448         PI_LAN_ADDR             mac_old_upstream_nbr;
449         PI_LAN_ADDR             mac_old_downstream_nbr;
450         PI_UINT32               mac_dup_address_test;
451         PI_UINT32               mac_requested_paths;
452         PI_UINT32               mac_downstream_port_type;
453         PI_LAN_ADDR             mac_smt_address;
454         PI_UINT32               mac_t_req;
455         PI_UINT32               mac_t_neg;
456         PI_UINT32               mac_t_max;
457         PI_UINT32               mac_tvx_value;
458         PI_UINT32               mac_frame_error_threshold;
459         PI_UINT32               mac_frame_error_ratio;
460         PI_UINT32               mac_rmt_state;
461         PI_UINT32               mac_da_flag;
462         PI_UINT32               mac_unda_flag;
463         PI_UINT32               mac_frame_error_flag;
464         PI_UINT32               mac_ma_unitdata_available;
465         PI_UINT32               mac_hardware_present;
466         PI_UINT32               mac_ma_unitdata_enable;
467
468         /* PATH GROUP */
469
470         PI_UINT32               path_configuration[8];
471         PI_UINT32               path_tvx_lower_bound;
472         PI_UINT32               path_t_max_lower_bound;
473         PI_UINT32               path_max_t_req;
474
475         /* PORT GROUP */
476
477         PI_UINT32               port_my_type[PI_PHY_K_MAX];
478         PI_UINT32               port_neighbor_type[PI_PHY_K_MAX];
479         PI_UINT32               port_connection_policies[PI_PHY_K_MAX];
480         PI_UINT32               port_mac_indicated[PI_PHY_K_MAX];
481         PI_UINT32               port_current_path[PI_PHY_K_MAX];
482         PI_UINT32               port_requested_paths[PI_PHY_K_MAX];
483         PI_UINT32               port_mac_placement[PI_PHY_K_MAX];
484         PI_UINT32               port_available_paths[PI_PHY_K_MAX];
485         PI_UINT32               port_pmd_class[PI_PHY_K_MAX];
486         PI_UINT32               port_connection_capabilities[PI_PHY_K_MAX];
487         PI_UINT32               port_bs_flag[PI_PHY_K_MAX];
488         PI_UINT32               port_ler_estimate[PI_PHY_K_MAX];
489         PI_UINT32               port_ler_cutoff[PI_PHY_K_MAX];
490         PI_UINT32               port_ler_alarm[PI_PHY_K_MAX];
491         PI_UINT32               port_connect_state[PI_PHY_K_MAX];
492         PI_UINT32               port_pcm_state[PI_PHY_K_MAX];
493         PI_UINT32               port_pc_withhold[PI_PHY_K_MAX];
494         PI_UINT32               port_ler_flag[PI_PHY_K_MAX];
495         PI_UINT32               port_hardware_present[PI_PHY_K_MAX];
496
497         /* GROUP for things that were added later, so must be at the end. */
498
499         PI_CNTR                 path_ring_latency;
500
501         } PI_CMD_SMT_MIB_GET_RSP;
502
503
504 /*
505  *  Item and group code definitions for SMT 7.3 mandatory objects.  These
506  *  definitions are to be used as appropriate in SMT_MIB_SET commands and
507  *  certain host-sent SMT frames such as PMF Get and Set requests.  The
508  *  codes have been taken from the MIB summary section of ANSI SMT 7.3.
509  */
510
511 #define PI_GRP_K_SMT_STATION_ID                 0x100A
512 #define PI_ITEM_K_SMT_STATION_ID                0x100B
513 #define PI_ITEM_K_SMT_OP_VERS_ID                0x100D
514 #define PI_ITEM_K_SMT_HI_VERS_ID                0x100E
515 #define PI_ITEM_K_SMT_LO_VERS_ID                0x100F
516 #define PI_ITEM_K_SMT_USER_DATA                 0x1011
517 #define PI_ITEM_K_SMT_MIB_VERS_ID               0x1012
518
519 #define PI_GRP_K_SMT_STATION_CONFIG             0x1014
520 #define PI_ITEM_K_SMT_MAC_CT                    0x1015
521 #define PI_ITEM_K_SMT_NON_MASTER_CT             0x1016
522 #define PI_ITEM_K_SMT_MASTER_CT                 0x1017
523 #define PI_ITEM_K_SMT_AVAIL_PATHS               0x1018
524 #define PI_ITEM_K_SMT_CONFIG_CAPS               0x1019
525 #define PI_ITEM_K_SMT_CONFIG_POL                0x101A
526 #define PI_ITEM_K_SMT_CONN_POL                  0x101B
527 #define PI_ITEM_K_SMT_T_NOTIFY                  0x101D
528 #define PI_ITEM_K_SMT_STAT_POL                  0x101E
529 #define PI_ITEM_K_SMT_TR_MAX_EXP                0x101F
530 #define PI_ITEM_K_SMT_PORT_INDEXES              0x1020
531 #define PI_ITEM_K_SMT_MAC_INDEXES               0x1021
532 #define PI_ITEM_K_SMT_BYPASS_PRESENT    0x1022
533
534 #define PI_GRP_K_SMT_STATUS                             0x1028
535 #define PI_ITEM_K_SMT_ECM_STATE                 0x1029
536 #define PI_ITEM_K_SMT_CF_STATE                  0x102A
537 #define PI_ITEM_K_SMT_REM_DISC_FLAG             0x102C
538 #define PI_ITEM_K_SMT_STATION_STATUS    0x102D
539 #define PI_ITEM_K_SMT_PEER_WRAP_FLAG    0x102E
540
541 #define PI_GRP_K_SMT_MIB_OPERATION              0x1032
542 #define PI_ITEM_K_SMT_MSG_TIME_STAMP    0x1033
543 #define PI_ITEM_K_SMT_TRN_TIME_STAMP    0x1034
544
545 #define PI_ITEM_K_SMT_STATION_ACT               0x103C
546
547 #define PI_GRP_K_MAC_CAPABILITIES               0x200A
548 #define PI_ITEM_K_MAC_FRM_STAT_FUNC             0x200B
549 #define PI_ITEM_K_MAC_T_MAX_CAP                 0x200D
550 #define PI_ITEM_K_MAC_TVX_CAP                   0x200E
551
552 #define PI_GRP_K_MAC_CONFIG                             0x2014
553 #define PI_ITEM_K_MAC_AVAIL_PATHS               0x2016
554 #define PI_ITEM_K_MAC_CURRENT_PATH              0x2017
555 #define PI_ITEM_K_MAC_UP_NBR                    0x2018
556 #define PI_ITEM_K_MAC_DOWN_NBR                  0x2019
557 #define PI_ITEM_K_MAC_OLD_UP_NBR                0x201A
558 #define PI_ITEM_K_MAC_OLD_DOWN_NBR              0x201B
559 #define PI_ITEM_K_MAC_DUP_ADDR_TEST             0x201D
560 #define PI_ITEM_K_MAC_REQ_PATHS                 0x2020
561 #define PI_ITEM_K_MAC_DOWN_PORT_TYPE    0x2021
562 #define PI_ITEM_K_MAC_INDEX                             0x2022
563
564 #define PI_GRP_K_MAC_ADDRESS                    0x2028
565 #define PI_ITEM_K_MAC_SMT_ADDRESS               0x2029
566
567 #define PI_GRP_K_MAC_OPERATION                  0x2032
568 #define PI_ITEM_K_MAC_TREQ                              0x2033
569 #define PI_ITEM_K_MAC_TNEG                              0x2034
570 #define PI_ITEM_K_MAC_TMAX                              0x2035
571 #define PI_ITEM_K_MAC_TVX_VALUE                 0x2036
572
573 #define PI_GRP_K_MAC_COUNTERS                   0x2046
574 #define PI_ITEM_K_MAC_FRAME_CT                  0x2047
575 #define PI_ITEM_K_MAC_COPIED_CT                 0x2048
576 #define PI_ITEM_K_MAC_TRANSMIT_CT               0x2049
577 #define PI_ITEM_K_MAC_ERROR_CT                  0x2051
578 #define PI_ITEM_K_MAC_LOST_CT                   0x2052
579
580 #define PI_GRP_K_MAC_FRM_ERR_COND               0x205A
581 #define PI_ITEM_K_MAC_FRM_ERR_THR               0x205F
582 #define PI_ITEM_K_MAC_FRM_ERR_RAT               0x2060
583
584 #define PI_GRP_K_MAC_STATUS                             0x206E
585 #define PI_ITEM_K_MAC_RMT_STATE                 0x206F
586 #define PI_ITEM_K_MAC_DA_FLAG                   0x2070
587 #define PI_ITEM_K_MAC_UNDA_FLAG                 0x2071
588 #define PI_ITEM_K_MAC_FRM_ERR_FLAG              0x2072
589 #define PI_ITEM_K_MAC_MA_UNIT_AVAIL             0x2074
590 #define PI_ITEM_K_MAC_HW_PRESENT                0x2075
591 #define PI_ITEM_K_MAC_MA_UNIT_ENAB              0x2076
592
593 #define PI_GRP_K_PATH_CONFIG                    0x320A
594 #define PI_ITEM_K_PATH_INDEX                    0x320B
595 #define PI_ITEM_K_PATH_CONFIGURATION    0x3212
596 #define PI_ITEM_K_PATH_TVX_LB                   0x3215
597 #define PI_ITEM_K_PATH_T_MAX_LB                 0x3216
598 #define PI_ITEM_K_PATH_MAX_T_REQ                0x3217
599
600 #define PI_GRP_K_PORT_CONFIG                    0x400A
601 #define PI_ITEM_K_PORT_MY_TYPE                  0x400C
602 #define PI_ITEM_K_PORT_NBR_TYPE                 0x400D
603 #define PI_ITEM_K_PORT_CONN_POLS                0x400E
604 #define PI_ITEM_K_PORT_MAC_INDICATED    0x400F
605 #define PI_ITEM_K_PORT_CURRENT_PATH             0x4010
606 #define PI_ITEM_K_PORT_REQ_PATHS                0x4011
607 #define PI_ITEM_K_PORT_MAC_PLACEMENT    0x4012
608 #define PI_ITEM_K_PORT_AVAIL_PATHS              0x4013
609 #define PI_ITEM_K_PORT_PMD_CLASS                0x4016
610 #define PI_ITEM_K_PORT_CONN_CAPS                0x4017
611 #define PI_ITEM_K_PORT_INDEX                    0x401D
612
613 #define PI_GRP_K_PORT_OPERATION                 0x401E
614 #define PI_ITEM_K_PORT_BS_FLAG                  0x4021
615
616 #define PI_GRP_K_PORT_ERR_CNTRS                 0x4028
617 #define PI_ITEM_K_PORT_LCT_FAIL_CT              0x402A
618
619 #define PI_GRP_K_PORT_LER                               0x4032
620 #define PI_ITEM_K_PORT_LER_ESTIMATE             0x4033
621 #define PI_ITEM_K_PORT_LEM_REJ_CT               0x4034
622 #define PI_ITEM_K_PORT_LEM_CT                   0x4035
623 #define PI_ITEM_K_PORT_LER_CUTOFF               0x403A
624 #define PI_ITEM_K_PORT_LER_ALARM                0x403B
625
626 #define PI_GRP_K_PORT_STATUS                    0x403C
627 #define PI_ITEM_K_PORT_CONNECT_STATE    0x403D
628 #define PI_ITEM_K_PORT_PCM_STATE                0x403E
629 #define PI_ITEM_K_PORT_PC_WITHHOLD              0x403F
630 #define PI_ITEM_K_PORT_LER_FLAG                 0x4040
631 #define PI_ITEM_K_PORT_HW_PRESENT               0x4041
632
633 #define PI_ITEM_K_PORT_ACT                              0x4046
634
635 /* Addr_Filter_Set Request */
636
637 #define PI_CMD_ADDR_FILTER_K_SIZE   62
638
639 typedef struct
640         {
641         PI_UINT32       cmd_type;
642         PI_LAN_ADDR     entry[PI_CMD_ADDR_FILTER_K_SIZE];
643         } PI_CMD_ADDR_FILTER_SET_REQ;
644
645 /* Addr_Filter_Set Response */
646
647 typedef struct
648         {
649         PI_RSP_HEADER   header;
650         } PI_CMD_ADDR_FILTER_SET_RSP;
651
652 /* Addr_Filter_Get Request */
653
654 typedef struct
655         {
656         PI_UINT32       cmd_type;
657         } PI_CMD_ADDR_FILTER_GET_REQ;
658
659 /* Addr_Filter_Get Response */
660
661 typedef struct
662         {
663         PI_RSP_HEADER   header;
664         PI_LAN_ADDR             entry[PI_CMD_ADDR_FILTER_K_SIZE];
665         } PI_CMD_ADDR_FILTER_GET_RSP;
666
667 /* Status_Chars_Get Request */
668
669 typedef struct
670         {
671         PI_UINT32  cmd_type;
672         } PI_CMD_STATUS_CHARS_GET_REQ;
673
674 /* Status_Chars_Get Response */
675
676 typedef struct
677         {
678         PI_RSP_HEADER   header;
679         PI_STATION_ID   station_id;                                             /* Station */
680         PI_UINT32               station_type;
681         PI_UINT32               smt_ver_id;
682         PI_UINT32               smt_ver_id_max;
683         PI_UINT32               smt_ver_id_min;
684         PI_UINT32               station_state;
685         PI_LAN_ADDR             link_addr;                                              /* Link */
686         PI_UINT32               t_req;
687         PI_UINT32               tvx;
688         PI_UINT32               token_timeout;
689         PI_UINT32               purger_enb;
690         PI_UINT32               link_state;
691         PI_UINT32               tneg;
692         PI_UINT32               dup_addr_flag;
693         PI_LAN_ADDR             una;
694         PI_LAN_ADDR             una_old;
695         PI_UINT32               un_dup_addr_flag;
696         PI_LAN_ADDR             dna;
697         PI_LAN_ADDR             dna_old;
698         PI_UINT32               purger_state;
699         PI_UINT32               fci_mode;
700         PI_UINT32               error_reason;
701         PI_UINT32               loopback;
702         PI_UINT32               ring_latency;
703         PI_LAN_ADDR             last_dir_beacon_sa;
704         PI_LAN_ADDR             last_dir_beacon_una;
705         PI_UINT32               phy_type[PI_PHY_K_MAX];                 /* Phy */
706         PI_UINT32               pmd_type[PI_PHY_K_MAX];
707         PI_UINT32               lem_threshold[PI_PHY_K_MAX];
708         PI_UINT32               phy_state[PI_PHY_K_MAX];
709         PI_UINT32               nbor_phy_type[PI_PHY_K_MAX];
710         PI_UINT32               link_error_est[PI_PHY_K_MAX];
711         PI_UINT32               broken_reason[PI_PHY_K_MAX];
712         PI_UINT32               reject_reason[PI_PHY_K_MAX];
713         PI_UINT32               cntr_interval;                                  /* Miscellaneous */
714         PI_UINT32               module_rev;
715         PI_UINT32               firmware_rev;
716         PI_UINT32               mop_device_type;
717         PI_UINT32               phy_led[PI_PHY_K_MAX];
718         PI_UINT32               flush_time;
719         } PI_CMD_STATUS_CHARS_GET_RSP;
720
721 /* FDDI_MIB_Get Request */
722
723 typedef struct
724         {
725         PI_UINT32  cmd_type;
726         } PI_CMD_FDDI_MIB_GET_REQ;
727
728 /* FDDI_MIB_Get Response */
729
730 typedef struct
731         {
732         PI_RSP_HEADER   header;
733
734         /* SMT GROUP */
735
736         PI_STATION_ID   smt_station_id;
737         PI_UINT32               smt_op_version_id;
738         PI_UINT32               smt_hi_version_id;
739         PI_UINT32               smt_lo_version_id;
740         PI_UINT32               smt_mac_ct;
741         PI_UINT32               smt_non_master_ct;
742         PI_UINT32               smt_master_ct;
743         PI_UINT32               smt_paths_available;
744         PI_UINT32               smt_config_capabilities;
745         PI_UINT32               smt_config_policy;
746         PI_UINT32               smt_connection_policy;
747         PI_UINT32               smt_t_notify;
748         PI_UINT32               smt_status_reporting;
749         PI_UINT32               smt_ecm_state;
750         PI_UINT32               smt_cf_state;
751         PI_UINT32               smt_hold_state;
752         PI_UINT32               smt_remote_disconnect_flag;
753         PI_UINT32               smt_station_action;
754
755         /* MAC GROUP */
756
757         PI_UINT32               mac_frame_status_capabilities;
758         PI_UINT32               mac_t_max_greatest_lower_bound;
759         PI_UINT32               mac_tvx_greatest_lower_bound;
760         PI_UINT32               mac_paths_available;
761         PI_UINT32               mac_current_path;
762         PI_LAN_ADDR             mac_upstream_nbr;
763         PI_LAN_ADDR             mac_old_upstream_nbr;
764         PI_UINT32               mac_dup_addr_test;
765         PI_UINT32               mac_paths_requested;
766         PI_UINT32               mac_downstream_port_type;
767         PI_LAN_ADDR             mac_smt_address;
768         PI_UINT32               mac_t_req;
769         PI_UINT32               mac_t_neg;
770         PI_UINT32               mac_t_max;
771         PI_UINT32               mac_tvx_value;
772         PI_UINT32               mac_t_min;
773         PI_UINT32               mac_current_frame_status;
774         /*                              mac_frame_cts                   */
775         /*                              mac_error_cts                   */
776         /*                              mac_lost_cts                    */
777         PI_UINT32               mac_frame_error_threshold;
778         PI_UINT32               mac_frame_error_ratio;
779         PI_UINT32               mac_rmt_state;
780         PI_UINT32               mac_da_flag;
781         PI_UINT32               mac_una_da_flag;
782         PI_UINT32               mac_frame_condition;
783         PI_UINT32               mac_chip_set;
784         PI_UINT32               mac_action;
785
786         /* PATH GROUP => Does not need to be implemented */
787
788         /* PORT GROUP */
789
790         PI_UINT32               port_pc_type[PI_PHY_K_MAX];
791         PI_UINT32               port_pc_neighbor[PI_PHY_K_MAX];
792         PI_UINT32               port_connection_policies[PI_PHY_K_MAX];
793         PI_UINT32               port_remote_mac_indicated[PI_PHY_K_MAX];
794         PI_UINT32               port_ce_state[PI_PHY_K_MAX];
795         PI_UINT32               port_paths_requested[PI_PHY_K_MAX];
796         PI_UINT32               port_mac_placement[PI_PHY_K_MAX];
797         PI_UINT32               port_available_paths[PI_PHY_K_MAX];
798         PI_UINT32               port_mac_loop_time[PI_PHY_K_MAX];
799         PI_UINT32               port_tb_max[PI_PHY_K_MAX];
800         PI_UINT32               port_bs_flag[PI_PHY_K_MAX];
801         /*                              port_lct_fail_cts[PI_PHY_K_MAX];        */
802         PI_UINT32               port_ler_estimate[PI_PHY_K_MAX];
803         /*                              port_lem_reject_cts[PI_PHY_K_MAX];      */
804         /*                              port_lem_cts[PI_PHY_K_MAX];             */
805         PI_UINT32               port_ler_cutoff[PI_PHY_K_MAX];
806         PI_UINT32               port_ler_alarm[PI_PHY_K_MAX];
807         PI_UINT32               port_connect_state[PI_PHY_K_MAX];
808         PI_UINT32               port_pcm_state[PI_PHY_K_MAX];
809         PI_UINT32               port_pc_withhold[PI_PHY_K_MAX];
810         PI_UINT32               port_ler_condition[PI_PHY_K_MAX];
811         PI_UINT32               port_chip_set[PI_PHY_K_MAX];
812         PI_UINT32               port_action[PI_PHY_K_MAX];
813
814         /* ATTACHMENT GROUP */
815
816         PI_UINT32               attachment_class;
817         PI_UINT32               attachment_ob_present;
818         PI_UINT32               attachment_imax_expiration;
819         PI_UINT32               attachment_inserted_status;
820         PI_UINT32               attachment_insert_policy;
821
822         /* CHIP SET GROUP => Does not need to be implemented */
823
824         } PI_CMD_FDDI_MIB_GET_RSP;
825
826 /* DEC_Ext_MIB_Get Request */
827
828 typedef struct
829         {
830         PI_UINT32  cmd_type;
831         } PI_CMD_DEC_EXT_MIB_GET_REQ;
832
833 /* DEC_Ext_MIB_Get (efddi and efdx groups only) Response */
834
835 typedef struct
836         {
837         PI_RSP_HEADER   header;
838
839         /* SMT GROUP */
840
841         PI_UINT32               esmt_station_type;
842
843         /* MAC GROUP */
844
845         PI_UINT32               emac_link_state;
846         PI_UINT32               emac_ring_purger_state;
847         PI_UINT32               emac_ring_purger_enable;
848         PI_UINT32               emac_frame_strip_mode;
849         PI_UINT32               emac_ring_error_reason;
850         PI_UINT32               emac_up_nbr_dup_addr_flag;
851         PI_UINT32               emac_restricted_token_timeout;
852
853         /* PORT GROUP */
854
855         PI_UINT32               eport_pmd_type[PI_PHY_K_MAX];
856         PI_UINT32               eport_phy_state[PI_PHY_K_MAX];
857         PI_UINT32               eport_reject_reason[PI_PHY_K_MAX];
858
859         /* FDX (Full-Duplex) GROUP */
860
861         PI_UINT32               efdx_enable;                            /* Valid only in SMT 7.3 */
862         PI_UINT32               efdx_op;                                        /* Valid only in SMT 7.3 */
863         PI_UINT32               efdx_state;                                     /* Valid only in SMT 7.3 */
864
865         } PI_CMD_DEC_EXT_MIB_GET_RSP;
866
867 typedef struct
868         {
869         PI_CNTR         traces_rcvd;                                    /* Station */
870         PI_CNTR         frame_cnt;                                              /* Link */
871         PI_CNTR         error_cnt;
872         PI_CNTR         lost_cnt;
873         PI_CNTR         octets_rcvd;
874         PI_CNTR         octets_sent;
875         PI_CNTR         pdus_rcvd;
876         PI_CNTR         pdus_sent;
877         PI_CNTR         mcast_octets_rcvd;
878         PI_CNTR         mcast_octets_sent;
879         PI_CNTR         mcast_pdus_rcvd;
880         PI_CNTR         mcast_pdus_sent;
881         PI_CNTR         xmt_underruns;
882         PI_CNTR         xmt_failures;
883         PI_CNTR         block_check_errors;
884         PI_CNTR         frame_status_errors;
885         PI_CNTR         pdu_length_errors;
886         PI_CNTR         rcv_overruns;
887         PI_CNTR         user_buff_unavailable;
888         PI_CNTR         inits_initiated;
889         PI_CNTR         inits_rcvd;
890         PI_CNTR         beacons_initiated;
891         PI_CNTR         dup_addrs;
892         PI_CNTR         dup_tokens;
893         PI_CNTR         purge_errors;
894         PI_CNTR         fci_strip_errors;
895         PI_CNTR         traces_initiated;
896         PI_CNTR         directed_beacons_rcvd;
897         PI_CNTR         emac_frame_alignment_errors;
898         PI_CNTR         ebuff_errors[PI_PHY_K_MAX];             /* Phy */
899         PI_CNTR         lct_rejects[PI_PHY_K_MAX];
900         PI_CNTR         lem_rejects[PI_PHY_K_MAX];
901         PI_CNTR         link_errors[PI_PHY_K_MAX];
902         PI_CNTR         connections[PI_PHY_K_MAX];
903         PI_CNTR         copied_cnt;                                             /* Valid only if using SMT 7.3 */
904         PI_CNTR         transmit_cnt;                                   /* Valid only if using SMT 7.3 */
905         PI_CNTR         tokens;
906         } PI_CNTR_BLK;
907
908 /* Counters_Get Request */
909
910 typedef struct
911         {
912         PI_UINT32  cmd_type;
913         } PI_CMD_CNTRS_GET_REQ;
914
915 /* Counters_Get Response */
916
917 typedef struct
918         {
919         PI_RSP_HEADER   header;
920         PI_CNTR         time_since_reset;
921         PI_CNTR_BLK             cntrs;
922         } PI_CMD_CNTRS_GET_RSP;
923
924 /* Counters_Set Request */
925
926 typedef struct
927         {
928         PI_UINT32       cmd_type;
929         PI_CNTR_BLK     cntrs;
930         } PI_CMD_CNTRS_SET_REQ;
931
932 /* Counters_Set Response */
933
934 typedef struct
935         {
936         PI_RSP_HEADER   header;
937         } PI_CMD_CNTRS_SET_RSP;
938
939 /* Error_Log_Clear Request */
940
941 typedef struct
942         {
943         PI_UINT32  cmd_type;
944         } PI_CMD_ERROR_LOG_CLEAR_REQ;
945
946 /* Error_Log_Clear Response */
947
948 typedef struct
949         {
950         PI_RSP_HEADER   header;
951         } PI_CMD_ERROR_LOG_CLEAR_RSP;
952
953 /* Error_Log_Get Request */
954
955 #define PI_LOG_ENTRY_K_INDEX_MIN        0               /* Minimum index for entry */
956
957 typedef struct
958         {
959         PI_UINT32  cmd_type;
960         PI_UINT32  entry_index;
961         } PI_CMD_ERROR_LOG_GET_REQ;
962
963 /* Error_Log_Get Response */
964
965 #define PI_K_LOG_FW_SIZE                        111             /* Max number of fw longwords */
966 #define PI_K_LOG_DIAG_SIZE                      6               /* Max number of diag longwords */
967
968 typedef struct
969         {
970         struct
971                 {
972                 PI_UINT32       fru_imp_mask;
973                 PI_UINT32       test_id;
974                 PI_UINT32       reserved[PI_K_LOG_DIAG_SIZE];
975                 } diag;
976         PI_UINT32               fw[PI_K_LOG_FW_SIZE];
977         } PI_LOG_ENTRY;
978
979 typedef struct
980         {
981         PI_RSP_HEADER   header;
982         PI_UINT32               event_status;
983         PI_UINT32               caller_id;
984         PI_UINT32               timestamp_l;
985         PI_UINT32               timestamp_h;
986         PI_UINT32               write_count;
987         PI_LOG_ENTRY    entry_info;
988         } PI_CMD_ERROR_LOG_GET_RSP;
989
990 /* Define error log related constants and types.                                        */
991 /*   Not all of the caller id's can occur.  The only ones currently */
992 /*   implemented are: none, selftest, mfg, fw, console                          */
993
994 #define PI_LOG_EVENT_STATUS_K_VALID             0       /* Valid Event Status           */
995 #define PI_LOG_EVENT_STATUS_K_INVALID   1       /* Invalid Event Status         */
996 #define PI_LOG_CALLER_ID_K_NONE                 0       /* No caller                            */
997 #define PI_LOG_CALLER_ID_K_SELFTEST             1       /* Normal power-up selftest */
998 #define PI_LOG_CALLER_ID_K_MFG                  2       /* Mfg power-up selftest        */
999 #define PI_LOG_CALLER_ID_K_ONLINE               3       /* On-line diagnostics          */
1000 #define PI_LOG_CALLER_ID_K_HW                   4       /* Hardware                             */
1001 #define PI_LOG_CALLER_ID_K_FW                   5       /* Firmware                             */
1002 #define PI_LOG_CALLER_ID_K_CNS_HW               6       /* CNS firmware                         */
1003 #define PI_LOG_CALLER_ID_K_CNS_FW               7       /* CNS hardware                         */
1004 #define PI_LOG_CALLER_ID_K_CONSOLE              8   /* Console Caller Id                */
1005
1006 /*
1007  *  Place all DMA commands in the following request and response structures
1008  *  to simplify code.
1009  */
1010
1011 typedef union
1012         {
1013         PI_UINT32                                       cmd_type;
1014         PI_CMD_START_REQ                        start;
1015         PI_CMD_FILTERS_SET_REQ          filter_set;
1016         PI_CMD_FILTERS_GET_REQ          filter_get;
1017         PI_CMD_CHARS_SET_REQ            char_set;
1018         PI_CMD_ADDR_FILTER_SET_REQ      addr_filter_set;
1019         PI_CMD_ADDR_FILTER_GET_REQ      addr_filter_get;
1020         PI_CMD_STATUS_CHARS_GET_REQ     stat_char_get;
1021         PI_CMD_CNTRS_GET_REQ            cntrs_get;
1022         PI_CMD_CNTRS_SET_REQ            cntrs_set;
1023         PI_CMD_ERROR_LOG_CLEAR_REQ      error_log_clear;
1024         PI_CMD_ERROR_LOG_GET_REQ        error_log_read;
1025         PI_CMD_SNMP_SET_REQ                     snmp_set;
1026         PI_CMD_FDDI_MIB_GET_REQ         fddi_mib_get;
1027         PI_CMD_DEC_EXT_MIB_GET_REQ      dec_mib_get;
1028         PI_CMD_SMT_MIB_SET_REQ          smt_mib_set;
1029         PI_CMD_SMT_MIB_GET_REQ          smt_mib_get;
1030         char                                            pad[PI_CMD_REQ_K_SIZE_MAX];
1031         } PI_DMA_CMD_REQ;
1032
1033 typedef union
1034         {
1035         PI_RSP_HEADER                           header;
1036         PI_CMD_START_RSP                        start;
1037         PI_CMD_FILTERS_SET_RSP          filter_set;
1038         PI_CMD_FILTERS_GET_RSP          filter_get;
1039         PI_CMD_CHARS_SET_RSP            char_set;
1040         PI_CMD_ADDR_FILTER_SET_RSP      addr_filter_set;
1041         PI_CMD_ADDR_FILTER_GET_RSP      addr_filter_get;
1042         PI_CMD_STATUS_CHARS_GET_RSP     stat_char_get;
1043         PI_CMD_CNTRS_GET_RSP            cntrs_get;
1044         PI_CMD_CNTRS_SET_RSP            cntrs_set;
1045         PI_CMD_ERROR_LOG_CLEAR_RSP      error_log_clear;
1046         PI_CMD_ERROR_LOG_GET_RSP        error_log_get;
1047         PI_CMD_SNMP_SET_RSP                     snmp_set;
1048         PI_CMD_FDDI_MIB_GET_RSP         fddi_mib_get;
1049         PI_CMD_DEC_EXT_MIB_GET_RSP      dec_mib_get;
1050         PI_CMD_SMT_MIB_SET_RSP          smt_mib_set;
1051         PI_CMD_SMT_MIB_GET_RSP          smt_mib_get;
1052         char                                            pad[PI_CMD_RSP_K_SIZE_MAX];
1053         } PI_DMA_CMD_RSP;
1054
1055 typedef union
1056         {
1057         PI_DMA_CMD_REQ  request;
1058         PI_DMA_CMD_RSP  response;
1059         } PI_DMA_CMD_BUFFER;
1060
1061
1062 /* Define format of Consumer Block (resident in host memory) */
1063
1064 typedef struct
1065         {
1066         volatile PI_UINT32      xmt_rcv_data;
1067         volatile PI_UINT32      reserved_1;
1068         volatile PI_UINT32      smt_host;
1069         volatile PI_UINT32      reserved_2;
1070         volatile PI_UINT32      unsol;
1071         volatile PI_UINT32      reserved_3;
1072         volatile PI_UINT32      cmd_rsp;
1073         volatile PI_UINT32      reserved_4;
1074         volatile PI_UINT32      cmd_req;
1075         volatile PI_UINT32      reserved_5;
1076         } PI_CONSUMER_BLOCK;
1077
1078 #define PI_CONS_M_RCV_INDEX                     0x000000FF
1079 #define PI_CONS_M_XMT_INDEX                     0x00FF0000
1080 #define PI_CONS_V_RCV_INDEX                     0
1081 #define PI_CONS_V_XMT_INDEX                     16
1082
1083 /* Offsets into consumer block */
1084
1085 #define PI_CONS_BLK_K_XMT_RCV           0x00
1086 #define PI_CONS_BLK_K_SMT_HOST          0x08
1087 #define PI_CONS_BLK_K_UNSOL                     0x10
1088 #define PI_CONS_BLK_K_CMD_RSP           0x18
1089 #define PI_CONS_BLK_K_CMD_REQ           0x20
1090
1091 /* Offsets into descriptor block */
1092
1093 #define PI_DESCR_BLK_K_RCV_DATA         0x0000
1094 #define PI_DESCR_BLK_K_XMT_DATA         0x0800
1095 #define PI_DESCR_BLK_K_SMT_HOST         0x1000
1096 #define PI_DESCR_BLK_K_UNSOL            0x1200
1097 #define PI_DESCR_BLK_K_CMD_RSP          0x1280
1098 #define PI_DESCR_BLK_K_CMD_REQ          0x1300
1099
1100 /* Define format of a rcv descr (Rcv Data, Cmd Rsp, Unsolicited, SMT Host)   */
1101 /*   Note a field has been added for later versions of the PDQ to allow for  */
1102 /*   finer granularity of the rcv buffer alignment.  For backwards                       */
1103 /*   compatibility, the two bits (which allow the rcv buffer to be longword  */
1104 /*   aligned) have been added at the MBZ bits.  To support previous drivers, */
1105 /*   the MBZ definition is left intact.                                                                          */
1106
1107 typedef struct
1108         {
1109         PI_UINT32       long_0;
1110         PI_UINT32       long_1;
1111         } PI_RCV_DESCR;
1112
1113 #define PI_RCV_DESCR_M_SOP                      0x80000000
1114 #define PI_RCV_DESCR_M_SEG_LEN_LO       0x60000000
1115 #define PI_RCV_DESCR_M_MBZ                      0x60000000
1116 #define PI_RCV_DESCR_M_SEG_LEN          0x1F800000
1117 #define PI_RCV_DESCR_M_SEG_LEN_HI       0x1FF00000
1118 #define PI_RCV_DESCR_M_SEG_CNT          0x000F0000
1119 #define PI_RCV_DESCR_M_BUFF_HI          0x0000FFFF
1120
1121 #define PI_RCV_DESCR_V_SOP                      31
1122 #define PI_RCV_DESCR_V_SEG_LEN_LO       29
1123 #define PI_RCV_DESCR_V_MBZ                      29
1124 #define PI_RCV_DESCR_V_SEG_LEN          23
1125 #define PI_RCV_DESCR_V_SEG_LEN_HI       20
1126 #define PI_RCV_DESCR_V_SEG_CNT          16
1127 #define PI_RCV_DESCR_V_BUFF_HI          0
1128
1129 /* Define the format of a transmit descriptor (Xmt Data, Cmd Req) */
1130
1131 typedef struct
1132         {
1133         PI_UINT32       long_0;
1134         PI_UINT32       long_1;
1135         } PI_XMT_DESCR;
1136
1137 #define PI_XMT_DESCR_M_SOP                      0x80000000
1138 #define PI_XMT_DESCR_M_EOP                      0x40000000
1139 #define PI_XMT_DESCR_M_MBZ                      0x20000000
1140 #define PI_XMT_DESCR_M_SEG_LEN          0x1FFF0000
1141 #define PI_XMT_DESCR_M_BUFF_HI          0x0000FFFF
1142
1143 #define PI_XMT_DESCR_V_SOP                      31
1144 #define PI_XMT_DESCR_V_EOP                      30
1145 #define PI_XMT_DESCR_V_MBZ                      29
1146 #define PI_XMT_DESCR_V_SEG_LEN          16
1147 #define PI_XMT_DESCR_V_BUFF_HI          0
1148
1149 /* Define format of the Descriptor Block (resident in host memory) */
1150
1151 #define PI_RCV_DATA_K_NUM_ENTRIES                       256
1152 #define PI_XMT_DATA_K_NUM_ENTRIES                       256
1153 #define PI_SMT_HOST_K_NUM_ENTRIES                       64
1154 #define PI_UNSOL_K_NUM_ENTRIES                          16
1155 #define PI_CMD_RSP_K_NUM_ENTRIES                        16
1156 #define PI_CMD_REQ_K_NUM_ENTRIES                        16
1157
1158 typedef struct
1159         {
1160         PI_RCV_DESCR  rcv_data[PI_RCV_DATA_K_NUM_ENTRIES];
1161         PI_XMT_DESCR  xmt_data[PI_XMT_DATA_K_NUM_ENTRIES];
1162         PI_RCV_DESCR  smt_host[PI_SMT_HOST_K_NUM_ENTRIES];
1163         PI_RCV_DESCR  unsol[PI_UNSOL_K_NUM_ENTRIES];
1164         PI_RCV_DESCR  cmd_rsp[PI_CMD_RSP_K_NUM_ENTRIES];
1165         PI_XMT_DESCR  cmd_req[PI_CMD_REQ_K_NUM_ENTRIES];
1166         } PI_DESCR_BLOCK;
1167
1168 /* Define Port Registers - offsets from PDQ Base address */
1169
1170 #define PI_PDQ_K_REG_PORT_RESET                 0x00000000
1171 #define PI_PDQ_K_REG_HOST_DATA                  0x00000004
1172 #define PI_PDQ_K_REG_PORT_CTRL                  0x00000008
1173 #define PI_PDQ_K_REG_PORT_DATA_A                0x0000000C
1174 #define PI_PDQ_K_REG_PORT_DATA_B                0x00000010
1175 #define PI_PDQ_K_REG_PORT_STATUS                0x00000014
1176 #define PI_PDQ_K_REG_TYPE_0_STATUS              0x00000018
1177 #define PI_PDQ_K_REG_HOST_INT_ENB               0x0000001C
1178 #define PI_PDQ_K_REG_TYPE_2_PROD_NOINT  0x00000020
1179 #define PI_PDQ_K_REG_TYPE_2_PROD                0x00000024
1180 #define PI_PDQ_K_REG_CMD_RSP_PROD               0x00000028
1181 #define PI_PDQ_K_REG_CMD_REQ_PROD               0x0000002C
1182 #define PI_PDQ_K_REG_SMT_HOST_PROD      0x00000030
1183 #define PI_PDQ_K_REG_UNSOL_PROD                 0x00000034
1184
1185 /* Port Control Register - Command codes for primary commands */
1186
1187 #define PI_PCTRL_M_CMD_ERROR                    0x8000
1188 #define PI_PCTRL_M_BLAST_FLASH                  0x4000
1189 #define PI_PCTRL_M_HALT                                 0x2000
1190 #define PI_PCTRL_M_COPY_DATA                    0x1000
1191 #define PI_PCTRL_M_ERROR_LOG_START              0x0800
1192 #define PI_PCTRL_M_ERROR_LOG_READ               0x0400
1193 #define PI_PCTRL_M_XMT_DATA_FLUSH_DONE  0x0200
1194 #define PI_PCTRL_M_INIT                                 0x0100
1195 #define PI_PCTRL_M_INIT_START               0x0080
1196 #define PI_PCTRL_M_CONS_BLOCK                   0x0040
1197 #define PI_PCTRL_M_UNINIT                               0x0020
1198 #define PI_PCTRL_M_RING_MEMBER                  0x0010
1199 #define PI_PCTRL_M_MLA                                  0x0008
1200 #define PI_PCTRL_M_FW_REV_READ                  0x0004
1201 #define PI_PCTRL_M_DEV_SPECIFIC                 0x0002
1202 #define PI_PCTRL_M_SUB_CMD                              0x0001
1203
1204 /* Define sub-commands accessed via the PI_PCTRL_M_SUB_CMD command */
1205
1206 #define PI_SUB_CMD_K_LINK_UNINIT                0x0001
1207 #define PI_SUB_CMD_K_BURST_SIZE_SET             0x0002
1208 #define PI_SUB_CMD_K_PDQ_REV_GET                0x0004
1209 #define PI_SUB_CMD_K_HW_REV_GET                 0x0008
1210
1211 /* Define some Port Data B values */
1212
1213 #define PI_PDATA_B_DMA_BURST_SIZE_4             0               /* valid values for command */
1214 #define PI_PDATA_B_DMA_BURST_SIZE_8             1
1215 #define PI_PDATA_B_DMA_BURST_SIZE_16    2
1216 #define PI_PDATA_B_DMA_BURST_SIZE_32    3               /* not supported on PCI */
1217 #define PI_PDATA_B_DMA_BURST_SIZE_DEF   PI_PDATA_B_DMA_BURST_SIZE_16
1218
1219 /* Port Data A Reset state */
1220
1221 #define PI_PDATA_A_RESET_M_UPGRADE              0x00000001
1222 #define PI_PDATA_A_RESET_M_SOFT_RESET   0x00000002
1223 #define PI_PDATA_A_RESET_M_SKIP_ST              0x00000004
1224
1225 /* Read adapter MLA address port control command constants */
1226
1227 #define PI_PDATA_A_MLA_K_LO                             0
1228 #define PI_PDATA_A_MLA_K_HI                             1
1229
1230 /* Byte Swap values for init command */
1231
1232 #define PI_PDATA_A_INIT_M_DESC_BLK_ADDR                 0x0FFFFE000
1233 #define PI_PDATA_A_INIT_M_RESERVED                              0x000001FFC
1234 #define PI_PDATA_A_INIT_M_BSWAP_DATA                    0x000000002
1235 #define PI_PDATA_A_INIT_M_BSWAP_LITERAL                 0x000000001
1236
1237 #define PI_PDATA_A_INIT_V_DESC_BLK_ADDR                 13
1238 #define PI_PDATA_A_INIT_V_RESERVED                              3
1239 #define PI_PDATA_A_INIT_V_BSWAP_DATA                    1
1240 #define PI_PDATA_A_INIT_V_BSWAP_LITERAL                 0
1241
1242 /* Port Reset Register */
1243
1244 #define PI_RESET_M_ASSERT_RESET                 1
1245
1246 /* Port Status register */
1247
1248 #define PI_PSTATUS_V_RCV_DATA_PENDING   31
1249 #define PI_PSTATUS_V_XMT_DATA_PENDING   30
1250 #define PI_PSTATUS_V_SMT_HOST_PENDING   29
1251 #define PI_PSTATUS_V_UNSOL_PENDING              28
1252 #define PI_PSTATUS_V_CMD_RSP_PENDING    27
1253 #define PI_PSTATUS_V_CMD_REQ_PENDING    26
1254 #define PI_PSTATUS_V_TYPE_0_PENDING             25
1255 #define PI_PSTATUS_V_RESERVED_1                 16
1256 #define PI_PSTATUS_V_RESERVED_2                 11
1257 #define PI_PSTATUS_V_STATE                              8
1258 #define PI_PSTATUS_V_HALT_ID                    0
1259
1260 #define PI_PSTATUS_M_RCV_DATA_PENDING   0x80000000
1261 #define PI_PSTATUS_M_XMT_DATA_PENDING   0x40000000
1262 #define PI_PSTATUS_M_SMT_HOST_PENDING   0x20000000
1263 #define PI_PSTATUS_M_UNSOL_PENDING              0x10000000
1264 #define PI_PSTATUS_M_CMD_RSP_PENDING    0x08000000
1265 #define PI_PSTATUS_M_CMD_REQ_PENDING    0x04000000
1266 #define PI_PSTATUS_M_TYPE_0_PENDING             0x02000000
1267 #define PI_PSTATUS_M_RESERVED_1                 0x01FF0000
1268 #define PI_PSTATUS_M_RESERVED_2                 0x0000F800
1269 #define PI_PSTATUS_M_STATE                              0x00000700
1270 #define PI_PSTATUS_M_HALT_ID                    0x000000FF
1271
1272 /* Define Halt Id's                                                             */
1273 /*   Do not insert into this list, only append. */
1274
1275 #define PI_HALT_ID_K_SELFTEST_TIMEOUT   0
1276 #define PI_HALT_ID_K_PARITY_ERROR               1
1277 #define PI_HALT_ID_K_HOST_DIR_HALT              2
1278 #define PI_HALT_ID_K_SW_FAULT                   3
1279 #define PI_HALT_ID_K_HW_FAULT                   4
1280 #define PI_HALT_ID_K_PC_TRACE                   5
1281 #define PI_HALT_ID_K_DMA_ERROR                  6                       /* Host Data has error reg */
1282 #define PI_HALT_ID_K_IMAGE_CRC_ERROR    7               /* Image is bad, update it */
1283 #define PI_HALT_ID_K_BUS_EXCEPTION              8               /* 68K bus exception       */
1284
1285 /* Host Interrupt Enable Register as seen by host */
1286
1287 #define PI_HOST_INT_M_XMT_DATA_ENB              0x80000000      /* Type 2 Enables */
1288 #define PI_HOST_INT_M_RCV_DATA_ENB              0x40000000
1289 #define PI_HOST_INT_M_SMT_HOST_ENB              0x10000000      /* Type 1 Enables */
1290 #define PI_HOST_INT_M_UNSOL_ENB                 0x20000000
1291 #define PI_HOST_INT_M_CMD_RSP_ENB               0x08000000
1292 #define PI_HOST_INT_M_CMD_REQ_ENB               0x04000000
1293 #define PI_HOST_INT_M_TYPE_1_RESERVED   0x00FF0000
1294 #define PI_HOST_INT_M_TYPE_0_RESERVED   0x0000FF00      /* Type 0 Enables */
1295 #define PI_HOST_INT_M_1MS                               0x00000080
1296 #define PI_HOST_INT_M_20MS                              0x00000040
1297 #define PI_HOST_INT_M_CSR_CMD_DONE              0x00000020
1298 #define PI_HOST_INT_M_STATE_CHANGE              0x00000010
1299 #define PI_HOST_INT_M_XMT_FLUSH                 0x00000008
1300 #define PI_HOST_INT_M_NXM                               0x00000004
1301 #define PI_HOST_INT_M_PM_PAR_ERR                0x00000002
1302 #define PI_HOST_INT_M_BUS_PAR_ERR               0x00000001
1303
1304 #define PI_HOST_INT_V_XMT_DATA_ENB              31                      /* Type 2 Enables */
1305 #define PI_HOST_INT_V_RCV_DATA_ENB              30
1306 #define PI_HOST_INT_V_SMT_HOST_ENB              29                      /* Type 1 Enables */
1307 #define PI_HOST_INT_V_UNSOL_ENB                 28
1308 #define PI_HOST_INT_V_CMD_RSP_ENB               27
1309 #define PI_HOST_INT_V_CMD_REQ_ENB               26
1310 #define PI_HOST_INT_V_TYPE_1_RESERVED   16
1311 #define PI_HOST_INT_V_TYPE_0_RESERVED   8                       /* Type 0 Enables */
1312 #define PI_HOST_INT_V_1MS_ENB                   7
1313 #define PI_HOST_INT_V_20MS_ENB                  6
1314 #define PI_HOST_INT_V_CSR_CMD_DONE_ENB  5
1315 #define PI_HOST_INT_V_STATE_CHANGE_ENB  4
1316 #define PI_HOST_INT_V_XMT_FLUSH_ENB     3
1317 #define PI_HOST_INT_V_NXM_ENB                   2
1318 #define PI_HOST_INT_V_PM_PAR_ERR_ENB    1
1319 #define PI_HOST_INT_V_BUS_PAR_ERR_ENB   0
1320
1321 #define PI_HOST_INT_K_ACK_ALL_TYPE_0    0x000000FF
1322 #define PI_HOST_INT_K_DISABLE_ALL_INTS  0x00000000
1323 #define PI_HOST_INT_K_ENABLE_ALL_INTS   0xFFFFFFFF
1324 #define PI_HOST_INT_K_ENABLE_DEF_INTS   0xC000001F
1325
1326 /* Type 0 Interrupt Status Register */
1327
1328 #define PI_TYPE_0_STAT_M_1MS                    0x00000080
1329 #define PI_TYPE_0_STAT_M_20MS                   0x00000040
1330 #define PI_TYPE_0_STAT_M_CSR_CMD_DONE   0x00000020
1331 #define PI_TYPE_0_STAT_M_STATE_CHANGE   0x00000010
1332 #define PI_TYPE_0_STAT_M_XMT_FLUSH              0x00000008
1333 #define PI_TYPE_0_STAT_M_NXM                    0x00000004
1334 #define PI_TYPE_0_STAT_M_PM_PAR_ERR             0x00000002
1335 #define PI_TYPE_0_STAT_M_BUS_PAR_ERR    0x00000001
1336
1337 #define PI_TYPE_0_STAT_V_1MS                    7
1338 #define PI_TYPE_0_STAT_V_20MS                   6
1339 #define PI_TYPE_0_STAT_V_CSR_CMD_DONE   5
1340 #define PI_TYPE_0_STAT_V_STATE_CHANGE   4
1341 #define PI_TYPE_0_STAT_V_XMT_FLUSH              3
1342 #define PI_TYPE_0_STAT_V_NXM                    2
1343 #define PI_TYPE_0_STAT_V_PM_PAR_ERR             1
1344 #define PI_TYPE_0_STAT_V_BUS_PAR_ERR    0
1345
1346 /* Register definition structures are defined for both big and little endian systems */
1347
1348 #ifndef __BIG_ENDIAN
1349
1350 /* Little endian format of Type 1 Producer register */
1351
1352 typedef union
1353         {
1354         PI_UINT32       lword;
1355         struct
1356                 {
1357                 PI_UINT8        prod;
1358                 PI_UINT8        comp;
1359                 PI_UINT8        mbz_1;
1360                 PI_UINT8        mbz_2;
1361                 } index;
1362         } PI_TYPE_1_PROD_REG;
1363
1364 /* Little endian format of Type 2 Producer register */
1365
1366 typedef union
1367         {
1368         PI_UINT32       lword;
1369         struct
1370                 {
1371                 PI_UINT8        rcv_prod;
1372                 PI_UINT8        xmt_prod;
1373                 PI_UINT8        rcv_comp;
1374                 PI_UINT8        xmt_comp;
1375                 } index;
1376         } PI_TYPE_2_PROD_REG;
1377
1378 /* Little endian format of Type 1 Consumer Block longword */
1379
1380 typedef union
1381         {
1382         PI_UINT32       lword;
1383         struct
1384                 {
1385                 PI_UINT8        cons;
1386                 PI_UINT8        res0;
1387                 PI_UINT8        res1;
1388                 PI_UINT8        res2;
1389                 } index;
1390         } PI_TYPE_1_CONSUMER;
1391
1392 /* Little endian format of Type 2 Consumer Block longword */
1393
1394 typedef union
1395         {
1396         PI_UINT32       lword;
1397         struct
1398                 {
1399                 PI_UINT8        rcv_cons;
1400                 PI_UINT8        res0;
1401                 PI_UINT8        xmt_cons;
1402                 PI_UINT8        res1;
1403                 } index;
1404         } PI_TYPE_2_CONSUMER;
1405
1406 /* Define swapping required by DMA transfers.  */
1407 #define PI_PDATA_A_INIT_M_BSWAP_INIT    \
1408         (PI_PDATA_A_INIT_M_BSWAP_DATA)
1409
1410 #else /* __BIG_ENDIAN */
1411
1412 /* Big endian format of Type 1 Producer register */
1413
1414 typedef union
1415         {
1416         PI_UINT32       lword;
1417         struct
1418                 {
1419                 PI_UINT8        mbz_2;
1420                 PI_UINT8        mbz_1;
1421                 PI_UINT8        comp;
1422                 PI_UINT8        prod;
1423                 } index;
1424         } PI_TYPE_1_PROD_REG;
1425
1426 /* Big endian format of Type 2 Producer register */
1427
1428 typedef union
1429         {
1430         PI_UINT32       lword;
1431         struct
1432                 {
1433                 PI_UINT8        xmt_comp;
1434                 PI_UINT8        rcv_comp;
1435                 PI_UINT8        xmt_prod;
1436                 PI_UINT8        rcv_prod;
1437                 } index;
1438         } PI_TYPE_2_PROD_REG;
1439
1440 /* Big endian format of Type 1 Consumer Block longword */
1441
1442 typedef union
1443         {
1444         PI_UINT32       lword;
1445         struct
1446                 {
1447                 PI_UINT8        res2;
1448                 PI_UINT8        res1;
1449                 PI_UINT8        res0;
1450                 PI_UINT8        cons;
1451                 } index;
1452         } PI_TYPE_1_CONSUMER;
1453
1454 /* Big endian format of Type 2 Consumer Block longword */
1455
1456 typedef union
1457         {
1458         PI_UINT32       lword;
1459         struct
1460                 {
1461                 PI_UINT8        res1;
1462                 PI_UINT8        xmt_cons;
1463                 PI_UINT8        res0;
1464                 PI_UINT8        rcv_cons;
1465                 } index;
1466         } PI_TYPE_2_CONSUMER;
1467
1468 /* Define swapping required by DMA transfers.  */
1469 #define PI_PDATA_A_INIT_M_BSWAP_INIT    \
1470         (PI_PDATA_A_INIT_M_BSWAP_DATA | PI_PDATA_A_INIT_M_BSWAP_LITERAL)
1471
1472 #endif /* __BIG_ENDIAN */
1473
1474 /* Define EISA controller register offsets */
1475
1476 #define PI_ESIC_K_BURST_HOLDOFF         0x040
1477 #define PI_ESIC_K_SLOT_ID               0xC80
1478 #define PI_ESIC_K_SLOT_CNTRL            0xC84
1479 #define PI_ESIC_K_MEM_ADD_CMP_0         0xC85
1480 #define PI_ESIC_K_MEM_ADD_CMP_1         0xC86
1481 #define PI_ESIC_K_MEM_ADD_CMP_2         0xC87
1482 #define PI_ESIC_K_MEM_ADD_HI_CMP_0      0xC88
1483 #define PI_ESIC_K_MEM_ADD_HI_CMP_1      0xC89
1484 #define PI_ESIC_K_MEM_ADD_HI_CMP_2      0xC8A
1485 #define PI_ESIC_K_MEM_ADD_MASK_0        0xC8B
1486 #define PI_ESIC_K_MEM_ADD_MASK_1        0xC8C
1487 #define PI_ESIC_K_MEM_ADD_MASK_2        0xC8D
1488 #define PI_ESIC_K_MEM_ADD_LO_CMP_0      0xC8E
1489 #define PI_ESIC_K_MEM_ADD_LO_CMP_1      0xC8F
1490 #define PI_ESIC_K_MEM_ADD_LO_CMP_2      0xC90
1491 #define PI_ESIC_K_IO_CMP_0_0            0xC91
1492 #define PI_ESIC_K_IO_CMP_0_1            0xC92
1493 #define PI_ESIC_K_IO_CMP_1_0            0xC93
1494 #define PI_ESIC_K_IO_CMP_1_1            0xC94
1495 #define PI_ESIC_K_IO_CMP_2_0            0xC95
1496 #define PI_ESIC_K_IO_CMP_2_1            0xC96
1497 #define PI_ESIC_K_IO_CMP_3_0            0xC97
1498 #define PI_ESIC_K_IO_CMP_3_1            0xC98
1499 #define PI_ESIC_K_IO_ADD_MASK_0_0       0xC99
1500 #define PI_ESIC_K_IO_ADD_MASK_0_1       0xC9A
1501 #define PI_ESIC_K_IO_ADD_MASK_1_0       0xC9B
1502 #define PI_ESIC_K_IO_ADD_MASK_1_1       0xC9C
1503 #define PI_ESIC_K_IO_ADD_MASK_2_0       0xC9D
1504 #define PI_ESIC_K_IO_ADD_MASK_2_1       0xC9E
1505 #define PI_ESIC_K_IO_ADD_MASK_3_0       0xC9F
1506 #define PI_ESIC_K_IO_ADD_MASK_3_1       0xCA0
1507 #define PI_ESIC_K_MOD_CONFIG_1          0xCA1
1508 #define PI_ESIC_K_MOD_CONFIG_2          0xCA2
1509 #define PI_ESIC_K_MOD_CONFIG_3          0xCA3
1510 #define PI_ESIC_K_MOD_CONFIG_4          0xCA4
1511 #define PI_ESIC_K_MOD_CONFIG_5          0xCA5
1512 #define PI_ESIC_K_MOD_CONFIG_6          0xCA6
1513 #define PI_ESIC_K_MOD_CONFIG_7          0xCA7
1514 #define PI_ESIC_K_DIP_SWITCH            0xCA8
1515 #define PI_ESIC_K_IO_CONFIG_STAT_0      0xCA9
1516 #define PI_ESIC_K_IO_CONFIG_STAT_1      0xCAA
1517 #define PI_ESIC_K_DMA_CONFIG            0xCAB
1518 #define PI_ESIC_K_INPUT_PORT            0xCAC
1519 #define PI_ESIC_K_OUTPUT_PORT           0xCAD
1520 #define PI_ESIC_K_FUNCTION_CNTRL        0xCAE
1521 #define PI_ESIC_K_CSR_IO_LEN            PI_ESIC_K_FUNCTION_CNTRL+1      /* always last reg + 1 */
1522
1523 /* Define the value all drivers must write to the function control register. */
1524
1525 #define PI_ESIC_K_FUNCTION_CNTRL_IO_ENB 0x03
1526
1527 /* Define the bits in the slot control register. */
1528
1529 #define PI_SLOT_CNTRL_M_RESET           0x04    /* Don't use.       */
1530 #define PI_SLOT_CNTRL_M_ERROR           0x02    /* Not implemented. */
1531 #define PI_SLOT_CNTRL_M_ENB             0x01    /* Must be set.     */
1532
1533 /* Define the bits in the burst holdoff register. */
1534
1535 #define PI_BURST_HOLDOFF_M_HOLDOFF      0xFC
1536 #define PI_BURST_HOLDOFF_M_RESERVED     0x02
1537 #define PI_BURST_HOLDOFF_M_MEM_MAP      0x01
1538
1539 #define PI_BURST_HOLDOFF_V_HOLDOFF      2
1540 #define PI_BURST_HOLDOFF_V_RESERVED     1
1541 #define PI_BURST_HOLDOFF_V_MEM_MAP      0
1542
1543 /*
1544  * Define the fields in the IO Compare registers.
1545  * The driver must initialize the slot field with the slot ID shifted by the
1546  * amount shown below.
1547  */
1548
1549 #define PI_IO_CMP_V_SLOT                4
1550
1551 /* Define the fields in the Interrupt Channel Configuration and Status reg */
1552
1553 #define PI_CONFIG_STAT_0_M_PEND                 0x80
1554 #define PI_CONFIG_STAT_0_M_RES_1                0x40
1555 #define PI_CONFIG_STAT_0_M_IREQ_OUT             0x20
1556 #define PI_CONFIG_STAT_0_M_IREQ_IN              0x10
1557 #define PI_CONFIG_STAT_0_M_INT_ENB              0x08
1558 #define PI_CONFIG_STAT_0_M_RES_0                0x04
1559 #define PI_CONFIG_STAT_0_M_IRQ                  0x03
1560
1561 #define PI_CONFIG_STAT_0_V_PEND                 7
1562 #define PI_CONFIG_STAT_0_V_RES_1                6
1563 #define PI_CONFIG_STAT_0_V_IREQ_OUT             5
1564 #define PI_CONFIG_STAT_0_V_IREQ_IN              4
1565 #define PI_CONFIG_STAT_0_V_INT_ENB              3
1566 #define PI_CONFIG_STAT_0_V_RES_0                2
1567 #define PI_CONFIG_STAT_0_V_IRQ                  0
1568
1569 #define PI_CONFIG_STAT_0_IRQ_K_9                0
1570 #define PI_CONFIG_STAT_0_IRQ_K_10               1
1571 #define PI_CONFIG_STAT_0_IRQ_K_11               2
1572 #define PI_CONFIG_STAT_0_IRQ_K_15               3
1573
1574 /* Define DEC FDDIcontroller/EISA (DEFEA) EISA hardware ID's */
1575
1576 #define DEFEA_PRODUCT_ID        0x0030A310              /* DEC product 300 (no rev)     */
1577 #define DEFEA_PROD_ID_1         0x0130A310              /* DEC product 300, rev 1       */
1578 #define DEFEA_PROD_ID_2         0x0230A310              /* DEC product 300, rev 2       */
1579 #define DEFEA_PROD_ID_3         0x0330A310              /* DEC product 300, rev 3       */
1580
1581 /**********************************************/
1582 /* Digital PFI Specification v1.0 Definitions */
1583 /**********************************************/
1584
1585 /* PCI Configuration Space Constants */
1586
1587 #define PFI_K_LAT_TIMER_DEF                     0x88    /* def max master latency timer */
1588 #define PFI_K_LAT_TIMER_MIN                     0x20    /* min max master latency timer */
1589 #define PFI_K_CSR_MEM_LEN                       0x80    /* 128 bytes */
1590 #define PFI_K_CSR_IO_LEN                        0x80    /* 128 bytes */
1591 #define PFI_K_PKT_MEM_LEN                       0x10000 /* 64K bytes */
1592
1593 /* PFI Register Offsets (starting at PDQ Register Base Address) */
1594
1595 #define PFI_K_REG_RESERVED_0             0X00000038
1596 #define PFI_K_REG_RESERVED_1             0X0000003C
1597 #define PFI_K_REG_MODE_CTRL              0X00000040
1598 #define PFI_K_REG_STATUS                 0X00000044
1599 #define PFI_K_REG_FIFO_WRITE             0X00000048
1600 #define PFI_K_REG_FIFO_READ              0X0000004C
1601
1602 /* PFI Mode Control Register Constants */
1603
1604 #define PFI_MODE_M_RESERVED              0XFFFFFFF0
1605 #define PFI_MODE_M_TGT_ABORT_ENB         0X00000008
1606 #define PFI_MODE_M_PDQ_INT_ENB           0X00000004
1607 #define PFI_MODE_M_PFI_INT_ENB           0X00000002
1608 #define PFI_MODE_M_DMA_ENB               0X00000001
1609
1610 #define PFI_MODE_V_RESERVED              4
1611 #define PFI_MODE_V_TGT_ABORT_ENB         3
1612 #define PFI_MODE_V_PDQ_INT_ENB           2
1613 #define PFI_MODE_V_PFI_INT_ENB           1
1614 #define PFI_MODE_V_DMA_ENB               0
1615
1616 #define PFI_MODE_K_ALL_DISABLE           0X00000000
1617
1618 /* PFI Status Register Constants */
1619
1620 #define PFI_STATUS_M_RESERVED            0XFFFFFFC0
1621 #define PFI_STATUS_M_PFI_ERROR           0X00000020             /* only valid in rev 1 or later PFI */
1622 #define PFI_STATUS_M_PDQ_INT             0X00000010
1623 #define PFI_STATUS_M_PDQ_DMA_ABORT       0X00000008
1624 #define PFI_STATUS_M_FIFO_FULL           0X00000004
1625 #define PFI_STATUS_M_FIFO_EMPTY          0X00000002
1626 #define PFI_STATUS_M_DMA_IN_PROGRESS     0X00000001
1627
1628 #define PFI_STATUS_V_RESERVED            6
1629 #define PFI_STATUS_V_PFI_ERROR           5                      /* only valid in rev 1 or later PFI */
1630 #define PFI_STATUS_V_PDQ_INT             4
1631 #define PFI_STATUS_V_PDQ_DMA_ABORT       3
1632 #define PFI_STATUS_V_FIFO_FULL           2
1633 #define PFI_STATUS_V_FIFO_EMPTY          1
1634 #define PFI_STATUS_V_DMA_IN_PROGRESS 0
1635
1636 #define DFX_MAX_EISA_SLOTS              16                      /* maximum number of EISA slots to scan */
1637 #define DFX_MAX_NUM_BOARDS              8                       /* maximum number of adapters supported */
1638
1639 #define DFX_BUS_TYPE_PCI                0                       /* type code for DEC FDDIcontroller/PCI */
1640 #define DFX_BUS_TYPE_EISA               1                       /* type code for DEC FDDIcontroller/EISA */
1641
1642 #define DFX_FC_PRH2_PRH1_PRH0           0x54003820      /* Packet Request Header bytes + FC */
1643 #define DFX_PRH0_BYTE                   0x20            /* Packet Request Header byte 0 */
1644 #define DFX_PRH1_BYTE                   0x38            /* Packet Request Header byte 1 */
1645 #define DFX_PRH2_BYTE                   0x00            /* Packet Request Header byte 2 */
1646
1647 /* Driver routine status (return) codes */
1648
1649 #define DFX_K_SUCCESS                   0                       /* routine succeeded */
1650 #define DFX_K_FAILURE                   1                       /* routine failed */
1651 #define DFX_K_OUTSTATE                  2                       /* bad state for command */
1652 #define DFX_K_HW_TIMEOUT                3                       /* command timed out */
1653
1654 /* Define LLC host receive buffer min/max/default values */
1655
1656 #define RCV_BUFS_MIN    2                                       /* minimum pre-allocated receive buffers */
1657 #define RCV_BUFS_MAX    32                                      /* maximum pre-allocated receive buffers */
1658 #define RCV_BUFS_DEF    8                                       /* default pre-allocated receive buffers */
1659
1660 /* Define offsets into FDDI LLC or SMT receive frame buffers - used when indicating frames */
1661
1662 #define RCV_BUFF_K_DESCR        0                               /* four byte FMC descriptor */
1663 #define RCV_BUFF_K_PADDING      4                               /* three null bytes */
1664 #define RCV_BUFF_K_FC           7                               /* one byte frame control */
1665 #define RCV_BUFF_K_DA           8                               /* six byte destination address */
1666 #define RCV_BUFF_K_SA           14                              /* six byte source address */
1667 #define RCV_BUFF_K_DATA         20                              /* offset to start of packet data */
1668
1669 /* Define offsets into FDDI LLC transmit frame buffers - used when sending frames */
1670
1671 #define XMT_BUFF_K_FC           0                               /* one byte frame control */
1672 #define XMT_BUFF_K_DA           1                               /* six byte destination address */
1673 #define XMT_BUFF_K_SA           7                               /* six byte source address */
1674 #define XMT_BUFF_K_DATA         13                              /* offset to start of packet data */
1675
1676 /* Macro for checking a "value" is within a specific range */
1677
1678 #define IN_RANGE(value,low,high) ((value >= low) && (value <= high))
1679
1680 /* Only execute special print call when debug driver was built */
1681
1682 #ifdef DEFXX_DEBUG
1683 #define DBG_printk(args...) printk(## args)
1684 #else
1685 #define DBG_printk(args...)
1686 #endif
1687
1688 /* Define constants for masking/unmasking interrupts */
1689
1690 #define DFX_MASK_INTERRUPTS             1
1691 #define DFX_UNMASK_INTERRUPTS           0
1692
1693 /* Define structure for driver transmit descriptor block */
1694
1695 typedef struct
1696         {
1697         struct sk_buff  *p_skb;                                 /* ptr to skb */
1698         } XMT_DRIVER_DESCR;
1699
1700 typedef struct DFX_board_tag
1701         {
1702         /* Keep virtual and physical pointers to locked, physically contiguous memory */
1703
1704         char                            *kmalloced;                                     /* pci_free_consistent this on unload */
1705         dma_addr_t                      kmalloced_dma;
1706         /* DMA handle for the above */
1707         PI_DESCR_BLOCK                  *descr_block_virt;                              /* PDQ descriptor block virt address */
1708         dma_addr_t                      descr_block_phys;                               /* PDQ descriptor block phys address */
1709         PI_DMA_CMD_REQ                  *cmd_req_virt;                                  /* Command request buffer virt address */
1710         dma_addr_t                      cmd_req_phys;                                   /* Command request buffer phys address */
1711         PI_DMA_CMD_RSP                  *cmd_rsp_virt;                                  /* Command response buffer virt address */
1712         dma_addr_t                      cmd_rsp_phys;                                   /* Command response buffer phys address */
1713         char                            *rcv_block_virt;                                /* LLC host receive queue buf blk virt */
1714         dma_addr_t                      rcv_block_phys;                                 /* LLC host receive queue buf blk phys */
1715         PI_CONSUMER_BLOCK               *cons_block_virt;                               /* PDQ consumer block virt address */
1716         dma_addr_t                      cons_block_phys;                                /* PDQ consumer block phys address */
1717
1718         /* Keep local copies of Type 1 and Type 2 register data */
1719
1720         PI_TYPE_1_PROD_REG              cmd_req_reg;                                    /* Command Request register */
1721         PI_TYPE_1_PROD_REG              cmd_rsp_reg;                                    /* Command Response register */
1722         PI_TYPE_2_PROD_REG              rcv_xmt_reg;                                    /* Type 2 (RCV/XMT) register */
1723
1724         /* Storage for unicast and multicast address entries in adapter CAM */
1725
1726         u8                              uc_table[1*FDDI_K_ALEN];
1727         u32                             uc_count;                                               /* number of unicast addresses */
1728         u8                              mc_table[PI_CMD_ADDR_FILTER_K_SIZE*FDDI_K_ALEN];
1729         u32                             mc_count;                                               /* number of multicast addresses */
1730
1731         /* Current packet filter settings */
1732
1733         u32                             ind_group_prom;                                 /* LLC individual & group frame prom mode */
1734         u32                             group_prom;                                     /* LLC group (multicast) frame prom mode */
1735
1736         /* Link available flag needed to determine whether to drop outgoing packet requests */
1737
1738         u32                             link_available;                                 /* is link available? */
1739
1740         /* Resources to indicate reset type when resetting adapter */
1741
1742         u32                             reset_type;                                     /* skip or rerun diagnostics */
1743
1744         /* Store pointers to receive buffers for queue processing code */
1745
1746         char                            *p_rcv_buff_va[PI_RCV_DATA_K_NUM_ENTRIES];
1747
1748         /* Store pointers to transmit buffers for transmit completion code */
1749
1750         XMT_DRIVER_DESCR                xmt_drv_descr_blk[PI_XMT_DATA_K_NUM_ENTRIES];
1751
1752         /* Transmit spinlocks */
1753
1754         spinlock_t                      lock;
1755
1756         /* Store device, bus-specific, and parameter information for this adapter */
1757
1758         struct net_device               *dev;                                           /* pointer to device structure */
1759         struct net_device               *next;
1760         u32                             bus_type;                                       /* bus type (0 == PCI, 1 == EISA) */
1761         u16                             base_addr;                                      /* base I/O address (same as dev->base_addr) */
1762         struct pci_dev *                pci_dev;
1763         u32                             full_duplex_enb;                                /* FDDI Full Duplex enable (1 == on, 2 == off) */
1764         u32                             req_ttrt;                                       /* requested TTRT value (in 80ns units) */
1765         u32                             burst_size;                                     /* adapter burst size (enumerated) */
1766         u32                             rcv_bufs_to_post;                               /* receive buffers to post for LLC host queue */
1767         u8                              factory_mac_addr[FDDI_K_ALEN];                  /* factory (on-board) MAC address */
1768
1769         /* Common FDDI statistics structure and private counters */
1770
1771         struct fddi_statistics  stats;
1772
1773         u32                             rcv_discards;
1774         u32                             rcv_crc_errors;
1775         u32                             rcv_frame_status_errors;
1776         u32                             rcv_length_errors;
1777         u32                             rcv_total_frames;
1778         u32                             rcv_multicast_frames;
1779         u32                             rcv_total_bytes;
1780
1781         u32                             xmt_discards;
1782         u32                             xmt_length_errors;
1783         u32                             xmt_total_frames;
1784         u32                             xmt_total_bytes;
1785         } DFX_board_t;
1786
1787 #endif  /* #ifndef _DEFXX_H_ */