drivers/net/can/bfin_can.c

   1 /*
   2  * Blackfin On-Chip CAN Driver
   3  *
   4  * Copyright 2004-2009 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/init.h>
  13 #include <linux/kernel.h>
  14 #include <linux/bitops.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/errno.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/skbuff.h>
  19 #include <linux/platform_device.h>
  20
  21 #include <linux/can.h>
  22 #include <linux/can/dev.h>
  23 #include <linux/can/error.h>
  24
  25 #include <asm/portmux.h>
  26
  27 #define DRV_NAME "bfin_can"
  28 #define BFIN_CAN_TIMEOUT 100
  29
  30 /*
  31  * transmit and receive channels
  32  */
  33 #define TRANSMIT_CHL            24
  34 #define RECEIVE_STD_CHL         0
  35 #define RECEIVE_EXT_CHL         4
  36 #define RECEIVE_RTR_CHL         8
  37 #define RECEIVE_EXT_RTR_CHL     12
  38 #define MAX_CHL_NUMBER          32
  39
  40 /*
  41  * bfin can registers layout
  42  */
  43 struct bfin_can_mask_regs {
  44         u16 aml;
  45         u16 dummy1;
  46         u16 amh;
  47         u16 dummy2;
  48 };
  49
  50 struct bfin_can_channel_regs {
  51         u16 data[8];
  52         u16 dlc;
  53         u16 dummy1;
  54         u16 tsv;
  55         u16 dummy2;
  56         u16 id0;
  57         u16 dummy3;
  58         u16 id1;
  59         u16 dummy4;
  60 };
  61
  62 struct bfin_can_regs {
  63         /*
  64          * global control and status registers
  65          */
  66         u16 mc1;           /* offset 0 */
  67         u16 dummy1;
  68         u16 md1;           /* offset 4 */
  69         u16 rsv1[13];
  70         u16 mbtif1;        /* offset 0x20 */
  71         u16 dummy2;
  72         u16 mbrif1;        /* offset 0x24 */
  73         u16 dummy3;
  74         u16 mbim1;         /* offset 0x28 */
  75         u16 rsv2[11];
  76         u16 mc2;           /* offset 0x40 */
  77         u16 dummy4;
  78         u16 md2;           /* offset 0x44 */
  79         u16 dummy5;
  80         u16 trs2;          /* offset 0x48 */
  81         u16 rsv3[11];
  82         u16 mbtif2;        /* offset 0x60 */
  83         u16 dummy6;
  84         u16 mbrif2;        /* offset 0x64 */
  85         u16 dummy7;
  86         u16 mbim2;         /* offset 0x68 */
  87         u16 rsv4[11];
  88         u16 clk;           /* offset 0x80 */
  89         u16 dummy8;
  90         u16 timing;        /* offset 0x84 */
  91         u16 rsv5[3];
  92         u16 status;        /* offset 0x8c */
  93         u16 dummy9;
  94         u16 cec;           /* offset 0x90 */
  95         u16 dummy10;
  96         u16 gis;           /* offset 0x94 */
  97         u16 dummy11;
  98         u16 gim;           /* offset 0x98 */
  99         u16 rsv6[3];
 100         u16 ctrl;          /* offset 0xa0 */
 101         u16 dummy12;
 102         u16 intr;          /* offset 0xa4 */
 103         u16 rsv7[7];
 104         u16 esr;           /* offset 0xb4 */
 105         u16 rsv8[37];
 106
 107         /*
 108          * channel(mailbox) mask and message registers
 109          */
 110         struct bfin_can_mask_regs msk[MAX_CHL_NUMBER];    /* offset 0x100 */
 111         struct bfin_can_channel_regs chl[MAX_CHL_NUMBER]; /* offset 0x200 */
 112 };
 113
 114 /*
 115  * bfin can private data
 116  */
 117 struct bfin_can_priv {
 118         struct can_priv can;    /* must be the first member */
 119         struct net_device *dev;
 120         void __iomem *membase;
 121         int rx_irq;
 122         int tx_irq;
 123         int err_irq;
 124         unsigned short *pin_list;
 125 };
 126
 127 /*
 128  * bfin can timing parameters
 129  */
 130 static struct can_bittiming_const bfin_can_bittiming_const = {
 131         .name = DRV_NAME,
 132         .tseg1_min = 1,
 133         .tseg1_max = 16,
 134         .tseg2_min = 1,
 135         .tseg2_max = 8,
 136         .sjw_max = 4,
 137         /*
 138          * Although the BRP field can be set to any value, it is recommended
 139          * that the value be greater than or equal to 4, as restrictions
 140          * apply to the bit timing configuration when BRP is less than 4.
 141          */
 142         .brp_min = 4,
 143         .brp_max = 1024,
 144         .brp_inc = 1,
 145 };
 146
 147 static int bfin_can_set_bittiming(struct net_device *dev)
 148 {
 149         struct bfin_can_priv *priv = netdev_priv(dev);
 150         struct bfin_can_regs __iomem *reg = priv->membase;
 151         struct can_bittiming *bt = &priv->can.bittiming;
 152         u16 clk, timing;
 153
 154         clk = bt->brp - 1;
 155         timing = ((bt->sjw - 1) << 8) | (bt->prop_seg + bt->phase_seg1 - 1) |
 156                 ((bt->phase_seg2 - 1) << 4);
 157
 158         /*
 159          * If the SAM bit is set, the input signal is oversampled three times
 160          * at the SCLK rate.
 161          */
 162         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
 163                 timing |= SAM;
 164
 165         bfin_write16(&reg->clk, clk);
 166         bfin_write16(&reg->timing, timing);
 167
 168         dev_info(dev->dev.parent, "setting CLOCK=0x%04x TIMING=0x%04x\n",
 169                         clk, timing);
 170
 171         return 0;
 172 }
 173
 174 static void bfin_can_set_reset_mode(struct net_device *dev)
 175 {
 176         struct bfin_can_priv *priv = netdev_priv(dev);
 177         struct bfin_can_regs __iomem *reg = priv->membase;
 178         int timeout = BFIN_CAN_TIMEOUT;
 179         int i;
 180
 181         /* disable interrupts */
 182         bfin_write16(&reg->mbim1, 0);
 183         bfin_write16(&reg->mbim2, 0);
 184         bfin_write16(&reg->gim, 0);
 185
 186         /* reset can and enter configuration mode */
 187         bfin_write16(&reg->ctrl, SRS | CCR);
 188         SSYNC();
 189         bfin_write16(&reg->ctrl, CCR);
 190         SSYNC();
 191         while (!(bfin_read16(&reg->ctrl) & CCA)) {
 192                 udelay(10);
 193                 if (--timeout == 0) {
 194                         dev_err(dev->dev.parent,
 195                                         "fail to enter configuration mode\n");
 196                         BUG();
 197                 }
 198         }
 199
 200         /*
 201          * All mailbox configurations are marked as inactive
 202          * by writing to CAN Mailbox Configuration Registers 1 and 2
 203          * For all bits: 0 - Mailbox disabled, 1 - Mailbox enabled
 204          */
 205         bfin_write16(&reg->mc1, 0);
 206         bfin_write16(&reg->mc2, 0);
 207
 208         /* Set Mailbox Direction */
 209         bfin_write16(&reg->md1, 0xFFFF);   /* mailbox 1-16 are RX */
 210         bfin_write16(&reg->md2, 0);   /* mailbox 17-32 are TX */
 211
 212         /* RECEIVE_STD_CHL */
 213         for (i = 0; i < 2; i++) {
 214                 bfin_write16(&reg->chl[RECEIVE_STD_CHL + i].id0, 0);
 215                 bfin_write16(&reg->chl[RECEIVE_STD_CHL + i].id1, AME);
 216                 bfin_write16(&reg->chl[RECEIVE_STD_CHL + i].dlc, 0);
 217                 bfin_write16(&reg->msk[RECEIVE_STD_CHL + i].amh, 0x1FFF);
 218                 bfin_write16(&reg->msk[RECEIVE_STD_CHL + i].aml, 0xFFFF);
 219         }
 220
 221         /* RECEIVE_EXT_CHL */
 222         for (i = 0; i < 2; i++) {
 223                 bfin_write16(&reg->chl[RECEIVE_EXT_CHL + i].id0, 0);
 224                 bfin_write16(&reg->chl[RECEIVE_EXT_CHL + i].id1, AME | IDE);
 225                 bfin_write16(&reg->chl[RECEIVE_EXT_CHL + i].dlc, 0);
 226                 bfin_write16(&reg->msk[RECEIVE_EXT_CHL + i].amh, 0x1FFF);
 227                 bfin_write16(&reg->msk[RECEIVE_EXT_CHL + i].aml, 0xFFFF);
 228         }
 229
 230         bfin_write16(&reg->mc2, BIT(TRANSMIT_CHL - 16));
 231         bfin_write16(&reg->mc1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL));
 232         SSYNC();
 233
 234         priv->can.state = CAN_STATE_STOPPED;
 235 }
 236
 237 static void bfin_can_set_normal_mode(struct net_device *dev)
 238 {
 239         struct bfin_can_priv *priv = netdev_priv(dev);
 240         struct bfin_can_regs __iomem *reg = priv->membase;
 241         int timeout = BFIN_CAN_TIMEOUT;
 242
 243         /*
 244          * leave configuration mode
 245          */
 246         bfin_write16(&reg->ctrl, bfin_read16(&reg->ctrl) & ~CCR);
 247
 248         while (bfin_read16(&reg->status) & CCA) {
 249                 udelay(10);
 250                 if (--timeout == 0) {
 251                         dev_err(dev->dev.parent,
 252                                         "fail to leave configuration mode\n");
 253                         BUG();
 254                 }
 255         }
 256
 257         /*
 258          * clear _All_  tx and rx interrupts
 259          */
 260         bfin_write16(&reg->mbtif1, 0xFFFF);
 261         bfin_write16(&reg->mbtif2, 0xFFFF);
 262         bfin_write16(&reg->mbrif1, 0xFFFF);
 263         bfin_write16(&reg->mbrif2, 0xFFFF);
 264
 265         /*
 266          * clear global interrupt status register
 267          */
 268         bfin_write16(&reg->gis, 0x7FF); /* overwrites with '1' */
 269
 270         /*
 271          * Initialize Interrupts
 272          * - set bits in the mailbox interrupt mask register
 273          * - global interrupt mask
 274          */
 275         bfin_write16(&reg->mbim1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL));
 276         bfin_write16(&reg->mbim2, BIT(TRANSMIT_CHL - 16));
 277
 278         bfin_write16(&reg->gim, EPIM | BOIM | RMLIM);
 279         SSYNC();
 280 }
 281
 282 static void bfin_can_start(struct net_device *dev)
 283 {
 284         struct bfin_can_priv *priv = netdev_priv(dev);
 285
 286         /* enter reset mode */
 287         if (priv->can.state != CAN_STATE_STOPPED)
 288                 bfin_can_set_reset_mode(dev);
 289
 290         /* leave reset mode */
 291         bfin_can_set_normal_mode(dev);
 292 }
 293
 294 static int bfin_can_set_mode(struct net_device *dev, enum can_mode mode)
 295 {
 296         switch (mode) {
 297         case CAN_MODE_START:
 298                 bfin_can_start(dev);
 299                 if (netif_queue_stopped(dev))
 300                         netif_wake_queue(dev);
 301                 break;
 302
 303         default:
 304                 return -EOPNOTSUPP;
 305         }
 306
 307         return 0;
 308 }
 309
 310 static int bfin_can_start_xmit(struct sk_buff *skb, struct net_device *dev)
 311 {
 312         struct bfin_can_priv *priv = netdev_priv(dev);
 313         struct bfin_can_regs __iomem *reg = priv->membase;
 314         struct can_frame *cf = (struct can_frame *)skb->data;
 315         u8 dlc = cf->can_dlc;
 316         canid_t id = cf->can_id;
 317         u8 *data = cf->data;
 318         u16 val;
 319         int i;
 320
 321         netif_stop_queue(dev);
 322
 323         /* fill id */
 324         if (id & CAN_EFF_FLAG) {
 325                 bfin_write16(&reg->chl[TRANSMIT_CHL].id0, id);
 326                 if (id & CAN_RTR_FLAG)
 327                         writew(((id & 0x1FFF0000) >> 16) | IDE | AME | RTR,
 328                                         &reg->chl[TRANSMIT_CHL].id1);
 329                 else
 330                         writew(((id & 0x1FFF0000) >> 16) | IDE | AME,
 331                                         &reg->chl[TRANSMIT_CHL].id1);
 332
 333         } else {
 334                 if (id & CAN_RTR_FLAG)
 335                         writew((id << 2) | AME | RTR,
 336                                 &reg->chl[TRANSMIT_CHL].id1);
 337                 else
 338                         bfin_write16(&reg->chl[TRANSMIT_CHL].id1,
 339                                         (id << 2) | AME);
 340         }
 341
 342         /* fill payload */
 343         for (i = 0; i < 8; i += 2) {
 344                 val = ((7 - i) < dlc ? (data[7 - i]) : 0) +
 345                         ((6 - i) < dlc ? (data[6 - i] << 8) : 0);
 346                 bfin_write16(&reg->chl[TRANSMIT_CHL].data[i], val);
 347         }
 348
 349         /* fill data length code */
 350         bfin_write16(&reg->chl[TRANSMIT_CHL].dlc, dlc);
 351
 352         dev->trans_start = jiffies;
 353
 354         can_put_echo_skb(skb, dev, 0);
 355
 356         /* set transmit request */
 357         bfin_write16(&reg->trs2, BIT(TRANSMIT_CHL - 16));
 358
 359         return 0;
 360 }
 361
 362 static void bfin_can_rx(struct net_device *dev, u16 isrc)
 363 {
 364         struct bfin_can_priv *priv = netdev_priv(dev);
 365         struct net_device_stats *stats = &dev->stats;
 366         struct bfin_can_regs __iomem *reg = priv->membase;
 367         struct can_frame *cf;
 368         struct sk_buff *skb;
 369         int obj;
 370         int i;
 371         u16 val;
 372
 373         skb = alloc_can_skb(dev, &cf);
 374         if (skb == NULL)
 375                 return;
 376
 377         /* get id */
 378         if (isrc & BIT(RECEIVE_EXT_CHL)) {
 379                 /* extended frame format (EFF) */
 380                 cf->can_id = ((bfin_read16(&reg->chl[RECEIVE_EXT_CHL].id1)
 381                              & 0x1FFF) << 16)
 382                              + bfin_read16(&reg->chl[RECEIVE_EXT_CHL].id0);
 383                 cf->can_id |= CAN_EFF_FLAG;
 384                 obj = RECEIVE_EXT_CHL;
 385         } else {
 386                 /* standard frame format (SFF) */
 387                 cf->can_id = (bfin_read16(&reg->chl[RECEIVE_STD_CHL].id1)
 388                              & 0x1ffc) >> 2;
 389                 obj = RECEIVE_STD_CHL;
 390         }
 391         if (bfin_read16(&reg->chl[obj].id1) & RTR)
 392                 cf->can_id |= CAN_RTR_FLAG;
 393
 394         /* get data length code */
 395         cf->can_dlc = bfin_read16(&reg->chl[obj].dlc);
 396
 397         /* get payload */
 398         for (i = 0; i < 8; i += 2) {
 399                 val = bfin_read16(&reg->chl[obj].data[i]);
 400                 cf->data[7 - i] = (7 - i) < cf->can_dlc ? val : 0;
 401                 cf->data[6 - i] = (6 - i) < cf->can_dlc ? (val >> 8) : 0;
 402         }
 403
 404         netif_rx(skb);
 405
 406         stats->rx_packets++;
 407         stats->rx_bytes += cf->can_dlc;
 408 }
 409
 410 static int bfin_can_err(struct net_device *dev, u16 isrc, u16 status)
 411 {
 412         struct bfin_can_priv *priv = netdev_priv(dev);
 413         struct bfin_can_regs __iomem *reg = priv->membase;
 414         struct net_device_stats *stats = &dev->stats;
 415         struct can_frame *cf;
 416         struct sk_buff *skb;
 417         enum can_state state = priv->can.state;
 418
 419         skb = alloc_can_err_skb(dev, &cf);
 420         if (skb == NULL)
 421                 return -ENOMEM;
 422
 423         if (isrc & RMLIS) {
 424                 /* data overrun interrupt */
 425                 dev_dbg(dev->dev.parent, "data overrun interrupt\n");
 426                 cf->can_id |= CAN_ERR_CRTL;
 427                 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
 428                 stats->rx_over_errors++;
 429                 stats->rx_errors++;
 430         }
 431
 432         if (isrc & BOIS) {
 433                 dev_dbg(dev->dev.parent, "bus-off mode interrupt\n");
 434                 state = CAN_STATE_BUS_OFF;
 435                 cf->can_id |= CAN_ERR_BUSOFF;
 436                 can_bus_off(dev);
 437         }
 438
 439         if (isrc & EPIS) {
 440                 /* error passive interrupt */
 441                 dev_dbg(dev->dev.parent, "error passive interrupt\n");
 442                 state = CAN_STATE_ERROR_PASSIVE;
 443         }
 444
 445         if ((isrc & EWTIS) || (isrc & EWRIS)) {
 446                 dev_dbg(dev->dev.parent,
 447                                 "Error Warning Transmit/Receive Interrupt\n");
 448                 state = CAN_STATE_ERROR_WARNING;
 449         }
 450
 451         if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING ||
 452                                 state == CAN_STATE_ERROR_PASSIVE)) {
 453                 u16 cec = bfin_read16(&reg->cec);
 454                 u8 rxerr = cec;
 455                 u8 txerr = cec >> 8;
 456
 457                 cf->can_id |= CAN_ERR_CRTL;
 458                 if (state == CAN_STATE_ERROR_WARNING) {
 459                         priv->can.can_stats.error_warning++;
 460                         cf->data[1] = (txerr > rxerr) ?
 461                                 CAN_ERR_CRTL_TX_WARNING :
 462                                 CAN_ERR_CRTL_RX_WARNING;
 463                 } else {
 464                         priv->can.can_stats.error_passive++;
 465                         cf->data[1] = (txerr > rxerr) ?
 466                                 CAN_ERR_CRTL_TX_PASSIVE :
 467                                 CAN_ERR_CRTL_RX_PASSIVE;
 468                 }
 469         }
 470
 471         if (status) {
 472                 priv->can.can_stats.bus_error++;
 473
 474                 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 475
 476                 if (status & BEF)
 477                         cf->data[2] |= CAN_ERR_PROT_BIT;
 478                 else if (status & FER)
 479                         cf->data[2] |= CAN_ERR_PROT_FORM;
 480                 else if (status & SER)
 481                         cf->data[2] |= CAN_ERR_PROT_STUFF;
 482                 else
 483                         cf->data[2] |= CAN_ERR_PROT_UNSPEC;
 484         }
 485
 486         priv->can.state = state;
 487
 488         netif_rx(skb);
 489
 490         stats->rx_packets++;
 491         stats->rx_bytes += cf->can_dlc;
 492
 493         return 0;
 494 }
 495
 496 irqreturn_t bfin_can_interrupt(int irq, void *dev_id)
 497 {
 498         struct net_device *dev = dev_id;
 499         struct bfin_can_priv *priv = netdev_priv(dev);
 500         struct bfin_can_regs __iomem *reg = priv->membase;
 501         struct net_device_stats *stats = &dev->stats;
 502         u16 status, isrc;
 503
 504         if ((irq == priv->tx_irq) && bfin_read16(&reg->mbtif2)) {
 505                 /* transmission complete interrupt */
 506                 bfin_write16(&reg->mbtif2, 0xFFFF);
 507                 stats->tx_packets++;
 508                 stats->tx_bytes += bfin_read16(&reg->chl[TRANSMIT_CHL].dlc);
 509                 can_get_echo_skb(dev, 0);
 510                 netif_wake_queue(dev);
 511         } else if ((irq == priv->rx_irq) && bfin_read16(&reg->mbrif1)) {
 512                 /* receive interrupt */
 513                 isrc = bfin_read16(&reg->mbrif1);
 514                 bfin_write16(&reg->mbrif1, 0xFFFF);
 515                 bfin_can_rx(dev, isrc);
 516         } else if ((irq == priv->err_irq) && bfin_read16(&reg->gis)) {
 517                 /* error interrupt */
 518                 isrc = bfin_read16(&reg->gis);
 519                 status = bfin_read16(&reg->esr);
 520                 bfin_write16(&reg->gis, 0x7FF);
 521                 bfin_can_err(dev, isrc, status);
 522         } else {
 523                 return IRQ_NONE;
 524         }
 525
 526         return IRQ_HANDLED;
 527 }
 528
 529 static int bfin_can_open(struct net_device *dev)
 530 {
 531         struct bfin_can_priv *priv = netdev_priv(dev);
 532         int err;
 533
 534         /* set chip into reset mode */
 535         bfin_can_set_reset_mode(dev);
 536
 537         /* common open */
 538         err = open_candev(dev);
 539         if (err)
 540                 goto exit_open;
 541
 542         /* register interrupt handler */
 543         err = request_irq(priv->rx_irq, &bfin_can_interrupt, 0,
 544                         "bfin-can-rx", dev);
 545         if (err)
 546                 goto exit_rx_irq;
 547         err = request_irq(priv->tx_irq, &bfin_can_interrupt, 0,
 548                         "bfin-can-tx", dev);
 549         if (err)
 550                 goto exit_tx_irq;
 551         err = request_irq(priv->err_irq, &bfin_can_interrupt, 0,
 552                         "bfin-can-err", dev);
 553         if (err)
 554                 goto exit_err_irq;
 555
 556         bfin_can_start(dev);
 557
 558         netif_start_queue(dev);
 559
 560         return 0;
 561
 562 exit_err_irq:
 563         free_irq(priv->tx_irq, dev);
 564 exit_tx_irq:
 565         free_irq(priv->rx_irq, dev);
 566 exit_rx_irq:
 567         close_candev(dev);
 568 exit_open:
 569         return err;
 570 }
 571
 572 static int bfin_can_close(struct net_device *dev)
 573 {
 574         struct bfin_can_priv *priv = netdev_priv(dev);
 575
 576         netif_stop_queue(dev);
 577         bfin_can_set_reset_mode(dev);
 578
 579         close_candev(dev);
 580
 581         free_irq(priv->rx_irq, dev);
 582         free_irq(priv->tx_irq, dev);
 583         free_irq(priv->err_irq, dev);
 584
 585         return 0;
 586 }
 587
 588 struct net_device *alloc_bfin_candev(void)
 589 {
 590         struct net_device *dev;
 591         struct bfin_can_priv *priv;
 592
 593         dev = alloc_candev(sizeof(*priv));
 594         if (!dev)
 595                 return NULL;
 596
 597         priv = netdev_priv(dev);
 598
 599         priv->dev = dev;
 600         priv->can.bittiming_const = &bfin_can_bittiming_const;
 601         priv->can.do_set_bittiming = bfin_can_set_bittiming;
 602         priv->can.do_set_mode = bfin_can_set_mode;
 603
 604         return dev;
 605 }
 606
 607 static const struct net_device_ops bfin_can_netdev_ops = {
 608         .ndo_open               = bfin_can_open,
 609         .ndo_stop               = bfin_can_close,
 610         .ndo_start_xmit         = bfin_can_start_xmit,
 611 };
 612
 613 static int __devinit bfin_can_probe(struct platform_device *pdev)
 614 {
 615         int err;
 616         struct net_device *dev;
 617         struct bfin_can_priv *priv;
 618         struct resource *res_mem, *rx_irq, *tx_irq, *err_irq;
 619         unsigned short *pdata;
 620
 621         pdata = pdev->dev.platform_data;
 622         if (!pdata) {
 623                 dev_err(&pdev->dev, "No platform data provided!\n");
 624                 err = -EINVAL;
 625                 goto exit;
 626         }
 627
 628         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 629         rx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 630         tx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 631         err_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
 632         if (!res_mem || !rx_irq || !tx_irq || !err_irq) {
 633                 err = -EINVAL;
 634                 goto exit;
 635         }
 636
 637         if (!request_mem_region(res_mem->start, resource_size(res_mem),
 638                                 dev_name(&pdev->dev))) {
 639                 err = -EBUSY;
 640                 goto exit;
 641         }
 642
 643         /* request peripheral pins */
 644         err = peripheral_request_list(pdata, dev_name(&pdev->dev));
 645         if (err)
 646                 goto exit_mem_release;
 647
 648         dev = alloc_bfin_candev();
 649         if (!dev) {
 650                 err = -ENOMEM;
 651                 goto exit_peri_pin_free;
 652         }
 653
 654         priv = netdev_priv(dev);
 655         priv->membase = (void __iomem *)res_mem->start;
 656         priv->rx_irq = rx_irq->start;
 657         priv->tx_irq = tx_irq->start;
 658         priv->err_irq = err_irq->start;
 659         priv->pin_list = pdata;
 660         priv->can.clock.freq = get_sclk();
 661
 662         dev_set_drvdata(&pdev->dev, dev);
 663         SET_NETDEV_DEV(dev, &pdev->dev);
 664
 665         dev->flags |= IFF_ECHO; /* we support local echo */
 666         dev->netdev_ops = &bfin_can_netdev_ops;
 667
 668         bfin_can_set_reset_mode(dev);
 669
 670         err = register_candev(dev);
 671         if (err) {
 672                 dev_err(&pdev->dev, "registering failed (err=%d)\n", err);
 673                 goto exit_candev_free;
 674         }
 675
 676         dev_info(&pdev->dev,
 677                 "%s device registered"
 678                 "(&reg_base=%p, rx_irq=%d, tx_irq=%d, err_irq=%d, sclk=%d)\n",
 679                 DRV_NAME, (void *)priv->membase, priv->rx_irq,
 680                 priv->tx_irq, priv->err_irq, priv->can.clock.freq);
 681         return 0;
 682
 683 exit_candev_free:
 684         free_candev(dev);
 685 exit_peri_pin_free:
 686         peripheral_free_list(pdata);
 687 exit_mem_release:
 688         release_mem_region(res_mem->start, resource_size(res_mem));
 689 exit:
 690         return err;
 691 }
 692
 693 static int __devexit bfin_can_remove(struct platform_device *pdev)
 694 {
 695         struct net_device *dev = dev_get_drvdata(&pdev->dev);
 696         struct bfin_can_priv *priv = netdev_priv(dev);
 697         struct resource *res;
 698
 699         bfin_can_set_reset_mode(dev);
 700
 701         unregister_candev(dev);
 702
 703         dev_set_drvdata(&pdev->dev, NULL);
 704
 705         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 706         release_mem_region(res->start, resource_size(res));
 707
 708         peripheral_free_list(priv->pin_list);
 709
 710         free_candev(dev);
 711         return 0;
 712 }
 713
 714 #ifdef CONFIG_PM
 715 static int bfin_can_suspend(struct platform_device *pdev, pm_message_t mesg)
 716 {
 717         struct net_device *dev = dev_get_drvdata(&pdev->dev);
 718         struct bfin_can_priv *priv = netdev_priv(dev);
 719         struct bfin_can_regs __iomem *reg = priv->membase;
 720         int timeout = BFIN_CAN_TIMEOUT;
 721
 722         if (netif_running(dev)) {
 723                 /* enter sleep mode */
 724                 bfin_write16(&reg->ctrl, bfin_read16(&reg->ctrl) | SMR);
 725                 SSYNC();
 726                 while (!(bfin_read16(&reg->intr) & SMACK)) {
 727                         udelay(10);
 728                         if (--timeout == 0) {
 729                                 dev_err(dev->dev.parent,
 730                                                 "fail to enter sleep mode\n");
 731                                 BUG();
 732                         }
 733                 }
 734         }
 735
 736         return 0;
 737 }
 738
 739 static int bfin_can_resume(struct platform_device *pdev)
 740 {
 741         struct net_device *dev = dev_get_drvdata(&pdev->dev);
 742         struct bfin_can_priv *priv = netdev_priv(dev);
 743         struct bfin_can_regs __iomem *reg = priv->membase;
 744
 745         if (netif_running(dev)) {
 746                 /* leave sleep mode */
 747                 bfin_write16(&reg->intr, 0);
 748                 SSYNC();
 749         }
 750
 751         return 0;
 752 }
 753 #else
 754 #define bfin_can_suspend NULL
 755 #define bfin_can_resume NULL
 756 #endif  /* CONFIG_PM */
 757
 758 static struct platform_driver bfin_can_driver = {
 759         .probe = bfin_can_probe,
 760         .remove = __devexit_p(bfin_can_remove),
 761         .suspend = bfin_can_suspend,
 762         .resume = bfin_can_resume,
 763         .driver = {
 764                 .name = DRV_NAME,
 765                 .owner = THIS_MODULE,
 766         },
 767 };
 768
 769 static int __init bfin_can_init(void)
 770 {
 771         return platform_driver_register(&bfin_can_driver);
 772 }
 773 module_init(bfin_can_init);
 774
 775 static void __exit bfin_can_exit(void)
 776 {
 777         platform_driver_unregister(&bfin_can_driver);
 778 }
 779 module_exit(bfin_can_exit);
 780
 781 MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
 782 MODULE_LICENSE("GPL");
 783 MODULE_DESCRIPTION("Blackfin on-chip CAN netdevice driver");