drivers/net/bnx2.h

   1 /* bnx2.h: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004-2007 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12
  13 #ifndef BNX2_H
  14 #define BNX2_H
  15
  16 /* Hardware data structures and register definitions automatically
  17  * generated from RTL code. Do not modify.
  18  */
  19
  20 /*
  21  *  tx_bd definition
  22  */
  23 struct tx_bd {
  24         u32 tx_bd_haddr_hi;
  25         u32 tx_bd_haddr_lo;
  26         u32 tx_bd_mss_nbytes;
  27                 #define TX_BD_TCP6_OFF2_SHL             (14)
  28         u32 tx_bd_vlan_tag_flags;
  29                 #define TX_BD_FLAGS_CONN_FAULT          (1<<0)
  30                 #define TX_BD_FLAGS_TCP6_OFF0_MSK       (3<<1)
  31                 #define TX_BD_FLAGS_TCP6_OFF0_SHL       (1)
  32                 #define TX_BD_FLAGS_TCP_UDP_CKSUM       (1<<1)
  33                 #define TX_BD_FLAGS_IP_CKSUM            (1<<2)
  34                 #define TX_BD_FLAGS_VLAN_TAG            (1<<3)
  35                 #define TX_BD_FLAGS_COAL_NOW            (1<<4)
  36                 #define TX_BD_FLAGS_DONT_GEN_CRC        (1<<5)
  37                 #define TX_BD_FLAGS_END                 (1<<6)
  38                 #define TX_BD_FLAGS_START               (1<<7)
  39                 #define TX_BD_FLAGS_SW_OPTION_WORD      (0x1f<<8)
  40                 #define TX_BD_FLAGS_TCP6_OFF4_SHL       (12)
  41                 #define TX_BD_FLAGS_SW_FLAGS            (1<<13)
  42                 #define TX_BD_FLAGS_SW_SNAP             (1<<14)
  43                 #define TX_BD_FLAGS_SW_LSO              (1<<15)
  44
  45 };
  46
  47
  48 /*
  49  *  rx_bd definition
  50  */
  51 struct rx_bd {
  52         u32 rx_bd_haddr_hi;
  53         u32 rx_bd_haddr_lo;
  54         u32 rx_bd_len;
  55         u32 rx_bd_flags;
  56                 #define RX_BD_FLAGS_NOPUSH              (1<<0)
  57                 #define RX_BD_FLAGS_DUMMY               (1<<1)
  58                 #define RX_BD_FLAGS_END                 (1<<2)
  59                 #define RX_BD_FLAGS_START               (1<<3)
  60
  61 };
  62
  63 #define BNX2_RX_ALIGN                   16
  64
  65 /*
  66  *  status_block definition
  67  */
  68 struct status_block {
  69         u32 status_attn_bits;
  70                 #define STATUS_ATTN_BITS_LINK_STATE             (1L<<0)
  71                 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT     (1L<<1)
  72                 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT       (1L<<2)
  73                 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT      (1L<<3)
  74                 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT     (1L<<4)
  75                 #define STATUS_ATTN_BITS_TX_DMA_ABORT           (1L<<5)
  76                 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT       (1L<<6)
  77                 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT     (1L<<7)
  78                 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT    (1L<<8)
  79                 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT        (1L<<9)
  80                 #define STATUS_ATTN_BITS_RX_MBUF_ABORT          (1L<<10)
  81                 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT        (1L<<11)
  82                 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT     (1L<<12)
  83                 #define STATUS_ATTN_BITS_RX_V2P_ABORT           (1L<<13)
  84                 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT      (1L<<14)
  85                 #define STATUS_ATTN_BITS_RX_DMA_ABORT           (1L<<15)
  86                 #define STATUS_ATTN_BITS_COMPLETION_ABORT       (1L<<16)
  87                 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT    (1L<<17)
  88                 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT    (1L<<18)
  89                 #define STATUS_ATTN_BITS_CONTEXT_ABORT          (1L<<19)
  90                 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT    (1L<<20)
  91                 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT    (1L<<21)
  92                 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT   (1L<<22)
  93                 #define STATUS_ATTN_BITS_MAC_ABORT              (1L<<23)
  94                 #define STATUS_ATTN_BITS_TIMER_ABORT            (1L<<24)
  95                 #define STATUS_ATTN_BITS_DMAE_ABORT             (1L<<25)
  96                 #define STATUS_ATTN_BITS_FLSH_ABORT             (1L<<26)
  97                 #define STATUS_ATTN_BITS_GRC_ABORT              (1L<<27)
  98                 #define STATUS_ATTN_BITS_EPB_ERROR              (1L<<30)
  99                 #define STATUS_ATTN_BITS_PARITY_ERROR           (1L<<31)
 100
 101         u32 status_attn_bits_ack;
 102 #if defined(__BIG_ENDIAN)
 103         u16 status_tx_quick_consumer_index0;
 104         u16 status_tx_quick_consumer_index1;
 105         u16 status_tx_quick_consumer_index2;
 106         u16 status_tx_quick_consumer_index3;
 107         u16 status_rx_quick_consumer_index0;
 108         u16 status_rx_quick_consumer_index1;
 109         u16 status_rx_quick_consumer_index2;
 110         u16 status_rx_quick_consumer_index3;
 111         u16 status_rx_quick_consumer_index4;
 112         u16 status_rx_quick_consumer_index5;
 113         u16 status_rx_quick_consumer_index6;
 114         u16 status_rx_quick_consumer_index7;
 115         u16 status_rx_quick_consumer_index8;
 116         u16 status_rx_quick_consumer_index9;
 117         u16 status_rx_quick_consumer_index10;
 118         u16 status_rx_quick_consumer_index11;
 119         u16 status_rx_quick_consumer_index12;
 120         u16 status_rx_quick_consumer_index13;
 121         u16 status_rx_quick_consumer_index14;
 122         u16 status_rx_quick_consumer_index15;
 123         u16 status_completion_producer_index;
 124         u16 status_cmd_consumer_index;
 125         u16 status_idx;
 126         u8 status_unused;
 127         u8 status_blk_num;
 128 #elif defined(__LITTLE_ENDIAN)
 129         u16 status_tx_quick_consumer_index1;
 130         u16 status_tx_quick_consumer_index0;
 131         u16 status_tx_quick_consumer_index3;
 132         u16 status_tx_quick_consumer_index2;
 133         u16 status_rx_quick_consumer_index1;
 134         u16 status_rx_quick_consumer_index0;
 135         u16 status_rx_quick_consumer_index3;
 136         u16 status_rx_quick_consumer_index2;
 137         u16 status_rx_quick_consumer_index5;
 138         u16 status_rx_quick_consumer_index4;
 139         u16 status_rx_quick_consumer_index7;
 140         u16 status_rx_quick_consumer_index6;
 141         u16 status_rx_quick_consumer_index9;
 142         u16 status_rx_quick_consumer_index8;
 143         u16 status_rx_quick_consumer_index11;
 144         u16 status_rx_quick_consumer_index10;
 145         u16 status_rx_quick_consumer_index13;
 146         u16 status_rx_quick_consumer_index12;
 147         u16 status_rx_quick_consumer_index15;
 148         u16 status_rx_quick_consumer_index14;
 149         u16 status_cmd_consumer_index;
 150         u16 status_completion_producer_index;
 151         u8 status_blk_num;
 152         u8 status_unused;
 153         u16 status_idx;
 154 #endif
 155 };
 156
 157
 158 /*
 159  *  statistics_block definition
 160  */
 161 struct statistics_block {
 162         u32 stat_IfHCInOctets_hi;
 163         u32 stat_IfHCInOctets_lo;
 164         u32 stat_IfHCInBadOctets_hi;
 165         u32 stat_IfHCInBadOctets_lo;
 166         u32 stat_IfHCOutOctets_hi;
 167         u32 stat_IfHCOutOctets_lo;
 168         u32 stat_IfHCOutBadOctets_hi;
 169         u32 stat_IfHCOutBadOctets_lo;
 170         u32 stat_IfHCInUcastPkts_hi;
 171         u32 stat_IfHCInUcastPkts_lo;
 172         u32 stat_IfHCInMulticastPkts_hi;
 173         u32 stat_IfHCInMulticastPkts_lo;
 174         u32 stat_IfHCInBroadcastPkts_hi;
 175         u32 stat_IfHCInBroadcastPkts_lo;
 176         u32 stat_IfHCOutUcastPkts_hi;
 177         u32 stat_IfHCOutUcastPkts_lo;
 178         u32 stat_IfHCOutMulticastPkts_hi;
 179         u32 stat_IfHCOutMulticastPkts_lo;
 180         u32 stat_IfHCOutBroadcastPkts_hi;
 181         u32 stat_IfHCOutBroadcastPkts_lo;
 182         u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
 183         u32 stat_Dot3StatsCarrierSenseErrors;
 184         u32 stat_Dot3StatsFCSErrors;
 185         u32 stat_Dot3StatsAlignmentErrors;
 186         u32 stat_Dot3StatsSingleCollisionFrames;
 187         u32 stat_Dot3StatsMultipleCollisionFrames;
 188         u32 stat_Dot3StatsDeferredTransmissions;
 189         u32 stat_Dot3StatsExcessiveCollisions;
 190         u32 stat_Dot3StatsLateCollisions;
 191         u32 stat_EtherStatsCollisions;
 192         u32 stat_EtherStatsFragments;
 193         u32 stat_EtherStatsJabbers;
 194         u32 stat_EtherStatsUndersizePkts;
 195         u32 stat_EtherStatsOverrsizePkts;
 196         u32 stat_EtherStatsPktsRx64Octets;
 197         u32 stat_EtherStatsPktsRx65Octetsto127Octets;
 198         u32 stat_EtherStatsPktsRx128Octetsto255Octets;
 199         u32 stat_EtherStatsPktsRx256Octetsto511Octets;
 200         u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
 201         u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
 202         u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
 203         u32 stat_EtherStatsPktsTx64Octets;
 204         u32 stat_EtherStatsPktsTx65Octetsto127Octets;
 205         u32 stat_EtherStatsPktsTx128Octetsto255Octets;
 206         u32 stat_EtherStatsPktsTx256Octetsto511Octets;
 207         u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
 208         u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
 209         u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
 210         u32 stat_XonPauseFramesReceived;
 211         u32 stat_XoffPauseFramesReceived;
 212         u32 stat_OutXonSent;
 213         u32 stat_OutXoffSent;
 214         u32 stat_FlowControlDone;
 215         u32 stat_MacControlFramesReceived;
 216         u32 stat_XoffStateEntered;
 217         u32 stat_IfInFramesL2FilterDiscards;
 218         u32 stat_IfInRuleCheckerDiscards;
 219         u32 stat_IfInFTQDiscards;
 220         u32 stat_IfInMBUFDiscards;
 221         u32 stat_IfInRuleCheckerP4Hit;
 222         u32 stat_CatchupInRuleCheckerDiscards;
 223         u32 stat_CatchupInFTQDiscards;
 224         u32 stat_CatchupInMBUFDiscards;
 225         u32 stat_CatchupInRuleCheckerP4Hit;
 226         u32 stat_GenStat00;
 227         u32 stat_GenStat01;
 228         u32 stat_GenStat02;
 229         u32 stat_GenStat03;
 230         u32 stat_GenStat04;
 231         u32 stat_GenStat05;
 232         u32 stat_GenStat06;
 233         u32 stat_GenStat07;
 234         u32 stat_GenStat08;
 235         u32 stat_GenStat09;
 236         u32 stat_GenStat10;
 237         u32 stat_GenStat11;
 238         u32 stat_GenStat12;
 239         u32 stat_GenStat13;
 240         u32 stat_GenStat14;
 241         u32 stat_GenStat15;
 242         u32 stat_FwRxDrop;
 243 };
 244
 245
 246 /*
 247  *  l2_fhdr definition
 248  */
 249 struct l2_fhdr {
 250         u32 l2_fhdr_status;
 251                 #define L2_FHDR_STATUS_RULE_CLASS       (0x7<<0)
 252                 #define L2_FHDR_STATUS_RULE_P2          (1<<3)
 253                 #define L2_FHDR_STATUS_RULE_P3          (1<<4)
 254                 #define L2_FHDR_STATUS_RULE_P4          (1<<5)
 255                 #define L2_FHDR_STATUS_L2_VLAN_TAG      (1<<6)
 256                 #define L2_FHDR_STATUS_L2_LLC_SNAP      (1<<7)
 257                 #define L2_FHDR_STATUS_RSS_HASH         (1<<8)
 258                 #define L2_FHDR_STATUS_IP_DATAGRAM      (1<<13)
 259                 #define L2_FHDR_STATUS_TCP_SEGMENT      (1<<14)
 260                 #define L2_FHDR_STATUS_UDP_DATAGRAM     (1<<15)
 261
 262                 #define L2_FHDR_ERRORS_BAD_CRC          (1<<17)
 263                 #define L2_FHDR_ERRORS_PHY_DECODE       (1<<18)
 264                 #define L2_FHDR_ERRORS_ALIGNMENT        (1<<19)
 265                 #define L2_FHDR_ERRORS_TOO_SHORT        (1<<20)
 266                 #define L2_FHDR_ERRORS_GIANT_FRAME      (1<<21)
 267                 #define L2_FHDR_ERRORS_TCP_XSUM         (1<<28)
 268                 #define L2_FHDR_ERRORS_UDP_XSUM         (1<<31)
 269
 270         u32 l2_fhdr_hash;
 271 #if defined(__BIG_ENDIAN)
 272         u16 l2_fhdr_pkt_len;
 273         u16 l2_fhdr_vlan_tag;
 274         u16 l2_fhdr_ip_xsum;
 275         u16 l2_fhdr_tcp_udp_xsum;
 276 #elif defined(__LITTLE_ENDIAN)
 277         u16 l2_fhdr_vlan_tag;
 278         u16 l2_fhdr_pkt_len;
 279         u16 l2_fhdr_tcp_udp_xsum;
 280         u16 l2_fhdr_ip_xsum;
 281 #endif
 282 };
 283
 284
 285 /*
 286  *  l2_context definition
 287  */
 288 #define BNX2_L2CTX_TYPE                                 0x00000000
 289 #define BNX2_L2CTX_TYPE_SIZE_L2                          ((0xc0/0x20)<<16)
 290 #define BNX2_L2CTX_TYPE_TYPE                             (0xf<<28)
 291 #define BNX2_L2CTX_TYPE_TYPE_EMPTY                       (0<<28)
 292 #define BNX2_L2CTX_TYPE_TYPE_L2                          (1<<28)
 293
 294 #define BNX2_L2CTX_TX_HOST_BIDX                         0x00000088
 295 #define BNX2_L2CTX_EST_NBD                              0x00000088
 296 #define BNX2_L2CTX_CMD_TYPE                             0x00000088
 297 #define BNX2_L2CTX_CMD_TYPE_TYPE                         (0xf<<24)
 298 #define BNX2_L2CTX_CMD_TYPE_TYPE_L2                      (0<<24)
 299 #define BNX2_L2CTX_CMD_TYPE_TYPE_TCP                     (1<<24)
 300
 301 #define BNX2_L2CTX_TX_HOST_BSEQ                         0x00000090
 302 #define BNX2_L2CTX_TSCH_BSEQ                            0x00000094
 303 #define BNX2_L2CTX_TBDR_BSEQ                            0x00000098
 304 #define BNX2_L2CTX_TBDR_BOFF                            0x0000009c
 305 #define BNX2_L2CTX_TBDR_BIDX                            0x0000009c
 306 #define BNX2_L2CTX_TBDR_BHADDR_HI                       0x000000a0
 307 #define BNX2_L2CTX_TBDR_BHADDR_LO                       0x000000a4
 308 #define BNX2_L2CTX_TXP_BOFF                             0x000000a8
 309 #define BNX2_L2CTX_TXP_BIDX                             0x000000a8
 310 #define BNX2_L2CTX_TXP_BSEQ                             0x000000ac
 311
 312 #define BNX2_L2CTX_TYPE_XI                              0x00000080
 313 #define BNX2_L2CTX_CMD_TYPE_XI                          0x00000240
 314 #define BNX2_L2CTX_TBDR_BHADDR_HI_XI                    0x00000258
 315 #define BNX2_L2CTX_TBDR_BHADDR_LO_XI                    0x0000025c
 316
 317 /*
 318  *  l2_bd_chain_context definition
 319  */
 320 #define BNX2_L2CTX_BD_PRE_READ                          0x00000000
 321 #define BNX2_L2CTX_CTX_SIZE                             0x00000000
 322 #define BNX2_L2CTX_CTX_TYPE                             0x00000000
 323 #define BNX2_L2CTX_CTX_TYPE_SIZE_L2                      ((0x20/20)<<16)
 324 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE              (0xf<<28)
 325 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED    (0<<28)
 326 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE        (1<<28)
 327
 328 #define BNX2_L2CTX_HOST_BDIDX                           0x00000004
 329 #define BNX2_L2CTX_HOST_BSEQ                            0x00000008
 330 #define BNX2_L2CTX_NX_BSEQ                              0x0000000c
 331 #define BNX2_L2CTX_NX_BDHADDR_HI                        0x00000010
 332 #define BNX2_L2CTX_NX_BDHADDR_LO                        0x00000014
 333 #define BNX2_L2CTX_NX_BDIDX                             0x00000018
 334
 335
 336 /*
 337  *  pci_config_l definition
 338  *  offset: 0000
 339  */
 340 #define BNX2_PCICFG_MISC_CONFIG                         0x00000068
 341 #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP         (1L<<2)
 342 #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP      (1L<<3)
 343 #define BNX2_PCICFG_MISC_CONFIG_RESERVED1                (1L<<4)
 344 #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA            (1L<<5)
 345 #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP     (1L<<6)
 346 #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA           (1L<<7)
 347 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ             (1L<<8)
 348 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY             (1L<<9)
 349 #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN         (1L<<10)
 350 #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN         (1L<<11)
 351 #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN         (1L<<12)
 352 #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV           (0xffL<<16)
 353 #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV            (0xfL<<24)
 354 #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID                  (0xfL<<28)
 355
 356 #define BNX2_PCICFG_MISC_STATUS                         0x0000006c
 357 #define BNX2_PCICFG_MISC_STATUS_INTA_VALUE               (1L<<0)
 358 #define BNX2_PCICFG_MISC_STATUS_32BIT_DET                (1L<<1)
 359 #define BNX2_PCICFG_MISC_STATUS_M66EN                    (1L<<2)
 360 #define BNX2_PCICFG_MISC_STATUS_PCIX_DET                 (1L<<3)
 361 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED               (0x3L<<4)
 362 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66            (0L<<4)
 363 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100           (1L<<4)
 364 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133           (2L<<4)
 365 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE      (3L<<4)
 366 #define BNX2_PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE         (1L<<8)
 367
 368 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS              0x00000070
 369 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET       (0xfL<<0)
 370 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ         (0L<<0)
 371 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ         (1L<<0)
 372 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ         (2L<<0)
 373 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ         (3L<<0)
 374 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ         (4L<<0)
 375 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ         (5L<<0)
 376 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ         (6L<<0)
 377 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ        (7L<<0)
 378 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW   (0xfL<<0)
 379 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE      (1L<<6)
 380 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT  (1L<<7)
 381 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC      (0x7L<<8)
 382 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF        (0L<<8)
 383 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12   (1L<<8)
 384 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6    (2L<<8)
 385 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62   (4L<<8)
 386 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER     (1L<<11)
 387 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED    (0xfL<<12)
 388 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100        (0L<<12)
 389 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80         (1L<<12)
 390 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50         (2L<<12)
 391 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40         (4L<<12)
 392 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25         (8L<<12)
 393 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP     (1L<<16)
 394 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17   (1L<<17)
 395 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18   (1L<<18)
 396 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19   (1L<<19)
 397 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED      (0xfffL<<20)
 398
 399 #define BNX2_PCICFG_REG_WINDOW_ADDRESS                  0x00000078
 400 #define BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL               (0xfffffL<<2)
 401
 402 #define BNX2_PCICFG_REG_WINDOW                          0x00000080
 403 #define BNX2_PCICFG_INT_ACK_CMD                         0x00000084
 404 #define BNX2_PCICFG_INT_ACK_CMD_INDEX                    (0xffffL<<0)
 405 #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID              (1L<<16)
 406 #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM         (1L<<17)
 407 #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT                 (1L<<18)
 408 #define BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM            (0xfL<<24)
 409
 410 #define BNX2_PCICFG_STATUS_BIT_SET_CMD                  0x00000088
 411 #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD                0x0000008c
 412 #define BNX2_PCICFG_MAILBOX_QUEUE_ADDR                  0x00000090
 413 #define BNX2_PCICFG_MAILBOX_QUEUE_DATA                  0x00000094
 414
 415
 416 /*
 417  *  pci_reg definition
 418  *  offset: 0x400
 419  */
 420 #define BNX2_PCI_GRC_WINDOW_ADDR                        0x00000400
 421 #define BNX2_PCI_GRC_WINDOW_ADDR_VALUE                   (0x1ffL<<13)
 422 #define BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN                 (1L<<31)
 423
 424 #define BNX2_PCI_CONFIG_1                               0x00000404
 425 #define BNX2_PCI_CONFIG_1_RESERVED0                      (0xffL<<0)
 426 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY                  (0x7L<<8)
 427 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF              (0L<<8)
 428 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16               (1L<<8)
 429 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32               (2L<<8)
 430 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64               (3L<<8)
 431 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128              (4L<<8)
 432 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256              (5L<<8)
 433 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512              (6L<<8)
 434 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024             (7L<<8)
 435 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY                 (0x7L<<11)
 436 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF             (0L<<11)
 437 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16              (1L<<11)
 438 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32              (2L<<11)
 439 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64              (3L<<11)
 440 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128             (4L<<11)
 441 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256             (5L<<11)
 442 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512             (6L<<11)
 443 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024            (7L<<11)
 444 #define BNX2_PCI_CONFIG_1_RESERVED1                      (0x3ffffL<<14)
 445
 446 #define BNX2_PCI_CONFIG_2                               0x00000408
 447 #define BNX2_PCI_CONFIG_2_BAR1_SIZE                      (0xfL<<0)
 448 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED             (0L<<0)
 449 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K                  (1L<<0)
 450 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K                 (2L<<0)
 451 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K                 (3L<<0)
 452 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K                 (4L<<0)
 453 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M                   (5L<<0)
 454 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M                   (6L<<0)
 455 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M                   (7L<<0)
 456 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M                   (8L<<0)
 457 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M                  (9L<<0)
 458 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M                  (10L<<0)
 459 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M                  (11L<<0)
 460 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M                 (12L<<0)
 461 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M                 (13L<<0)
 462 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M                 (14L<<0)
 463 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G                   (15L<<0)
 464 #define BNX2_PCI_CONFIG_2_BAR1_64ENA                     (1L<<4)
 465 #define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY                  (1L<<5)
 466 #define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY                (1L<<6)
 467 #define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE                 (1L<<7)
 468 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE                   (0xffL<<8)
 469 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED          (0L<<8)
 470 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K                (1L<<8)
 471 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K                (2L<<8)
 472 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K                (3L<<8)
 473 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K                (4L<<8)
 474 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K               (5L<<8)
 475 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K               (6L<<8)
 476 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K               (7L<<8)
 477 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K              (8L<<8)
 478 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K              (9L<<8)
 479 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K              (10L<<8)
 480 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M                (11L<<8)
 481 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M                (12L<<8)
 482 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M                (13L<<8)
 483 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M                (14L<<8)
 484 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M               (15L<<8)
 485 #define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT                (0x1fL<<16)
 486 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT                 (0x3L<<21)
 487 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512             (0L<<21)
 488 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K              (1L<<21)
 489 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K              (2L<<21)
 490 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K              (3L<<21)
 491 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR              (1L<<23)
 492 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT               (1L<<24)
 493 #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT                (1L<<25)
 494 #define BNX2_PCI_CONFIG_2_RESERVED0                      (0x3fL<<26)
 495 #define BNX2_PCI_CONFIG_2_BAR_PREFETCH_XI                (1L<<16)
 496 #define BNX2_PCI_CONFIG_2_RESERVED0_XI                   (0x7fffL<<17)
 497
 498 #define BNX2_PCI_CONFIG_3                               0x0000040c
 499 #define BNX2_PCI_CONFIG_3_STICKY_BYTE                    (0xffL<<0)
 500 #define BNX2_PCI_CONFIG_3_REG_STICKY_BYTE                (0xffL<<8)
 501 #define BNX2_PCI_CONFIG_3_FORCE_PME                      (1L<<24)
 502 #define BNX2_PCI_CONFIG_3_PME_STATUS                     (1L<<25)
 503 #define BNX2_PCI_CONFIG_3_PME_ENABLE                     (1L<<26)
 504 #define BNX2_PCI_CONFIG_3_PM_STATE                       (0x3L<<27)
 505 #define BNX2_PCI_CONFIG_3_VAUX_PRESET                    (1L<<30)
 506 #define BNX2_PCI_CONFIG_3_PCI_POWER                      (1L<<31)
 507
 508 #define BNX2_PCI_PM_DATA_A                              0x00000410
 509 #define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG                 (0xffL<<0)
 510 #define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG                 (0xffL<<8)
 511 #define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG                 (0xffL<<16)
 512 #define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG                 (0xffL<<24)
 513
 514 #define BNX2_PCI_PM_DATA_B                              0x00000414
 515 #define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG                 (0xffL<<0)
 516 #define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG                 (0xffL<<8)
 517 #define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG                 (0xffL<<16)
 518 #define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG                 (0xffL<<24)
 519
 520 #define BNX2_PCI_SWAP_DIAG0                             0x00000418
 521 #define BNX2_PCI_SWAP_DIAG1                             0x0000041c
 522 #define BNX2_PCI_EXP_ROM_ADDR                           0x00000420
 523 #define BNX2_PCI_EXP_ROM_ADDR_ADDRESS                    (0x3fffffL<<2)
 524 #define BNX2_PCI_EXP_ROM_ADDR_REQ                        (1L<<31)
 525
 526 #define BNX2_PCI_EXP_ROM_DATA                           0x00000424
 527 #define BNX2_PCI_VPD_INTF                               0x00000428
 528 #define BNX2_PCI_VPD_INTF_INTF_REQ                       (1L<<0)
 529
 530 #define BNX2_PCI_VPD_ADDR_FLAG                          0x0000042c
 531 #define BNX2_PCI_VPD_ADDR_FLAG_MSK                      0x0000ffff
 532 #define BNX2_PCI_VPD_ADDR_FLAG_SL                       0L
 533 #define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS                   (0x1fffL<<2)
 534 #define BNX2_PCI_VPD_ADDR_FLAG_WR                        (1L<<15)
 535
 536 #define BNX2_PCI_VPD_DATA                               0x00000430
 537 #define BNX2_PCI_ID_VAL1                                0x00000434
 538 #define BNX2_PCI_ID_VAL1_DEVICE_ID                       (0xffffL<<0)
 539 #define BNX2_PCI_ID_VAL1_VENDOR_ID                       (0xffffL<<16)
 540
 541 #define BNX2_PCI_ID_VAL2                                0x00000438
 542 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID             (0xffffL<<0)
 543 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID                    (0xffffL<<16)
 544
 545 #define BNX2_PCI_ID_VAL3                                0x0000043c
 546 #define BNX2_PCI_ID_VAL3_CLASS_CODE                      (0xffffffL<<0)
 547 #define BNX2_PCI_ID_VAL3_REVISION_ID                     (0xffL<<24)
 548
 549 #define BNX2_PCI_ID_VAL4                                0x00000440
 550 #define BNX2_PCI_ID_VAL4_CAP_ENA                         (0xfL<<0)
 551 #define BNX2_PCI_ID_VAL4_CAP_ENA_0                       (0L<<0)
 552 #define BNX2_PCI_ID_VAL4_CAP_ENA_1                       (1L<<0)
 553 #define BNX2_PCI_ID_VAL4_CAP_ENA_2                       (2L<<0)
 554 #define BNX2_PCI_ID_VAL4_CAP_ENA_3                       (3L<<0)
 555 #define BNX2_PCI_ID_VAL4_CAP_ENA_4                       (4L<<0)
 556 #define BNX2_PCI_ID_VAL4_CAP_ENA_5                       (5L<<0)
 557 #define BNX2_PCI_ID_VAL4_CAP_ENA_6                       (6L<<0)
 558 #define BNX2_PCI_ID_VAL4_CAP_ENA_7                       (7L<<0)
 559 #define BNX2_PCI_ID_VAL4_CAP_ENA_8                       (8L<<0)
 560 #define BNX2_PCI_ID_VAL4_CAP_ENA_9                       (9L<<0)
 561 #define BNX2_PCI_ID_VAL4_CAP_ENA_10                      (10L<<0)
 562 #define BNX2_PCI_ID_VAL4_CAP_ENA_11                      (11L<<0)
 563 #define BNX2_PCI_ID_VAL4_CAP_ENA_12                      (12L<<0)
 564 #define BNX2_PCI_ID_VAL4_CAP_ENA_13                      (13L<<0)
 565 #define BNX2_PCI_ID_VAL4_CAP_ENA_14                      (14L<<0)
 566 #define BNX2_PCI_ID_VAL4_CAP_ENA_15                      (15L<<0)
 567 #define BNX2_PCI_ID_VAL4_RESERVED0                       (0x3L<<4)
 568 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG                    (0x3L<<6)
 569 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0                  (0L<<6)
 570 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1                  (1L<<6)
 571 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2                  (2L<<6)
 572 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3                  (3L<<6)
 573 #define BNX2_PCI_ID_VAL4_MSI_PV_MASK_CAP                 (1L<<8)
 574 #define BNX2_PCI_ID_VAL4_MSI_LIMIT                       (0x7L<<9)
 575 #define BNX2_PCI_ID_VAL4_MULTI_MSG_CAP                   (0x7L<<12)
 576 #define BNX2_PCI_ID_VAL4_MSI_ENABLE                      (1L<<15)
 577 #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE                (1L<<16)
 578 #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE               (1L<<17)
 579 #define BNX2_PCI_ID_VAL4_RESERVED2                       (0x7L<<18)
 580 #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21         (0x3L<<21)
 581 #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B21              (0x3L<<23)
 582 #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0          (1L<<25)
 583 #define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10           (0x3L<<26)
 584 #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B0               (1L<<28)
 585 #define BNX2_PCI_ID_VAL4_RESERVED3                       (0x7L<<29)
 586 #define BNX2_PCI_ID_VAL4_RESERVED3_XI                    (0xffffL<<16)
 587
 588 #define BNX2_PCI_ID_VAL5                                0x00000444
 589 #define BNX2_PCI_ID_VAL5_D1_SUPPORT                      (1L<<0)
 590 #define BNX2_PCI_ID_VAL5_D2_SUPPORT                      (1L<<1)
 591 #define BNX2_PCI_ID_VAL5_PME_IN_D0                       (1L<<2)
 592 #define BNX2_PCI_ID_VAL5_PME_IN_D1                       (1L<<3)
 593 #define BNX2_PCI_ID_VAL5_PME_IN_D2                       (1L<<4)
 594 #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT                   (1L<<5)
 595 #define BNX2_PCI_ID_VAL5_RESERVED0_TE                    (0x3ffffffL<<6)
 596 #define BNX2_PCI_ID_VAL5_PM_VERSION_XI                   (0x7L<<6)
 597 #define BNX2_PCI_ID_VAL5_NO_SOFT_RESET_XI                (1L<<9)
 598 #define BNX2_PCI_ID_VAL5_RESERVED0_XI                    (0x3fffffL<<10)
 599
 600 #define BNX2_PCI_PCIX_EXTENDED_STATUS                   0x00000448
 601 #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP           (1L<<8)
 602 #define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST         (1L<<9)
 603 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS       (0xfL<<16)
 604 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX         (0xffL<<24)
 605
 606 #define BNX2_PCI_ID_VAL6                                0x0000044c
 607 #define BNX2_PCI_ID_VAL6_MAX_LAT                         (0xffL<<0)
 608 #define BNX2_PCI_ID_VAL6_MIN_GNT                         (0xffL<<8)
 609 #define BNX2_PCI_ID_VAL6_BIST                            (0xffL<<16)
 610 #define BNX2_PCI_ID_VAL6_RESERVED0                       (0xffL<<24)
 611
 612 #define BNX2_PCI_MSI_DATA                               0x00000450
 613 #define BNX2_PCI_MSI_DATA_MSI_DATA                       (0xffffL<<0)
 614
 615 #define BNX2_PCI_MSI_ADDR_H                             0x00000454
 616 #define BNX2_PCI_MSI_ADDR_L                             0x00000458
 617 #define BNX2_PCI_MSI_ADDR_L_VAL                          (0x3fffffffL<<2)
 618
 619 #define BNX2_PCI_CFG_ACCESS_CMD                         0x0000045c
 620 #define BNX2_PCI_CFG_ACCESS_CMD_ADR                      (0x3fL<<2)
 621 #define BNX2_PCI_CFG_ACCESS_CMD_RD_REQ                   (1L<<27)
 622 #define BNX2_PCI_CFG_ACCESS_CMD_WR_REQ                   (0xfL<<28)
 623
 624 #define BNX2_PCI_CFG_ACCESS_DATA                        0x00000460
 625 #define BNX2_PCI_MSI_MASK                               0x00000464
 626 #define BNX2_PCI_MSI_MASK_MSI_MASK                       (0xffffffffL<<0)
 627
 628 #define BNX2_PCI_MSI_PEND                               0x00000468
 629 #define BNX2_PCI_MSI_PEND_MSI_PEND                       (0xffffffffL<<0)
 630
 631 #define BNX2_PCI_PM_DATA_C                              0x0000046c
 632 #define BNX2_PCI_PM_DATA_C_PM_DATA_8_PRG                 (0xffL<<0)
 633 #define BNX2_PCI_PM_DATA_C_RESERVED0                     (0xffffffL<<8)
 634
 635 #define BNX2_PCI_MSIX_CONTROL                           0x000004c0
 636 #define BNX2_PCI_MSIX_CONTROL_MSIX_TBL_SIZ               (0x7ffL<<0)
 637 #define BNX2_PCI_MSIX_CONTROL_RESERVED0                  (0x1fffffL<<11)
 638
 639 #define BNX2_PCI_MSIX_TBL_OFF_BIR                       0x000004c4
 640 #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR           (0x7L<<0)
 641 #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF           (0x1fffffffL<<3)
 642
 643 #define BNX2_PCI_MSIX_PBA_OFF_BIT                       0x000004c8
 644 #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR           (0x7L<<0)
 645 #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF           (0x1fffffffL<<3)
 646
 647 #define BNX2_PCI_PCIE_CAPABILITY                        0x000004d0
 648 #define BNX2_PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM       (0x1fL<<0)
 649 #define BNX2_PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1         (1L<<5)
 650
 651 #define BNX2_PCI_DEVICE_CAPABILITY                      0x000004d4
 652 #define BNX2_PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED  (0x7L<<0)
 653 #define BNX2_PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT  (1L<<5)
 654 #define BNX2_PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY        (0x7L<<6)
 655 #define BNX2_PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY         (0x7L<<9)
 656 #define BNX2_PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT    (1L<<15)
 657
 658 #define BNX2_PCI_LINK_CAPABILITY                        0x000004dc
 659 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED          (0xfL<<0)
 660 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001     (1L<<0)
 661 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010     (1L<<0)
 662 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_WIDTH          (0x1fL<<4)
 663 #define BNX2_PCI_LINK_CAPABILITY_CLK_POWER_MGMT          (1L<<9)
 664 #define BNX2_PCI_LINK_CAPABILITY_ASPM_SUPPORT            (0x3L<<10)
 665 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT            (0x7L<<12)
 666 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101        (5L<<12)
 667 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110        (6L<<12)
 668 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT             (0x7L<<15)
 669 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_001         (1L<<15)
 670 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_010         (2L<<15)
 671 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT       (0x7L<<18)
 672 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101   (5L<<18)
 673 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110   (6L<<18)
 674 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT        (0x7L<<21)
 675 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001    (1L<<21)
 676 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010    (2L<<21)
 677 #define BNX2_PCI_LINK_CAPABILITY_PORT_NUM                (0xffL<<24)
 678
 679 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2               0x000004e4
 680 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP     (0xfL<<0)
 681 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP    (1L<<4)
 682 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED       (0x7ffffffL<<5)
 683
 684 #define BNX2_PCI_PCIE_LINK_CAPABILITY_2                 0x000004e8
 685 #define BNX2_PCI_PCIE_LINK_CAPABILITY_2_RESERVED         (0xffffffffL<<0)
 686
 687 #define BNX2_PCI_GRC_WINDOW1_ADDR                       0x00000610
 688 #define BNX2_PCI_GRC_WINDOW1_ADDR_VALUE                  (0x1ffL<<13)
 689
 690 #define BNX2_PCI_GRC_WINDOW2_ADDR                       0x00000614
 691 #define BNX2_PCI_GRC_WINDOW2_ADDR_VALUE                  (0x1ffL<<13)
 692
 693 #define BNX2_PCI_GRC_WINDOW3_ADDR                       0x00000618
 694 #define BNX2_PCI_GRC_WINDOW3_ADDR_VALUE                  (0x1ffL<<13)
 695
 696
 697 /*
 698  *  misc_reg definition
 699  *  offset: 0x800
 700  */
 701 #define BNX2_MISC_COMMAND                               0x00000800
 702 #define BNX2_MISC_COMMAND_ENABLE_ALL                     (1L<<0)
 703 #define BNX2_MISC_COMMAND_DISABLE_ALL                    (1L<<1)
 704 #define BNX2_MISC_COMMAND_SW_RESET                       (1L<<4)
 705 #define BNX2_MISC_COMMAND_POR_RESET                      (1L<<5)
 706 #define BNX2_MISC_COMMAND_HD_RESET                       (1L<<6)
 707 #define BNX2_MISC_COMMAND_CMN_SW_RESET                   (1L<<7)
 708 #define BNX2_MISC_COMMAND_PAR_ERROR                      (1L<<8)
 709 #define BNX2_MISC_COMMAND_CS16_ERR                       (1L<<9)
 710 #define BNX2_MISC_COMMAND_CS16_ERR_LOC                   (0xfL<<12)
 711 #define BNX2_MISC_COMMAND_PAR_ERR_RAM                    (0x7fL<<16)
 712 #define BNX2_MISC_COMMAND_POWERDOWN_EVENT                (1L<<23)
 713 #define BNX2_MISC_COMMAND_SW_SHUTDOWN                    (1L<<24)
 714 #define BNX2_MISC_COMMAND_SHUTDOWN_EN                    (1L<<25)
 715 #define BNX2_MISC_COMMAND_DINTEG_ATTN_EN                 (1L<<26)
 716 #define BNX2_MISC_COMMAND_PCIE_LINK_IN_L23               (1L<<27)
 717 #define BNX2_MISC_COMMAND_PCIE_DIS                       (1L<<28)
 718
 719 #define BNX2_MISC_CFG                                   0x00000804
 720 #define BNX2_MISC_CFG_GRC_TMOUT                          (1L<<0)
 721 #define BNX2_MISC_CFG_NVM_WR_EN                          (0x3L<<1)
 722 #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT                  (0L<<1)
 723 #define BNX2_MISC_CFG_NVM_WR_EN_PCI                      (1L<<1)
 724 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW                    (2L<<1)
 725 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2                   (3L<<1)
 726 #define BNX2_MISC_CFG_BIST_EN                            (1L<<3)
 727 #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC                   (1L<<4)
 728 #define BNX2_MISC_CFG_RESERVED5_TE                       (1L<<5)
 729 #define BNX2_MISC_CFG_RESERVED6_TE                       (1L<<6)
 730 #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE                   (1L<<7)
 731 #define BNX2_MISC_CFG_LEDMODE                            (0x7L<<8)
 732 #define BNX2_MISC_CFG_LEDMODE_MAC                        (0L<<8)
 733 #define BNX2_MISC_CFG_LEDMODE_PHY1_TE                    (1L<<8)
 734 #define BNX2_MISC_CFG_LEDMODE_PHY2_TE                    (2L<<8)
 735 #define BNX2_MISC_CFG_LEDMODE_PHY3_TE                    (3L<<8)
 736 #define BNX2_MISC_CFG_LEDMODE_PHY4_TE                    (4L<<8)
 737 #define BNX2_MISC_CFG_LEDMODE_PHY5_TE                    (5L<<8)
 738 #define BNX2_MISC_CFG_LEDMODE_PHY6_TE                    (6L<<8)
 739 #define BNX2_MISC_CFG_LEDMODE_PHY7_TE                    (7L<<8)
 740 #define BNX2_MISC_CFG_MCP_GRC_TMOUT_TE                   (1L<<11)
 741 #define BNX2_MISC_CFG_DBU_GRC_TMOUT_TE                   (1L<<12)
 742 #define BNX2_MISC_CFG_LEDMODE_XI                         (0xfL<<8)
 743 #define BNX2_MISC_CFG_LEDMODE_MAC_XI                     (0L<<8)
 744 #define BNX2_MISC_CFG_LEDMODE_PHY1_XI                    (1L<<8)
 745 #define BNX2_MISC_CFG_LEDMODE_PHY2_XI                    (2L<<8)
 746 #define BNX2_MISC_CFG_LEDMODE_PHY3_XI                    (3L<<8)
 747 #define BNX2_MISC_CFG_LEDMODE_MAC2_XI                    (4L<<8)
 748 #define BNX2_MISC_CFG_LEDMODE_PHY4_XI                    (5L<<8)
 749 #define BNX2_MISC_CFG_LEDMODE_PHY5_XI                    (6L<<8)
 750 #define BNX2_MISC_CFG_LEDMODE_PHY6_XI                    (7L<<8)
 751 #define BNX2_MISC_CFG_LEDMODE_MAC3_XI                    (8L<<8)
 752 #define BNX2_MISC_CFG_LEDMODE_PHY7_XI                    (9L<<8)
 753 #define BNX2_MISC_CFG_LEDMODE_PHY8_XI                    (10L<<8)
 754 #define BNX2_MISC_CFG_LEDMODE_PHY9_XI                    (11L<<8)
 755 #define BNX2_MISC_CFG_LEDMODE_MAC4_XI                    (12L<<8)
 756 #define BNX2_MISC_CFG_LEDMODE_PHY10_XI                   (13L<<8)
 757 #define BNX2_MISC_CFG_LEDMODE_PHY11_XI                   (14L<<8)
 758 #define BNX2_MISC_CFG_LEDMODE_UNUSED_XI                  (15L<<8)
 759 #define BNX2_MISC_CFG_PORT_SELECT_XI                     (1L<<13)
 760 #define BNX2_MISC_CFG_PARITY_MODE_XI                     (1L<<14)
 761
 762 #define BNX2_MISC_ID                                    0x00000808
 763 #define BNX2_MISC_ID_BOND_ID                             (0xfL<<0)
 764 #define BNX2_MISC_ID_BOND_ID_X                           (0L<<0)
 765 #define BNX2_MISC_ID_BOND_ID_C                           (3L<<0)
 766 #define BNX2_MISC_ID_BOND_ID_S                           (12L<<0)
 767 #define BNX2_MISC_ID_CHIP_METAL                          (0xffL<<4)
 768 #define BNX2_MISC_ID_CHIP_REV                            (0xfL<<12)
 769 #define BNX2_MISC_ID_CHIP_NUM                            (0xffffL<<16)
 770
 771 #define BNX2_MISC_ENABLE_STATUS_BITS                    0x0000080c
 772 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE         (1L<<0)
 773 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE   (1L<<1)
 774 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE  (1L<<2)
 775 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE         (1L<<3)
 776 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE       (1L<<4)
 777 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE   (1L<<5)
 778 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE         (1L<<6)
 779 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE  (1L<<7)
 780 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE         (1L<<8)
 781 #define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE         (1L<<9)
 782 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE        (1L<<10)
 783 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE    (1L<<11)
 784 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE      (1L<<12)
 785 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE    (1L<<13)
 786 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE         (1L<<14)
 787 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE       (1L<<15)
 788 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE  (1L<<16)
 789 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE       (1L<<17)
 790 #define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE   (1L<<18)
 791 #define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE        (1L<<19)
 792 #define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE        (1L<<20)
 793 #define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE      (1L<<21)
 794 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE        (1L<<22)
 795 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE        (1L<<23)
 796 #define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE       (1L<<24)
 797 #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE        (1L<<25)
 798 #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE   (1L<<26)
 799 #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE          (1L<<27)
 800 #define BNX2_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE   (1L<<28)
 801 #define BNX2_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE  (0x7L<<29)
 802
 803 #define BNX2_MISC_ENABLE_SET_BITS                       0x00000810
 804 #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
 805 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE      (1L<<1)
 806 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE     (1L<<2)
 807 #define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE    (1L<<3)
 808 #define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE          (1L<<4)
 809 #define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE      (1L<<5)
 810 #define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE    (1L<<6)
 811 #define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE     (1L<<7)
 812 #define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE    (1L<<8)
 813 #define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE            (1L<<9)
 814 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE   (1L<<10)
 815 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE       (1L<<11)
 816 #define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE         (1L<<12)
 817 #define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE       (1L<<13)
 818 #define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE    (1L<<14)
 819 #define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE          (1L<<15)
 820 #define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE     (1L<<16)
 821 #define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE          (1L<<17)
 822 #define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE      (1L<<18)
 823 #define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE   (1L<<19)
 824 #define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE   (1L<<20)
 825 #define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE         (1L<<21)
 826 #define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE   (1L<<22)
 827 #define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE   (1L<<23)
 828 #define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE  (1L<<24)
 829 #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE           (1L<<25)
 830 #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE      (1L<<26)
 831 #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE             (1L<<27)
 832 #define BNX2_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE      (1L<<28)
 833 #define BNX2_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE     (0x7L<<29)
 834
 835 #define BNX2_MISC_ENABLE_CLR_BITS                       0x00000814
 836 #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
 837 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE      (1L<<1)
 838 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE     (1L<<2)
 839 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE    (1L<<3)
 840 #define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE          (1L<<4)
 841 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE      (1L<<5)
 842 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE    (1L<<6)
 843 #define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE     (1L<<7)
 844 #define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE    (1L<<8)
 845 #define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE            (1L<<9)
 846 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE   (1L<<10)
 847 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE       (1L<<11)
 848 #define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE         (1L<<12)
 849 #define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE       (1L<<13)
 850 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE    (1L<<14)
 851 #define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE          (1L<<15)
 852 #define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE     (1L<<16)
 853 #define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE          (1L<<17)
 854 #define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE      (1L<<18)
 855 #define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE   (1L<<19)
 856 #define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE   (1L<<20)
 857 #define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE         (1L<<21)
 858 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE   (1L<<22)
 859 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE   (1L<<23)
 860 #define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE  (1L<<24)
 861 #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE           (1L<<25)
 862 #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE      (1L<<26)
 863 #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE             (1L<<27)
 864 #define BNX2_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE      (1L<<28)
 865 #define BNX2_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE     (0x7L<<29)
 866
 867 #define BNX2_MISC_CLOCK_CONTROL_BITS                    0x00000818
 868 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET     (0xfL<<0)
 869 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ       (0L<<0)
 870 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ       (1L<<0)
 871 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ       (2L<<0)
 872 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ       (3L<<0)
 873 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ       (4L<<0)
 874 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ       (5L<<0)
 875 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ       (6L<<0)
 876 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ      (7L<<0)
 877 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW         (0xfL<<0)
 878 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE    (1L<<6)
 879 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT        (1L<<7)
 880 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC    (0x7L<<8)
 881 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF      (0L<<8)
 882 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12         (1L<<8)
 883 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6  (2L<<8)
 884 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62         (4L<<8)
 885 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI        (0x7L<<8)
 886 #define BNX2_MISC_CLOCK_CONTROL_BITS_MIN_POWER           (1L<<11)
 887 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED  (0xfL<<12)
 888 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100      (0L<<12)
 889 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80       (1L<<12)
 890 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50       (2L<<12)
 891 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40       (4L<<12)
 892 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25       (8L<<12)
 893 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI        (0xfL<<12)
 894 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP   (1L<<16)
 895 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE      (1L<<17)
 896 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE      (1L<<18)
 897 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE      (1L<<19)
 898 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_TE         (0xfffL<<20)
 899 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI        (1L<<17)
 900 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI        (0x3fL<<18)
 901 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI         (0x7L<<24)
 902 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI        (1L<<27)
 903 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI       (0xfL<<28)
 904
 905 #define BNX2_MISC_SPIO                                  0x0000081c
 906 #define BNX2_MISC_SPIO_VALUE                             (0xffL<<0)
 907 #define BNX2_MISC_SPIO_SET                               (0xffL<<8)
 908 #define BNX2_MISC_SPIO_CLR                               (0xffL<<16)
 909 #define BNX2_MISC_SPIO_FLOAT                             (0xffL<<24)
 910
 911 #define BNX2_MISC_SPIO_INT                              0x00000820
 912 #define BNX2_MISC_SPIO_INT_INT_STATE_TE                  (0xfL<<0)
 913 #define BNX2_MISC_SPIO_INT_OLD_VALUE_TE                  (0xfL<<8)
 914 #define BNX2_MISC_SPIO_INT_OLD_SET_TE                    (0xfL<<16)
 915 #define BNX2_MISC_SPIO_INT_OLD_CLR_TE                    (0xfL<<24)
 916 #define BNX2_MISC_SPIO_INT_INT_STATE_XI                  (0xffL<<0)
 917 #define BNX2_MISC_SPIO_INT_OLD_VALUE_XI                  (0xffL<<8)
 918 #define BNX2_MISC_SPIO_INT_OLD_SET_XI                    (0xffL<<16)
 919 #define BNX2_MISC_SPIO_INT_OLD_CLR_XI                    (0xffL<<24)
 920
 921 #define BNX2_MISC_CONFIG_LFSR                           0x00000824
 922 #define BNX2_MISC_CONFIG_LFSR_DIV                        (0xffffL<<0)
 923
 924 #define BNX2_MISC_LFSR_MASK_BITS                        0x00000828
 925 #define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE     (1L<<0)
 926 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE       (1L<<1)
 927 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE      (1L<<2)
 928 #define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE     (1L<<3)
 929 #define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE           (1L<<4)
 930 #define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE       (1L<<5)
 931 #define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE     (1L<<6)
 932 #define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE      (1L<<7)
 933 #define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE     (1L<<8)
 934 #define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE             (1L<<9)
 935 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE    (1L<<10)
 936 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE        (1L<<11)
 937 #define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE          (1L<<12)
 938 #define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE        (1L<<13)
 939 #define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE     (1L<<14)
 940 #define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE           (1L<<15)
 941 #define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE      (1L<<16)
 942 #define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE           (1L<<17)
 943 #define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE       (1L<<18)
 944 #define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE    (1L<<19)
 945 #define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE    (1L<<20)
 946 #define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE          (1L<<21)
 947 #define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE    (1L<<22)
 948 #define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE    (1L<<23)
 949 #define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE   (1L<<24)
 950 #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE            (1L<<25)
 951 #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE       (1L<<26)
 952 #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE              (1L<<27)
 953 #define BNX2_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE       (1L<<28)
 954 #define BNX2_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE      (0x7L<<29)
 955
 956 #define BNX2_MISC_ARB_REQ0                              0x0000082c
 957 #define BNX2_MISC_ARB_REQ1                              0x00000830
 958 #define BNX2_MISC_ARB_REQ2                              0x00000834
 959 #define BNX2_MISC_ARB_REQ3                              0x00000838
 960 #define BNX2_MISC_ARB_REQ4                              0x0000083c
 961 #define BNX2_MISC_ARB_FREE0                             0x00000840
 962 #define BNX2_MISC_ARB_FREE1                             0x00000844
 963 #define BNX2_MISC_ARB_FREE2                             0x00000848
 964 #define BNX2_MISC_ARB_FREE3                             0x0000084c
 965 #define BNX2_MISC_ARB_FREE4                             0x00000850
 966 #define BNX2_MISC_ARB_REQ_STATUS0                       0x00000854
 967 #define BNX2_MISC_ARB_REQ_STATUS1                       0x00000858
 968 #define BNX2_MISC_ARB_REQ_STATUS2                       0x0000085c
 969 #define BNX2_MISC_ARB_REQ_STATUS3                       0x00000860
 970 #define BNX2_MISC_ARB_REQ_STATUS4                       0x00000864
 971 #define BNX2_MISC_ARB_GNT0                              0x00000868
 972 #define BNX2_MISC_ARB_GNT0_0                             (0x7L<<0)
 973 #define BNX2_MISC_ARB_GNT0_1                             (0x7L<<4)
 974 #define BNX2_MISC_ARB_GNT0_2                             (0x7L<<8)
 975 #define BNX2_MISC_ARB_GNT0_3                             (0x7L<<12)
 976 #define BNX2_MISC_ARB_GNT0_4                             (0x7L<<16)
 977 #define BNX2_MISC_ARB_GNT0_5                             (0x7L<<20)
 978 #define BNX2_MISC_ARB_GNT0_6                             (0x7L<<24)
 979 #define BNX2_MISC_ARB_GNT0_7                             (0x7L<<28)
 980
 981 #define BNX2_MISC_ARB_GNT1                              0x0000086c
 982 #define BNX2_MISC_ARB_GNT1_8                             (0x7L<<0)
 983 #define BNX2_MISC_ARB_GNT1_9                             (0x7L<<4)
 984 #define BNX2_MISC_ARB_GNT1_10                            (0x7L<<8)
 985 #define BNX2_MISC_ARB_GNT1_11                            (0x7L<<12)
 986 #define BNX2_MISC_ARB_GNT1_12                            (0x7L<<16)
 987 #define BNX2_MISC_ARB_GNT1_13                            (0x7L<<20)
 988 #define BNX2_MISC_ARB_GNT1_14                            (0x7L<<24)
 989 #define BNX2_MISC_ARB_GNT1_15                            (0x7L<<28)
 990
 991 #define BNX2_MISC_ARB_GNT2                              0x00000870
 992 #define BNX2_MISC_ARB_GNT2_16                            (0x7L<<0)
 993 #define BNX2_MISC_ARB_GNT2_17                            (0x7L<<4)
 994 #define BNX2_MISC_ARB_GNT2_18                            (0x7L<<8)
 995 #define BNX2_MISC_ARB_GNT2_19                            (0x7L<<12)
 996 #define BNX2_MISC_ARB_GNT2_20                            (0x7L<<16)
 997 #define BNX2_MISC_ARB_GNT2_21                            (0x7L<<20)
 998 #define BNX2_MISC_ARB_GNT2_22                            (0x7L<<24)
 999 #define BNX2_MISC_ARB_GNT2_23                            (0x7L<<28)
1000
1001 #define BNX2_MISC_ARB_GNT3                              0x00000874
1002 #define BNX2_MISC_ARB_GNT3_24                            (0x7L<<0)
1003 #define BNX2_MISC_ARB_GNT3_25                            (0x7L<<4)
1004 #define BNX2_MISC_ARB_GNT3_26                            (0x7L<<8)
1005 #define BNX2_MISC_ARB_GNT3_27                            (0x7L<<12)
1006 #define BNX2_MISC_ARB_GNT3_28                            (0x7L<<16)
1007 #define BNX2_MISC_ARB_GNT3_29                            (0x7L<<20)
1008 #define BNX2_MISC_ARB_GNT3_30                            (0x7L<<24)
1009 #define BNX2_MISC_ARB_GNT3_31                            (0x7L<<28)
1010
1011 #define BNX2_MISC_RESERVED1                             0x00000878
1012 #define BNX2_MISC_RESERVED1_MISC_RESERVED1_VALUE         (0x3fL<<0)
1013
1014 #define BNX2_MISC_RESERVED2                             0x0000087c
1015 #define BNX2_MISC_RESERVED2_PCIE_DIS                     (1L<<0)
1016 #define BNX2_MISC_RESERVED2_LINK_IN_L23                  (1L<<1)
1017
1018 #define BNX2_MISC_SM_ASF_CONTROL                        0x00000880
1019 #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST                 (1L<<0)
1020 #define BNX2_MISC_SM_ASF_CONTROL_TSC_EN                  (1L<<1)
1021 #define BNX2_MISC_SM_ASF_CONTROL_WG_TO                   (1L<<2)
1022 #define BNX2_MISC_SM_ASF_CONTROL_HB_TO                   (1L<<3)
1023 #define BNX2_MISC_SM_ASF_CONTROL_PA_TO                   (1L<<4)
1024 #define BNX2_MISC_SM_ASF_CONTROL_PL_TO                   (1L<<5)
1025 #define BNX2_MISC_SM_ASF_CONTROL_RT_TO                   (1L<<6)
1026 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT               (1L<<7)
1027 #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_EN              (1L<<8)
1028 #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_PULSE           (1L<<9)
1029 #define BNX2_MISC_SM_ASF_CONTROL_RES                     (0x3L<<10)
1030 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN                  (1L<<12)
1031 #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN               (1L<<13)
1032 #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT        (1L<<14)
1033 #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD            (1L<<15)
1034 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1           (0x7fL<<16)
1035 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2           (0x7fL<<23)
1036 #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0       (1L<<30)
1037 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN          (1L<<31)
1038
1039 #define BNX2_MISC_SMB_IN                                0x00000884
1040 #define BNX2_MISC_SMB_IN_DAT_IN                          (0xffL<<0)
1041 #define BNX2_MISC_SMB_IN_RDY                             (1L<<8)
1042 #define BNX2_MISC_SMB_IN_DONE                            (1L<<9)
1043 #define BNX2_MISC_SMB_IN_FIRSTBYTE                       (1L<<10)
1044 #define BNX2_MISC_SMB_IN_STATUS                          (0x7L<<11)
1045 #define BNX2_MISC_SMB_IN_STATUS_OK                       (0x0L<<11)
1046 #define BNX2_MISC_SMB_IN_STATUS_PEC                      (0x1L<<11)
1047 #define BNX2_MISC_SMB_IN_STATUS_OFLOW                    (0x2L<<11)
1048 #define BNX2_MISC_SMB_IN_STATUS_STOP                     (0x3L<<11)
1049 #define BNX2_MISC_SMB_IN_STATUS_TIMEOUT                  (0x4L<<11)
1050
1051 #define BNX2_MISC_SMB_OUT                               0x00000888
1052 #define BNX2_MISC_SMB_OUT_DAT_OUT                        (0xffL<<0)
1053 #define BNX2_MISC_SMB_OUT_RDY                            (1L<<8)
1054 #define BNX2_MISC_SMB_OUT_START                          (1L<<9)
1055 #define BNX2_MISC_SMB_OUT_LAST                           (1L<<10)
1056 #define BNX2_MISC_SMB_OUT_ACC_TYPE                       (1L<<11)
1057 #define BNX2_MISC_SMB_OUT_ENB_PEC                        (1L<<12)
1058 #define BNX2_MISC_SMB_OUT_GET_RX_LEN                     (1L<<13)
1059 #define BNX2_MISC_SMB_OUT_SMB_READ_LEN                   (0x3fL<<14)
1060 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS                 (0xfL<<20)
1061 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK              (0L<<20)
1062 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK      (1L<<20)
1063 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW           (2L<<20)
1064 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP            (3L<<20)
1065 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT         (4L<<20)
1066 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST      (5L<<20)
1067 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK          (6L<<20)
1068 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK        (9L<<20)
1069 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST        (0xdL<<20)
1070 #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE              (1L<<24)
1071 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN                 (1L<<25)
1072 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN                 (1L<<26)
1073 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN                 (1L<<27)
1074 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN                 (1L<<28)
1075
1076 #define BNX2_MISC_SMB_WATCHDOG                          0x0000088c
1077 #define BNX2_MISC_SMB_WATCHDOG_WATCHDOG                  (0xffffL<<0)
1078
1079 #define BNX2_MISC_SMB_HEARTBEAT                         0x00000890
1080 #define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT                (0xffffL<<0)
1081
1082 #define BNX2_MISC_SMB_POLL_ASF                          0x00000894
1083 #define BNX2_MISC_SMB_POLL_ASF_POLL_ASF                  (0xffffL<<0)
1084
1085 #define BNX2_MISC_SMB_POLL_LEGACY                       0x00000898
1086 #define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY            (0xffffL<<0)
1087
1088 #define BNX2_MISC_SMB_RETRAN                            0x0000089c
1089 #define BNX2_MISC_SMB_RETRAN_RETRAN                      (0xffL<<0)
1090
1091 #define BNX2_MISC_SMB_TIMESTAMP                         0x000008a0
1092 #define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP                (0xffffffffL<<0)
1093
1094 #define BNX2_MISC_PERR_ENA0                             0x000008a4
1095 #define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC                (1L<<0)
1096 #define BNX2_MISC_PERR_ENA0_COM_MISC_REGF                (1L<<1)
1097 #define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD               (1L<<2)
1098 #define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC                 (1L<<3)
1099 #define BNX2_MISC_PERR_ENA0_CP_MISC_REGF                 (1L<<4)
1100 #define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD                (1L<<5)
1101 #define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM                 (1L<<6)
1102 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0               (1L<<7)
1103 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1               (1L<<8)
1104 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2               (1L<<9)
1105 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3               (1L<<10)
1106 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4               (1L<<11)
1107 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5               (1L<<12)
1108 #define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL               (1L<<13)
1109 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0                (1L<<14)
1110 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1                (1L<<15)
1111 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2                (1L<<16)
1112 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3                (1L<<17)
1113 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4                (1L<<18)
1114 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0                (1L<<19)
1115 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1                (1L<<20)
1116 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2                (1L<<21)
1117 #define BNX2_MISC_PERR_ENA0_HC_MISC_DMA                  (1L<<22)
1118 #define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF                (1L<<23)
1119 #define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD               (1L<<24)
1120 #define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX                  (1L<<25)
1121 #define BNX2_MISC_PERR_ENA0_RBDC_MISC                    (1L<<26)
1122 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB                 (1L<<27)
1123 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR                (1L<<28)
1124 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC                 (1L<<29)
1125 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM                 (1L<<30)
1126 #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS            (1L<<31)
1127 #define BNX2_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI          (1L<<0)
1128 #define BNX2_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI           (1L<<1)
1129 #define BNX2_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI     (1L<<2)
1130 #define BNX2_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI     (1L<<3)
1131 #define BNX2_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI         (1L<<4)
1132 #define BNX2_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI         (1L<<5)
1133 #define BNX2_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI        (1L<<6)
1134 #define BNX2_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI          (1L<<7)
1135 #define BNX2_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI         (1L<<8)
1136 #define BNX2_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI           (1L<<9)
1137 #define BNX2_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI          (1L<<10)
1138 #define BNX2_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI         (1L<<11)
1139 #define BNX2_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI          (1L<<12)
1140 #define BNX2_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI         (1L<<13)
1141 #define BNX2_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI        (1L<<14)
1142 #define BNX2_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI          (1L<<15)
1143 #define BNX2_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI         (1L<<16)
1144 #define BNX2_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI           (1L<<17)
1145 #define BNX2_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI            (1L<<18)
1146 #define BNX2_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI      (1L<<19)
1147 #define BNX2_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI      (1L<<20)
1148 #define BNX2_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI       (1L<<21)
1149 #define BNX2_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI      (1L<<22)
1150 #define BNX2_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI       (1L<<23)
1151 #define BNX2_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI       (1L<<24)
1152 #define BNX2_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI      (1L<<25)
1153 #define BNX2_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI      (1L<<26)
1154 #define BNX2_MISC_PERR_ENA0_TPBUF_PERR_EN_XI             (1L<<27)
1155 #define BNX2_MISC_PERR_ENA0_THBUF_PERR_EN_XI             (1L<<28)
1156 #define BNX2_MISC_PERR_ENA0_TDMA_PERR_EN_XI              (1L<<29)
1157 #define BNX2_MISC_PERR_ENA0_TBDC_PERR_EN_XI              (1L<<30)
1158 #define BNX2_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI           (1L<<31)
1159
1160 #define BNX2_MISC_PERR_ENA1                             0x000008a8
1161 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS            (1L<<0)
1162 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM             (1L<<1)
1163 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM             (1L<<2)
1164 #define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC                (1L<<3)
1165 #define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF                (1L<<4)
1166 #define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD               (1L<<5)
1167 #define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC               (1L<<6)
1168 #define BNX2_MISC_PERR_ENA1_TBDC_MISC                    (1L<<7)
1169 #define BNX2_MISC_PERR_ENA1_TDMA_MISC                    (1L<<8)
1170 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0               (1L<<9)
1171 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1               (1L<<10)
1172 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF               (1L<<11)
1173 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD              (1L<<12)
1174 #define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB                (1L<<13)
1175 #define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR                 (1L<<14)
1176 #define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC                (1L<<15)
1177 #define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF                (1L<<16)
1178 #define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD               (1L<<17)
1179 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX               (1L<<18)
1180 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX               (1L<<19)
1181 #define BNX2_MISC_PERR_ENA1_UMP_MISC_RX                  (1L<<20)
1182 #define BNX2_MISC_PERR_ENA1_UMP_MISC_TX                  (1L<<21)
1183 #define BNX2_MISC_PERR_ENA1_RDMAQ_MISC                   (1L<<22)
1184 #define BNX2_MISC_PERR_ENA1_CSQ_MISC                     (1L<<23)
1185 #define BNX2_MISC_PERR_ENA1_CPQ_MISC                     (1L<<24)
1186 #define BNX2_MISC_PERR_ENA1_MCPQ_MISC                    (1L<<25)
1187 #define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC                  (1L<<26)
1188 #define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC                  (1L<<27)
1189 #define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC                  (1L<<28)
1190 #define BNX2_MISC_PERR_ENA1_RXPQ_MISC                    (1L<<29)
1191 #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC                   (1L<<30)
1192 #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC                   (1L<<31)
1193 #define BNX2_MISC_PERR_ENA1_RBDC_PERR_EN_XI              (1L<<0)
1194 #define BNX2_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI        (1L<<2)
1195 #define BNX2_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI          (1L<<3)
1196 #define BNX2_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI           (1L<<4)
1197 #define BNX2_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI      (1L<<5)
1198 #define BNX2_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI      (1L<<6)
1199 #define BNX2_MISC_PERR_ENA1_TPATQ_PERR_EN_XI             (1L<<7)
1200 #define BNX2_MISC_PERR_ENA1_MCPQ_PERR_EN_XI              (1L<<8)
1201 #define BNX2_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI             (1L<<9)
1202 #define BNX2_MISC_PERR_ENA1_TXPQ_PERR_EN_XI              (1L<<10)
1203 #define BNX2_MISC_PERR_ENA1_COMTQ_PERR_EN_XI             (1L<<11)
1204 #define BNX2_MISC_PERR_ENA1_COMQ_PERR_EN_XI              (1L<<12)
1205 #define BNX2_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI             (1L<<13)
1206 #define BNX2_MISC_PERR_ENA1_RXPQ_PERR_EN_XI              (1L<<14)
1207 #define BNX2_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI            (1L<<15)
1208 #define BNX2_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI             (1L<<16)
1209 #define BNX2_MISC_PERR_ENA1_TASQ_PERR_EN_XI              (1L<<17)
1210 #define BNX2_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI             (1L<<18)
1211 #define BNX2_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI             (1L<<19)
1212 #define BNX2_MISC_PERR_ENA1_COMXQ_PERR_EN_XI             (1L<<20)
1213 #define BNX2_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI             (1L<<21)
1214 #define BNX2_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI            (1L<<22)
1215 #define BNX2_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI            (1L<<23)
1216 #define BNX2_MISC_PERR_ENA1_CPQ_PERR_EN_XI               (1L<<24)
1217 #define BNX2_MISC_PERR_ENA1_CSQ_PERR_EN_XI               (1L<<25)
1218 #define BNX2_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI          (1L<<26)
1219 #define BNX2_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI       (1L<<27)
1220 #define BNX2_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI           (1L<<28)
1221 #define BNX2_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI            (1L<<29)
1222
1223 #define BNX2_MISC_PERR_ENA2                             0x000008ac
1224 #define BNX2_MISC_PERR_ENA2_COMQ_MISC                    (1L<<0)
1225 #define BNX2_MISC_PERR_ENA2_COMXQ_MISC                   (1L<<1)
1226 #define BNX2_MISC_PERR_ENA2_COMTQ_MISC                   (1L<<2)
1227 #define BNX2_MISC_PERR_ENA2_TSCHQ_MISC                   (1L<<3)
1228 #define BNX2_MISC_PERR_ENA2_TBDRQ_MISC                   (1L<<4)
1229 #define BNX2_MISC_PERR_ENA2_TXPQ_MISC                    (1L<<5)
1230 #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC                   (1L<<6)
1231 #define BNX2_MISC_PERR_ENA2_TPATQ_MISC                   (1L<<7)
1232 #define BNX2_MISC_PERR_ENA2_TASQ_MISC                    (1L<<8)
1233 #define BNX2_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI          (1L<<0)
1234 #define BNX2_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI            (1L<<1)
1235 #define BNX2_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI            (1L<<2)
1236 #define BNX2_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI           (1L<<3)
1237 #define BNX2_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI         (1L<<4)
1238 #define BNX2_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI            (1L<<5)
1239 #define BNX2_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI       (1L<<6)
1240
1241 #define BNX2_MISC_DEBUG_VECTOR_SEL                      0x000008b0
1242 #define BNX2_MISC_DEBUG_VECTOR_SEL_0                     (0xfffL<<0)
1243 #define BNX2_MISC_DEBUG_VECTOR_SEL_1                     (0xfffL<<12)
1244 #define BNX2_MISC_DEBUG_VECTOR_SEL_1_XI                  (0xfffL<<15)
1245
1246 #define BNX2_MISC_VREG_CONTROL                          0x000008b4
1247 #define BNX2_MISC_VREG_CONTROL_1_2                       (0xfL<<0)
1248 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_XI               (0xfL<<0)
1249 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI        (0L<<0)
1250 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI        (1L<<0)
1251 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI        (2L<<0)
1252 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI         (3L<<0)
1253 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI         (4L<<0)
1254 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI         (5L<<0)
1255 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI         (6L<<0)
1256 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI           (7L<<0)
1257 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI        (8L<<0)
1258 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI        (9L<<0)
1259 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI        (10L<<0)
1260 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI        (11L<<0)
1261 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI       (12L<<0)
1262 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI       (13L<<0)
1263 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI       (14L<<0)
1264 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI       (15L<<0)
1265 #define BNX2_MISC_VREG_CONTROL_2_5                       (0xfL<<4)
1266 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS14                (0L<<4)
1267 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS12                (1L<<4)
1268 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS10                (2L<<4)
1269 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS8                 (3L<<4)
1270 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS6                 (4L<<4)
1271 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS4                 (5L<<4)
1272 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS2                 (6L<<4)
1273 #define BNX2_MISC_VREG_CONTROL_2_5_NOM                   (7L<<4)
1274 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS2                (8L<<4)
1275 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS4                (9L<<4)
1276 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS6                (10L<<4)
1277 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS8                (11L<<4)
1278 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS10               (12L<<4)
1279 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS12               (13L<<4)
1280 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS14               (14L<<4)
1281 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS16               (15L<<4)
1282 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT                  (0xfL<<8)
1283 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14           (0L<<8)
1284 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS12           (1L<<8)
1285 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS10           (2L<<8)
1286 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS8            (3L<<8)
1287 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS6            (4L<<8)
1288 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS4            (5L<<8)
1289 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS2            (6L<<8)
1290 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_NOM              (7L<<8)
1291 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS2           (8L<<8)
1292 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS4           (9L<<8)
1293 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS6           (10L<<8)
1294 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS8           (11L<<8)
1295 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS10          (12L<<8)
1296 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS12          (13L<<8)
1297 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS14          (14L<<8)
1298 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS16          (15L<<8)
1299
1300 #define BNX2_MISC_FINAL_CLK_CTL_VAL                     0x000008b8
1301 #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL       (0x3ffffffL<<6)
1302
1303 #define BNX2_MISC_GP_HW_CTL0                            0x000008bc
1304 #define BNX2_MISC_GP_HW_CTL0_TX_DRIVE                    (1L<<0)
1305 #define BNX2_MISC_GP_HW_CTL0_RMII_MODE                   (1L<<1)
1306 #define BNX2_MISC_GP_HW_CTL0_RMII_CRSDV_SEL              (1L<<2)
1307 #define BNX2_MISC_GP_HW_CTL0_RVMII_MODE                  (1L<<3)
1308 #define BNX2_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE  (1L<<4)
1309 #define BNX2_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE       (1L<<5)
1310 #define BNX2_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE    (1L<<6)
1311 #define BNX2_MISC_GP_HW_CTL0_RESERVED1_XI                (0x7L<<4)
1312 #define BNX2_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY         (1L<<7)
1313 #define BNX2_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE     (1L<<8)
1314 #define BNX2_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE         (1L<<9)
1315 #define BNX2_MISC_GP_HW_CTL0_LED_ACT_SEL_TE              (1L<<10)
1316 #define BNX2_MISC_GP_HW_CTL0_RESERVED2_XI                (0x7L<<8)
1317 #define BNX2_MISC_GP_HW_CTL0_UP1_DEF0                    (1L<<11)
1318 #define BNX2_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF          (1L<<12)
1319 #define BNX2_MISC_GP_HW_CTL0_FORCE2500_DEF               (1L<<13)
1320 #define BNX2_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF          (1L<<14)
1321 #define BNX2_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF         (1L<<15)
1322 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI                 (0xfL<<16)
1323 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA             (0L<<16)
1324 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA           (1L<<16)
1325 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA           (3L<<16)
1326 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA           (5L<<16)
1327 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA           (7L<<16)
1328 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN           (15L<<16)
1329 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS             (1L<<20)
1330 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS             (1L<<21)
1331 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT                (0x3L<<22)
1332 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P            (0L<<22)
1333 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P            (1L<<22)
1334 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P            (2L<<22)
1335 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P            (3L<<22)
1336 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT                (0x3L<<24)
1337 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P            (0L<<24)
1338 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P            (1L<<24)
1339 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P            (2L<<24)
1340 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P            (3L<<24)
1341 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ            (0x3L<<26)
1342 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA      (0L<<26)
1343 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA      (1L<<26)
1344 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA      (2L<<26)
1345 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA      (3L<<26)
1346 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ           (0x3L<<28)
1347 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA     (0L<<28)
1348 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA     (1L<<28)
1349 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA     (2L<<28)
1350 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA     (3L<<28)
1351 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ            (0x3L<<30)
1352 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57       (0L<<30)
1353 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45       (1L<<30)
1354 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62       (2L<<30)
1355 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66       (3L<<30)
1356
1357 #define BNX2_MISC_GP_HW_CTL1                            0x000008c0
1358 #define BNX2_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE         (1L<<0)
1359 #define BNX2_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE         (1L<<1)
1360 #define BNX2_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE          (1L<<2)
1361 #define BNX2_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE          (1L<<3)
1362 #define BNX2_MISC_GP_HW_CTL1_RESERVED_SOFT_XI            (0xffffL<<0)
1363 #define BNX2_MISC_GP_HW_CTL1_RESERVED_HARD_XI            (0xffffL<<16)
1364
1365 #define BNX2_MISC_NEW_HW_CTL                            0x000008c4
1366 #define BNX2_MISC_NEW_HW_CTL_MAIN_POR_BYPASS             (1L<<0)
1367 #define BNX2_MISC_NEW_HW_CTL_RINGOSC_ENABLE              (1L<<1)
1368 #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL0                (1L<<2)
1369 #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL1                (1L<<3)
1370 #define BNX2_MISC_NEW_HW_CTL_RESERVED_SHARED             (0xfffL<<4)
1371 #define BNX2_MISC_NEW_HW_CTL_RESERVED_SPLIT              (0xffffL<<16)
1372
1373 #define BNX2_MISC_NEW_CORE_CTL                          0x000008c8
1374 #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS      (1L<<0)
1375 #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ          (1L<<1)
1376 #define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN              (0x3fffL<<2)
1377 #define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC               (0xffffL<<16)
1378
1379 #define BNX2_MISC_ECO_HW_CTL                            0x000008cc
1380 #define BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN          (1L<<0)
1381 #define BNX2_MISC_ECO_HW_CTL_RESERVED_SOFT               (0x7fffL<<1)
1382 #define BNX2_MISC_ECO_HW_CTL_RESERVED_HARD               (0xffffL<<16)
1383
1384 #define BNX2_MISC_ECO_CORE_CTL                          0x000008d0
1385 #define BNX2_MISC_ECO_CORE_CTL_RESERVED_SOFT             (0xffffL<<0)
1386 #define BNX2_MISC_ECO_CORE_CTL_RESERVED_HARD             (0xffffL<<16)
1387
1388 #define BNX2_MISC_PPIO                                  0x000008d4
1389 #define BNX2_MISC_PPIO_VALUE                             (0xfL<<0)
1390 #define BNX2_MISC_PPIO_SET                               (0xfL<<8)
1391 #define BNX2_MISC_PPIO_CLR                               (0xfL<<16)
1392 #define BNX2_MISC_PPIO_FLOAT                             (0xfL<<24)
1393
1394 #define BNX2_MISC_PPIO_INT                              0x000008d8
1395 #define BNX2_MISC_PPIO_INT_INT_STATE                     (0xfL<<0)
1396 #define BNX2_MISC_PPIO_INT_OLD_VALUE                     (0xfL<<8)
1397 #define BNX2_MISC_PPIO_INT_OLD_SET                       (0xfL<<16)
1398 #define BNX2_MISC_PPIO_INT_OLD_CLR                       (0xfL<<24)
1399
1400 #define BNX2_MISC_RESET_NUMS                            0x000008dc
1401 #define BNX2_MISC_RESET_NUMS_NUM_HARD_RESETS             (0x7L<<0)
1402 #define BNX2_MISC_RESET_NUMS_NUM_PCIE_RESETS             (0x7L<<4)
1403 #define BNX2_MISC_RESET_NUMS_NUM_PERSTB_RESETS           (0x7L<<8)
1404 #define BNX2_MISC_RESET_NUMS_NUM_CMN_RESETS              (0x7L<<12)
1405 #define BNX2_MISC_RESET_NUMS_NUM_PORT_RESETS             (0x7L<<16)
1406
1407 #define BNX2_MISC_CS16_ERR                              0x000008e0
1408 #define BNX2_MISC_CS16_ERR_ENA_PCI                       (1L<<0)
1409 #define BNX2_MISC_CS16_ERR_ENA_RDMA                      (1L<<1)
1410 #define BNX2_MISC_CS16_ERR_ENA_TDMA                      (1L<<2)
1411 #define BNX2_MISC_CS16_ERR_ENA_EMAC                      (1L<<3)
1412 #define BNX2_MISC_CS16_ERR_ENA_CTX                       (1L<<4)
1413 #define BNX2_MISC_CS16_ERR_ENA_TBDR                      (1L<<5)
1414 #define BNX2_MISC_CS16_ERR_ENA_RBDC                      (1L<<6)
1415 #define BNX2_MISC_CS16_ERR_ENA_COM                       (1L<<7)
1416 #define BNX2_MISC_CS16_ERR_ENA_CP                        (1L<<8)
1417 #define BNX2_MISC_CS16_ERR_STA_PCI                       (1L<<16)
1418 #define BNX2_MISC_CS16_ERR_STA_RDMA                      (1L<<17)
1419 #define BNX2_MISC_CS16_ERR_STA_TDMA                      (1L<<18)
1420 #define BNX2_MISC_CS16_ERR_STA_EMAC                      (1L<<19)
1421 #define BNX2_MISC_CS16_ERR_STA_CTX                       (1L<<20)
1422 #define BNX2_MISC_CS16_ERR_STA_TBDR                      (1L<<21)
1423 #define BNX2_MISC_CS16_ERR_STA_RBDC                      (1L<<22)
1424 #define BNX2_MISC_CS16_ERR_STA_COM                       (1L<<23)
1425 #define BNX2_MISC_CS16_ERR_STA_CP                        (1L<<24)
1426
1427 #define BNX2_MISC_SPIO_EVENT                            0x000008e4
1428 #define BNX2_MISC_SPIO_EVENT_ENABLE                      (0xffL<<0)
1429
1430 #define BNX2_MISC_PPIO_EVENT                            0x000008e8
1431 #define BNX2_MISC_PPIO_EVENT_ENABLE                      (0xfL<<0)
1432
1433 #define BNX2_MISC_DUAL_MEDIA_CTRL                       0x000008ec
1434 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID                (0xffL<<0)
1435 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X              (0L<<0)
1436 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C              (3L<<0)
1437 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S              (12L<<0)
1438 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP         (0x7L<<8)
1439 #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN          (1L<<11)
1440 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET         (1L<<12)
1441 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET         (1L<<13)
1442 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET            (1L<<14)
1443 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET            (1L<<15)
1444 #define BNX2_MISC_DUAL_MEDIA_CTRL_LCPLL_RST              (1L<<16)
1445 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_RST            (1L<<17)
1446 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_RST            (1L<<18)
1447 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_RST               (1L<<19)
1448 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_RST               (1L<<20)
1449 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL               (0x7L<<21)
1450 #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP              (1L<<24)
1451 #define BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE         (1L<<25)
1452 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ        (0xfL<<26)
1453 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ      (1L<<26)
1454 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ      (2L<<26)
1455 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ      (4L<<26)
1456 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ      (8L<<26)
1457
1458 #define BNX2_MISC_OTP_CMD1                              0x000008f0
1459 #define BNX2_MISC_OTP_CMD1_FMODE                         (0x7L<<0)
1460 #define BNX2_MISC_OTP_CMD1_FMODE_IDLE                    (0L<<0)
1461 #define BNX2_MISC_OTP_CMD1_FMODE_WRITE                   (1L<<0)
1462 #define BNX2_MISC_OTP_CMD1_FMODE_INIT                    (2L<<0)
1463 #define BNX2_MISC_OTP_CMD1_FMODE_SET                     (3L<<0)
1464 #define BNX2_MISC_OTP_CMD1_FMODE_RST                     (4L<<0)
1465 #define BNX2_MISC_OTP_CMD1_FMODE_VERIFY                  (5L<<0)
1466 #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED0               (6L<<0)
1467 #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED1               (7L<<0)
1468 #define BNX2_MISC_OTP_CMD1_USEPINS                       (1L<<8)
1469 #define BNX2_MISC_OTP_CMD1_PROGSEL                       (1L<<9)
1470 #define BNX2_MISC_OTP_CMD1_PROGSTART                     (1L<<10)
1471 #define BNX2_MISC_OTP_CMD1_PCOUNT                        (0x7L<<16)
1472 #define BNX2_MISC_OTP_CMD1_PBYP                          (1L<<19)
1473 #define BNX2_MISC_OTP_CMD1_VSEL                          (0xfL<<20)
1474 #define BNX2_MISC_OTP_CMD1_TM                            (0x7L<<27)
1475 #define BNX2_MISC_OTP_CMD1_SADBYP                        (1L<<30)
1476 #define BNX2_MISC_OTP_CMD1_DEBUG                         (1L<<31)
1477
1478 #define BNX2_MISC_OTP_CMD2                              0x000008f4
1479 #define BNX2_MISC_OTP_CMD2_OTP_ROM_ADDR                  (0x3ffL<<0)
1480 #define BNX2_MISC_OTP_CMD2_DOSEL                         (0x7fL<<16)
1481 #define BNX2_MISC_OTP_CMD2_DOSEL_0                       (0L<<16)
1482 #define BNX2_MISC_OTP_CMD2_DOSEL_1                       (1L<<16)
1483 #define BNX2_MISC_OTP_CMD2_DOSEL_127                     (127L<<16)
1484
1485 #define BNX2_MISC_OTP_STATUS                            0x000008f8
1486 #define BNX2_MISC_OTP_STATUS_DATA                        (0xffL<<0)
1487 #define BNX2_MISC_OTP_STATUS_VALID                       (1L<<8)
1488 #define BNX2_MISC_OTP_STATUS_BUSY                        (1L<<9)
1489 #define BNX2_MISC_OTP_STATUS_BUSYSM                      (1L<<10)
1490 #define BNX2_MISC_OTP_STATUS_DONE                        (1L<<11)
1491
1492 #define BNX2_MISC_OTP_SHIFT1_CMD                        0x000008fc
1493 #define BNX2_MISC_OTP_SHIFT1_CMD_RESET_MODE_N            (1L<<0)
1494 #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_DONE              (1L<<1)
1495 #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_START             (1L<<2)
1496 #define BNX2_MISC_OTP_SHIFT1_CMD_LOAD_DATA               (1L<<3)
1497 #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT            (0x1fL<<8)
1498
1499 #define BNX2_MISC_OTP_SHIFT1_DATA                       0x00000900
1500 #define BNX2_MISC_OTP_SHIFT2_CMD                        0x00000904
1501 #define BNX2_MISC_OTP_SHIFT2_CMD_RESET_MODE_N            (1L<<0)
1502 #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_DONE              (1L<<1)
1503 #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_START             (1L<<2)
1504 #define BNX2_MISC_OTP_SHIFT2_CMD_LOAD_DATA               (1L<<3)
1505 #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT            (0x1fL<<8)
1506
1507 #define BNX2_MISC_OTP_SHIFT2_DATA                       0x00000908
1508 #define BNX2_MISC_BIST_CS0                              0x0000090c
1509 #define BNX2_MISC_BIST_CS0_MBIST_EN                      (1L<<0)
1510 #define BNX2_MISC_BIST_CS0_BIST_SETUP                    (0x3L<<1)
1511 #define BNX2_MISC_BIST_CS0_MBIST_ASYNC_RESET             (1L<<3)
1512 #define BNX2_MISC_BIST_CS0_MBIST_DONE                    (1L<<8)
1513 #define BNX2_MISC_BIST_CS0_MBIST_GO                      (1L<<9)
1514 #define BNX2_MISC_BIST_CS0_BIST_OVERRIDE                 (1L<<31)
1515
1516 #define BNX2_MISC_BIST_MEMSTATUS0                       0x00000910
1517 #define BNX2_MISC_BIST_CS1                              0x00000914
1518 #define BNX2_MISC_BIST_CS1_MBIST_EN                      (1L<<0)
1519 #define BNX2_MISC_BIST_CS1_BIST_SETUP                    (0x3L<<1)
1520 #define BNX2_MISC_BIST_CS1_MBIST_ASYNC_RESET             (1L<<3)
1521 #define BNX2_MISC_BIST_CS1_MBIST_DONE                    (1L<<8)
1522 #define BNX2_MISC_BIST_CS1_MBIST_GO                      (1L<<9)
1523
1524 #define BNX2_MISC_BIST_MEMSTATUS1                       0x00000918
1525 #define BNX2_MISC_BIST_CS2                              0x0000091c
1526 #define BNX2_MISC_BIST_CS2_MBIST_EN                      (1L<<0)
1527 #define BNX2_MISC_BIST_CS2_BIST_SETUP                    (0x3L<<1)
1528 #define BNX2_MISC_BIST_CS2_MBIST_ASYNC_RESET             (1L<<3)
1529 #define BNX2_MISC_BIST_CS2_MBIST_DONE                    (1L<<8)
1530 #define BNX2_MISC_BIST_CS2_MBIST_GO                      (1L<<9)
1531
1532 #define BNX2_MISC_BIST_MEMSTATUS2                       0x00000920
1533 #define BNX2_MISC_BIST_CS3                              0x00000924
1534 #define BNX2_MISC_BIST_CS3_MBIST_EN                      (1L<<0)
1535 #define BNX2_MISC_BIST_CS3_BIST_SETUP                    (0x3L<<1)
1536 #define BNX2_MISC_BIST_CS3_MBIST_ASYNC_RESET             (1L<<3)
1537 #define BNX2_MISC_BIST_CS3_MBIST_DONE                    (1L<<8)
1538 #define BNX2_MISC_BIST_CS3_MBIST_GO                      (1L<<9)
1539
1540 #define BNX2_MISC_BIST_MEMSTATUS3                       0x00000928
1541 #define BNX2_MISC_BIST_CS4                              0x0000092c
1542 #define BNX2_MISC_BIST_CS4_MBIST_EN                      (1L<<0)
1543 #define BNX2_MISC_BIST_CS4_BIST_SETUP                    (0x3L<<1)
1544 #define BNX2_MISC_BIST_CS4_MBIST_ASYNC_RESET             (1L<<3)
1545 #define BNX2_MISC_BIST_CS4_MBIST_DONE                    (1L<<8)
1546 #define BNX2_MISC_BIST_CS4_MBIST_GO                      (1L<<9)
1547
1548 #define BNX2_MISC_BIST_MEMSTATUS4                       0x00000930
1549 #define BNX2_MISC_BIST_CS5                              0x00000934
1550 #define BNX2_MISC_BIST_CS5_MBIST_EN                      (1L<<0)
1551 #define BNX2_MISC_BIST_CS5_BIST_SETUP                    (0x3L<<1)
1552 #define BNX2_MISC_BIST_CS5_MBIST_ASYNC_RESET             (1L<<3)
1553 #define BNX2_MISC_BIST_CS5_MBIST_DONE                    (1L<<8)
1554 #define BNX2_MISC_BIST_CS5_MBIST_GO                      (1L<<9)
1555
1556 #define BNX2_MISC_BIST_MEMSTATUS5                       0x00000938
1557 #define BNX2_MISC_MEM_TM0                               0x0000093c
1558 #define BNX2_MISC_MEM_TM0_PCIE_REPLAY_TM                 (0xfL<<0)
1559 #define BNX2_MISC_MEM_TM0_MCP_SCPAD                      (0xfL<<8)
1560 #define BNX2_MISC_MEM_TM0_UMP_TM                         (0xffL<<16)
1561 #define BNX2_MISC_MEM_TM0_HB_MEM_TM                      (0xfL<<24)
1562
1563 #define BNX2_MISC_USPLL_CTRL                            0x00000940
1564 #define BNX2_MISC_USPLL_CTRL_PH_DET_DIS                  (1L<<0)
1565 #define BNX2_MISC_USPLL_CTRL_FREQ_DET_DIS                (1L<<1)
1566 #define BNX2_MISC_USPLL_CTRL_LCPX                        (0x3fL<<2)
1567 #define BNX2_MISC_USPLL_CTRL_RX                          (0x3L<<8)
1568 #define BNX2_MISC_USPLL_CTRL_VC_EN                       (1L<<10)
1569 #define BNX2_MISC_USPLL_CTRL_VCO_MG                      (0x3L<<11)
1570 #define BNX2_MISC_USPLL_CTRL_KVCO_XF                     (0x7L<<13)
1571 #define BNX2_MISC_USPLL_CTRL_KVCO_XS                     (0x7L<<16)
1572 #define BNX2_MISC_USPLL_CTRL_TESTD_EN                    (1L<<19)
1573 #define BNX2_MISC_USPLL_CTRL_TESTD_SEL                   (0x7L<<20)
1574 #define BNX2_MISC_USPLL_CTRL_TESTA_EN                    (1L<<23)
1575 #define BNX2_MISC_USPLL_CTRL_TESTA_SEL                   (0x3L<<24)
1576 #define BNX2_MISC_USPLL_CTRL_ATTEN_FREF                  (1L<<26)
1577 #define BNX2_MISC_USPLL_CTRL_DIGITAL_RST                 (1L<<27)
1578 #define BNX2_MISC_USPLL_CTRL_ANALOG_RST                  (1L<<28)
1579 #define BNX2_MISC_USPLL_CTRL_LOCK                        (1L<<29)
1580
1581 #define BNX2_MISC_PERR_STATUS0                          0x00000944
1582 #define BNX2_MISC_PERR_STATUS0_COM_DMAE_PERR             (1L<<0)
1583 #define BNX2_MISC_PERR_STATUS0_CP_DMAE_PERR              (1L<<1)
1584 #define BNX2_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR        (1L<<2)
1585 #define BNX2_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR        (1L<<3)
1586 #define BNX2_MISC_PERR_STATUS0_CTX_PGTBL_PERR            (1L<<4)
1587 #define BNX2_MISC_PERR_STATUS0_CTX_CACHE_PERR            (1L<<5)
1588 #define BNX2_MISC_PERR_STATUS0_CTX_MIRROR_PERR           (1L<<6)
1589 #define BNX2_MISC_PERR_STATUS0_COM_CTXC_PERR             (1L<<7)
1590 #define BNX2_MISC_PERR_STATUS0_COM_SCPAD_PERR            (1L<<8)
1591 #define BNX2_MISC_PERR_STATUS0_CP_CTXC_PERR              (1L<<9)
1592 #define BNX2_MISC_PERR_STATUS0_CP_SCPAD_PERR             (1L<<10)
1593 #define BNX2_MISC_PERR_STATUS0_RXP_RBUFC_PERR            (1L<<11)
1594 #define BNX2_MISC_PERR_STATUS0_RXP_CTXC_PERR             (1L<<12)
1595 #define BNX2_MISC_PERR_STATUS0_RXP_SCPAD_PERR            (1L<<13)
1596 #define BNX2_MISC_PERR_STATUS0_TPAT_SCPAD_PERR           (1L<<14)
1597 #define BNX2_MISC_PERR_STATUS0_TXP_CTXC_PERR             (1L<<15)
1598 #define BNX2_MISC_PERR_STATUS0_TXP_SCPAD_PERR            (1L<<16)
1599 #define BNX2_MISC_PERR_STATUS0_CS_TMEM_PERR              (1L<<17)
1600 #define BNX2_MISC_PERR_STATUS0_MQ_CTX_PERR               (1L<<18)
1601 #define BNX2_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR         (1L<<19)
1602 #define BNX2_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR         (1L<<20)
1603 #define BNX2_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR          (1L<<21)
1604 #define BNX2_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR         (1L<<22)
1605 #define BNX2_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR          (1L<<23)
1606 #define BNX2_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR          (1L<<24)
1607 #define BNX2_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR         (1L<<25)
1608 #define BNX2_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR         (1L<<26)
1609 #define BNX2_MISC_PERR_STATUS0_TPBUF_PERR                (1L<<27)
1610 #define BNX2_MISC_PERR_STATUS0_THBUF_PERR                (1L<<28)
1611 #define BNX2_MISC_PERR_STATUS0_TDMA_PERR                 (1L<<29)
1612 #define BNX2_MISC_PERR_STATUS0_TBDC_PERR                 (1L<<30)
1613 #define BNX2_MISC_PERR_STATUS0_TSCH_LR_PERR              (1L<<31)
1614
1615 #define BNX2_MISC_PERR_STATUS1                          0x00000948
1616 #define BNX2_MISC_PERR_STATUS1_RBDC_PERR                 (1L<<0)
1617 #define BNX2_MISC_PERR_STATUS1_RDMA_DFIFO_PERR           (1L<<2)
1618 #define BNX2_MISC_PERR_STATUS1_HC_STATS_PERR             (1L<<3)
1619 #define BNX2_MISC_PERR_STATUS1_HC_MSIX_PERR              (1L<<4)
1620 #define BNX2_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR         (1L<<5)
1621 #define BNX2_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR         (1L<<6)
1622 #define BNX2_MISC_PERR_STATUS1_TPATQ_PERR                (1L<<7)
1623 #define BNX2_MISC_PERR_STATUS1_MCPQ_PERR                 (1L<<8)
1624 #define BNX2_MISC_PERR_STATUS1_TDMAQ_PERR                (1L<<9)
1625 #define BNX2_MISC_PERR_STATUS1_TXPQ_PERR                 (1L<<10)
1626 #define BNX2_MISC_PERR_STATUS1_COMTQ_PERR                (1L<<11)
1627 #define BNX2_MISC_PERR_STATUS1_COMQ_PERR                 (1L<<12)
1628 #define BNX2_MISC_PERR_STATUS1_RLUPQ_PERR                (1L<<13)
1629 #define BNX2_MISC_PERR_STATUS1_RXPQ_PERR                 (1L<<14)
1630 #define BNX2_MISC_PERR_STATUS1_RV2PPQ_PERR               (1L<<15)
1631 #define BNX2_MISC_PERR_STATUS1_RDMAQ_PERR                (1L<<16)
1632 #define BNX2_MISC_PERR_STATUS1_TASQ_PERR                 (1L<<17)
1633 #define BNX2_MISC_PERR_STATUS1_TBDRQ_PERR                (1L<<18)
1634 #define BNX2_MISC_PERR_STATUS1_TSCHQ_PERR                (1L<<19)
1635 #define BNX2_MISC_PERR_STATUS1_COMXQ_PERR                (1L<<20)
1636 #define BNX2_MISC_PERR_STATUS1_RXPCQ_PERR                (1L<<21)
1637 #define BNX2_MISC_PERR_STATUS1_RV2PTQ_PERR               (1L<<22)
1638 #define BNX2_MISC_PERR_STATUS1_RV2PMQ_PERR               (1L<<23)
1639 #define BNX2_MISC_PERR_STATUS1_CPQ_PERR                  (1L<<24)
1640 #define BNX2_MISC_PERR_STATUS1_CSQ_PERR                  (1L<<25)
1641 #define BNX2_MISC_PERR_STATUS1_RLUP_CID_PERR             (1L<<26)
1642 #define BNX2_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR          (1L<<27)
1643 #define BNX2_MISC_PERR_STATUS1_RV2PCSQ_PERR              (1L<<28)
1644 #define BNX2_MISC_PERR_STATUS1_MQ_IDX_PERR               (1L<<29)
1645
1646 #define BNX2_MISC_PERR_STATUS2                          0x0000094c
1647 #define BNX2_MISC_PERR_STATUS2_TGT_FIFO_PERR             (1L<<0)
1648 #define BNX2_MISC_PERR_STATUS2_UMP_TX_PERR               (1L<<1)
1649 #define BNX2_MISC_PERR_STATUS2_UMP_RX_PERR               (1L<<2)
1650 #define BNX2_MISC_PERR_STATUS2_MCP_ROM_PERR              (1L<<3)
1651 #define BNX2_MISC_PERR_STATUS2_MCP_SCPAD_PERR            (1L<<4)
1652 #define BNX2_MISC_PERR_STATUS2_HB_MEM_PERR               (1L<<5)
1653 #define BNX2_MISC_PERR_STATUS2_PCIE_REPLAY_PERR          (1L<<6)
1654
1655 #define BNX2_MISC_LCPLL_CTRL0                           0x00000950
1656 #define BNX2_MISC_LCPLL_CTRL0_OAC                        (0x7L<<0)
1657 #define BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY              (0L<<0)
1658 #define BNX2_MISC_LCPLL_CTRL0_OAC_ZERO                   (1L<<0)
1659 #define BNX2_MISC_LCPLL_CTRL0_OAC_TWENTY                 (3L<<0)
1660 #define BNX2_MISC_LCPLL_CTRL0_OAC_FORTY                  (7L<<0)
1661 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL                   (0x7L<<3)
1662 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360               (0L<<3)
1663 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_480               (1L<<3)
1664 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_600               (3L<<3)
1665 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_720               (7L<<3)
1666 #define BNX2_MISC_LCPLL_CTRL0_BIAS_CTRL                  (0x3L<<6)
1667 #define BNX2_MISC_LCPLL_CTRL0_PLL_OBSERVE                (0x7L<<8)
1668 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL                   (0x3L<<11)
1669 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0                 (0L<<11)
1670 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_1                 (1L<<11)
1671 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_2                 (2L<<11)
1672 #define BNX2_MISC_LCPLL_CTRL0_PLLSEQSTART                (1L<<13)
1673 #define BNX2_MISC_LCPLL_CTRL0_RESERVED                   (1L<<14)
1674 #define BNX2_MISC_LCPLL_CTRL0_CAPRETRY_EN                (1L<<15)
1675 #define BNX2_MISC_LCPLL_CTRL0_FREQMONITOR_EN             (1L<<16)
1676 #define BNX2_MISC_LCPLL_CTRL0_FREQDETRESTART_EN          (1L<<17)
1677 #define BNX2_MISC_LCPLL_CTRL0_FREQDETRETRY_EN            (1L<<18)
1678 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN           (1L<<19)
1679 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE              (1L<<20)
1680 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFPASS              (1L<<21)
1681 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN         (1L<<22)
1682 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE            (1L<<23)
1683 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN         (1L<<24)
1684 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS            (1L<<25)
1685 #define BNX2_MISC_LCPLL_CTRL0_CAPRESTART                 (1L<<26)
1686 #define BNX2_MISC_LCPLL_CTRL0_CAPSELECTM_EN              (1L<<27)
1687
1688 #define BNX2_MISC_LCPLL_CTRL1                           0x00000954
1689 #define BNX2_MISC_LCPLL_CTRL1_CAPSELECTM                 (0x1fL<<0)
1690 #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN        (1L<<5)
1691 #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN           (1L<<6)
1692 #define BNX2_MISC_LCPLL_CTRL1_SLOWDN_XOR                 (1L<<7)
1693
1694 #define BNX2_MISC_LCPLL_STATUS                          0x00000958
1695 #define BNX2_MISC_LCPLL_STATUS_FREQDONE_SM               (1L<<0)
1696 #define BNX2_MISC_LCPLL_STATUS_FREQPASS_SM               (1L<<1)
1697 #define BNX2_MISC_LCPLL_STATUS_PLLSEQDONE                (1L<<2)
1698 #define BNX2_MISC_LCPLL_STATUS_PLLSEQPASS                (1L<<3)
1699 #define BNX2_MISC_LCPLL_STATUS_PLLSTATE                  (0x7L<<4)
1700 #define BNX2_MISC_LCPLL_STATUS_CAPSTATE                  (0x7L<<7)
1701 #define BNX2_MISC_LCPLL_STATUS_CAPSELECT                 (0x1fL<<10)
1702 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR          (1L<<15)
1703 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0        (0L<<15)
1704 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1        (1L<<15)
1705
1706 #define BNX2_MISC_OSCFUNDS_CTRL                         0x0000095c
1707 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON                 (1L<<5)
1708 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF             (0L<<5)
1709 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_ON              (1L<<5)
1710 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM               (0x3L<<6)
1711 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0             (0L<<6)
1712 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1             (1L<<6)
1713 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2             (2L<<6)
1714 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3             (3L<<6)
1715 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ                (0x3L<<8)
1716 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0              (0L<<8)
1717 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1              (1L<<8)
1718 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2              (2L<<8)
1719 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3              (3L<<8)
1720 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ                 (0x3L<<10)
1721 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0               (0L<<10)
1722 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1               (1L<<10)
1723 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2               (2L<<10)
1724 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3               (3L<<10)
1725
1726
1727 /*
1728  *  nvm_reg definition
1729  *  offset: 0x6400
1730  */
1731 #define BNX2_NVM_COMMAND                                0x00006400
1732 #define BNX2_NVM_COMMAND_RST                             (1L<<0)
1733 #define BNX2_NVM_COMMAND_DONE                            (1L<<3)
1734 #define BNX2_NVM_COMMAND_DOIT                            (1L<<4)
1735 #define BNX2_NVM_COMMAND_WR                              (1L<<5)
1736 #define BNX2_NVM_COMMAND_ERASE                           (1L<<6)
1737 #define BNX2_NVM_COMMAND_FIRST                           (1L<<7)
1738 #define BNX2_NVM_COMMAND_LAST                            (1L<<8)
1739 #define BNX2_NVM_COMMAND_WREN                            (1L<<16)
1740 #define BNX2_NVM_COMMAND_WRDI                            (1L<<17)
1741 #define BNX2_NVM_COMMAND_EWSR                            (1L<<18)
1742 #define BNX2_NVM_COMMAND_WRSR                            (1L<<19)
1743 #define BNX2_NVM_COMMAND_RD_ID                           (1L<<20)
1744 #define BNX2_NVM_COMMAND_RD_STATUS                       (1L<<21)
1745 #define BNX2_NVM_COMMAND_MODE_256                        (1L<<22)
1746
1747 #define BNX2_NVM_STATUS                                 0x00006404
1748 #define BNX2_NVM_STATUS_PI_FSM_STATE                     (0xfL<<0)
1749 #define BNX2_NVM_STATUS_EE_FSM_STATE                     (0xfL<<4)
1750 #define BNX2_NVM_STATUS_EQ_FSM_STATE                     (0xfL<<8)
1751 #define BNX2_NVM_STATUS_SPI_FSM_STATE_XI                 (0x1fL<<0)
1752 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI        (0L<<0)
1753 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI        (1L<<0)
1754 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI        (2L<<0)
1755 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI         (3L<<0)
1756 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI         (4L<<0)
1757 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI       (5L<<0)
1758 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI         (6L<<0)
1759 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI         (7L<<0)
1760 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI         (8L<<0)
1761 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI  (9L<<0)
1762 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI  (10L<<0)
1763 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI  (11L<<0)
1764 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI   (12L<<0)
1765 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI   (13L<<0)
1766 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI   (14L<<0)
1767 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI   (15L<<0)
1768 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI   (16L<<0)
1769 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI         (17L<<0)
1770 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI     (18L<<0)
1771 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI        (19L<<0)
1772
1773 #define BNX2_NVM_WRITE                                  0x00006408
1774 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE                   (0xffffffffL<<0)
1775 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG          (0L<<0)
1776 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK             (1L<<0)
1777 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA            (2L<<0)
1778 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK              (4L<<0)
1779 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B              (8L<<0)
1780 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO                (16L<<0)
1781 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI                (32L<<0)
1782 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI_XI             (1L<<0)
1783 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO_XI             (2L<<0)
1784 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI           (4L<<0)
1785 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI           (8L<<0)
1786
1787 #define BNX2_NVM_ADDR                                   0x0000640c
1788 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE                     (0xffffffL<<0)
1789 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG            (0L<<0)
1790 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK               (1L<<0)
1791 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA              (2L<<0)
1792 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK                (4L<<0)
1793 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B                (8L<<0)
1794 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO                  (16L<<0)
1795 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI                  (32L<<0)
1796 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI_XI               (1L<<0)
1797 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO_XI               (2L<<0)
1798 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI             (4L<<0)
1799 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI             (8L<<0)
1800
1801 #define BNX2_NVM_READ                                   0x00006410
1802 #define BNX2_NVM_READ_NVM_READ_VALUE                     (0xffffffffL<<0)
1803 #define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG            (0L<<0)
1804 #define BNX2_NVM_READ_NVM_READ_VALUE_EECLK               (1L<<0)
1805 #define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA              (2L<<0)
1806 #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK                (4L<<0)
1807 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B                (8L<<0)
1808 #define BNX2_NVM_READ_NVM_READ_VALUE_SO                  (16L<<0)
1809 #define BNX2_NVM_READ_NVM_READ_VALUE_SI                  (32L<<0)
1810 #define BNX2_NVM_READ_NVM_READ_VALUE_SI_XI               (1L<<0)
1811 #define BNX2_NVM_READ_NVM_READ_VALUE_SO_XI               (2L<<0)
1812 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B_XI             (4L<<0)
1813 #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK_XI             (8L<<0)
1814
1815 #define BNX2_NVM_CFG1                                   0x00006414
1816 #define BNX2_NVM_CFG1_FLASH_MODE                         (1L<<0)
1817 #define BNX2_NVM_CFG1_BUFFER_MODE                        (1L<<1)
1818 #define BNX2_NVM_CFG1_PASS_MODE                          (1L<<2)
1819 #define BNX2_NVM_CFG1_BITBANG_MODE                       (1L<<3)
1820 #define BNX2_NVM_CFG1_STATUS_BIT                         (0x7L<<4)
1821 #define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY               (0L<<4)
1822 #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY              (7L<<4)
1823 #define BNX2_NVM_CFG1_SPI_CLK_DIV                        (0xfL<<7)
1824 #define BNX2_NVM_CFG1_SEE_CLK_DIV                        (0x7ffL<<11)
1825 #define BNX2_NVM_CFG1_STRAP_CONTROL_0                    (1L<<23)
1826 #define BNX2_NVM_CFG1_PROTECT_MODE                       (1L<<24)
1827 #define BNX2_NVM_CFG1_FLASH_SIZE                         (1L<<25)
1828 #define BNX2_NVM_CFG1_FW_USTRAP_1                        (1L<<26)
1829 #define BNX2_NVM_CFG1_FW_USTRAP_0                        (1L<<27)
1830 #define BNX2_NVM_CFG1_FW_USTRAP_2                        (1L<<28)
1831 #define BNX2_NVM_CFG1_FW_USTRAP_3                        (1L<<29)
1832 #define BNX2_NVM_CFG1_FW_FLASH_TYPE_EN                   (1L<<30)
1833 #define BNX2_NVM_CFG1_COMPAT_BYPASSS                     (1L<<31)
1834
1835 #define BNX2_NVM_CFG2                                   0x00006418
1836 #define BNX2_NVM_CFG2_ERASE_CMD                          (0xffL<<0)
1837 #define BNX2_NVM_CFG2_DUMMY                              (0xffL<<8)
1838 #define BNX2_NVM_CFG2_STATUS_CMD                         (0xffL<<16)
1839 #define BNX2_NVM_CFG2_READ_ID                            (0xffL<<24)
1840
1841 #define BNX2_NVM_CFG3                                   0x0000641c
1842 #define BNX2_NVM_CFG3_BUFFER_RD_CMD                      (0xffL<<0)
1843 #define BNX2_NVM_CFG3_WRITE_CMD                          (0xffL<<8)
1844 #define BNX2_NVM_CFG3_BUFFER_WRITE_CMD                   (0xffL<<16)
1845 #define BNX2_NVM_CFG3_READ_CMD                           (0xffL<<24)
1846
1847 #define BNX2_NVM_SW_ARB                                 0x00006420
1848 #define BNX2_NVM_SW_ARB_ARB_REQ_SET0                     (1L<<0)
1849 #define BNX2_NVM_SW_ARB_ARB_REQ_SET1                     (1L<<1)
1850 #define BNX2_NVM_SW_ARB_ARB_REQ_SET2                     (1L<<2)
1851 #define BNX2_NVM_SW_ARB_ARB_REQ_SET3                     (1L<<3)
1852 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR0                     (1L<<4)
1853 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR1                     (1L<<5)
1854 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR2                     (1L<<6)
1855 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR3                     (1L<<7)
1856 #define BNX2_NVM_SW_ARB_ARB_ARB0                         (1L<<8)
1857 #define BNX2_NVM_SW_ARB_ARB_ARB1                         (1L<<9)
1858 #define BNX2_NVM_SW_ARB_ARB_ARB2                         (1L<<10)
1859 #define BNX2_NVM_SW_ARB_ARB_ARB3                         (1L<<11)
1860 #define BNX2_NVM_SW_ARB_REQ0                             (1L<<12)
1861 #define BNX2_NVM_SW_ARB_REQ1                             (1L<<13)
1862 #define BNX2_NVM_SW_ARB_REQ2                             (1L<<14)
1863 #define BNX2_NVM_SW_ARB_REQ3                             (1L<<15)
1864
1865 #define BNX2_NVM_ACCESS_ENABLE                          0x00006424
1866 #define BNX2_NVM_ACCESS_ENABLE_EN                        (1L<<0)
1867 #define BNX2_NVM_ACCESS_ENABLE_WR_EN                     (1L<<1)
1868
1869 #define BNX2_NVM_WRITE1                                 0x00006428
1870 #define BNX2_NVM_WRITE1_WREN_CMD                         (0xffL<<0)
1871 #define BNX2_NVM_WRITE1_WRDI_CMD                         (0xffL<<8)
1872 #define BNX2_NVM_WRITE1_SR_DATA                          (0xffL<<16)
1873
1874 #define BNX2_NVM_CFG4                                   0x0000642c
1875 #define BNX2_NVM_CFG4_FLASH_SIZE                         (0x7L<<0)
1876 #define BNX2_NVM_CFG4_FLASH_SIZE_1MBIT                   (0L<<0)
1877 #define BNX2_NVM_CFG4_FLASH_SIZE_2MBIT                   (1L<<0)
1878 #define BNX2_NVM_CFG4_FLASH_SIZE_4MBIT                   (2L<<0)
1879 #define BNX2_NVM_CFG4_FLASH_SIZE_8MBIT                   (3L<<0)
1880 #define BNX2_NVM_CFG4_FLASH_SIZE_16MBIT                  (4L<<0)
1881 #define BNX2_NVM_CFG4_FLASH_SIZE_32MBIT                  (5L<<0)
1882 #define BNX2_NVM_CFG4_FLASH_SIZE_64MBIT                  (6L<<0)
1883 #define BNX2_NVM_CFG4_FLASH_SIZE_128MBIT                 (7L<<0)
1884 #define BNX2_NVM_CFG4_FLASH_VENDOR                       (1L<<3)
1885 #define BNX2_NVM_CFG4_FLASH_VENDOR_ST                    (0L<<3)
1886 #define BNX2_NVM_CFG4_FLASH_VENDOR_ATMEL                 (1L<<3)
1887 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC             (0x3L<<4)
1888 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8        (0L<<4)
1889 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9        (1L<<4)
1890 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10       (2L<<4)
1891 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11       (3L<<4)
1892 #define BNX2_NVM_CFG4_STATUS_BIT_POLARITY                (1L<<6)
1893 #define BNX2_NVM_CFG4_RESERVED                           (0x1ffffffL<<7)
1894
1895 #define BNX2_NVM_RECONFIG                               0x00006430
1896 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE               (0xfL<<0)
1897 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST            (0L<<0)
1898 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL         (1L<<0)
1899 #define BNX2_NVM_RECONFIG_RECONFIG_STRAP_VALUE           (0xfL<<4)
1900 #define BNX2_NVM_RECONFIG_RESERVED                       (0x7fffffL<<8)
1901 #define BNX2_NVM_RECONFIG_RECONFIG_DONE                  (1L<<31)
1902
1903
1904
1905 /*
1906  *  dma_reg definition
1907  *  offset: 0xc00
1908  */
1909 #define BNX2_DMA_COMMAND                                0x00000c00
1910 #define BNX2_DMA_COMMAND_ENABLE                          (1L<<0)
1911
1912 #define BNX2_DMA_STATUS                                 0x00000c04
1913 #define BNX2_DMA_STATUS_PAR_ERROR_STATE                  (1L<<0)
1914 #define BNX2_DMA_STATUS_READ_TRANSFERS_STAT              (1L<<16)
1915 #define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT         (1L<<17)
1916 #define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT          (1L<<18)
1917 #define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT     (1L<<19)
1918 #define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT   (1L<<20)
1919 #define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT             (1L<<21)
1920 #define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT        (1L<<22)
1921 #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT         (1L<<23)
1922 #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT    (1L<<24)
1923 #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT  (1L<<25)
1924 #define BNX2_DMA_STATUS_GLOBAL_ERR_XI                    (1L<<0)
1925 #define BNX2_DMA_STATUS_BME_XI                           (1L<<4)
1926
1927 #define BNX2_DMA_CONFIG                                 0x00000c08
1928 #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP                   (1L<<0)
1929 #define BNX2_DMA_CONFIG_DATA_WORD_SWAP                   (1L<<1)
1930 #define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP                   (1L<<4)
1931 #define BNX2_DMA_CONFIG_CNTL_WORD_SWAP                   (1L<<5)
1932 #define BNX2_DMA_CONFIG_ONE_DMA                          (1L<<6)
1933 #define BNX2_DMA_CONFIG_CNTL_TWO_DMA                     (1L<<7)
1934 #define BNX2_DMA_CONFIG_CNTL_FPGA_MODE                   (1L<<8)
1935 #define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA               (1L<<10)
1936 #define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY                (1L<<11)
1937 #define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE                 (0xfL<<12)
1938 #define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE                 (0xfL<<16)
1939 #define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS                 (0x7L<<20)
1940 #define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP                 (1L<<23)
1941 #define BNX2_DMA_CONFIG_BIG_SIZE                         (0xfL<<24)
1942 #define BNX2_DMA_CONFIG_BIG_SIZE_NONE                    (0x0L<<24)
1943 #define BNX2_DMA_CONFIG_BIG_SIZE_64                      (0x1L<<24)
1944 #define BNX2_DMA_CONFIG_BIG_SIZE_128                     (0x2L<<24)
1945 #define BNX2_DMA_CONFIG_BIG_SIZE_256                     (0x4L<<24)
1946 #define BNX2_DMA_CONFIG_BIG_SIZE_512                     (0x8L<<24)
1947 #define BNX2_DMA_CONFIG_DAT_WBSWAP_MODE_XI               (0x3L<<0)
1948 #define BNX2_DMA_CONFIG_CTL_WBSWAP_MODE_XI               (0x3L<<4)
1949 #define BNX2_DMA_CONFIG_MAX_PL_XI                        (0x7L<<12)
1950 #define BNX2_DMA_CONFIG_MAX_PL_128B_XI                   (0L<<12)
1951 #define BNX2_DMA_CONFIG_MAX_PL_256B_XI                   (1L<<12)
1952 #define BNX2_DMA_CONFIG_MAX_PL_512B_XI                   (2L<<12)
1953 #define BNX2_DMA_CONFIG_MAX_PL_EN_XI                     (1L<<15)
1954 #define BNX2_DMA_CONFIG_MAX_RRS_XI                       (0x7L<<16)
1955 #define BNX2_DMA_CONFIG_MAX_RRS_128B_XI                  (0L<<16)
1956 #define BNX2_DMA_CONFIG_MAX_RRS_256B_XI                  (1L<<16)
1957 #define BNX2_DMA_CONFIG_MAX_RRS_512B_XI                  (2L<<16)
1958 #define BNX2_DMA_CONFIG_MAX_RRS_1024B_XI                 (3L<<16)
1959 #define BNX2_DMA_CONFIG_MAX_RRS_2048B_XI                 (4L<<16)
1960 #define BNX2_DMA_CONFIG_MAX_RRS_4096B_XI                 (5L<<16)
1961 #define BNX2_DMA_CONFIG_MAX_RRS_EN_XI                    (1L<<19)
1962 #define BNX2_DMA_CONFIG_NO_64SWAP_EN_XI                  (1L<<31)
1963
1964 #define BNX2_DMA_BLACKOUT                               0x00000c0c
1965 #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT              (0xffL<<0)
1966 #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT          (0xffL<<8)
1967 #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT              (0xffL<<16)
1968
1969 #define BNX2_DMA_READ_MASTER_SETTING_0                  0x00000c10
1970 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP     (1L<<0)
1971 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER  (1L<<1)
1972 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY     (1L<<2)
1973 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS        (0x7L<<4)
1974 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN     (1L<<7)
1975 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP     (1L<<8)
1976 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER  (1L<<9)
1977 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY     (1L<<10)
1978 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS        (0x7L<<12)
1979 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN     (1L<<15)
1980 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP     (1L<<16)
1981 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER  (1L<<17)
1982 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY     (1L<<18)
1983 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS        (0x7L<<20)
1984 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN     (1L<<23)
1985 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP      (1L<<24)
1986 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER   (1L<<25)
1987 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PRIORITY      (1L<<26)
1988 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS         (0x7L<<28)
1989 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN      (1L<<31)
1990
1991 #define BNX2_DMA_READ_MASTER_SETTING_1                  0x00000c14
1992 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP      (1L<<0)
1993 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER   (1L<<1)
1994 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PRIORITY      (1L<<2)
1995 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS         (0x7L<<4)
1996 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PARAM_EN      (1L<<7)
1997 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP       (1L<<8)
1998 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER    (1L<<9)
1999 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PRIORITY       (1L<<10)
2000 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS  (0x7L<<12)
2001 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PARAM_EN       (1L<<15)
2002
2003 #define BNX2_DMA_WRITE_MASTER_SETTING_0                 0x00000c18
2004 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP      (1L<<0)
2005 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER   (1L<<1)
2006 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY      (1L<<2)
2007 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD        (1L<<3)
2008 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS         (0x7L<<4)
2009 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN      (1L<<7)
2010 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP    (1L<<8)
2011 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER         (1L<<9)
2012 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY    (1L<<10)
2013 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD      (1L<<11)
2014 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS       (0x7L<<12)
2015 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN    (1L<<15)
2016 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP     (1L<<24)
2017 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER  (1L<<25)
2018 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY     (1L<<26)
2019 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD       (1L<<27)
2020 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS        (0x7L<<28)
2021 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN     (1L<<31)
2022
2023 #define BNX2_DMA_WRITE_MASTER_SETTING_1                 0x00000c1c
2024 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP     (1L<<0)
2025 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER  (1L<<1)
2026 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY     (1L<<2)
2027 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD       (1L<<3)
2028 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS        (0x7L<<4)
2029 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN     (1L<<7)
2030 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP      (1L<<8)
2031 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER   (1L<<9)
2032 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY      (1L<<10)
2033 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD        (1L<<11)
2034 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS         (0x7L<<12)
2035 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN      (1L<<15)
2036
2037 #define BNX2_DMA_ARBITER                                0x00000c20
2038 #define BNX2_DMA_ARBITER_NUM_READS                       (0x7L<<0)
2039 #define BNX2_DMA_ARBITER_WR_ARB_MODE                     (1L<<4)
2040 #define BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT              (0L<<4)
2041 #define BNX2_DMA_ARBITER_WR_ARB_MODE_RND_RBN             (1L<<4)
2042 #define BNX2_DMA_ARBITER_RD_ARB_MODE                     (0x3L<<5)
2043 #define BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT              (0L<<5)
2044 #define BNX2_DMA_ARBITER_RD_ARB_MODE_RND_RBN             (1L<<5)
2045 #define BNX2_DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN         (2L<<5)
2046 #define BNX2_DMA_ARBITER_ALT_MODE_EN                     (1L<<8)
2047 #define BNX2_DMA_ARBITER_RR_MODE                         (1L<<9)
2048 #define BNX2_DMA_ARBITER_TIMER_MODE                      (1L<<10)
2049 #define BNX2_DMA_ARBITER_OUSTD_READ_REQ                  (0xfL<<12)
2050
2051 #define BNX2_DMA_ARB_TIMERS                             0x00000c24
2052 #define BNX2_DMA_ARB_TIMERS_RD_DRR_WAIT_TIME             (0xffL<<0)
2053 #define BNX2_DMA_ARB_TIMERS_TM_MIN_TIMEOUT               (0xffL<<12)
2054 #define BNX2_DMA_ARB_TIMERS_TM_MAX_TIMEOUT               (0xfffL<<20)
2055
2056 #define BNX2_DMA_DEBUG_VECT_PEEK                        0x00000c2c
2057 #define BNX2_DMA_DEBUG_VECT_PEEK_1_VALUE                 (0x7ffL<<0)
2058 #define BNX2_DMA_DEBUG_VECT_PEEK_1_PEEK_EN               (1L<<11)
2059 #define BNX2_DMA_DEBUG_VECT_PEEK_1_SEL                   (0xfL<<12)
2060 #define BNX2_DMA_DEBUG_VECT_PEEK_2_VALUE                 (0x7ffL<<16)
2061 #define BNX2_DMA_DEBUG_VECT_PEEK_2_PEEK_EN               (1L<<27)
2062 #define BNX2_DMA_DEBUG_VECT_PEEK_2_SEL                   (0xfL<<28)
2063
2064 #define BNX2_DMA_TAG_RAM_00                             0x00000c30
2065 #define BNX2_DMA_TAG_RAM_00_CHANNEL                      (0xfL<<0)
2066 #define BNX2_DMA_TAG_RAM_00_MASTER                       (0x7L<<4)
2067 #define BNX2_DMA_TAG_RAM_00_MASTER_CTX                   (0L<<4)
2068 #define BNX2_DMA_TAG_RAM_00_MASTER_RBDC                  (1L<<4)
2069 #define BNX2_DMA_TAG_RAM_00_MASTER_TBDC                  (2L<<4)
2070 #define BNX2_DMA_TAG_RAM_00_MASTER_COM                   (3L<<4)
2071 #define BNX2_DMA_TAG_RAM_00_MASTER_CP                    (4L<<4)
2072 #define BNX2_DMA_TAG_RAM_00_MASTER_TDMA                  (5L<<4)
2073 #define BNX2_DMA_TAG_RAM_00_SWAP                         (0x3L<<7)
2074 #define BNX2_DMA_TAG_RAM_00_SWAP_CONFIG                  (0L<<7)
2075 #define BNX2_DMA_TAG_RAM_00_SWAP_DATA                    (1L<<7)
2076 #define BNX2_DMA_TAG_RAM_00_SWAP_CONTROL                 (2L<<7)
2077 #define BNX2_DMA_TAG_RAM_00_FUNCTION                     (1L<<9)
2078 #define BNX2_DMA_TAG_RAM_00_VALID                        (1L<<10)
2079
2080 #define BNX2_DMA_TAG_RAM_01                             0x00000c34
2081 #define BNX2_DMA_TAG_RAM_01_CHANNEL                      (0xfL<<0)
2082 #define BNX2_DMA_TAG_RAM_01_MASTER                       (0x7L<<4)
2083 #define BNX2_DMA_TAG_RAM_01_MASTER_CTX                   (0L<<4)
2084 #define BNX2_DMA_TAG_RAM_01_MASTER_RBDC                  (1L<<4)
2085 #define BNX2_DMA_TAG_RAM_01_MASTER_TBDC                  (2L<<4)
2086 #define BNX2_DMA_TAG_RAM_01_MASTER_COM                   (3L<<4)
2087 #define BNX2_DMA_TAG_RAM_01_MASTER_CP                    (4L<<4)
2088 #define BNX2_DMA_TAG_RAM_01_MASTER_TDMA                  (5L<<4)
2089 #define BNX2_DMA_TAG_RAM_01_SWAP                         (0x3L<<7)
2090 #define BNX2_DMA_TAG_RAM_01_SWAP_CONFIG                  (0L<<7)
2091 #define BNX2_DMA_TAG_RAM_01_SWAP_DATA                    (1L<<7)
2092 #define BNX2_DMA_TAG_RAM_01_SWAP_CONTROL                 (2L<<7)
2093 #define BNX2_DMA_TAG_RAM_01_FUNCTION                     (1L<<9)
2094 #define BNX2_DMA_TAG_RAM_01_VALID                        (1L<<10)
2095
2096 #define BNX2_DMA_TAG_RAM_02                             0x00000c38
2097 #define BNX2_DMA_TAG_RAM_02_CHANNEL                      (0xfL<<0)
2098 #define BNX2_DMA_TAG_RAM_02_MASTER                       (0x7L<<4)
2099 #define BNX2_DMA_TAG_RAM_02_MASTER_CTX                   (0L<<4)
2100 #define BNX2_DMA_TAG_RAM_02_MASTER_RBDC                  (1L<<4)
2101 #define BNX2_DMA_TAG_RAM_02_MASTER_TBDC                  (2L<<4)
2102 #define BNX2_DMA_TAG_RAM_02_MASTER_COM                   (3L<<4)
2103 #define BNX2_DMA_TAG_RAM_02_MASTER_CP                    (4L<<4)
2104 #define BNX2_DMA_TAG_RAM_02_MASTER_TDMA                  (5L<<4)
2105 #define BNX2_DMA_TAG_RAM_02_SWAP                         (0x3L<<7)
2106 #define BNX2_DMA_TAG_RAM_02_SWAP_CONFIG                  (0L<<7)
2107 #define BNX2_DMA_TAG_RAM_02_SWAP_DATA                    (1L<<7)
2108 #define BNX2_DMA_TAG_RAM_02_SWAP_CONTROL                 (2L<<7)
2109 #define BNX2_DMA_TAG_RAM_02_FUNCTION                     (1L<<9)
2110 #define BNX2_DMA_TAG_RAM_02_VALID                        (1L<<10)
2111
2112 #define BNX2_DMA_TAG_RAM_03                             0x00000c3c
2113 #define BNX2_DMA_TAG_RAM_03_CHANNEL                      (0xfL<<0)
2114 #define BNX2_DMA_TAG_RAM_03_MASTER                       (0x7L<<4)
2115 #define BNX2_DMA_TAG_RAM_03_MASTER_CTX                   (0L<<4)
2116 #define BNX2_DMA_TAG_RAM_03_MASTER_RBDC                  (1L<<4)
2117 #define BNX2_DMA_TAG_RAM_03_MASTER_TBDC                  (2L<<4)
2118 #define BNX2_DMA_TAG_RAM_03_MASTER_COM                   (3L<<4)
2119 #define BNX2_DMA_TAG_RAM_03_MASTER_CP                    (4L<<4)
2120 #define BNX2_DMA_TAG_RAM_03_MASTER_TDMA                  (5L<<4)
2121 #define BNX2_DMA_TAG_RAM_03_SWAP                         (0x3L<<7)
2122 #define BNX2_DMA_TAG_RAM_03_SWAP_CONFIG                  (0L<<7)
2123 #define BNX2_DMA_TAG_RAM_03_SWAP_DATA                    (1L<<7)
2124 #define BNX2_DMA_TAG_RAM_03_SWAP_CONTROL                 (2L<<7)
2125 #define BNX2_DMA_TAG_RAM_03_FUNCTION                     (1L<<9)
2126 #define BNX2_DMA_TAG_RAM_03_VALID                        (1L<<10)
2127
2128 #define BNX2_DMA_TAG_RAM_04                             0x00000c40
2129 #define BNX2_DMA_TAG_RAM_04_CHANNEL                      (0xfL<<0)
2130 #define BNX2_DMA_TAG_RAM_04_MASTER                       (0x7L<<4)
2131 #define BNX2_DMA_TAG_RAM_04_MASTER_CTX                   (0L<<4)
2132 #define BNX2_DMA_TAG_RAM_04_MASTER_RBDC                  (1L<<4)
2133 #define BNX2_DMA_TAG_RAM_04_MASTER_TBDC                  (2L<<4)
2134 #define BNX2_DMA_TAG_RAM_04_MASTER_COM                   (3L<<4)
2135 #define BNX2_DMA_TAG_RAM_04_MASTER_CP                    (4L<<4)
2136 #define BNX2_DMA_TAG_RAM_04_MASTER_TDMA                  (5L<<4)
2137 #define BNX2_DMA_TAG_RAM_04_SWAP                         (0x3L<<7)
2138 #define BNX2_DMA_TAG_RAM_04_SWAP_CONFIG                  (0L<<7)
2139 #define BNX2_DMA_TAG_RAM_04_SWAP_DATA                    (1L<<7)
2140 #define BNX2_DMA_TAG_RAM_04_SWAP_CONTROL                 (2L<<7)
2141 #define BNX2_DMA_TAG_RAM_04_FUNCTION                     (1L<<9)
2142 #define BNX2_DMA_TAG_RAM_04_VALID                        (1L<<10)
2143
2144 #define BNX2_DMA_TAG_RAM_05                             0x00000c44
2145 #define BNX2_DMA_TAG_RAM_05_CHANNEL                      (0xfL<<0)
2146 #define BNX2_DMA_TAG_RAM_05_MASTER                       (0x7L<<4)
2147 #define BNX2_DMA_TAG_RAM_05_MASTER_CTX                   (0L<<4)
2148 #define BNX2_DMA_TAG_RAM_05_MASTER_RBDC                  (1L<<4)
2149 #define BNX2_DMA_TAG_RAM_05_MASTER_TBDC                  (2L<<4)
2150 #define BNX2_DMA_TAG_RAM_05_MASTER_COM                   (3L<<4)
2151 #define BNX2_DMA_TAG_RAM_05_MASTER_CP                    (4L<<4)
2152 #define BNX2_DMA_TAG_RAM_05_MASTER_TDMA                  (5L<<4)
2153 #define BNX2_DMA_TAG_RAM_05_SWAP                         (0x3L<<7)
2154 #define BNX2_DMA_TAG_RAM_05_SWAP_CONFIG                  (0L<<7)
2155 #define BNX2_DMA_TAG_RAM_05_SWAP_DATA                    (1L<<7)
2156 #define BNX2_DMA_TAG_RAM_05_SWAP_CONTROL                 (2L<<7)
2157 #define BNX2_DMA_TAG_RAM_05_FUNCTION                     (1L<<9)
2158 #define BNX2_DMA_TAG_RAM_05_VALID                        (1L<<10)
2159
2160 #define BNX2_DMA_TAG_RAM_06                             0x00000c48
2161 #define BNX2_DMA_TAG_RAM_06_CHANNEL                      (0xfL<<0)
2162 #define BNX2_DMA_TAG_RAM_06_MASTER                       (0x7L<<4)
2163 #define BNX2_DMA_TAG_RAM_06_MASTER_CTX                   (0L<<4)
2164 #define BNX2_DMA_TAG_RAM_06_MASTER_RBDC                  (1L<<4)
2165 #define BNX2_DMA_TAG_RAM_06_MASTER_TBDC                  (2L<<4)
2166 #define BNX2_DMA_TAG_RAM_06_MASTER_COM                   (3L<<4)
2167 #define BNX2_DMA_TAG_RAM_06_MASTER_CP                    (4L<<4)
2168 #define BNX2_DMA_TAG_RAM_06_MASTER_TDMA                  (5L<<4)
2169 #define BNX2_DMA_TAG_RAM_06_SWAP                         (0x3L<<7)
2170 #define BNX2_DMA_TAG_RAM_06_SWAP_CONFIG                  (0L<<7)
2171 #define BNX2_DMA_TAG_RAM_06_SWAP_DATA                    (1L<<7)
2172 #define BNX2_DMA_TAG_RAM_06_SWAP_CONTROL                 (2L<<7)
2173 #define BNX2_DMA_TAG_RAM_06_FUNCTION                     (1L<<9)
2174 #define BNX2_DMA_TAG_RAM_06_VALID                        (1L<<10)
2175
2176 #define BNX2_DMA_TAG_RAM_07                             0x00000c4c
2177 #define BNX2_DMA_TAG_RAM_07_CHANNEL                      (0xfL<<0)
2178 #define BNX2_DMA_TAG_RAM_07_MASTER                       (0x7L<<4)
2179 #define BNX2_DMA_TAG_RAM_07_MASTER_CTX                   (0L<<4)
2180 #define BNX2_DMA_TAG_RAM_07_MASTER_RBDC                  (1L<<4)
2181 #define BNX2_DMA_TAG_RAM_07_MASTER_TBDC                  (2L<<4)
2182 #define BNX2_DMA_TAG_RAM_07_MASTER_COM                   (3L<<4)
2183 #define BNX2_DMA_TAG_RAM_07_MASTER_CP                    (4L<<4)
2184 #define BNX2_DMA_TAG_RAM_07_MASTER_TDMA                  (5L<<4)
2185 #define BNX2_DMA_TAG_RAM_07_SWAP                         (0x3L<<7)
2186 #define BNX2_DMA_TAG_RAM_07_SWAP_CONFIG                  (0L<<7)
2187 #define BNX2_DMA_TAG_RAM_07_SWAP_DATA                    (1L<<7)
2188 #define BNX2_DMA_TAG_RAM_07_SWAP_CONTROL                 (2L<<7)
2189 #define BNX2_DMA_TAG_RAM_07_FUNCTION                     (1L<<9)
2190 #define BNX2_DMA_TAG_RAM_07_VALID                        (1L<<10)
2191
2192 #define BNX2_DMA_TAG_RAM_08                             0x00000c50
2193 #define BNX2_DMA_TAG_RAM_08_CHANNEL                      (0xfL<<0)
2194 #define BNX2_DMA_TAG_RAM_08_MASTER                       (0x7L<<4)
2195 #define BNX2_DMA_TAG_RAM_08_MASTER_CTX                   (0L<<4)
2196 #define BNX2_DMA_TAG_RAM_08_MASTER_RBDC                  (1L<<4)
2197 #define BNX2_DMA_TAG_RAM_08_MASTER_TBDC                  (2L<<4)
2198 #define BNX2_DMA_TAG_RAM_08_MASTER_COM                   (3L<<4)
2199 #define BNX2_DMA_TAG_RAM_08_MASTER_CP                    (4L<<4)
2200 #define BNX2_DMA_TAG_RAM_08_MASTER_TDMA                  (5L<<4)
2201 #define BNX2_DMA_TAG_RAM_08_SWAP                         (0x3L<<7)
2202 #define BNX2_DMA_TAG_RAM_08_SWAP_CONFIG                  (0L<<7)
2203 #define BNX2_DMA_TAG_RAM_08_SWAP_DATA                    (1L<<7)
2204 #define BNX2_DMA_TAG_RAM_08_SWAP_CONTROL                 (2L<<7)
2205 #define BNX2_DMA_TAG_RAM_08_FUNCTION                     (1L<<9)
2206 #define BNX2_DMA_TAG_RAM_08_VALID                        (1L<<10)
2207
2208 #define BNX2_DMA_TAG_RAM_09                             0x00000c54
2209 #define BNX2_DMA_TAG_RAM_09_CHANNEL                      (0xfL<<0)
2210 #define BNX2_DMA_TAG_RAM_09_MASTER                       (0x7L<<4)
2211 #define BNX2_DMA_TAG_RAM_09_MASTER_CTX                   (0L<<4)
2212 #define BNX2_DMA_TAG_RAM_09_MASTER_RBDC                  (1L<<4)
2213 #define BNX2_DMA_TAG_RAM_09_MASTER_TBDC                  (2L<<4)
2214 #define BNX2_DMA_TAG_RAM_09_MASTER_COM                   (3L<<4)
2215 #define BNX2_DMA_TAG_RAM_09_MASTER_CP                    (4L<<4)
2216 #define BNX2_DMA_TAG_RAM_09_MASTER_TDMA                  (5L<<4)
2217 #define BNX2_DMA_TAG_RAM_09_SWAP                         (0x3L<<7)
2218 #define BNX2_DMA_TAG_RAM_09_SWAP_CONFIG                  (0L<<7)
2219 #define BNX2_DMA_TAG_RAM_09_SWAP_DATA                    (1L<<7)
2220 #define BNX2_DMA_TAG_RAM_09_SWAP_CONTROL                 (2L<<7)
2221 #define BNX2_DMA_TAG_RAM_09_FUNCTION                     (1L<<9)
2222 #define BNX2_DMA_TAG_RAM_09_VALID                        (1L<<10)
2223
2224 #define BNX2_DMA_TAG_RAM_10                             0x00000c58
2225 #define BNX2_DMA_TAG_RAM_10_CHANNEL                      (0xfL<<0)
2226 #define BNX2_DMA_TAG_RAM_10_MASTER                       (0x7L<<4)
2227 #define BNX2_DMA_TAG_RAM_10_MASTER_CTX                   (0L<<4)
2228 #define BNX2_DMA_TAG_RAM_10_MASTER_RBDC                  (1L<<4)
2229 #define BNX2_DMA_TAG_RAM_10_MASTER_TBDC                  (2L<<4)
2230 #define BNX2_DMA_TAG_RAM_10_MASTER_COM                   (3L<<4)
2231 #define BNX2_DMA_TAG_RAM_10_MASTER_CP                    (4L<<4)
2232 #define BNX2_DMA_TAG_RAM_10_MASTER_TDMA                  (5L<<4)
2233 #define BNX2_DMA_TAG_RAM_10_SWAP                         (0x3L<<7)
2234 #define BNX2_DMA_TAG_RAM_10_SWAP_CONFIG                  (0L<<7)
2235 #define BNX2_DMA_TAG_RAM_10_SWAP_DATA                    (1L<<7)
2236 #define BNX2_DMA_TAG_RAM_10_SWAP_CONTROL                 (2L<<7)
2237 #define BNX2_DMA_TAG_RAM_10_FUNCTION                     (1L<<9)
2238 #define BNX2_DMA_TAG_RAM_10_VALID                        (1L<<10)
2239
2240 #define BNX2_DMA_TAG_RAM_11                             0x00000c5c
2241 #define BNX2_DMA_TAG_RAM_11_CHANNEL                      (0xfL<<0)
2242 #define BNX2_DMA_TAG_RAM_11_MASTER                       (0x7L<<4)
2243 #define BNX2_DMA_TAG_RAM_11_MASTER_CTX                   (0L<<4)
2244 #define BNX2_DMA_TAG_RAM_11_MASTER_RBDC                  (1L<<4)
2245 #define BNX2_DMA_TAG_RAM_11_MASTER_TBDC                  (2L<<4)
2246 #define BNX2_DMA_TAG_RAM_11_MASTER_COM                   (3L<<4)
2247 #define BNX2_DMA_TAG_RAM_11_MASTER_CP                    (4L<<4)
2248 #define BNX2_DMA_TAG_RAM_11_MASTER_TDMA                  (5L<<4)
2249 #define BNX2_DMA_TAG_RAM_11_SWAP                         (0x3L<<7)
2250 #define BNX2_DMA_TAG_RAM_11_SWAP_CONFIG                  (0L<<7)
2251 #define BNX2_DMA_TAG_RAM_11_SWAP_DATA                    (1L<<7)
2252 #define BNX2_DMA_TAG_RAM_11_SWAP_CONTROL                 (2L<<7)
2253 #define BNX2_DMA_TAG_RAM_11_FUNCTION                     (1L<<9)
2254 #define BNX2_DMA_TAG_RAM_11_VALID                        (1L<<10)
2255
2256 #define BNX2_DMA_RCHAN_STAT_22                          0x00000c60
2257 #define BNX2_DMA_RCHAN_STAT_30                          0x00000c64
2258 #define BNX2_DMA_RCHAN_STAT_31                          0x00000c68
2259 #define BNX2_DMA_RCHAN_STAT_32                          0x00000c6c
2260 #define BNX2_DMA_RCHAN_STAT_40                          0x00000c70
2261 #define BNX2_DMA_RCHAN_STAT_41                          0x00000c74
2262 #define BNX2_DMA_RCHAN_STAT_42                          0x00000c78
2263 #define BNX2_DMA_RCHAN_STAT_50                          0x00000c7c
2264 #define BNX2_DMA_RCHAN_STAT_51                          0x00000c80
2265 #define BNX2_DMA_RCHAN_STAT_52                          0x00000c84
2266 #define BNX2_DMA_RCHAN_STAT_60                          0x00000c88
2267 #define BNX2_DMA_RCHAN_STAT_61                          0x00000c8c
2268 #define BNX2_DMA_RCHAN_STAT_62                          0x00000c90
2269 #define BNX2_DMA_RCHAN_STAT_70                          0x00000c94
2270 #define BNX2_DMA_RCHAN_STAT_71                          0x00000c98
2271 #define BNX2_DMA_RCHAN_STAT_72                          0x00000c9c
2272 #define BNX2_DMA_WCHAN_STAT_00                          0x00000ca0
2273 #define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW   (0xffffffffL<<0)
2274
2275 #define BNX2_DMA_WCHAN_STAT_01                          0x00000ca4
2276 #define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH  (0xffffffffL<<0)
2277
2278 #define BNX2_DMA_WCHAN_STAT_02                          0x00000ca8
2279 #define BNX2_DMA_WCHAN_STAT_02_LENGTH                    (0xffffL<<0)
2280 #define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP                 (1L<<16)
2281 #define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP                 (1L<<17)
2282 #define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL              (1L<<18)
2283
2284 #define BNX2_DMA_WCHAN_STAT_10                          0x00000cac
2285 #define BNX2_DMA_WCHAN_STAT_11                          0x00000cb0
2286 #define BNX2_DMA_WCHAN_STAT_12                          0x00000cb4
2287 #define BNX2_DMA_WCHAN_STAT_20                          0x00000cb8
2288 #define BNX2_DMA_WCHAN_STAT_21                          0x00000cbc
2289 #define BNX2_DMA_WCHAN_STAT_22                          0x00000cc0
2290 #define BNX2_DMA_WCHAN_STAT_30                          0x00000cc4
2291 #define BNX2_DMA_WCHAN_STAT_31                          0x00000cc8
2292 #define BNX2_DMA_WCHAN_STAT_32                          0x00000ccc
2293 #define BNX2_DMA_WCHAN_STAT_40                          0x00000cd0
2294 #define BNX2_DMA_WCHAN_STAT_41                          0x00000cd4
2295 #define BNX2_DMA_WCHAN_STAT_42                          0x00000cd8
2296 #define BNX2_DMA_WCHAN_STAT_50                          0x00000cdc
2297 #define BNX2_DMA_WCHAN_STAT_51                          0x00000ce0
2298 #define BNX2_DMA_WCHAN_STAT_52                          0x00000ce4
2299 #define BNX2_DMA_WCHAN_STAT_60                          0x00000ce8
2300 #define BNX2_DMA_WCHAN_STAT_61                          0x00000cec
2301 #define BNX2_DMA_WCHAN_STAT_62                          0x00000cf0
2302 #define BNX2_DMA_WCHAN_STAT_70                          0x00000cf4
2303 #define BNX2_DMA_WCHAN_STAT_71                          0x00000cf8
2304 #define BNX2_DMA_WCHAN_STAT_72                          0x00000cfc
2305 #define BNX2_DMA_ARB_STAT_00                            0x00000d00
2306 #define BNX2_DMA_ARB_STAT_00_MASTER                      (0xffffL<<0)
2307 #define BNX2_DMA_ARB_STAT_00_MASTER_ENC                  (0xffL<<16)
2308 #define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR                 (0xffL<<24)
2309
2310 #define BNX2_DMA_ARB_STAT_01                            0x00000d04
2311 #define BNX2_DMA_ARB_STAT_01_LPR_RPTR                    (0xfL<<0)
2312 #define BNX2_DMA_ARB_STAT_01_LPR_WPTR                    (0xfL<<4)
2313 #define BNX2_DMA_ARB_STAT_01_LPB_RPTR                    (0xfL<<8)
2314 #define BNX2_DMA_ARB_STAT_01_LPB_WPTR                    (0xfL<<12)
2315 #define BNX2_DMA_ARB_STAT_01_HPR_RPTR                    (0xfL<<16)
2316 #define BNX2_DMA_ARB_STAT_01_HPR_WPTR                    (0xfL<<20)
2317 #define BNX2_DMA_ARB_STAT_01_HPB_RPTR                    (0xfL<<24)
2318 #define BNX2_DMA_ARB_STAT_01_HPB_WPTR                    (0xfL<<28)
2319
2320 #define BNX2_DMA_FUSE_CTRL0_CMD                         0x00000f00
2321 #define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE               (1L<<0)
2322 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE               (1L<<1)
2323 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT                    (1L<<2)
2324 #define BNX2_DMA_FUSE_CTRL0_CMD_LOAD                     (1L<<3)
2325 #define BNX2_DMA_FUSE_CTRL0_CMD_SEL                      (0xfL<<8)
2326
2327 #define BNX2_DMA_FUSE_CTRL0_DATA                        0x00000f04
2328 #define BNX2_DMA_FUSE_CTRL1_CMD                         0x00000f08
2329 #define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE               (1L<<0)
2330 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE               (1L<<1)
2331 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT                    (1L<<2)
2332 #define BNX2_DMA_FUSE_CTRL1_CMD_LOAD                     (1L<<3)
2333 #define BNX2_DMA_FUSE_CTRL1_CMD_SEL                      (0xfL<<8)
2334
2335 #define BNX2_DMA_FUSE_CTRL1_DATA                        0x00000f0c
2336 #define BNX2_DMA_FUSE_CTRL2_CMD                         0x00000f10
2337 #define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE               (1L<<0)
2338 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE               (1L<<1)
2339 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT                    (1L<<2)
2340 #define BNX2_DMA_FUSE_CTRL2_CMD_LOAD                     (1L<<3)
2341 #define BNX2_DMA_FUSE_CTRL2_CMD_SEL                      (0xfL<<8)
2342
2343 #define BNX2_DMA_FUSE_CTRL2_DATA                        0x00000f14
2344
2345
2346 /*
2347  *  context_reg definition
2348  *  offset: 0x1000
2349  */
2350 #define BNX2_CTX_COMMAND                                0x00001000
2351 #define BNX2_CTX_COMMAND_ENABLED                         (1L<<0)
2352 #define BNX2_CTX_COMMAND_DISABLE_USAGE_CNT               (1L<<1)
2353 #define BNX2_CTX_COMMAND_DISABLE_PLRU                    (1L<<2)
2354 #define BNX2_CTX_COMMAND_DISABLE_COMBINE_READ            (1L<<3)
2355 #define BNX2_CTX_COMMAND_FLUSH_AHEAD                     (0x1fL<<8)
2356 #define BNX2_CTX_COMMAND_MEM_INIT                        (1L<<13)
2357 #define BNX2_CTX_COMMAND_PAGE_SIZE                       (0xfL<<16)
2358 #define BNX2_CTX_COMMAND_PAGE_SIZE_256                   (0L<<16)
2359 #define BNX2_CTX_COMMAND_PAGE_SIZE_512                   (1L<<16)
2360 #define BNX2_CTX_COMMAND_PAGE_SIZE_1K                    (2L<<16)
2361 #define BNX2_CTX_COMMAND_PAGE_SIZE_2K                    (3L<<16)
2362 #define BNX2_CTX_COMMAND_PAGE_SIZE_4K                    (4L<<16)
2363 #define BNX2_CTX_COMMAND_PAGE_SIZE_8K                    (5L<<16)
2364 #define BNX2_CTX_COMMAND_PAGE_SIZE_16K                   (6L<<16)
2365 #define BNX2_CTX_COMMAND_PAGE_SIZE_32K                   (7L<<16)
2366 #define BNX2_CTX_COMMAND_PAGE_SIZE_64K                   (8L<<16)
2367 #define BNX2_CTX_COMMAND_PAGE_SIZE_128K                  (9L<<16)
2368 #define BNX2_CTX_COMMAND_PAGE_SIZE_256K                  (10L<<16)
2369 #define BNX2_CTX_COMMAND_PAGE_SIZE_512K                  (11L<<16)
2370 #define BNX2_CTX_COMMAND_PAGE_SIZE_1M                    (12L<<16)
2371
2372 #define BNX2_CTX_STATUS                                 0x00001004
2373 #define BNX2_CTX_STATUS_LOCK_WAIT                        (1L<<0)
2374 #define BNX2_CTX_STATUS_READ_STAT                        (1L<<16)
2375 #define BNX2_CTX_STATUS_WRITE_STAT                       (1L<<17)
2376 #define BNX2_CTX_STATUS_ACC_STALL_STAT                   (1L<<18)
2377 #define BNX2_CTX_STATUS_LOCK_STALL_STAT                  (1L<<19)
2378 #define BNX2_CTX_STATUS_EXT_READ_STAT                    (1L<<20)
2379 #define BNX2_CTX_STATUS_EXT_WRITE_STAT                   (1L<<21)
2380 #define BNX2_CTX_STATUS_MISS_STAT                        (1L<<22)
2381 #define BNX2_CTX_STATUS_HIT_STAT                         (1L<<23)
2382 #define BNX2_CTX_STATUS_DEAD_LOCK                        (1L<<24)
2383 #define BNX2_CTX_STATUS_USAGE_CNT_ERR                    (1L<<25)
2384 #define BNX2_CTX_STATUS_INVALID_PAGE                     (1L<<26)
2385
2386 #define BNX2_CTX_VIRT_ADDR                              0x00001008
2387 #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR                     (0x7fffL<<6)
2388
2389 #define BNX2_CTX_PAGE_TBL                               0x0000100c
2390 #define BNX2_CTX_PAGE_TBL_PAGE_TBL                       (0x3fffL<<6)
2391
2392 #define BNX2_CTX_DATA_ADR                               0x00001010
2393 #define BNX2_CTX_DATA_ADR_DATA_ADR                       (0x7ffffL<<2)
2394
2395 #define BNX2_CTX_DATA                                   0x00001014
2396 #define BNX2_CTX_LOCK                                   0x00001018
2397 #define BNX2_CTX_LOCK_TYPE                               (0x7L<<0)
2398 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID                (0x0L<<0)
2399 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL            (0x1L<<0)
2400 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX                  (0x2L<<0)
2401 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER               (0x4L<<0)
2402 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE            (0x7L<<0)
2403 #define BNX2_CTX_LOCK_TYPE_VOID_XI                       (0L<<0)
2404 #define BNX2_CTX_LOCK_TYPE_PROTOCOL_XI                   (1L<<0)
2405 #define BNX2_CTX_LOCK_TYPE_TX_XI                         (2L<<0)
2406 #define BNX2_CTX_LOCK_TYPE_TIMER_XI                      (4L<<0)
2407 #define BNX2_CTX_LOCK_TYPE_COMPLETE_XI                   (7L<<0)
2408 #define BNX2_CTX_LOCK_CID_VALUE                          (0x3fffL<<7)
2409 #define BNX2_CTX_LOCK_GRANTED                            (1L<<26)
2410 #define BNX2_CTX_LOCK_MODE                               (0x7L<<27)
2411 #define BNX2_CTX_LOCK_MODE_UNLOCK                        (0x0L<<27)
2412 #define BNX2_CTX_LOCK_MODE_IMMEDIATE                     (0x1L<<27)
2413 #define BNX2_CTX_LOCK_MODE_SURE                          (0x2L<<27)
2414 #define BNX2_CTX_LOCK_STATUS                             (1L<<30)
2415 #define BNX2_CTX_LOCK_REQ                                (1L<<31)
2416
2417 #define BNX2_CTX_CTX_CTRL                               0x0000101c
2418 #define BNX2_CTX_CTX_CTRL_CTX_ADDR                       (0x7ffffL<<2)
2419 #define BNX2_CTX_CTX_CTRL_MOD_USAGE_CNT                  (0x3L<<21)
2420 #define BNX2_CTX_CTX_CTRL_NO_RAM_ACC                     (1L<<23)
2421 #define BNX2_CTX_CTX_CTRL_PREFETCH_SIZE                  (0x3L<<24)
2422 #define BNX2_CTX_CTX_CTRL_ATTR                           (1L<<26)
2423 #define BNX2_CTX_CTX_CTRL_WRITE_REQ                      (1L<<30)
2424 #define BNX2_CTX_CTX_CTRL_READ_REQ                       (1L<<31)
2425
2426 #define BNX2_CTX_CTX_DATA                               0x00001020
2427 #define BNX2_CTX_ACCESS_STATUS                          0x00001040
2428 #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED             (0xfL<<0)
2429 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM            (0x3L<<10)
2430 #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM           (0x3L<<12)
2431 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM        (0x3L<<14)
2432 #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST         (0x7ffL<<17)
2433 #define BNX2_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI       (0x1fL<<0)
2434 #define BNX2_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI     (0x1fL<<5)
2435 #define BNX2_CTX_ACCESS_STATUS_REQUEST_XI                (0x3fffffL<<10)
2436
2437 #define BNX2_CTX_DBG_LOCK_STATUS                        0x00001044
2438 #define BNX2_CTX_DBG_LOCK_STATUS_SM                      (0x3ffL<<0)
2439 #define BNX2_CTX_DBG_LOCK_STATUS_MATCH                   (0x3ffL<<22)
2440
2441 #define BNX2_CTX_CACHE_CTRL_STATUS                      0x00001048
2442 #define BNX2_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW        (1L<<0)
2443 #define BNX2_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP     (1L<<1)
2444 #define BNX2_CTX_CACHE_CTRL_STATUS_FLUSH_START           (1L<<6)
2445 #define BNX2_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT        (0x3fL<<7)
2446 #define BNX2_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED    (0x3fL<<13)
2447 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE       (1L<<19)
2448 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE       (1L<<20)
2449 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE       (1L<<21)
2450 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE       (1L<<22)
2451 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE       (1L<<23)
2452 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE       (1L<<24)
2453 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE       (1L<<25)
2454 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE       (1L<<26)
2455 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE       (1L<<27)
2456 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE       (1L<<28)
2457 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE      (1L<<29)
2458
2459 #define BNX2_CTX_CACHE_CTRL_SM_STATUS                   0x0000104c
2460 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_DWC             (0x7L<<0)
2461 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC          (0x7L<<3)
2462 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC           (0x7L<<6)
2463 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC          (0x7L<<9)
2464 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR   (0x7fffL<<16)
2465
2466 #define BNX2_CTX_CACHE_STATUS                           0x00001050
2467 #define BNX2_CTX_CACHE_STATUS_HELD_ENTRIES               (0x3ffL<<0)
2468 #define BNX2_CTX_CACHE_STATUS_MAX_HELD_ENTRIES           (0x3ffL<<16)
2469
2470 #define BNX2_CTX_DMA_STATUS                             0x00001054
2471 #define BNX2_CTX_DMA_STATUS_RD_CHAN0_STATUS              (0x3L<<0)
2472 #define BNX2_CTX_DMA_STATUS_RD_CHAN1_STATUS              (0x3L<<2)
2473 #define BNX2_CTX_DMA_STATUS_RD_CHAN2_STATUS              (0x3L<<4)
2474 #define BNX2_CTX_DMA_STATUS_RD_CHAN3_STATUS              (0x3L<<6)
2475 #define BNX2_CTX_DMA_STATUS_RD_CHAN4_STATUS              (0x3L<<8)
2476 #define BNX2_CTX_DMA_STATUS_RD_CHAN5_STATUS              (0x3L<<10)
2477 #define BNX2_CTX_DMA_STATUS_RD_CHAN6_STATUS              (0x3L<<12)
2478 #define BNX2_CTX_DMA_STATUS_RD_CHAN7_STATUS              (0x3L<<14)
2479 #define BNX2_CTX_DMA_STATUS_RD_CHAN8_STATUS              (0x3L<<16)
2480 #define BNX2_CTX_DMA_STATUS_RD_CHAN9_STATUS              (0x3L<<18)
2481 #define BNX2_CTX_DMA_STATUS_RD_CHAN10_STATUS             (0x3L<<20)
2482
2483 #define BNX2_CTX_REP_STATUS                             0x00001058
2484 #define BNX2_CTX_REP_STATUS_ERROR_ENTRY                  (0x3ffL<<0)
2485 #define BNX2_CTX_REP_STATUS_ERROR_CLIENT_ID              (0x1fL<<10)
2486 #define BNX2_CTX_REP_STATUS_USAGE_CNT_MAX_ERR            (1L<<16)
2487 #define BNX2_CTX_REP_STATUS_USAGE_CNT_MIN_ERR            (1L<<17)
2488 #define BNX2_CTX_REP_STATUS_USAGE_CNT_MISS_ERR           (1L<<18)
2489
2490 #define BNX2_CTX_CKSUM_ERROR_STATUS                     0x0000105c
2491 #define BNX2_CTX_CKSUM_ERROR_STATUS_CALCULATED           (0xffffL<<0)
2492 #define BNX2_CTX_CKSUM_ERROR_STATUS_EXPECTED             (0xffffL<<16)
2493
2494 #define BNX2_CTX_CHNL_LOCK_STATUS_0                     0x00001080
2495 #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID                  (0x3fffL<<0)
2496 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE                 (0x3L<<14)
2497 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE                 (1L<<16)
2498 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE_XI              (1L<<14)
2499 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE_XI              (0x7L<<15)
2500
2501 #define BNX2_CTX_CHNL_LOCK_STATUS_1                     0x00001084
2502 #define BNX2_CTX_CHNL_LOCK_STATUS_2                     0x00001088
2503 #define BNX2_CTX_CHNL_LOCK_STATUS_3                     0x0000108c
2504 #define BNX2_CTX_CHNL_LOCK_STATUS_4                     0x00001090
2505 #define BNX2_CTX_CHNL_LOCK_STATUS_5                     0x00001094
2506 #define BNX2_CTX_CHNL_LOCK_STATUS_6                     0x00001098
2507 #define BNX2_CTX_CHNL_LOCK_STATUS_7                     0x0000109c
2508 #define BNX2_CTX_CHNL_LOCK_STATUS_8                     0x000010a0
2509 #define BNX2_CTX_CHNL_LOCK_STATUS_9                     0x000010a4
2510
2511 #define BNX2_CTX_CACHE_DATA                             0x000010c4
2512 #define BNX2_CTX_HOST_PAGE_TBL_CTRL                     0x000010c8
2513 #define BNX2_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR        (0x1ffL<<0)
2514 #define BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ            (1L<<30)
2515 #define BNX2_CTX_HOST_PAGE_TBL_CTRL_READ_REQ             (1L<<31)
2516
2517 #define BNX2_CTX_HOST_PAGE_TBL_DATA0                    0x000010cc
2518 #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID               (1L<<0)
2519 #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALUE               (0xffffffL<<8)
2520
2521 #define BNX2_CTX_HOST_PAGE_TBL_DATA1                    0x000010d0
2522 #define BNX2_CTX_CAM_CTRL                               0x000010d4
2523 #define BNX2_CTX_CAM_CTRL_CAM_ADDR                       (0x3ffL<<0)
2524 #define BNX2_CTX_CAM_CTRL_RESET                          (1L<<27)
2525 #define BNX2_CTX_CAM_CTRL_INVALIDATE                     (1L<<28)
2526 #define BNX2_CTX_CAM_CTRL_SEARCH                         (1L<<29)
2527 #define BNX2_CTX_CAM_CTRL_WRITE_REQ                      (1L<<30)
2528 #define BNX2_CTX_CAM_CTRL_READ_REQ                       (1L<<31)
2529
2530
2531 /*
2532  *  emac_reg definition
2533  *  offset: 0x1400
2534  */
2535 #define BNX2_EMAC_MODE                                  0x00001400
2536 #define BNX2_EMAC_MODE_RESET                             (1L<<0)
2537 #define BNX2_EMAC_MODE_HALF_DUPLEX                       (1L<<1)
2538 #define BNX2_EMAC_MODE_PORT                              (0x3L<<2)
2539 #define BNX2_EMAC_MODE_PORT_NONE                         (0L<<2)
2540 #define BNX2_EMAC_MODE_PORT_MII                          (1L<<2)
2541 #define BNX2_EMAC_MODE_PORT_GMII                         (2L<<2)
2542 #define BNX2_EMAC_MODE_PORT_MII_10M                      (3L<<2)
2543 #define BNX2_EMAC_MODE_MAC_LOOP                          (1L<<4)
2544 #define BNX2_EMAC_MODE_25G_MODE                          (1L<<5)
2545 #define BNX2_EMAC_MODE_TAGGED_MAC_CTL                    (1L<<7)
2546 #define BNX2_EMAC_MODE_TX_BURST                          (1L<<8)
2547 #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA                (1L<<9)
2548 #define BNX2_EMAC_MODE_EXT_LINK_POL                      (1L<<10)
2549 #define BNX2_EMAC_MODE_FORCE_LINK                        (1L<<11)
2550 #define BNX2_EMAC_MODE_SERDES_MODE                       (1L<<12)
2551 #define BNX2_EMAC_MODE_BOND_OVRD                         (1L<<13)
2552 #define BNX2_EMAC_MODE_MPKT                              (1L<<18)
2553 #define BNX2_EMAC_MODE_MPKT_RCVD                         (1L<<19)
2554 #define BNX2_EMAC_MODE_ACPI_RCVD                         (1L<<20)
2555
2556 #define BNX2_EMAC_STATUS                                0x00001404
2557 #define BNX2_EMAC_STATUS_LINK                            (1L<<11)
2558 #define BNX2_EMAC_STATUS_LINK_CHANGE                     (1L<<12)
2559 #define BNX2_EMAC_STATUS_SERDES_AUTONEG_COMPLETE         (1L<<13)
2560 #define BNX2_EMAC_STATUS_SERDES_AUTONEG_CHANGE           (1L<<14)
2561 #define BNX2_EMAC_STATUS_SERDES_NXT_PG_CHANGE            (1L<<16)
2562 #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0           (1L<<17)
2563 #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE    (1L<<18)
2564 #define BNX2_EMAC_STATUS_MI_COMPLETE                     (1L<<22)
2565 #define BNX2_EMAC_STATUS_MI_INT                          (1L<<23)
2566 #define BNX2_EMAC_STATUS_AP_ERROR                        (1L<<24)
2567 #define BNX2_EMAC_STATUS_PARITY_ERROR_STATE              (1L<<31)
2568
2569 #define BNX2_EMAC_ATTENTION_ENA                         0x00001408
2570 #define BNX2_EMAC_ATTENTION_ENA_LINK                     (1L<<11)
2571 #define BNX2_EMAC_ATTENTION_ENA_AUTONEG_CHANGE           (1L<<14)
2572 #define BNX2_EMAC_ATTENTION_ENA_NXT_PG_CHANGE            (1L<<16)
2573 #define BNX2_EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE     (1L<<18)
2574 #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE              (1L<<22)
2575 #define BNX2_EMAC_ATTENTION_ENA_MI_INT                   (1L<<23)
2576 #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR                 (1L<<24)
2577
2578 #define BNX2_EMAC_LED                                   0x0000140c
2579 #define BNX2_EMAC_LED_OVERRIDE                           (1L<<0)
2580 #define BNX2_EMAC_LED_1000MB_OVERRIDE                    (1L<<1)
2581 #define BNX2_EMAC_LED_100MB_OVERRIDE                     (1L<<2)
2582 #define BNX2_EMAC_LED_10MB_OVERRIDE                      (1L<<3)
2583 #define BNX2_EMAC_LED_TRAFFIC_OVERRIDE                   (1L<<4)
2584 #define BNX2_EMAC_LED_BLNK_TRAFFIC                       (1L<<5)
2585 #define BNX2_EMAC_LED_TRAFFIC                            (1L<<6)
2586 #define BNX2_EMAC_LED_1000MB                             (1L<<7)
2587 #define BNX2_EMAC_LED_100MB                              (1L<<8)
2588 #define BNX2_EMAC_LED_10MB                               (1L<<9)
2589 #define BNX2_EMAC_LED_TRAFFIC_STAT                       (1L<<10)
2590 #define BNX2_EMAC_LED_2500MB                             (1L<<11)
2591 #define BNX2_EMAC_LED_2500MB_OVERRIDE                    (1L<<12)
2592 #define BNX2_EMAC_LED_ACTIVITY_SEL                       (0x3L<<17)
2593 #define BNX2_EMAC_LED_ACTIVITY_SEL_0                     (0L<<17)
2594 #define BNX2_EMAC_LED_ACTIVITY_SEL_1                     (1L<<17)
2595 #define BNX2_EMAC_LED_ACTIVITY_SEL_2                     (2L<<17)
2596 #define BNX2_EMAC_LED_ACTIVITY_SEL_3                     (3L<<17)
2597 #define BNX2_EMAC_LED_BLNK_RATE                          (0xfffL<<19)
2598 #define BNX2_EMAC_LED_BLNK_RATE_ENA                      (1L<<31)
2599
2600 #define BNX2_EMAC_MAC_MATCH0                            0x00001410
2601 #define BNX2_EMAC_MAC_MATCH1                            0x00001414
2602 #define BNX2_EMAC_MAC_MATCH2                            0x00001418
2603 #define BNX2_EMAC_MAC_MATCH3                            0x0000141c
2604 #define BNX2_EMAC_MAC_MATCH4                            0x00001420
2605 #define BNX2_EMAC_MAC_MATCH5                            0x00001424
2606 #define BNX2_EMAC_MAC_MATCH6                            0x00001428
2607 #define BNX2_EMAC_MAC_MATCH7                            0x0000142c
2608 #define BNX2_EMAC_MAC_MATCH8                            0x00001430
2609 #define BNX2_EMAC_MAC_MATCH9                            0x00001434
2610 #define BNX2_EMAC_MAC_MATCH10                           0x00001438
2611 #define BNX2_EMAC_MAC_MATCH11                           0x0000143c
2612 #define BNX2_EMAC_MAC_MATCH12                           0x00001440
2613 #define BNX2_EMAC_MAC_MATCH13                           0x00001444
2614 #define BNX2_EMAC_MAC_MATCH14                           0x00001448
2615 #define BNX2_EMAC_MAC_MATCH15                           0x0000144c
2616 #define BNX2_EMAC_MAC_MATCH16                           0x00001450
2617 #define BNX2_EMAC_MAC_MATCH17                           0x00001454
2618 #define BNX2_EMAC_MAC_MATCH18                           0x00001458
2619 #define BNX2_EMAC_MAC_MATCH19                           0x0000145c
2620 #define BNX2_EMAC_MAC_MATCH20                           0x00001460
2621 #define BNX2_EMAC_MAC_MATCH21                           0x00001464
2622 #define BNX2_EMAC_MAC_MATCH22                           0x00001468
2623 #define BNX2_EMAC_MAC_MATCH23                           0x0000146c
2624 #define BNX2_EMAC_MAC_MATCH24                           0x00001470
2625 #define BNX2_EMAC_MAC_MATCH25                           0x00001474
2626 #define BNX2_EMAC_MAC_MATCH26                           0x00001478
2627 #define BNX2_EMAC_MAC_MATCH27                           0x0000147c
2628 #define BNX2_EMAC_MAC_MATCH28                           0x00001480
2629 #define BNX2_EMAC_MAC_MATCH29                           0x00001484
2630 #define BNX2_EMAC_MAC_MATCH30                           0x00001488
2631 #define BNX2_EMAC_MAC_MATCH31                           0x0000148c
2632 #define BNX2_EMAC_BACKOFF_SEED                          0x00001498
2633 #define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED         (0x3ffL<<0)
2634
2635 #define BNX2_EMAC_RX_MTU_SIZE                           0x0000149c
2636 #define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE                   (0xffffL<<0)
2637 #define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA                  (1L<<31)
2638
2639 #define BNX2_EMAC_SERDES_CNTL                           0x000014a4
2640 #define BNX2_EMAC_SERDES_CNTL_RXR                        (0x7L<<0)
2641 #define BNX2_EMAC_SERDES_CNTL_RXG                        (0x3L<<3)
2642 #define BNX2_EMAC_SERDES_CNTL_RXCKSEL                    (1L<<6)
2643 #define BNX2_EMAC_SERDES_CNTL_TXBIAS                     (0x7L<<7)
2644 #define BNX2_EMAC_SERDES_CNTL_BGMAX                      (1L<<10)
2645 #define BNX2_EMAC_SERDES_CNTL_BGMIN                      (1L<<11)
2646 #define BNX2_EMAC_SERDES_CNTL_TXMODE                     (1L<<12)
2647 #define BNX2_EMAC_SERDES_CNTL_TXEDGE                     (1L<<13)
2648 #define BNX2_EMAC_SERDES_CNTL_SERDES_MODE                (1L<<14)
2649 #define BNX2_EMAC_SERDES_CNTL_PLLTEST                    (1L<<15)
2650 #define BNX2_EMAC_SERDES_CNTL_CDET_EN                    (1L<<16)
2651 #define BNX2_EMAC_SERDES_CNTL_TBI_LBK                    (1L<<17)
2652 #define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK                 (1L<<18)
2653 #define BNX2_EMAC_SERDES_CNTL_REV_PHASE                  (1L<<19)
2654 #define BNX2_EMAC_SERDES_CNTL_REGCTL12                   (0x3L<<20)
2655 #define BNX2_EMAC_SERDES_CNTL_REGCTL25                   (0x3L<<22)
2656
2657 #define BNX2_EMAC_SERDES_STATUS                         0x000014a8
2658 #define BNX2_EMAC_SERDES_STATUS_RX_STAT                  (0xffL<<0)
2659 #define BNX2_EMAC_SERDES_STATUS_COMMA_DET                (1L<<8)
2660
2661 #define BNX2_EMAC_MDIO_COMM                             0x000014ac
2662 #define BNX2_EMAC_MDIO_COMM_DATA                         (0xffffL<<0)
2663 #define BNX2_EMAC_MDIO_COMM_REG_ADDR                     (0x1fL<<16)
2664 #define BNX2_EMAC_MDIO_COMM_PHY_ADDR                     (0x1fL<<21)
2665 #define BNX2_EMAC_MDIO_COMM_COMMAND                      (0x3L<<26)
2666 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0          (0L<<26)
2667 #define BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS              (0L<<26)
2668 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE                (1L<<26)
2669 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ                 (2L<<26)
2670 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_22_XI          (1L<<26)
2671 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_45_XI          (1L<<26)
2672 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_22_XI           (2L<<26)
2673 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI       (2L<<26)
2674 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3          (3L<<26)
2675 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_45              (3L<<26)
2676 #define BNX2_EMAC_MDIO_COMM_FAIL                         (1L<<28)
2677 #define BNX2_EMAC_MDIO_COMM_START_BUSY                   (1L<<29)
2678 #define BNX2_EMAC_MDIO_COMM_DISEXT                       (1L<<30)
2679
2680 #define BNX2_EMAC_MDIO_STATUS                           0x000014b0
2681 #define BNX2_EMAC_MDIO_STATUS_LINK                       (1L<<0)
2682 #define BNX2_EMAC_MDIO_STATUS_10MB                       (1L<<1)
2683
2684 #define BNX2_EMAC_MDIO_MODE                             0x000014b4
2685 #define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE               (1L<<1)
2686 #define BNX2_EMAC_MDIO_MODE_AUTO_POLL                    (1L<<4)
2687 #define BNX2_EMAC_MDIO_MODE_BIT_BANG                     (1L<<8)
2688 #define BNX2_EMAC_MDIO_MODE_MDIO                         (1L<<9)
2689 #define BNX2_EMAC_MDIO_MODE_MDIO_OE                      (1L<<10)
2690 #define BNX2_EMAC_MDIO_MODE_MDC                          (1L<<11)
2691 #define BNX2_EMAC_MDIO_MODE_MDINT                        (1L<<12)
2692 #define BNX2_EMAC_MDIO_MODE_EXT_MDINT                    (1L<<13)
2693 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT                    (0x1fL<<16)
2694 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT_XI                 (0x3fL<<16)
2695 #define BNX2_EMAC_MDIO_MODE_CLAUSE_45_XI                 (1L<<31)
2696
2697 #define BNX2_EMAC_MDIO_AUTO_STATUS                      0x000014b8
2698 #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR              (1L<<0)
2699
2700 #define BNX2_EMAC_TX_MODE                               0x000014bc
2701 #define BNX2_EMAC_TX_MODE_RESET                          (1L<<0)
2702 #define BNX2_EMAC_TX_MODE_CS16_TEST                      (1L<<2)
2703 #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN                   (1L<<3)
2704 #define BNX2_EMAC_TX_MODE_FLOW_EN                        (1L<<4)
2705 #define BNX2_EMAC_TX_MODE_BIG_BACKOFF                    (1L<<5)
2706 #define BNX2_EMAC_TX_MODE_LONG_PAUSE                     (1L<<6)
2707 #define BNX2_EMAC_TX_MODE_LINK_AWARE                     (1L<<7)
2708
2709 #define BNX2_EMAC_TX_STATUS                             0x000014c0
2710 #define BNX2_EMAC_TX_STATUS_XOFFED                       (1L<<0)
2711 #define BNX2_EMAC_TX_STATUS_XOFF_SENT                    (1L<<1)
2712 #define BNX2_EMAC_TX_STATUS_XON_SENT                     (1L<<2)
2713 #define BNX2_EMAC_TX_STATUS_LINK_UP                      (1L<<3)
2714 #define BNX2_EMAC_TX_STATUS_UNDERRUN                     (1L<<4)
2715 #define BNX2_EMAC_TX_STATUS_CS16_ERROR                   (1L<<5)
2716
2717 #define BNX2_EMAC_TX_LENGTHS                            0x000014c4
2718 #define BNX2_EMAC_TX_LENGTHS_SLOT                        (0xffL<<0)
2719 #define BNX2_EMAC_TX_LENGTHS_IPG                         (0xfL<<8)
2720 #define BNX2_EMAC_TX_LENGTHS_IPG_CRS                     (0x3L<<12)
2721
2722 #define BNX2_EMAC_RX_MODE                               0x000014c8
2723 #define BNX2_EMAC_RX_MODE_RESET                          (1L<<0)
2724 #define BNX2_EMAC_RX_MODE_FLOW_EN                        (1L<<2)
2725 #define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL               (1L<<3)
2726 #define BNX2_EMAC_RX_MODE_KEEP_PAUSE                     (1L<<4)
2727 #define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE                (1L<<5)
2728 #define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS                   (1L<<6)
2729 #define BNX2_EMAC_RX_MODE_LLC_CHK                        (1L<<7)
2730 #define BNX2_EMAC_RX_MODE_PROMISCUOUS                    (1L<<8)
2731 #define BNX2_EMAC_RX_MODE_NO_CRC_CHK                     (1L<<9)
2732 #define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG                  (1L<<10)
2733 #define BNX2_EMAC_RX_MODE_FILT_BROADCAST                 (1L<<11)
2734 #define BNX2_EMAC_RX_MODE_SORT_MODE                      (1L<<12)
2735
2736 #define BNX2_EMAC_RX_STATUS                             0x000014cc
2737 #define BNX2_EMAC_RX_STATUS_FFED                         (1L<<0)
2738 #define BNX2_EMAC_RX_STATUS_FF_RECEIVED                  (1L<<1)
2739 #define BNX2_EMAC_RX_STATUS_N_RECEIVED                   (1L<<2)
2740
2741 #define BNX2_EMAC_MULTICAST_HASH0                       0x000014d0
2742 #define BNX2_EMAC_MULTICAST_HASH1                       0x000014d4
2743 #define BNX2_EMAC_MULTICAST_HASH2                       0x000014d8
2744 #define BNX2_EMAC_MULTICAST_HASH3                       0x000014dc
2745 #define BNX2_EMAC_MULTICAST_HASH4                       0x000014e0
2746 #define BNX2_EMAC_MULTICAST_HASH5                       0x000014e4
2747 #define BNX2_EMAC_MULTICAST_HASH6                       0x000014e8
2748 #define BNX2_EMAC_MULTICAST_HASH7                       0x000014ec
2749 #define BNX2_EMAC_CKSUM_ERROR_STATUS                    0x000014f0
2750 #define BNX2_EMAC_CKSUM_ERROR_STATUS_CALCULATED          (0xffffL<<0)
2751 #define BNX2_EMAC_CKSUM_ERROR_STATUS_EXPECTED            (0xffffL<<16)
2752
2753 #define BNX2_EMAC_RX_STAT_IFHCINOCTETS                  0x00001500
2754 #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS               0x00001504
2755 #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS           0x00001508
2756 #define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS               0x0000150c
2757 #define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS           0x00001510
2758 #define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS           0x00001514
2759 #define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS            0x00001518
2760 #define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS      0x0000151c
2761 #define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS   0x00001520
2762 #define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED        0x00001524
2763 #define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED       0x00001528
2764 #define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED      0x0000152c
2765 #define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED              0x00001530
2766 #define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG        0x00001534
2767 #define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS             0x00001538
2768 #define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS       0x0000153c
2769 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS        0x00001540
2770 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS     0x00001544
2771 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS    0x00001548
2772 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x0000154c
2773 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001550
2774 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x00001554
2775 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS  0x00001558
2776 #define BNX2_EMAC_RXMAC_DEBUG0                          0x0000155c
2777 #define BNX2_EMAC_RXMAC_DEBUG1                          0x00001560
2778 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT      (1L<<0)
2779 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE          (1L<<1)
2780 #define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC                   (1L<<2)
2781 #define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR                  (1L<<3)
2782 #define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR               (1L<<4)
2783 #define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA                 (1L<<5)
2784 #define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START            (1L<<6)
2785 #define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT                (0xffffL<<7)
2786 #define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME                 (0xffL<<23)
2787
2788 #define BNX2_EMAC_RXMAC_DEBUG2                          0x00001564
2789 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE                  (0x7L<<0)
2790 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE             (0x0L<<0)
2791 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD              (0x1L<<0)
2792 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA             (0x2L<<0)
2793 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP            (0x3L<<0)
2794 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT              (0x4L<<0)
2795 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP             (0x5L<<0)
2796 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP            (0x6L<<0)
2797 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC               (0x7L<<0)
2798 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE                 (0xfL<<3)
2799 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE            (0x0L<<3)
2800 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0           (0x1L<<3)
2801 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1           (0x2L<<3)
2802 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2           (0x3L<<3)
2803 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3           (0x4L<<3)
2804 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT           (0x5L<<3)
2805 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT            (0x6L<<3)
2806 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS          (0x7L<<3)
2807 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST            (0x8L<<3)
2808 #define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN                   (0xffL<<7)
2809 #define BNX2_EMAC_RXMAC_DEBUG2_FALSEC                    (1L<<15)
2810 #define BNX2_EMAC_RXMAC_DEBUG2_TAGGED                    (1L<<16)
2811 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE               (1L<<18)
2812 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE          (0L<<18)
2813 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED        (1L<<18)
2814 #define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER                (0xfL<<19)
2815 #define BNX2_EMAC_RXMAC_DEBUG2_QUANTA                    (0x1fL<<23)
2816
2817 #define BNX2_EMAC_RXMAC_DEBUG3                          0x00001568
2818 #define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR                 (0xffffL<<0)
2819 #define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR             (0xffffL<<16)
2820
2821 #define BNX2_EMAC_RXMAC_DEBUG4                          0x0000156c
2822 #define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD                (0xffffL<<0)
2823 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE                (0x3fL<<16)
2824 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE           (0x0L<<16)
2825 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2          (0x1L<<16)
2826 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3          (0x2L<<16)
2827 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI            (0x3L<<16)
2828 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3          (0x5L<<16)
2829 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1           (0x6L<<16)
2830 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2          (0x7L<<16)
2831 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2           (0x7L<<16)
2832 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3           (0x8L<<16)
2833 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2            (0x9L<<16)
2834 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3            (0xaL<<16)
2835 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1         (0xeL<<16)
2836 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2         (0xfL<<16)
2837 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK         (0x10L<<16)
2838 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC             (0x11L<<16)
2839 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2            (0x12L<<16)
2840 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3            (0x13L<<16)
2841 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1           (0x14L<<16)
2842 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2           (0x15L<<16)
2843 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3           (0x16L<<16)
2844 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE          (0x17L<<16)
2845 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC             (0x18L<<16)
2846 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE          (0x19L<<16)
2847 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD            (0x1aL<<16)
2848 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC            (0x1bL<<16)
2849 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH          (0x1cL<<16)
2850 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF           (0x1dL<<16)
2851 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON            (0x1eL<<16)
2852 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED         (0x1fL<<16)
2853 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED        (0x20L<<16)
2854 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE          (0x21L<<16)
2855 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL           (0x22L<<16)
2856 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1           (0x23L<<16)
2857 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2           (0x24L<<16)
2858 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3           (0x25L<<16)
2859 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE          (0x26L<<16)
2860 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE         (0x27L<<16)
2861 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL          (0x28L<<16)
2862 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE          (0x29L<<16)
2863 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP           (0x2aL<<16)
2864 #define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT                  (1L<<22)
2865 #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED               (1L<<23)
2866 #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER             (1L<<24)
2867 #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA                 (1L<<25)
2868 #define BNX2_EMAC_RXMAC_DEBUG4_SFD_FOUND                 (1L<<26)
2869 #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE                   (1L<<27)
2870 #define BNX2_EMAC_RXMAC_DEBUG4_START                     (1L<<28)
2871
2872 #define BNX2_EMAC_RXMAC_DEBUG5                          0x00001570
2873 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM                  (0x7L<<0)
2874 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE             (0L<<0)
2875 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF         (1L<<0)
2876 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT        (2L<<0)
2877 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC     (3L<<0)
2878 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE      (4L<<0)
2879 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL      (5L<<0)
2880 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT    (6L<<0)
2881 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1                (0x7L<<4)
2882 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW            (0x0L<<4)
2883 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT           (0x1L<<4)
2884 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF           (0x2L<<4)
2885 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF           (0x3L<<4)
2886 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF            (0x4L<<4)
2887 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF          (0x6L<<4)
2888 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF          (0x7L<<4)
2889 #define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED              (1L<<7)
2890 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0                (0x7L<<8)
2891 #define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL         (1L<<11)
2892 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE                (1L<<12)
2893 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA                 (1L<<13)
2894 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT                 (1L<<14)
2895 #define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT                  (1L<<15)
2896 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE             (0x3L<<16)
2897 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT            (1L<<19)
2898 #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN                     (0xfffL<<20)
2899
2900 #define BNX2_EMAC_RX_STAT_FALSECARRIERERRORS            0x00001574
2901 #define BNX2_EMAC_RX_STAT_AC0                           0x00001580
2902 #define BNX2_EMAC_RX_STAT_AC1                           0x00001584
2903 #define BNX2_EMAC_RX_STAT_AC2                           0x00001588
2904 #define BNX2_EMAC_RX_STAT_AC3                           0x0000158c
2905 #define BNX2_EMAC_RX_STAT_AC4                           0x00001590
2906 #define BNX2_EMAC_RX_STAT_AC5                           0x00001594
2907 #define BNX2_EMAC_RX_STAT_AC6                           0x00001598
2908 #define BNX2_EMAC_RX_STAT_AC7                           0x0000159c
2909 #define BNX2_EMAC_RX_STAT_AC8                           0x000015a0
2910 #define BNX2_EMAC_RX_STAT_AC9                           0x000015a4
2911 #define BNX2_EMAC_RX_STAT_AC10                          0x000015a8
2912 #define BNX2_EMAC_RX_STAT_AC11                          0x000015ac
2913 #define BNX2_EMAC_RX_STAT_AC12                          0x000015b0
2914 #define BNX2_EMAC_RX_STAT_AC13                          0x000015b4
2915 #define BNX2_EMAC_RX_STAT_AC14                          0x000015b8
2916 #define BNX2_EMAC_RX_STAT_AC15                          0x000015bc
2917 #define BNX2_EMAC_RX_STAT_AC16                          0x000015c0
2918 #define BNX2_EMAC_RX_STAT_AC17                          0x000015c4
2919 #define BNX2_EMAC_RX_STAT_AC18                          0x000015c8
2920 #define BNX2_EMAC_RX_STAT_AC19                          0x000015cc
2921 #define BNX2_EMAC_RX_STAT_AC20                          0x000015d0
2922 #define BNX2_EMAC_RX_STAT_AC21                          0x000015d4
2923 #define BNX2_EMAC_RX_STAT_AC22                          0x000015d8
2924 #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC              0x000015dc
2925 #define BNX2_EMAC_RX_STAT_AC_28                         0x000015f4
2926 #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS                 0x00001600
2927 #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS              0x00001604
2928 #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS          0x00001608
2929 #define BNX2_EMAC_TX_STAT_OUTXONSENT                    0x0000160c
2930 #define BNX2_EMAC_TX_STAT_OUTXOFFSENT                   0x00001610
2931 #define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE               0x00001614
2932 #define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES        0x00001618
2933 #define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES      0x0000161c
2934 #define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS        0x00001620
2935 #define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS  0x00001624
2936 #define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS       0x00001628
2937 #define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS              0x0000162c
2938 #define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS          0x00001630
2939 #define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS          0x00001634
2940 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS        0x00001638
2941 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS     0x0000163c
2942 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS    0x00001640
2943 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x00001644
2944 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001648
2945 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x0000164c
2946 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS  0x00001650
2947 #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS    0x00001654
2948 #define BNX2_EMAC_TXMAC_DEBUG0                          0x00001658
2949 #define BNX2_EMAC_TXMAC_DEBUG1                          0x0000165c
2950 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE                 (0xfL<<0)
2951 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE            (0x0L<<0)
2952 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0          (0x1L<<0)
2953 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0           (0x4L<<0)
2954 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1           (0x5L<<0)
2955 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2           (0x6L<<0)
2956 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3           (0x7L<<0)
2957 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0           (0x8L<<0)
2958 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1           (0x9L<<0)
2959 #define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE                (1L<<4)
2960 #define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC                   (1L<<5)
2961 #define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER                (0xfL<<6)
2962 #define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE                (1L<<10)
2963 #define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION            (1L<<11)
2964 #define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER                 (1L<<12)
2965 #define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED                  (1L<<13)
2966 #define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE                  (1L<<14)
2967 #define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME                  (0xfL<<15)
2968 #define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME                 (0xffL<<19)
2969
2970 #define BNX2_EMAC_TXMAC_DEBUG2                          0x00001660
2971 #define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF                  (0x3ffL<<0)
2972 #define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT                (0xffffL<<10)
2973 #define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT                 (0x1fL<<26)
2974 #define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT                   (1L<<31)
2975
2976 #define BNX2_EMAC_TXMAC_DEBUG3                          0x00001664
2977 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE                  (0xfL<<0)
2978 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE             (0x0L<<0)
2979 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1             (0x1L<<0)
2980 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2             (0x2L<<0)
2981 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD              (0x3L<<0)
2982 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA             (0x4L<<0)
2983 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1             (0x5L<<0)
2984 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2             (0x6L<<0)
2985 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT              (0x7L<<0)
2986 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB            (0x8L<<0)
2987 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG            (0x9L<<0)
2988 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM              (0xaL<<0)
2989 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM             (0xbL<<0)
2990 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM             (0xcL<<0)
2991 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT            (0xdL<<0)
2992 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF          (0xeL<<0)
2993 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE                (0x7L<<4)
2994 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE           (0x0L<<4)
2995 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT           (0x1L<<4)
2996 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI            (0x2L<<4)
2997 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC             (0x3L<<4)
2998 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2            (0x4L<<4)
2999 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3            (0x5L<<4)
3000 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC             (0x6L<<4)
3001 #define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE                  (1L<<7)
3002 #define BNX2_EMAC_TXMAC_DEBUG3_XOFF                      (1L<<8)
3003 #define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER                (0xfL<<9)
3004 #define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER            (0x1fL<<13)
3005
3006 #define BNX2_EMAC_TXMAC_DEBUG4                          0x00001668
3007 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER             (0xffffL<<0)
3008 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE               (0xfL<<16)
3009 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE          (0x0L<<16)
3010 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1          (0x2L<<16)
3011 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2          (0x3L<<16)
3012 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3          (0x4L<<16)
3013 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2          (0x5L<<16)
3014 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3          (0x6L<<16)
3015 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1          (0x7L<<16)
3016 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1          (0x8L<<16)
3017 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2          (0x9L<<16)
3018 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME          (0xaL<<16)
3019 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE          (0xcL<<16)
3020 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT          (0xdL<<16)
3021 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD           (0xeL<<16)
3022 #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID              (1L<<20)
3023 #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC                (1L<<21)
3024 #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED               (1L<<22)
3025 #define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER                 (1L<<23)
3026 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND               (1L<<24)
3027 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING              (1L<<25)
3028 #define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC                   (1L<<26)
3029 #define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING                 (1L<<27)
3030 #define BNX2_EMAC_TXMAC_DEBUG4_COL_IN                    (1L<<28)
3031 #define BNX2_EMAC_TXMAC_DEBUG4_BURSTING                  (1L<<29)
3032 #define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE                   (1L<<30)
3033 #define BNX2_EMAC_TXMAC_DEBUG4_GO                        (1L<<31)
3034
3035 #define BNX2_EMAC_TX_STAT_AC0                           0x00001680
3036 #define BNX2_EMAC_TX_STAT_AC1                           0x00001684
3037 #define BNX2_EMAC_TX_STAT_AC2                           0x00001688
3038 #define BNX2_EMAC_TX_STAT_AC3                           0x0000168c
3039 #define BNX2_EMAC_TX_STAT_AC4                           0x00001690
3040 #define BNX2_EMAC_TX_STAT_AC5                           0x00001694
3041 #define BNX2_EMAC_TX_STAT_AC6                           0x00001698
3042 #define BNX2_EMAC_TX_STAT_AC7                           0x0000169c
3043 #define BNX2_EMAC_TX_STAT_AC8                           0x000016a0
3044 #define BNX2_EMAC_TX_STAT_AC9                           0x000016a4
3045 #define BNX2_EMAC_TX_STAT_AC10                          0x000016a8
3046 #define BNX2_EMAC_TX_STAT_AC11                          0x000016ac
3047 #define BNX2_EMAC_TX_STAT_AC12                          0x000016b0
3048 #define BNX2_EMAC_TX_STAT_AC13                          0x000016b4
3049 #define BNX2_EMAC_TX_STAT_AC14                          0x000016b8
3050 #define BNX2_EMAC_TX_STAT_AC15                          0x000016bc
3051 #define BNX2_EMAC_TX_STAT_AC16                          0x000016c0
3052 #define BNX2_EMAC_TX_STAT_AC17                          0x000016c4
3053 #define BNX2_EMAC_TX_STAT_AC18                          0x000016c8
3054 #define BNX2_EMAC_TX_STAT_AC19                          0x000016cc
3055 #define BNX2_EMAC_TX_STAT_AC20                          0x000016d0
3056 #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC              0x000016d8
3057 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL                    0x000016fc
3058 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC     (0x7fL<<0)
3059 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM     (0x7fL<<16)
3060 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN     (1L<<31)
3061
3062
3063 /*
3064  *  rpm_reg definition
3065  *  offset: 0x1800
3066  */
3067 #define BNX2_RPM_COMMAND                                0x00001800
3068 #define BNX2_RPM_COMMAND_ENABLED                         (1L<<0)
3069 #define BNX2_RPM_COMMAND_OVERRUN_ABORT                   (1L<<4)
3070
3071 #define BNX2_RPM_STATUS                                 0x00001804
3072 #define BNX2_RPM_STATUS_MBUF_WAIT                        (1L<<0)
3073 #define BNX2_RPM_STATUS_FREE_WAIT                        (1L<<1)
3074
3075 #define BNX2_RPM_CONFIG                                 0x00001808
3076 #define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM                 (1L<<0)
3077 #define BNX2_RPM_CONFIG_ACPI_ENA                         (1L<<1)
3078 #define BNX2_RPM_CONFIG_ACPI_KEEP                        (1L<<2)
3079 #define BNX2_RPM_CONFIG_MP_KEEP                          (1L<<3)
3080 #define BNX2_RPM_CONFIG_SORT_VECT_VAL                    (0xfL<<4)
3081 #define BNX2_RPM_CONFIG_DISABLE_WOL_ASSERT               (1L<<30)
3082 #define BNX2_RPM_CONFIG_IGNORE_VLAN                      (1L<<31)
3083
3084 #define BNX2_RPM_MGMT_PKT_CTRL                          0x0000180c
3085 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_SORT                 (0xfL<<0)
3086 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_RULE                 (0xfL<<4)
3087 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN           (1L<<30)
3088 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_EN                   (1L<<31)
3089
3090 #define BNX2_RPM_VLAN_MATCH0                            0x00001810
3091 #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE        (0xfffL<<0)
3092
3093 #define BNX2_RPM_VLAN_MATCH1                            0x00001814
3094 #define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE        (0xfffL<<0)
3095
3096 #define BNX2_RPM_VLAN_MATCH2                            0x00001818
3097 #define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE        (0xfffL<<0)
3098
3099 #define BNX2_RPM_VLAN_MATCH3                            0x0000181c
3100 #define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE        (0xfffL<<0)
3101
3102 #define BNX2_RPM_SORT_USER0                             0x00001820
3103 #define BNX2_RPM_SORT_USER0_PM_EN                        (0xffffL<<0)
3104 #define BNX2_RPM_SORT_USER0_BC_EN                        (1L<<16)
3105 #define BNX2_RPM_SORT_USER0_MC_EN                        (1L<<17)
3106 #define BNX2_RPM_SORT_USER0_MC_HSH_EN                    (1L<<18)
3107 #define BNX2_RPM_SORT_USER0_PROM_EN                      (1L<<19)
3108 #define BNX2_RPM_SORT_USER0_VLAN_EN                      (0xfL<<20)
3109 #define BNX2_RPM_SORT_USER0_PROM_VLAN                    (1L<<24)
3110 #define BNX2_RPM_SORT_USER0_VLAN_NOTMATCH                (1L<<25)
3111 #define BNX2_RPM_SORT_USER0_ENA                          (1L<<31)
3112
3113 #define BNX2_RPM_SORT_USER1                             0x00001824
3114 #define BNX2_RPM_SORT_USER1_PM_EN                        (0xffffL<<0)
3115 #define BNX2_RPM_SORT_USER1_BC_EN                        (1L<<16)
3116 #define BNX2_RPM_SORT_USER1_MC_EN                        (1L<<17)
3117 #define BNX2_RPM_SORT_USER1_MC_HSH_EN                    (1L<<18)
3118 #define BNX2_RPM_SORT_USER1_PROM_EN                      (1L<<19)
3119 #define BNX2_RPM_SORT_USER1_VLAN_EN                      (0xfL<<20)
3120 #define BNX2_RPM_SORT_USER1_PROM_VLAN                    (1L<<24)
3121 #define BNX2_RPM_SORT_USER1_ENA                          (1L<<31)
3122
3123 #define BNX2_RPM_SORT_USER2                             0x00001828
3124 #define BNX2_RPM_SORT_USER2_PM_EN                        (0xffffL<<0)
3125 #define BNX2_RPM_SORT_USER2_BC_EN                        (1L<<16)
3126 #define BNX2_RPM_SORT_USER2_MC_EN                        (1L<<17)
3127 #define BNX2_RPM_SORT_USER2_MC_HSH_EN                    (1L<<18)
3128 #define BNX2_RPM_SORT_USER2_PROM_EN                      (1L<<19)
3129 #define BNX2_RPM_SORT_USER2_VLAN_EN                      (0xfL<<20)
3130 #define BNX2_RPM_SORT_USER2_PROM_VLAN                    (1L<<24)
3131 #define BNX2_RPM_SORT_USER2_ENA                          (1L<<31)
3132
3133 #define BNX2_RPM_SORT_USER3                             0x0000182c
3134 #define BNX2_RPM_SORT_USER3_PM_EN                        (0xffffL<<0)
3135 #define BNX2_RPM_SORT_USER3_BC_EN                        (1L<<16)
3136 #define BNX2_RPM_SORT_USER3_MC_EN                        (1L<<17)
3137 #define BNX2_RPM_SORT_USER3_MC_HSH_EN                    (1L<<18)
3138 #define BNX2_RPM_SORT_USER3_PROM_EN                      (1L<<19)
3139 #define BNX2_RPM_SORT_USER3_VLAN_EN                      (0xfL<<20)
3140 #define BNX2_RPM_SORT_USER3_PROM_VLAN                    (1L<<24)
3141 #define BNX2_RPM_SORT_USER3_ENA                          (1L<<31)
3142
3143 #define BNX2_RPM_STAT_L2_FILTER_DISCARDS                0x00001840
3144 #define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS             0x00001844
3145 #define BNX2_RPM_STAT_IFINFTQDISCARDS                   0x00001848
3146 #define BNX2_RPM_STAT_IFINMBUFDISCARD                   0x0000184c
3147 #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT               0x00001850
3148 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0           0x00001854
3149 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN    (0xffL<<0)
3150 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER        (0xffL<<16)
3151 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE       (1L<<30)
3152 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN     (1L<<31)
3153
3154 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1           0x00001858
3155 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN    (0xffL<<0)
3156 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER        (0xffL<<16)
3157 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE       (1L<<30)
3158 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN     (1L<<31)
3159
3160 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2           0x0000185c
3161 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN    (0xffL<<0)
3162 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER        (0xffL<<16)
3163 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE       (1L<<30)
3164 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN     (1L<<31)
3165
3166 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3           0x00001860
3167 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN    (0xffL<<0)
3168 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER        (0xffL<<16)
3169 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE       (1L<<30)
3170 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN     (1L<<31)
3171
3172 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4           0x00001864
3173 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN    (0xffL<<0)
3174 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER        (0xffL<<16)
3175 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE       (1L<<30)
3176 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN     (1L<<31)
3177
3178 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5           0x00001868
3179 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN    (0xffL<<0)
3180 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER        (0xffL<<16)
3181 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE       (1L<<30)
3182 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN     (1L<<31)
3183
3184 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6           0x0000186c
3185 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN    (0xffL<<0)
3186 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER        (0xffL<<16)
3187 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE       (1L<<30)
3188 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN     (1L<<31)
3189
3190 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7           0x00001870
3191 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN    (0xffL<<0)
3192 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER        (0xffL<<16)
3193 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE       (1L<<30)
3194 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN     (1L<<31)
3195
3196 #define BNX2_RPM_STAT_AC0                               0x00001880
3197 #define BNX2_RPM_STAT_AC1                               0x00001884
3198 #define BNX2_RPM_STAT_AC2                               0x00001888
3199 #define BNX2_RPM_STAT_AC3                               0x0000188c
3200 #define BNX2_RPM_STAT_AC4                               0x00001890
3201 #define BNX2_RPM_RC_CNTL_16                             0x000018e0
3202 #define BNX2_RPM_RC_CNTL_16_OFFSET                       (0xffL<<0)
3203 #define BNX2_RPM_RC_CNTL_16_CLASS                        (0x7L<<8)
3204 #define BNX2_RPM_RC_CNTL_16_PRIORITY                     (1L<<11)
3205 #define BNX2_RPM_RC_CNTL_16_P4                           (1L<<12)
3206 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE                     (0x7L<<13)
3207 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_START               (0L<<13)
3208 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_IP                  (1L<<13)
3209 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP                 (2L<<13)
3210 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_UDP                 (3L<<13)
3211 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_DATA                (4L<<13)
3212 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP_UDP             (5L<<13)
3213 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_ICMPV6              (6L<<13)
3214 #define BNX2_RPM_RC_CNTL_16_COMP                         (0x3L<<16)
3215 #define BNX2_RPM_RC_CNTL_16_COMP_EQUAL                   (0L<<16)
3216 #define BNX2_RPM_RC_CNTL_16_COMP_NEQUAL                  (1L<<16)
3217 #define BNX2_RPM_RC_CNTL_16_COMP_GREATER                 (2L<<16)
3218 #define BNX2_RPM_RC_CNTL_16_COMP_LESS                    (3L<<16)
3219 #define BNX2_RPM_RC_CNTL_16_MAP                          (1L<<18)
3220 #define BNX2_RPM_RC_CNTL_16_SBIT                         (1L<<19)
3221 #define BNX2_RPM_RC_CNTL_16_CMDSEL                       (0x1fL<<20)
3222 #define BNX2_RPM_RC_CNTL_16_DISCARD                      (1L<<25)
3223 #define BNX2_RPM_RC_CNTL_16_MASK                         (1L<<26)
3224 #define BNX2_RPM_RC_CNTL_16_P1                           (1L<<27)
3225 #define BNX2_RPM_RC_CNTL_16_P2                           (1L<<28)
3226 #define BNX2_RPM_RC_CNTL_16_P3                           (1L<<29)
3227 #define BNX2_RPM_RC_CNTL_16_NBIT                         (1L<<30)
3228
3229 #define BNX2_RPM_RC_VALUE_MASK_16                       0x000018e4
3230 #define BNX2_RPM_RC_VALUE_MASK_16_VALUE                  (0xffffL<<0)
3231 #define BNX2_RPM_RC_VALUE_MASK_16_MASK                   (0xffffL<<16)
3232
3233 #define BNX2_RPM_RC_CNTL_17                             0x000018e8
3234 #define BNX2_RPM_RC_CNTL_17_OFFSET                       (0xffL<<0)
3235 #define BNX2_RPM_RC_CNTL_17_CLASS                        (0x7L<<8)
3236 #define BNX2_RPM_RC_CNTL_17_PRIORITY                     (1L<<11)
3237 #define BNX2_RPM_RC_CNTL_17_P4                           (1L<<12)
3238 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE                     (0x7L<<13)
3239 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_START               (0L<<13)
3240 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_IP                  (1L<<13)
3241 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP                 (2L<<13)
3242 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_UDP                 (3L<<13)
3243 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_DATA                (4L<<13)
3244 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP_UDP             (5L<<13)
3245 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_ICMPV6              (6L<<13)
3246 #define BNX2_RPM_RC_CNTL_17_COMP                         (0x3L<<16)
3247 #define BNX2_RPM_RC_CNTL_17_COMP_EQUAL                   (0L<<16)
3248 #define BNX2_RPM_RC_CNTL_17_COMP_NEQUAL                  (1L<<16)
3249 #define BNX2_RPM_RC_CNTL_17_COMP_GREATER                 (2L<<16)
3250 #define BNX2_RPM_RC_CNTL_17_COMP_LESS                    (3L<<16)
3251 #define BNX2_RPM_RC_CNTL_17_MAP                          (1L<<18)
3252 #define BNX2_RPM_RC_CNTL_17_SBIT                         (1L<<19)
3253 #define BNX2_RPM_RC_CNTL_17_CMDSEL                       (0x1fL<<20)
3254 #define BNX2_RPM_RC_CNTL_17_DISCARD                      (1L<<25)
3255 #define BNX2_RPM_RC_CNTL_17_MASK                         (1L<<26)
3256 #define BNX2_RPM_RC_CNTL_17_P1                           (1L<<27)
3257 #define BNX2_RPM_RC_CNTL_17_P2                           (1L<<28)
3258 #define BNX2_RPM_RC_CNTL_17_P3                           (1L<<29)
3259 #define BNX2_RPM_RC_CNTL_17_NBIT                         (1L<<30)
3260
3261 #define BNX2_RPM_RC_VALUE_MASK_17                       0x000018ec
3262 #define BNX2_RPM_RC_VALUE_MASK_17_VALUE                  (0xffffL<<0)
3263 #define BNX2_RPM_RC_VALUE_MASK_17_MASK                   (0xffffL<<16)
3264
3265 #define BNX2_RPM_RC_CNTL_18                             0x000018f0
3266 #define BNX2_RPM_RC_CNTL_18_OFFSET                       (0xffL<<0)
3267 #define BNX2_RPM_RC_CNTL_18_CLASS                        (0x7L<<8)
3268 #define BNX2_RPM_RC_CNTL_18_PRIORITY                     (1L<<11)
3269 #define BNX2_RPM_RC_CNTL_18_P4                           (1L<<12)
3270 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE                     (0x7L<<13)
3271 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_START               (0L<<13)
3272 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_IP                  (1L<<13)
3273 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP                 (2L<<13)
3274 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_UDP                 (3L<<13)
3275 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_DATA                (4L<<13)
3276 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP_UDP             (5L<<13)
3277 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_ICMPV6              (6L<<13)
3278 #define BNX2_RPM_RC_CNTL_18_COMP                         (0x3L<<16)
3279 #define BNX2_RPM_RC_CNTL_18_COMP_EQUAL                   (0L<<16)
3280 #define BNX2_RPM_RC_CNTL_18_COMP_NEQUAL                  (1L<<16)
3281 #define BNX2_RPM_RC_CNTL_18_COMP_GREATER                 (2L<<16)
3282 #define BNX2_RPM_RC_CNTL_18_COMP_LESS                    (3L<<16)
3283 #define BNX2_RPM_RC_CNTL_18_MAP                          (1L<<18)
3284 #define BNX2_RPM_RC_CNTL_18_SBIT                         (1L<<19)
3285 #define BNX2_RPM_RC_CNTL_18_CMDSEL                       (0x1fL<<20)
3286 #define BNX2_RPM_RC_CNTL_18_DISCARD                      (1L<<25)
3287 #define BNX2_RPM_RC_CNTL_18_MASK                         (1L<<26)
3288 #define BNX2_RPM_RC_CNTL_18_P1                           (1L<<27)
3289 #define BNX2_RPM_RC_CNTL_18_P2                           (1L<<28)
3290 #define BNX2_RPM_RC_CNTL_18_P3                           (1L<<29)
3291 #define BNX2_RPM_RC_CNTL_18_NBIT                         (1L<<30)
3292
3293 #define BNX2_RPM_RC_VALUE_MASK_18                       0x000018f4
3294 #define BNX2_RPM_RC_VALUE_MASK_18_VALUE                  (0xffffL<<0)
3295 #define BNX2_RPM_RC_VALUE_MASK_18_MASK                   (0xffffL<<16)
3296
3297 #define BNX2_RPM_RC_CNTL_19                             0x000018f8
3298 #define BNX2_RPM_RC_CNTL_19_OFFSET                       (0xffL<<0)
3299 #define BNX2_RPM_RC_CNTL_19_CLASS                        (0x7L<<8)
3300 #define BNX2_RPM_RC_CNTL_19_PRIORITY                     (1L<<11)
3301 #define BNX2_RPM_RC_CNTL_19_P4                           (1L<<12)
3302 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE                     (0x7L<<13)
3303 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_START               (0L<<13)
3304 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_IP                  (1L<<13)
3305 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP                 (2L<<13)
3306 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_UDP                 (3L<<13)
3307 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_DATA                (4L<<13)
3308 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP_UDP             (5L<<13)
3309 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_ICMPV6              (6L<<13)
3310 #define BNX2_RPM_RC_CNTL_19_COMP                         (0x3L<<16)
3311 #define BNX2_RPM_RC_CNTL_19_COMP_EQUAL                   (0L<<16)
3312 #define BNX2_RPM_RC_CNTL_19_COMP_NEQUAL                  (1L<<16)
3313 #define BNX2_RPM_RC_CNTL_19_COMP_GREATER                 (2L<<16)
3314 #define BNX2_RPM_RC_CNTL_19_COMP_LESS                    (3L<<16)
3315 #define BNX2_RPM_RC_CNTL_19_MAP                          (1L<<18)
3316 #define BNX2_RPM_RC_CNTL_19_SBIT                         (1L<<19)
3317 #define BNX2_RPM_RC_CNTL_19_CMDSEL                       (0x1fL<<20)
3318 #define BNX2_RPM_RC_CNTL_19_DISCARD                      (1L<<25)
3319 #define BNX2_RPM_RC_CNTL_19_MASK                         (1L<<26)
3320 #define BNX2_RPM_RC_CNTL_19_P1                           (1L<<27)
3321 #define BNX2_RPM_RC_CNTL_19_P2                           (1L<<28)
3322 #define BNX2_RPM_RC_CNTL_19_P3                           (1L<<29)
3323 #define BNX2_RPM_RC_CNTL_19_NBIT                         (1L<<30)
3324
3325 #define BNX2_RPM_RC_VALUE_MASK_19                       0x000018fc
3326 #define BNX2_RPM_RC_VALUE_MASK_19_VALUE                  (0xffffL<<0)
3327 #define BNX2_RPM_RC_VALUE_MASK_19_MASK                   (0xffffL<<16)
3328
3329 #define BNX2_RPM_RC_CNTL_0                              0x00001900
3330 #define BNX2_RPM_RC_CNTL_0_OFFSET                        (0xffL<<0)
3331 #define BNX2_RPM_RC_CNTL_0_CLASS                         (0x7L<<8)
3332 #define BNX2_RPM_RC_CNTL_0_PRIORITY                      (1L<<11)
3333 #define BNX2_RPM_RC_CNTL_0_P4                            (1L<<12)
3334 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE                      (0x7L<<13)
3335 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START                (0L<<13)
3336 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP                   (1L<<13)
3337 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP                  (2L<<13)
3338 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP                  (3L<<13)
3339 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA                 (4L<<13)
3340 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP_UDP              (5L<<13)
3341 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_ICMPV6               (6L<<13)
3342 #define BNX2_RPM_RC_CNTL_0_COMP                          (0x3L<<16)
3343 #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL                    (0L<<16)
3344 #define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL                   (1L<<16)
3345 #define BNX2_RPM_RC_CNTL_0_COMP_GREATER                  (2L<<16)
3346 #define BNX2_RPM_RC_CNTL_0_COMP_LESS                     (3L<<16)
3347 #define BNX2_RPM_RC_CNTL_0_MAP_XI                        (1L<<18)
3348 #define BNX2_RPM_RC_CNTL_0_SBIT                          (1L<<19)
3349 #define BNX2_RPM_RC_CNTL_0_CMDSEL                        (0xfL<<20)
3350 #define BNX2_RPM_RC_CNTL_0_MAP                           (1L<<24)
3351 #define BNX2_RPM_RC_CNTL_0_CMDSEL_XI                     (0x1fL<<20)
3352 #define BNX2_RPM_RC_CNTL_0_DISCARD                       (1L<<25)
3353 #define BNX2_RPM_RC_CNTL_0_MASK                          (1L<<26)
3354 #define BNX2_RPM_RC_CNTL_0_P1                            (1L<<27)
3355 #define BNX2_RPM_RC_CNTL_0_P2                            (1L<<28)
3356 #define BNX2_RPM_RC_CNTL_0_P3                            (1L<<29)
3357 #define BNX2_RPM_RC_CNTL_0_NBIT                          (1L<<30)
3358
3359 #define BNX2_RPM_RC_VALUE_MASK_0                        0x00001904
3360 #define BNX2_RPM_RC_VALUE_MASK_0_VALUE                   (0xffffL<<0)
3361 #define BNX2_RPM_RC_VALUE_MASK_0_MASK                    (0xffffL<<16)
3362
3363 #define BNX2_RPM_RC_CNTL_1                              0x00001908
3364 #define BNX2_RPM_RC_CNTL_1_A                             (0x3ffffL<<0)
3365 #define BNX2_RPM_RC_CNTL_1_B                             (0xfffL<<19)
3366 #define BNX2_RPM_RC_CNTL_1_OFFSET_XI                     (0xffL<<0)
3367 #define BNX2_RPM_RC_CNTL_1_CLASS_XI                      (0x7L<<8)
3368 #define BNX2_RPM_RC_CNTL_1_PRIORITY_XI                   (1L<<11)
3369 #define BNX2_RPM_RC_CNTL_1_P4_XI                         (1L<<12)
3370 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_XI                   (0x7L<<13)
3371 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_START_XI             (0L<<13)
3372 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_IP_XI                (1L<<13)
3373 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_XI               (2L<<13)
3374 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_UDP_XI               (3L<<13)
3375 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_DATA_XI              (4L<<13)
3376 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3377 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_ICMPV6_XI            (6L<<13)
3378 #define BNX2_RPM_RC_CNTL_1_COMP_XI                       (0x3L<<16)
3379 #define BNX2_RPM_RC_CNTL_1_COMP_EQUAL_XI                 (0L<<16)
3380 #define BNX2_RPM_RC_CNTL_1_COMP_NEQUAL_XI                (1L<<16)
3381 #define BNX2_RPM_RC_CNTL_1_COMP_GREATER_XI               (2L<<16)
3382 #define BNX2_RPM_RC_CNTL_1_COMP_LESS_XI                  (3L<<16)
3383 #define BNX2_RPM_RC_CNTL_1_MAP_XI                        (1L<<18)
3384 #define BNX2_RPM_RC_CNTL_1_SBIT_XI                       (1L<<19)
3385 #define BNX2_RPM_RC_CNTL_1_CMDSEL_XI                     (0x1fL<<20)
3386 #define BNX2_RPM_RC_CNTL_1_DISCARD_XI                    (1L<<25)
3387 #define BNX2_RPM_RC_CNTL_1_MASK_XI                       (1L<<26)
3388 #define BNX2_RPM_RC_CNTL_1_P1_XI                         (1L<<27)
3389 #define BNX2_RPM_RC_CNTL_1_P2_XI                         (1L<<28)
3390 #define BNX2_RPM_RC_CNTL_1_P3_XI                         (1L<<29)
3391 #define BNX2_RPM_RC_CNTL_1_NBIT_XI                       (1L<<30)
3392
3393 #define BNX2_RPM_RC_VALUE_MASK_1                        0x0000190c
3394 #define BNX2_RPM_RC_VALUE_MASK_1_VALUE                   (0xffffL<<0)
3395 #define BNX2_RPM_RC_VALUE_MASK_1_MASK                    (0xffffL<<16)
3396
3397 #define BNX2_RPM_RC_CNTL_2                              0x00001910
3398 #define BNX2_RPM_RC_CNTL_2_A                             (0x3ffffL<<0)
3399 #define BNX2_RPM_RC_CNTL_2_B                             (0xfffL<<19)
3400 #define BNX2_RPM_RC_CNTL_2_OFFSET_XI                     (0xffL<<0)
3401 #define BNX2_RPM_RC_CNTL_2_CLASS_XI                      (0x7L<<8)
3402 #define BNX2_RPM_RC_CNTL_2_PRIORITY_XI                   (1L<<11)
3403 #define BNX2_RPM_RC_CNTL_2_P4_XI                         (1L<<12)
3404 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_XI                   (0x7L<<13)
3405 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_START_XI             (0L<<13)
3406 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_IP_XI                (1L<<13)
3407 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_XI               (2L<<13)
3408 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_UDP_XI               (3L<<13)
3409 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_DATA_XI              (4L<<13)
3410 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3411 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_ICMPV6_XI            (6L<<13)
3412 #define BNX2_RPM_RC_CNTL_2_COMP_XI                       (0x3L<<16)
3413 #define BNX2_RPM_RC_CNTL_2_COMP_EQUAL_XI                 (0L<<16)
3414 #define BNX2_RPM_RC_CNTL_2_COMP_NEQUAL_XI                (1L<<16)
3415 #define BNX2_RPM_RC_CNTL_2_COMP_GREATER_XI               (2L<<16)
3416 #define BNX2_RPM_RC_CNTL_2_COMP_LESS_XI                  (3L<<16)
3417 #define BNX2_RPM_RC_CNTL_2_MAP_XI                        (1L<<18)
3418 #define BNX2_RPM_RC_CNTL_2_SBIT_XI                       (1L<<19)
3419 #define BNX2_RPM_RC_CNTL_2_CMDSEL_XI                     (0x1fL<<20)
3420 #define BNX2_RPM_RC_CNTL_2_DISCARD_XI                    (1L<<25)
3421 #define BNX2_RPM_RC_CNTL_2_MASK_XI                       (1L<<26)
3422 #define BNX2_RPM_RC_CNTL_2_P1_XI                         (1L<<27)
3423 #define BNX2_RPM_RC_CNTL_2_P2_XI                         (1L<<28)
3424 #define BNX2_RPM_RC_CNTL_2_P3_XI                         (1L<<29)
3425 #define BNX2_RPM_RC_CNTL_2_NBIT_XI                       (1L<<30)
3426
3427 #define BNX2_RPM_RC_VALUE_MASK_2                        0x00001914
3428 #define BNX2_RPM_RC_VALUE_MASK_2_VALUE                   (0xffffL<<0)
3429 #define BNX2_RPM_RC_VALUE_MASK_2_MASK                    (0xffffL<<16)
3430
3431 #define BNX2_RPM_RC_CNTL_3                              0x00001918
3432 #define BNX2_RPM_RC_CNTL_3_A                             (0x3ffffL<<0)
3433 #define BNX2_RPM_RC_CNTL_3_B                             (0xfffL<<19)
3434 #define BNX2_RPM_RC_CNTL_3_OFFSET_XI                     (0xffL<<0)
3435 #define BNX2_RPM_RC_CNTL_3_CLASS_XI                      (0x7L<<8)
3436 #define BNX2_RPM_RC_CNTL_3_PRIORITY_XI                   (1L<<11)
3437 #define BNX2_RPM_RC_CNTL_3_P4_XI                         (1L<<12)
3438 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_XI                   (0x7L<<13)
3439 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_START_XI             (0L<<13)
3440 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_IP_XI                (1L<<13)
3441 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_XI               (2L<<13)
3442 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_UDP_XI               (3L<<13)
3443 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_DATA_XI              (4L<<13)
3444 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3445 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_ICMPV6_XI            (6L<<13)
3446 #define BNX2_RPM_RC_CNTL_3_COMP_XI                       (0x3L<<16)
3447 #define BNX2_RPM_RC_CNTL_3_COMP_EQUAL_XI                 (0L<<16)
3448 #define BNX2_RPM_RC_CNTL_3_COMP_NEQUAL_XI                (1L<<16)
3449 #define BNX2_RPM_RC_CNTL_3_COMP_GREATER_XI               (2L<<16)
3450 #define BNX2_RPM_RC_CNTL_3_COMP_LESS_XI                  (3L<<16)
3451 #define BNX2_RPM_RC_CNTL_3_MAP_XI                        (1L<<18)
3452 #define BNX2_RPM_RC_CNTL_3_SBIT_XI                       (1L<<19)
3453 #define BNX2_RPM_RC_CNTL_3_CMDSEL_XI                     (0x1fL<<20)
3454 #define BNX2_RPM_RC_CNTL_3_DISCARD_XI                    (1L<<25)
3455 #define BNX2_RPM_RC_CNTL_3_MASK_XI                       (1L<<26)
3456 #define BNX2_RPM_RC_CNTL_3_P1_XI                         (1L<<27)
3457 #define BNX2_RPM_RC_CNTL_3_P2_XI                         (1L<<28)
3458 #define BNX2_RPM_RC_CNTL_3_P3_XI                         (1L<<29)
3459 #define BNX2_RPM_RC_CNTL_3_NBIT_XI                       (1L<<30)
3460
3461 #define BNX2_RPM_RC_VALUE_MASK_3                        0x0000191c
3462 #define BNX2_RPM_RC_VALUE_MASK_3_VALUE                   (0xffffL<<0)
3463 #define BNX2_RPM_RC_VALUE_MASK_3_MASK                    (0xffffL<<16)
3464
3465 #define BNX2_RPM_RC_CNTL_4                              0x00001920
3466 #define BNX2_RPM_RC_CNTL_4_A                             (0x3ffffL<<0)
3467 #define BNX2_RPM_RC_CNTL_4_B                             (0xfffL<<19)
3468 #define BNX2_RPM_RC_CNTL_4_OFFSET_XI                     (0xffL<<0)
3469 #define BNX2_RPM_RC_CNTL_4_CLASS_XI                      (0x7L<<8)
3470 #define BNX2_RPM_RC_CNTL_4_PRIORITY_XI                   (1L<<11)
3471 #define BNX2_RPM_RC_CNTL_4_P4_XI                         (1L<<12)
3472 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_XI                   (0x7L<<13)
3473 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_START_XI             (0L<<13)
3474 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_IP_XI                (1L<<13)
3475 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_XI               (2L<<13)
3476 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_UDP_XI               (3L<<13)
3477 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_DATA_XI              (4L<<13)
3478 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3479 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_ICMPV6_XI            (6L<<13)
3480 #define BNX2_RPM_RC_CNTL_4_COMP_XI                       (0x3L<<16)
3481 #define BNX2_RPM_RC_CNTL_4_COMP_EQUAL_XI                 (0L<<16)
3482 #define BNX2_RPM_RC_CNTL_4_COMP_NEQUAL_XI                (1L<<16)
3483 #define BNX2_RPM_RC_CNTL_4_COMP_GREATER_XI               (2L<<16)
3484 #define BNX2_RPM_RC_CNTL_4_COMP_LESS_XI                  (3L<<16)
3485 #define BNX2_RPM_RC_CNTL_4_MAP_XI                        (1L<<18)
3486 #define BNX2_RPM_RC_CNTL_4_SBIT_XI                       (1L<<19)
3487 #define BNX2_RPM_RC_CNTL_4_CMDSEL_XI                     (0x1fL<<20)
3488 #define BNX2_RPM_RC_CNTL_4_DISCARD_XI                    (1L<<25)
3489 #define BNX2_RPM_RC_CNTL_4_MASK_XI                       (1L<<26)
3490 #define BNX2_RPM_RC_CNTL_4_P1_XI                         (1L<<27)
3491 #define BNX2_RPM_RC_CNTL_4_P2_XI                         (1L<<28)
3492 #define BNX2_RPM_RC_CNTL_4_P3_XI                         (1L<<29)
3493 #define BNX2_RPM_RC_CNTL_4_NBIT_XI                       (1L<<30)
3494
3495 #define BNX2_RPM_RC_VALUE_MASK_4                        0x00001924
3496 #define BNX2_RPM_RC_VALUE_MASK_4_VALUE                   (0xffffL<<0)
3497 #define BNX2_RPM_RC_VALUE_MASK_4_MASK                    (0xffffL<<16)
3498
3499 #define BNX2_RPM_RC_CNTL_5                              0x00001928
3500 #define BNX2_RPM_RC_CNTL_5_A                             (0x3ffffL<<0)
3501 #define BNX2_RPM_RC_CNTL_5_B                             (0xfffL<<19)
3502 #define BNX2_RPM_RC_CNTL_5_OFFSET_XI                     (0xffL<<0)
3503 #define BNX2_RPM_RC_CNTL_5_CLASS_XI                      (0x7L<<8)
3504 #define BNX2_RPM_RC_CNTL_5_PRIORITY_XI                   (1L<<11)
3505 #define BNX2_RPM_RC_CNTL_5_P4_XI                         (1L<<12)
3506 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_XI                   (0x7L<<13)
3507 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_START_XI             (0L<<13)
3508 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_IP_XI                (1L<<13)
3509 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_XI               (2L<<13)
3510 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_UDP_XI               (3L<<13)
3511 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_DATA_XI              (4L<<13)
3512 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3513 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_ICMPV6_XI            (6L<<13)
3514 #define BNX2_RPM_RC_CNTL_5_COMP_XI                       (0x3L<<16)
3515 #define BNX2_RPM_RC_CNTL_5_COMP_EQUAL_XI                 (0L<<16)
3516 #define BNX2_RPM_RC_CNTL_5_COMP_NEQUAL_XI                (1L<<16)
3517 #define BNX2_RPM_RC_CNTL_5_COMP_GREATER_XI               (2L<<16)
3518 #define BNX2_RPM_RC_CNTL_5_COMP_LESS_XI                  (3L<<16)
3519 #define BNX2_RPM_RC_CNTL_5_MAP_XI                        (1L<<18)
3520 #define BNX2_RPM_RC_CNTL_5_SBIT_XI                       (1L<<19)
3521 #define BNX2_RPM_RC_CNTL_5_CMDSEL_XI                     (0x1fL<<20)
3522 #define BNX2_RPM_RC_CNTL_5_DISCARD_XI                    (1L<<25)
3523 #define BNX2_RPM_RC_CNTL_5_MASK_XI                       (1L<<26)
3524 #define BNX2_RPM_RC_CNTL_5_P1_XI                         (1L<<27)
3525 #define BNX2_RPM_RC_CNTL_5_P2_XI                         (1L<<28)
3526 #define BNX2_RPM_RC_CNTL_5_P3_XI                         (1L<<29)
3527 #define BNX2_RPM_RC_CNTL_5_NBIT_XI                       (1L<<30)
3528
3529 #define BNX2_RPM_RC_VALUE_MASK_5                        0x0000192c
3530 #define BNX2_RPM_RC_VALUE_MASK_5_VALUE                   (0xffffL<<0)
3531 #define BNX2_RPM_RC_VALUE_MASK_5_MASK                    (0xffffL<<16)
3532
3533 #define BNX2_RPM_RC_CNTL_6                              0x00001930
3534 #define BNX2_RPM_RC_CNTL_6_A                             (0x3ffffL<<0)
3535 #define BNX2_RPM_RC_CNTL_6_B                             (0xfffL<<19)
3536 #define BNX2_RPM_RC_CNTL_6_OFFSET_XI                     (0xffL<<0)
3537 #define BNX2_RPM_RC_CNTL_6_CLASS_XI                      (0x7L<<8)
3538 #define BNX2_RPM_RC_CNTL_6_PRIORITY_XI                   (1L<<11)
3539 #define BNX2_RPM_RC_CNTL_6_P4_XI                         (1L<<12)
3540 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_XI                   (0x7L<<13)
3541 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_START_XI             (0L<<13)
3542 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_IP_XI                (1L<<13)
3543 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_XI               (2L<<13)
3544 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_UDP_XI               (3L<<13)
3545 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_DATA_XI              (4L<<13)
3546 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3547 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_ICMPV6_XI            (6L<<13)
3548 #define BNX2_RPM_RC_CNTL_6_COMP_XI                       (0x3L<<16)
3549 #define BNX2_RPM_RC_CNTL_6_COMP_EQUAL_XI                 (0L<<16)
3550 #define BNX2_RPM_RC_CNTL_6_COMP_NEQUAL_XI                (1L<<16)
3551 #define BNX2_RPM_RC_CNTL_6_COMP_GREATER_XI               (2L<<16)
3552 #define BNX2_RPM_RC_CNTL_6_COMP_LESS_XI                  (3L<<16)
3553 #define BNX2_RPM_RC_CNTL_6_MAP_XI                        (1L<<18)
3554 #define BNX2_RPM_RC_CNTL_6_SBIT_XI                       (1L<<19)
3555 #define BNX2_RPM_RC_CNTL_6_CMDSEL_XI                     (0x1fL<<20)
3556 #define BNX2_RPM_RC_CNTL_6_DISCARD_XI                    (1L<<25)
3557 #define BNX2_RPM_RC_CNTL_6_MASK_XI                       (1L<<26)
3558 #define BNX2_RPM_RC_CNTL_6_P1_XI                         (1L<<27)
3559 #define BNX2_RPM_RC_CNTL_6_P2_XI                         (1L<<28)
3560 #define BNX2_RPM_RC_CNTL_6_P3_XI                         (1L<<29)
3561 #define BNX2_RPM_RC_CNTL_6_NBIT_XI                       (1L<<30)
3562
3563 #define BNX2_RPM_RC_VALUE_MASK_6                        0x00001934
3564 #define BNX2_RPM_RC_VALUE_MASK_6_VALUE                   (0xffffL<<0)
3565 #define BNX2_RPM_RC_VALUE_MASK_6_MASK                    (0xffffL<<16)
3566
3567 #define BNX2_RPM_RC_CNTL_7                              0x00001938
3568 #define BNX2_RPM_RC_CNTL_7_A                             (0x3ffffL<<0)
3569 #define BNX2_RPM_RC_CNTL_7_B                             (0xfffL<<19)
3570 #define BNX2_RPM_RC_CNTL_7_OFFSET_XI                     (0xffL<<0)
3571 #define BNX2_RPM_RC_CNTL_7_CLASS_XI                      (0x7L<<8)
3572 #define BNX2_RPM_RC_CNTL_7_PRIORITY_XI                   (1L<<11)
3573 #define BNX2_RPM_RC_CNTL_7_P4_XI                         (1L<<12)
3574 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_XI                   (0x7L<<13)
3575 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_START_XI             (0L<<13)
3576 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_IP_XI                (1L<<13)
3577 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_XI               (2L<<13)
3578 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_UDP_XI               (3L<<13)
3579 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_DATA_XI              (4L<<13)
3580 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3581 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_ICMPV6_XI            (6L<<13)
3582 #define BNX2_RPM_RC_CNTL_7_COMP_XI                       (0x3L<<16)
3583 #define BNX2_RPM_RC_CNTL_7_COMP_EQUAL_XI                 (0L<<16)
3584 #define BNX2_RPM_RC_CNTL_7_COMP_NEQUAL_XI                (1L<<16)
3585 #define BNX2_RPM_RC_CNTL_7_COMP_GREATER_XI               (2L<<16)
3586 #define BNX2_RPM_RC_CNTL_7_COMP_LESS_XI                  (3L<<16)
3587 #define BNX2_RPM_RC_CNTL_7_MAP_XI                        (1L<<18)
3588 #define BNX2_RPM_RC_CNTL_7_SBIT_XI                       (1L<<19)
3589 #define BNX2_RPM_RC_CNTL_7_CMDSEL_XI                     (0x1fL<<20)
3590 #define BNX2_RPM_RC_CNTL_7_DISCARD_XI                    (1L<<25)
3591 #define BNX2_RPM_RC_CNTL_7_MASK_XI                       (1L<<26)
3592 #define BNX2_RPM_RC_CNTL_7_P1_XI                         (1L<<27)
3593 #define BNX2_RPM_RC_CNTL_7_P2_XI                         (1L<<28)
3594 #define BNX2_RPM_RC_CNTL_7_P3_XI                         (1L<<29)
3595 #define BNX2_RPM_RC_CNTL_7_NBIT_XI                       (1L<<30)
3596
3597 #define BNX2_RPM_RC_VALUE_MASK_7                        0x0000193c
3598 #define BNX2_RPM_RC_VALUE_MASK_7_VALUE                   (0xffffL<<0)
3599 #define BNX2_RPM_RC_VALUE_MASK_7_MASK                    (0xffffL<<16)
3600
3601 #define BNX2_RPM_RC_CNTL_8                              0x00001940
3602 #define BNX2_RPM_RC_CNTL_8_A                             (0x3ffffL<<0)
3603 #define BNX2_RPM_RC_CNTL_8_B                             (0xfffL<<19)
3604 #define BNX2_RPM_RC_CNTL_8_OFFSET_XI                     (0xffL<<0)
3605 #define BNX2_RPM_RC_CNTL_8_CLASS_XI                      (0x7L<<8)
3606 #define BNX2_RPM_RC_CNTL_8_PRIORITY_XI                   (1L<<11)
3607 #define BNX2_RPM_RC_CNTL_8_P4_XI                         (1L<<12)
3608 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_XI                   (0x7L<<13)
3609 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_START_XI             (0L<<13)
3610 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_IP_XI                (1L<<13)
3611 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_XI               (2L<<13)
3612 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_UDP_XI               (3L<<13)
3613 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_DATA_XI              (4L<<13)
3614 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3615 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_ICMPV6_XI            (6L<<13)
3616 #define BNX2_RPM_RC_CNTL_8_COMP_XI                       (0x3L<<16)
3617 #define BNX2_RPM_RC_CNTL_8_COMP_EQUAL_XI                 (0L<<16)
3618 #define BNX2_RPM_RC_CNTL_8_COMP_NEQUAL_XI                (1L<<16)
3619 #define BNX2_RPM_RC_CNTL_8_COMP_GREATER_XI               (2L<<16)
3620 #define BNX2_RPM_RC_CNTL_8_COMP_LESS_XI                  (3L<<16)
3621 #define BNX2_RPM_RC_CNTL_8_MAP_XI                        (1L<<18)
3622 #define BNX2_RPM_RC_CNTL_8_SBIT_XI                       (1L<<19)
3623 #define BNX2_RPM_RC_CNTL_8_CMDSEL_XI                     (0x1fL<<20)
3624 #define BNX2_RPM_RC_CNTL_8_DISCARD_XI                    (1L<<25)
3625 #define BNX2_RPM_RC_CNTL_8_MASK_XI                       (1L<<26)
3626 #define BNX2_RPM_RC_CNTL_8_P1_XI                         (1L<<27)
3627 #define BNX2_RPM_RC_CNTL_8_P2_XI                         (1L<<28)
3628 #define BNX2_RPM_RC_CNTL_8_P3_XI                         (1L<<29)
3629 #define BNX2_RPM_RC_CNTL_8_NBIT_XI                       (1L<<30)
3630
3631 #define BNX2_RPM_RC_VALUE_MASK_8                        0x00001944
3632 #define BNX2_RPM_RC_VALUE_MASK_8_VALUE                   (0xffffL<<0)
3633 #define BNX2_RPM_RC_VALUE_MASK_8_MASK                    (0xffffL<<16)
3634
3635 #define BNX2_RPM_RC_CNTL_9                              0x00001948
3636 #define BNX2_RPM_RC_CNTL_9_A                             (0x3ffffL<<0)
3637 #define BNX2_RPM_RC_CNTL_9_B                             (0xfffL<<19)
3638 #define BNX2_RPM_RC_CNTL_9_OFFSET_XI                     (0xffL<<0)
3639 #define BNX2_RPM_RC_CNTL_9_CLASS_XI                      (0x7L<<8)
3640 #define BNX2_RPM_RC_CNTL_9_PRIORITY_XI                   (1L<<11)
3641 #define BNX2_RPM_RC_CNTL_9_P4_XI                         (1L<<12)
3642 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_XI                   (0x7L<<13)
3643 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_START_XI             (0L<<13)
3644 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_IP_XI                (1L<<13)
3645 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_XI               (2L<<13)
3646 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_UDP_XI               (3L<<13)
3647 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_DATA_XI              (4L<<13)
3648 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_UDP_XI           (5L<<13)
3649 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_ICMPV6_XI            (6L<<13)
3650 #define BNX2_RPM_RC_CNTL_9_COMP_XI                       (0x3L<<16)
3651 #define BNX2_RPM_RC_CNTL_9_COMP_EQUAL_XI                 (0L<<16)
3652 #define BNX2_RPM_RC_CNTL_9_COMP_NEQUAL_XI                (1L<<16)
3653 #define BNX2_RPM_RC_CNTL_9_COMP_GREATER_XI               (2L<<16)
3654 #define BNX2_RPM_RC_CNTL_9_COMP_LESS_XI                  (3L<<16)
3655 #define BNX2_RPM_RC_CNTL_9_MAP_XI                        (1L<<18)
3656 #define BNX2_RPM_RC_CNTL_9_SBIT_XI                       (1L<<19)
3657 #define BNX2_RPM_RC_CNTL_9_CMDSEL_XI                     (0x1fL<<20)
3658 #define BNX2_RPM_RC_CNTL_9_DISCARD_XI                    (1L<<25)
3659 #define BNX2_RPM_RC_CNTL_9_MASK_XI                       (1L<<26)
3660 #define BNX2_RPM_RC_CNTL_9_P1_XI                         (1L<<27)
3661 #define BNX2_RPM_RC_CNTL_9_P2_XI                         (1L<<28)
3662 #define BNX2_RPM_RC_CNTL_9_P3_XI                         (1L<<29)
3663 #define BNX2_RPM_RC_CNTL_9_NBIT_XI                       (1L<<30)
3664
3665 #define BNX2_RPM_RC_VALUE_MASK_9                        0x0000194c
3666 #define BNX2_RPM_RC_VALUE_MASK_9_VALUE                   (0xffffL<<0)
3667 #define BNX2_RPM_RC_VALUE_MASK_9_MASK                    (0xffffL<<16)
3668
3669 #define BNX2_RPM_RC_CNTL_10                             0x00001950
3670 #define BNX2_RPM_RC_CNTL_10_A                            (0x3ffffL<<0)
3671 #define BNX2_RPM_RC_CNTL_10_B                            (0xfffL<<19)
3672 #define BNX2_RPM_RC_CNTL_10_OFFSET_XI                    (0xffL<<0)
3673 #define BNX2_RPM_RC_CNTL_10_CLASS_XI                     (0x7L<<8)
3674 #define BNX2_RPM_RC_CNTL_10_PRIORITY_XI                  (1L<<11)
3675 #define BNX2_RPM_RC_CNTL_10_P4_XI                        (1L<<12)
3676 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_XI                  (0x7L<<13)
3677 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_START_XI            (0L<<13)
3678 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_IP_XI               (1L<<13)
3679 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_XI              (2L<<13)
3680 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_UDP_XI              (3L<<13)
3681 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_DATA_XI             (4L<<13)
3682 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_UDP_XI          (5L<<13)
3683 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_ICMPV6_XI           (6L<<13)
3684 #define BNX2_RPM_RC_CNTL_10_COMP_XI                      (0x3L<<16)
3685 #define BNX2_RPM_RC_CNTL_10_COMP_EQUAL_XI                (0L<<16)
3686 #define BNX2_RPM_RC_CNTL_10_COMP_NEQUAL_XI               (1L<<16)
3687 #define BNX2_RPM_RC_CNTL_10_COMP_GREATER_XI              (2L<<16)
3688 #define BNX2_RPM_RC_CNTL_10_COMP_LESS_XI                 (3L<<16)
3689 #define BNX2_RPM_RC_CNTL_10_MAP_XI                       (1L<<18)
3690 #define BNX2_RPM_RC_CNTL_10_SBIT_XI                      (1L<<19)
3691 #define BNX2_RPM_RC_CNTL_10_CMDSEL_XI                    (0x1fL<<20)
3692 #define BNX2_RPM_RC_CNTL_10_DISCARD_XI                   (1L<<25)
3693 #define BNX2_RPM_RC_CNTL_10_MASK_XI                      (1L<<26)
3694 #define BNX2_RPM_RC_CNTL_10_P1_XI                        (1L<<27)
3695 #define BNX2_RPM_RC_CNTL_10_P2_XI                        (1L<<28)
3696 #define BNX2_RPM_RC_CNTL_10_P3_XI                        (1L<<29)
3697 #define BNX2_RPM_RC_CNTL_10_NBIT_XI                      (1L<<30)
3698
3699 #define BNX2_RPM_RC_VALUE_MASK_10                       0x00001954
3700 #define BNX2_RPM_RC_VALUE_MASK_10_VALUE                  (0xffffL<<0)
3701 #define BNX2_RPM_RC_VALUE_MASK_10_MASK                   (0xffffL<<16)
3702
3703 #define BNX2_RPM_RC_CNTL_11                             0x00001958
3704 #define BNX2_RPM_RC_CNTL_11_A                            (0x3ffffL<<0)
3705 #define BNX2_RPM_RC_CNTL_11_B                            (0xfffL<<19)
3706 #define BNX2_RPM_RC_CNTL_11_OFFSET_XI                    (0xffL<<0)
3707 #define BNX2_RPM_RC_CNTL_11_CLASS_XI                     (0x7L<<8)
3708 #define BNX2_RPM_RC_CNTL_11_PRIORITY_XI                  (1L<<11)
3709 #define BNX2_RPM_RC_CNTL_11_P4_XI                        (1L<<12)
3710 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_XI                  (0x7L<<13)
3711 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_START_XI            (0L<<13)
3712 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_IP_XI               (1L<<13)
3713 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_XI              (2L<<13)
3714 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_UDP_XI              (3L<<13)
3715 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_DATA_XI             (4L<<13)
3716 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_UDP_XI          (5L<<13)
3717 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_ICMPV6_XI           (6L<<13)
3718 #define BNX2_RPM_RC_CNTL_11_COMP_XI                      (0x3L<<16)
3719 #define BNX2_RPM_RC_CNTL_11_COMP_EQUAL_XI                (0L<<16)
3720 #define BNX2_RPM_RC_CNTL_11_COMP_NEQUAL_XI               (1L<<16)
3721 #define BNX2_RPM_RC_CNTL_11_COMP_GREATER_XI              (2L<<16)
3722 #define BNX2_RPM_RC_CNTL_11_COMP_LESS_XI                 (3L<<16)
3723 #define BNX2_RPM_RC_CNTL_11_MAP_XI                       (1L<<18)
3724 #define BNX2_RPM_RC_CNTL_11_SBIT_XI                      (1L<<19)
3725 #define BNX2_RPM_RC_CNTL_11_CMDSEL_XI                    (0x1fL<<20)
3726 #define BNX2_RPM_RC_CNTL_11_DISCARD_XI                   (1L<<25)
3727 #define BNX2_RPM_RC_CNTL_11_MASK_XI                      (1L<<26)
3728 #define BNX2_RPM_RC_CNTL_11_P1_XI                        (1L<<27)
3729 #define BNX2_RPM_RC_CNTL_11_P2_XI                        (1L<<28)
3730 #define BNX2_RPM_RC_CNTL_11_P3_XI                        (1L<<29)
3731 #define BNX2_RPM_RC_CNTL_11_NBIT_XI                      (1L<<30)
3732
3733 #define BNX2_RPM_RC_VALUE_MASK_11                       0x0000195c
3734 #define BNX2_RPM_RC_VALUE_MASK_11_VALUE                  (0xffffL<<0)
3735 #define BNX2_RPM_RC_VALUE_MASK_11_MASK                   (0xffffL<<16)
3736
3737 #define BNX2_RPM_RC_CNTL_12                             0x00001960
3738 #define BNX2_RPM_RC_CNTL_12_A                            (0x3ffffL<<0)
3739 #define BNX2_RPM_RC_CNTL_12_B                            (0xfffL<<19)
3740 #define BNX2_RPM_RC_CNTL_12_OFFSET_XI                    (0xffL<<0)
3741 #define BNX2_RPM_RC_CNTL_12_CLASS_XI                     (0x7L<<8)
3742 #define BNX2_RPM_RC_CNTL_12_PRIORITY_XI                  (1L<<11)
3743 #define BNX2_RPM_RC_CNTL_12_P4_XI                        (1L<<12)
3744 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_XI                  (0x7L<<13)
3745 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_START_XI            (0L<<13)
3746 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_IP_XI               (1L<<13)
3747 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_XI              (2L<<13)
3748 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_UDP_XI              (3L<<13)
3749 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_DATA_XI             (4L<<13)
3750 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_UDP_XI          (5L<<13)
3751 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_ICMPV6_XI           (6L<<13)
3752 #define BNX2_RPM_RC_CNTL_12_COMP_XI                      (0x3L<<16)
3753 #define BNX2_RPM_RC_CNTL_12_COMP_EQUAL_XI                (0L<<16)
3754 #define BNX2_RPM_RC_CNTL_12_COMP_NEQUAL_XI               (1L<<16)
3755 #define BNX2_RPM_RC_CNTL_12_COMP_GREATER_XI              (2L<<16)
3756 #define BNX2_RPM_RC_CNTL_12_COMP_LESS_XI                 (3L<<16)
3757 #define BNX2_RPM_RC_CNTL_12_MAP_XI                       (1L<<18)
3758 #define BNX2_RPM_RC_CNTL_12_SBIT_XI                      (1L<<19)
3759 #define BNX2_RPM_RC_CNTL_12_CMDSEL_XI                    (0x1fL<<20)
3760 #define BNX2_RPM_RC_CNTL_12_DISCARD_XI                   (1L<<25)
3761 #define BNX2_RPM_RC_CNTL_12_MASK_XI                      (1L<<26)
3762 #define BNX2_RPM_RC_CNTL_12_P1_XI                        (1L<<27)
3763 #define BNX2_RPM_RC_CNTL_12_P2_XI                        (1L<<28)
3764 #define BNX2_RPM_RC_CNTL_12_P3_XI                        (1L<<29)
3765 #define BNX2_RPM_RC_CNTL_12_NBIT_XI                      (1L<<30)
3766
3767 #define BNX2_RPM_RC_VALUE_MASK_12                       0x00001964
3768 #define BNX2_RPM_RC_VALUE_MASK_12_VALUE                  (0xffffL<<0)
3769 #define BNX2_RPM_RC_VALUE_MASK_12_MASK                   (0xffffL<<16)
3770
3771 #define BNX2_RPM_RC_CNTL_13                             0x00001968
3772 #define BNX2_RPM_RC_CNTL_13_A                            (0x3ffffL<<0)
3773 #define BNX2_RPM_RC_CNTL_13_B                            (0xfffL<<19)
3774 #define BNX2_RPM_RC_CNTL_13_OFFSET_XI                    (0xffL<<0)
3775 #define BNX2_RPM_RC_CNTL_13_CLASS_XI                     (0x7L<<8)
3776 #define BNX2_RPM_RC_CNTL_13_PRIORITY_XI                  (1L<<11)
3777 #define BNX2_RPM_RC_CNTL_13_P4_XI                        (1L<<12)
3778 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_XI                  (0x7L<<13)
3779 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_START_XI            (0L<<13)
3780 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_IP_XI               (1L<<13)
3781 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_XI              (2L<<13)
3782 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_UDP_XI              (3L<<13)
3783 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_DATA_XI             (4L<<13)
3784 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_UDP_XI          (5L<<13)
3785 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_ICMPV6_XI           (6L<<13)
3786 #define BNX2_RPM_RC_CNTL_13_COMP_XI                      (0x3L<<16)
3787 #define BNX2_RPM_RC_CNTL_13_COMP_EQUAL_XI                (0L<<16)
3788 #define BNX2_RPM_RC_CNTL_13_COMP_NEQUAL_XI               (1L<<16)
3789 #define BNX2_RPM_RC_CNTL_13_COMP_GREATER_XI              (2L<<16)
3790 #define BNX2_RPM_RC_CNTL_13_COMP_LESS_XI                 (3L<<16)
3791 #define BNX2_RPM_RC_CNTL_13_MAP_XI                       (1L<<18)
3792 #define BNX2_RPM_RC_CNTL_13_SBIT_XI                      (1L<<19)
3793 #define BNX2_RPM_RC_CNTL_13_CMDSEL_XI                    (0x1fL<<20)
3794 #define BNX2_RPM_RC_CNTL_13_DISCARD_XI                   (1L<<25)
3795 #define BNX2_RPM_RC_CNTL_13_MASK_XI                      (1L<<26)
3796 #define BNX2_RPM_RC_CNTL_13_P1_XI                        (1L<<27)
3797 #define BNX2_RPM_RC_CNTL_13_P2_XI                        (1L<<28)
3798 #define BNX2_RPM_RC_CNTL_13_P3_XI                        (1L<<29)
3799 #define BNX2_RPM_RC_CNTL_13_NBIT_XI                      (1L<<30)
3800
3801 #define BNX2_RPM_RC_VALUE_MASK_13                       0x0000196c
3802 #define BNX2_RPM_RC_VALUE_MASK_13_VALUE                  (0xffffL<<0)
3803 #define BNX2_RPM_RC_VALUE_MASK_13_MASK                   (0xffffL<<16)
3804
3805 #define BNX2_RPM_RC_CNTL_14                             0x00001970
3806 #define BNX2_RPM_RC_CNTL_14_A                            (0x3ffffL<<0)
3807 #define BNX2_RPM_RC_CNTL_14_B                            (0xfffL<<19)
3808 #define BNX2_RPM_RC_CNTL_14_OFFSET_XI                    (0xffL<<0)
3809 #define BNX2_RPM_RC_CNTL_14_CLASS_XI                     (0x7L<<8)
3810 #define BNX2_RPM_RC_CNTL_14_PRIORITY_XI                  (1L<<11)
3811 #define BNX2_RPM_RC_CNTL_14_P4_XI                        (1L<<12)
3812 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_XI                  (0x7L<<13)
3813 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_START_XI            (0L<<13)
3814 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_IP_XI               (1L<<13)
3815 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_XI              (2L<<13)
3816 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_UDP_XI              (3L<<13)
3817 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_DATA_XI             (4L<<13)
3818 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_UDP_XI          (5L<<13)
3819 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_ICMPV6_XI           (6L<<13)
3820 #define BNX2_RPM_RC_CNTL_14_COMP_XI                      (0x3L<<16)
3821 #define BNX2_RPM_RC_CNTL_14_COMP_EQUAL_XI                (0L<<16)
3822 #define BNX2_RPM_RC_CNTL_14_COMP_NEQUAL_XI               (1L<<16)
3823 #define BNX2_RPM_RC_CNTL_14_COMP_GREATER_XI              (2L<<16)
3824 #define BNX2_RPM_RC_CNTL_14_COMP_LESS_XI                 (3L<<16)
3825 #define BNX2_RPM_RC_CNTL_14_MAP_XI                       (1L<<18)
3826 #define BNX2_RPM_RC_CNTL_14_SBIT_XI                      (1L<<19)
3827 #define BNX2_RPM_RC_CNTL_14_CMDSEL_XI                    (0x1fL<<20)
3828 #define BNX2_RPM_RC_CNTL_14_DISCARD_XI                   (1L<<25)
3829 #define BNX2_RPM_RC_CNTL_14_MASK_XI                      (1L<<26)
3830 #define BNX2_RPM_RC_CNTL_14_P1_XI                        (1L<<27)
3831 #define BNX2_RPM_RC_CNTL_14_P2_XI                        (1L<<28)
3832 #define BNX2_RPM_RC_CNTL_14_P3_XI                        (1L<<29)
3833 #define BNX2_RPM_RC_CNTL_14_NBIT_XI                      (1L<<30)
3834
3835 #define BNX2_RPM_RC_VALUE_MASK_14                       0x00001974
3836 #define BNX2_RPM_RC_VALUE_MASK_14_VALUE                  (0xffffL<<0)
3837 #define BNX2_RPM_RC_VALUE_MASK_14_MASK                   (0xffffL<<16)
3838
3839 #define BNX2_RPM_RC_CNTL_15                             0x00001978
3840 #define BNX2_RPM_RC_CNTL_15_A                            (0x3ffffL<<0)
3841 #define BNX2_RPM_RC_CNTL_15_B                            (0xfffL<<19)
3842 #define BNX2_RPM_RC_CNTL_15_OFFSET_XI                    (0xffL<<0)
3843 #define BNX2_RPM_RC_CNTL_15_CLASS_XI                     (0x7L<<8)
3844 #define BNX2_RPM_RC_CNTL_15_PRIORITY_XI                  (1L<<11)
3845 #define BNX2_RPM_RC_CNTL_15_P4_XI                        (1L<<12)
3846 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_XI                  (0x7L<<13)
3847 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_START_XI            (0L<<13)
3848 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_IP_XI               (1L<<13)
3849 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_XI              (2L<<13)
3850 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_UDP_XI              (3L<<13)
3851 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_DATA_XI             (4L<<13)
3852 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_UDP_XI          (5L<<13)
3853 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_ICMPV6_XI           (6L<<13)
3854 #define BNX2_RPM_RC_CNTL_15_COMP_XI                      (0x3L<<16)
3855 #define BNX2_RPM_RC_CNTL_15_COMP_EQUAL_XI                (0L<<16)
3856 #define BNX2_RPM_RC_CNTL_15_COMP_NEQUAL_XI               (1L<<16)
3857 #define BNX2_RPM_RC_CNTL_15_COMP_GREATER_XI              (2L<<16)
3858 #define BNX2_RPM_RC_CNTL_15_COMP_LESS_XI                 (3L<<16)
3859 #define BNX2_RPM_RC_CNTL_15_MAP_XI                       (1L<<18)
3860 #define BNX2_RPM_RC_CNTL_15_SBIT_XI                      (1L<<19)
3861 #define BNX2_RPM_RC_CNTL_15_CMDSEL_XI                    (0x1fL<<20)
3862 #define BNX2_RPM_RC_CNTL_15_DISCARD_XI                   (1L<<25)
3863 #define BNX2_RPM_RC_CNTL_15_MASK_XI                      (1L<<26)
3864 #define BNX2_RPM_RC_CNTL_15_P1_XI                        (1L<<27)
3865 #define BNX2_RPM_RC_CNTL_15_P2_XI                        (1L<<28)
3866 #define BNX2_RPM_RC_CNTL_15_P3_XI                        (1L<<29)
3867 #define BNX2_RPM_RC_CNTL_15_NBIT_XI                      (1L<<30)
3868
3869 #define BNX2_RPM_RC_VALUE_MASK_15                       0x0000197c
3870 #define BNX2_RPM_RC_VALUE_MASK_15_VALUE                  (0xffffL<<0)
3871 #define BNX2_RPM_RC_VALUE_MASK_15_MASK                   (0xffffL<<16)
3872
3873 #define BNX2_RPM_RC_CONFIG                              0x00001980
3874 #define BNX2_RPM_RC_CONFIG_RULE_ENABLE                   (0xffffL<<0)
3875 #define BNX2_RPM_RC_CONFIG_RULE_ENABLE_XI                (0xfffffL<<0)
3876 #define BNX2_RPM_RC_CONFIG_DEF_CLASS                     (0x7L<<24)
3877 #define BNX2_RPM_RC_CONFIG_KNUM_OVERWRITE                (1L<<31)
3878
3879 #define BNX2_RPM_DEBUG0                                 0x00001984
3880 #define BNX2_RPM_DEBUG0_FM_BCNT                          (0xffffL<<0)
3881 #define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD                  (1L<<16)
3882 #define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD                   (1L<<17)
3883 #define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD                   (1L<<18)
3884 #define BNX2_RPM_DEBUG0_T_IP_OFST_VLD                    (1L<<19)
3885 #define BNX2_RPM_DEBUG0_IP_MORE_FRGMT                    (1L<<20)
3886 #define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR              (1L<<21)
3887 #define BNX2_RPM_DEBUG0_LLC_SNAP                         (1L<<22)
3888 #define BNX2_RPM_DEBUG0_FM_STARTED                       (1L<<23)
3889 #define BNX2_RPM_DEBUG0_DONE                             (1L<<24)
3890 #define BNX2_RPM_DEBUG0_WAIT_4_DONE                      (1L<<25)
3891 #define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM                  (1L<<26)
3892 #define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM              (1L<<27)
3893 #define BNX2_RPM_DEBUG0_IGNORE_VLAN                      (1L<<28)
3894 #define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE                    (1L<<31)
3895
3896 #define BNX2_RPM_DEBUG1                                 0x00001988
3897 #define BNX2_RPM_DEBUG1_FSM_CUR_ST                       (0xffffL<<0)
3898 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE                  (0L<<0)
3899 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL          (1L<<0)
3900 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC        (2L<<0)
3901 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP           (4L<<0)
3902 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP           (8L<<0)
3903 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START              (16L<<0)
3904 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP                    (32L<<0)
3905 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP                   (64L<<0)
3906 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP                   (128L<<0)
3907 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH                    (256L<<0)
3908 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP                   (512L<<0)
3909 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD           (1024L<<0)
3910 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA                  (2048L<<0)
3911 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY             (0x2000L<<0)
3912 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT          (0x4000L<<0)
3913 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT          (0x8000L<<0)
3914 #define BNX2_RPM_DEBUG1_HDR_BCNT                         (0x7ffL<<16)
3915 #define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D                  (1L<<28)
3916 #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2                  (1L<<29)
3917 #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1                  (1L<<30)
3918 #define BNX2_RPM_DEBUG1_EOF_0XTRA_WD                     (1L<<31)
3919
3920 #define BNX2_RPM_DEBUG2                                 0x0000198c
3921 #define BNX2_RPM_DEBUG2_CMD_HIT_VEC                      (0xffffL<<0)
3922 #define BNX2_RPM_DEBUG2_IP_BCNT                          (0xffL<<16)
3923 #define BNX2_RPM_DEBUG2_THIS_CMD_M4                      (1L<<24)
3924 #define BNX2_RPM_DEBUG2_THIS_CMD_M3                      (1L<<25)
3925 #define BNX2_RPM_DEBUG2_THIS_CMD_M2                      (1L<<26)
3926 #define BNX2_RPM_DEBUG2_THIS_CMD_M1                      (1L<<27)
3927 #define BNX2_RPM_DEBUG2_IPIPE_EMPTY                      (1L<<28)
3928 #define BNX2_RPM_DEBUG2_FM_DISCARD                       (1L<<29)
3929 #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2               (1L<<30)
3930 #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1               (1L<<31)
3931
3932 #define BNX2_RPM_DEBUG3                                 0x00001990
3933 #define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR                   (0x1ffL<<0)
3934 #define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT             (1L<<9)
3935 #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT             (1L<<10)
3936 #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT              (1L<<11)
3937 #define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ                (1L<<12)
3938 #define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ               (1L<<13)
3939 #define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL               (1L<<14)
3940 #define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP                (1L<<15)
3941 #define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT               (0xfL<<16)
3942 #define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL             (1L<<21)
3943 #define BNX2_RPM_DEBUG3_DROP_NXT_VLD                     (1L<<22)
3944 #define BNX2_RPM_DEBUG3_DROP_NXT                         (1L<<23)
3945 #define BNX2_RPM_DEBUG3_FTQ_FSM                          (0x3L<<24)
3946 #define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE                     (0x0L<<24)
3947 #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK                 (0x1L<<24)
3948 #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE                (0x2L<<24)
3949 #define BNX2_RPM_DEBUG3_MBWRITE_FSM                      (0x3L<<26)
3950 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF             (0x0L<<26)
3951 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF             (0x1L<<26)
3952 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA             (0x2L<<26)
3953 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA            (0x3L<<26)
3954 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF             (0x4L<<26)
3955 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK          (0x5L<<26)
3956 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD    (0x6L<<26)
3957 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE                 (0x7L<<26)
3958 #define BNX2_RPM_DEBUG3_MBFREE_FSM                       (1L<<29)
3959 #define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE                  (0L<<29)
3960 #define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK              (1L<<29)
3961 #define BNX2_RPM_DEBUG3_MBALLOC_FSM                      (1L<<30)
3962 #define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF              (0x0L<<30)
3963 #define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF             (0x1L<<30)
3964 #define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR                  (1L<<31)
3965
3966 #define BNX2_RPM_DEBUG4                                 0x00001994
3967 #define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER                (0x1ffffffL<<0)
3968 #define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE                  (0x7L<<25)
3969 #define BNX2_RPM_DEBUG4_MBWRITE_FSM                      (0x7L<<28)
3970 #define BNX2_RPM_DEBUG4_DFIFO_EMPTY                      (1L<<31)
3971
3972 #define BNX2_RPM_DEBUG5                                 0x00001998
3973 #define BNX2_RPM_DEBUG5_RDROP_WPTR                       (0x1fL<<0)
3974 #define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR                  (0x1fL<<5)
3975 #define BNX2_RPM_DEBUG5_RDROP_MC_RPTR                    (0x1fL<<10)
3976 #define BNX2_RPM_DEBUG5_RDROP_RC_RPTR                    (0x1fL<<15)
3977 #define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY                 (1L<<20)
3978 #define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY                   (1L<<21)
3979 #define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR  (1L<<22)
3980 #define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT             (1L<<23)
3981 #define BNX2_RPM_DEBUG5_HOLDREG_DISCARD                  (1L<<24)
3982 #define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL            (1L<<25)
3983 #define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY                 (1L<<26)
3984 #define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY                 (1L<<27)
3985 #define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY                 (1L<<28)
3986 #define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY               (1L<<29)
3987 #define BNX2_RPM_DEBUG5_HOLDREG_FULL_T                   (1L<<30)
3988 #define BNX2_RPM_DEBUG5_HOLDREG_RD                       (1L<<31)
3989
3990 #define BNX2_RPM_DEBUG6                                 0x0000199c
3991 #define BNX2_RPM_DEBUG6_ACPI_VEC                         (0xffffL<<0)
3992 #define BNX2_RPM_DEBUG6_VEC                              (0xffffL<<16)
3993
3994 #define BNX2_RPM_DEBUG7                                 0x000019a0
3995 #define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC                (0xffffffffL<<0)
3996
3997 #define BNX2_RPM_DEBUG8                                 0x000019a4
3998 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM                      (0xfL<<0)
3999 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE                 (0L<<0)
4000 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR          (1L<<0)
4001 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR          (2L<<0)
4002 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR          (3L<<0)
4003 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF       (4L<<0)
4004 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA              (5L<<0)
4005 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR              (6L<<0)
4006 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR              (7L<<0)
4007 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR              (8L<<0)
4008 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR              (9L<<0)
4009 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF           (10L<<0)
4010 #define BNX2_RPM_DEBUG8_COMPARE_AT_W0                    (1L<<4)
4011 #define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA               (1L<<5)
4012 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT              (1L<<6)
4013 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3                (1L<<7)
4014 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2                (1L<<8)
4015 #define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES             (1L<<9)
4016 #define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES             (1L<<10)
4017 #define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES            (1L<<11)
4018 #define BNX2_RPM_DEBUG8_EOF_DET                          (1L<<12)
4019 #define BNX2_RPM_DEBUG8_SOF_DET                          (1L<<13)
4020 #define BNX2_RPM_DEBUG8_WAIT_4_SOF                       (1L<<14)
4021 #define BNX2_RPM_DEBUG8_ALL_DONE                         (1L<<15)
4022 #define BNX2_RPM_DEBUG8_THBUF_ADDR                       (0x7fL<<16)
4023 #define BNX2_RPM_DEBUG8_BYTE_CTR                         (0xffL<<24)
4024
4025 #define BNX2_RPM_DEBUG9                                 0x000019a8
4026 #define BNX2_RPM_DEBUG9_OUTFIFO_COUNT                    (0x7L<<0)
4027 #define BNX2_RPM_DEBUG9_RDE_ACPI_RDY                     (1L<<3)
4028 #define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT                  (0x7L<<4)
4029 #define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED         (1L<<28)
4030 #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED          (1L<<29)
4031 #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT                   (1L<<30)
4032 #define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN                  (1L<<31)
4033 #define BNX2_RPM_DEBUG9_BEMEM_R_XI                       (0x1fL<<0)
4034 #define BNX2_RPM_DEBUG9_EO_XI                            (1L<<5)
4035 #define BNX2_RPM_DEBUG9_AEOF_DE_XI                       (1L<<6)
4036 #define BNX2_RPM_DEBUG9_SO_XI                            (1L<<7)
4037 #define BNX2_RPM_DEBUG9_WD64_CT_XI                       (0x1fL<<8)
4038 #define BNX2_RPM_DEBUG9_EOF_VLDBYTE_XI                   (0x7L<<13)
4039 #define BNX2_RPM_DEBUG9_ACPI_RDE_PAT_ID_XI               (0xfL<<16)
4040 #define BNX2_RPM_DEBUG9_CALCRC_RESULT_XI                 (0x3ffL<<20)
4041 #define BNX2_RPM_DEBUG9_DATA_IN_VL_XI                    (1L<<30)
4042 #define BNX2_RPM_DEBUG9_CALCRC_BUFFER_VLD_XI             (1L<<31)
4043
4044 #define BNX2_RPM_ACPI_DBG_BUF_W00                       0x000019c0
4045 #define BNX2_RPM_ACPI_DBG_BUF_W01                       0x000019c4
4046 #define BNX2_RPM_ACPI_DBG_BUF_W02                       0x000019c8
4047 #define BNX2_RPM_ACPI_DBG_BUF_W03                       0x000019cc
4048 #define BNX2_RPM_ACPI_DBG_BUF_W10                       0x000019d0
4049 #define BNX2_RPM_ACPI_DBG_BUF_W11                       0x000019d4
4050 #define BNX2_RPM_ACPI_DBG_BUF_W12                       0x000019d8
4051 #define BNX2_RPM_ACPI_DBG_BUF_W13                       0x000019dc
4052 #define BNX2_RPM_ACPI_DBG_BUF_W20                       0x000019e0
4053 #define BNX2_RPM_ACPI_DBG_BUF_W21                       0x000019e4
4054 #define BNX2_RPM_ACPI_DBG_BUF_W22                       0x000019e8
4055 #define BNX2_RPM_ACPI_DBG_BUF_W23                       0x000019ec
4056 #define BNX2_RPM_ACPI_DBG_BUF_W30                       0x000019f0
4057 #define BNX2_RPM_ACPI_DBG_BUF_W31                       0x000019f4
4058 #define BNX2_RPM_ACPI_DBG_BUF_W32                       0x000019f8
4059 #define BNX2_RPM_ACPI_DBG_BUF_W33                       0x000019fc
4060 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL                  0x00001a00
4061 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_BYTE_ADDRESS      (0xffffL<<0)
4062 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_DEBUGRD           (1L<<28)
4063 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_MODE              (1L<<29)
4064 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_INIT              (1L<<30)
4065 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_WR                (1L<<31)
4066
4067 #define BNX2_RPM_ACPI_PATTERN_CTRL                      0x00001a04
4068 #define BNX2_RPM_ACPI_PATTERN_CTRL_PATTERN_ID            (0xfL<<0)
4069 #define BNX2_RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR            (1L<<30)
4070 #define BNX2_RPM_ACPI_PATTERN_CTRL_WR                    (1L<<31)
4071
4072 #define BNX2_RPM_ACPI_DATA                              0x00001a08
4073 #define BNX2_RPM_ACPI_DATA_PATTERN_BE                    (0xffffffffL<<0)
4074
4075 #define BNX2_RPM_ACPI_PATTERN_LEN0                      0x00001a0c
4076 #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN3          (0xffL<<0)
4077 #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN2          (0xffL<<8)
4078 #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN1          (0xffL<<16)
4079 #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN0          (0xffL<<24)
4080
4081 #define BNX2_RPM_ACPI_PATTERN_LEN1                      0x00001a10
4082 #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN7          (0xffL<<0)
4083 #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN6          (0xffL<<8)
4084 #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN5          (0xffL<<16)
4085 #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN4          (0xffL<<24)
4086
4087 #define BNX2_RPM_ACPI_PATTERN_CRC0                      0x00001a18
4088 #define BNX2_RPM_ACPI_PATTERN_CRC0_PATTERN_CRC0          (0xffffffffL<<0)
4089
4090 #define BNX2_RPM_ACPI_PATTERN_CRC1                      0x00001a1c
4091 #define BNX2_RPM_ACPI_PATTERN_CRC1_PATTERN_CRC1          (0xffffffffL<<0)
4092
4093 #define BNX2_RPM_ACPI_PATTERN_CRC2                      0x00001a20
4094 #define BNX2_RPM_ACPI_PATTERN_CRC2_PATTERN_CRC2          (0xffffffffL<<0)
4095
4096 #define BNX2_RPM_ACPI_PATTERN_CRC3                      0x00001a24
4097 #define BNX2_RPM_ACPI_PATTERN_CRC3_PATTERN_CRC3          (0xffffffffL<<0)
4098
4099 #define BNX2_RPM_ACPI_PATTERN_CRC4                      0x00001a28
4100 #define BNX2_RPM_ACPI_PATTERN_CRC4_PATTERN_CRC4          (0xffffffffL<<0)
4101
4102 #define BNX2_RPM_ACPI_PATTERN_CRC5                      0x00001a2c
4103 #define BNX2_RPM_ACPI_PATTERN_CRC5_PATTERN_CRC5          (0xffffffffL<<0)
4104
4105 #define BNX2_RPM_ACPI_PATTERN_CRC6                      0x00001a30
4106 #define BNX2_RPM_ACPI_PATTERN_CRC6_PATTERN_CRC6          (0xffffffffL<<0)
4107
4108 #define BNX2_RPM_ACPI_PATTERN_CRC7                      0x00001a34
4109 #define BNX2_RPM_ACPI_PATTERN_CRC7_PATTERN_CRC7          (0xffffffffL<<0)
4110
4111
4112 /*
4113  *  rbuf_reg definition
4114  *  offset: 0x200000
4115  */
4116 #define BNX2_RBUF_COMMAND                               0x00200000
4117 #define BNX2_RBUF_COMMAND_ENABLED                        (1L<<0)
4118 #define BNX2_RBUF_COMMAND_FREE_INIT                      (1L<<1)
4119 #define BNX2_RBUF_COMMAND_RAM_INIT                       (1L<<2)
4120 #define BNX2_RBUF_COMMAND_PKT_OFFSET_OVFL                (1L<<3)
4121 #define BNX2_RBUF_COMMAND_OVER_FREE                      (1L<<4)
4122 #define BNX2_RBUF_COMMAND_ALLOC_REQ                      (1L<<5)
4123 #define BNX2_RBUF_COMMAND_EN_PRI_CHNGE_TE                (1L<<6)
4124 #define BNX2_RBUF_COMMAND_CU_ISOLATE_XI                  (1L<<5)
4125 #define BNX2_RBUF_COMMAND_EN_PRI_CHANGE_XI               (1L<<6)
4126 #define BNX2_RBUF_COMMAND_GRC_ENDIAN_CONV_DIS_XI         (1L<<7)
4127
4128 #define BNX2_RBUF_STATUS1                               0x00200004
4129 #define BNX2_RBUF_STATUS1_FREE_COUNT                     (0x3ffL<<0)
4130
4131 #define BNX2_RBUF_STATUS2                               0x00200008
4132 #define BNX2_RBUF_STATUS2_FREE_TAIL                      (0x1ffL<<0)
4133 #define BNX2_RBUF_STATUS2_FREE_HEAD                      (0x1ffL<<16)
4134
4135 #define BNX2_RBUF_CONFIG                                0x0020000c
4136 #define BNX2_RBUF_CONFIG_XOFF_TRIP                       (0x3ffL<<0)
4137 #define BNX2_RBUF_CONFIG_XON_TRIP                        (0x3ffL<<16)
4138
4139 #define BNX2_RBUF_FW_BUF_ALLOC                          0x00200010
4140 #define BNX2_RBUF_FW_BUF_ALLOC_VALUE                     (0x1ffL<<7)
4141 #define BNX2_RBUF_FW_BUF_ALLOC_TYPE                      (1L<<16)
4142 #define BNX2_RBUF_FW_BUF_ALLOC_ALLOC_REQ                 (1L<<31)
4143
4144 #define BNX2_RBUF_FW_BUF_FREE                           0x00200014
4145 #define BNX2_RBUF_FW_BUF_FREE_COUNT                      (0x7fL<<0)
4146 #define BNX2_RBUF_FW_BUF_FREE_TAIL                       (0x1ffL<<7)
4147 #define BNX2_RBUF_FW_BUF_FREE_HEAD                       (0x1ffL<<16)
4148 #define BNX2_RBUF_FW_BUF_FREE_TYPE                       (1L<<25)
4149 #define BNX2_RBUF_FW_BUF_FREE_FREE_REQ                   (1L<<31)
4150
4151 #define BNX2_RBUF_FW_BUF_SEL                            0x00200018
4152 #define BNX2_RBUF_FW_BUF_SEL_COUNT                       (0x7fL<<0)
4153 #define BNX2_RBUF_FW_BUF_SEL_TAIL                        (0x1ffL<<7)
4154 #define BNX2_RBUF_FW_BUF_SEL_HEAD                        (0x1ffL<<16)
4155 #define BNX2_RBUF_FW_BUF_SEL_SEL_REQ                     (1L<<31)
4156
4157 #define BNX2_RBUF_CONFIG2                               0x0020001c
4158 #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP                  (0x3ffL<<0)
4159 #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP                  (0x3ffL<<16)
4160
4161 #define BNX2_RBUF_CONFIG3                               0x00200020
4162 #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP                   (0x3ffL<<0)
4163 #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP                   (0x3ffL<<16)
4164
4165 #define BNX2_RBUF_PKT_DATA                              0x00208000
4166 #define BNX2_RBUF_CLIST_DATA                            0x00210000
4167 #define BNX2_RBUF_BUF_DATA                              0x00220000
4168
4169
4170 /*
4171  *  rv2p_reg definition
4172  *  offset: 0x2800
4173  */
4174 #define BNX2_RV2P_COMMAND                               0x00002800
4175 #define BNX2_RV2P_COMMAND_ENABLED                        (1L<<0)
4176 #define BNX2_RV2P_COMMAND_PROC1_INTRPT                   (1L<<1)
4177 #define BNX2_RV2P_COMMAND_PROC2_INTRPT                   (1L<<2)
4178 #define BNX2_RV2P_COMMAND_ABORT0                         (1L<<4)
4179 #define BNX2_RV2P_COMMAND_ABORT1                         (1L<<5)
4180 #define BNX2_RV2P_COMMAND_ABORT2                         (1L<<6)
4181 #define BNX2_RV2P_COMMAND_ABORT3                         (1L<<7)
4182 #define BNX2_RV2P_COMMAND_ABORT4                         (1L<<8)
4183 #define BNX2_RV2P_COMMAND_ABORT5                         (1L<<9)
4184 #define BNX2_RV2P_COMMAND_PROC1_RESET                    (1L<<16)
4185 #define BNX2_RV2P_COMMAND_PROC2_RESET                    (1L<<17)
4186 #define BNX2_RV2P_COMMAND_CTXIF_RESET                    (1L<<18)
4187
4188 #define BNX2_RV2P_STATUS                                0x00002804
4189 #define BNX2_RV2P_STATUS_ALWAYS_0                        (1L<<0)
4190 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT              (1L<<8)
4191 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT              (1L<<9)
4192 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT              (1L<<10)
4193 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT              (1L<<11)
4194 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT              (1L<<12)
4195 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT              (1L<<13)
4196
4197 #define BNX2_RV2P_CONFIG                                0x00002808
4198 #define BNX2_RV2P_CONFIG_STALL_PROC1                     (1L<<0)
4199 #define BNX2_RV2P_CONFIG_STALL_PROC2                     (1L<<1)
4200 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0           (1L<<8)
4201 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1           (1L<<9)
4202 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2           (1L<<10)
4203 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3           (1L<<11)
4204 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4           (1L<<12)
4205 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5           (1L<<13)
4206 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0           (1L<<16)
4207 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1           (1L<<17)
4208 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2           (1L<<18)
4209 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3           (1L<<19)
4210 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4           (1L<<20)
4211 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5           (1L<<21)
4212 #define BNX2_RV2P_CONFIG_PAGE_SIZE                       (0xfL<<24)
4213 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256                   (0L<<24)
4214 #define BNX2_RV2P_CONFIG_PAGE_SIZE_512                   (1L<<24)
4215 #define BNX2_RV2P_CONFIG_PAGE_SIZE_1K                    (2L<<24)
4216 #define BNX2_RV2P_CONFIG_PAGE_SIZE_2K                    (3L<<24)
4217 #define BNX2_RV2P_CONFIG_PAGE_SIZE_4K                    (4L<<24)
4218 #define BNX2_RV2P_CONFIG_PAGE_SIZE_8K                    (5L<<24)
4219 #define BNX2_RV2P_CONFIG_PAGE_SIZE_16K                   (6L<<24)
4220 #define BNX2_RV2P_CONFIG_PAGE_SIZE_32K                   (7L<<24)
4221 #define BNX2_RV2P_CONFIG_PAGE_SIZE_64K                   (8L<<24)
4222 #define BNX2_RV2P_CONFIG_PAGE_SIZE_128K                  (9L<<24)
4223 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256K                  (10L<<24)
4224 #define BNX2_RV2P_CONFIG_PAGE_SIZE_512K                  (11L<<24)
4225 #define BNX2_RV2P_CONFIG_PAGE_SIZE_1M                    (12L<<24)
4226
4227 #define BNX2_RV2P_GEN_BFR_ADDR_0                        0x00002810
4228 #define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE                   (0xffffL<<16)
4229
4230 #define BNX2_RV2P_GEN_BFR_ADDR_1                        0x00002814
4231 #define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE                   (0xffffL<<16)
4232
4233 #define BNX2_RV2P_GEN_BFR_ADDR_2                        0x00002818
4234 #define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE                   (0xffffL<<16)
4235
4236 #define BNX2_RV2P_GEN_BFR_ADDR_3                        0x0000281c
4237 #define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE                   (0xffffL<<16)
4238
4239 #define BNX2_RV2P_INSTR_HIGH                            0x00002830
4240 #define BNX2_RV2P_INSTR_HIGH_HIGH                        (0x1fL<<0)
4241
4242 #define BNX2_RV2P_INSTR_LOW                             0x00002834
4243 #define BNX2_RV2P_INSTR_LOW_LOW                          (0xffffffffL<<0)
4244
4245 #define BNX2_RV2P_PROC1_ADDR_CMD                        0x00002838
4246 #define BNX2_RV2P_PROC1_ADDR_CMD_ADD                     (0x3ffL<<0)
4247 #define BNX2_RV2P_PROC1_ADDR_CMD_RDWR                    (1L<<31)
4248
4249 #define BNX2_RV2P_PROC2_ADDR_CMD                        0x0000283c
4250 #define BNX2_RV2P_PROC2_ADDR_CMD_ADD                     (0x3ffL<<0)
4251 #define BNX2_RV2P_PROC2_ADDR_CMD_RDWR                    (1L<<31)
4252
4253 #define BNX2_RV2P_PROC1_GRC_DEBUG                       0x00002840
4254 #define BNX2_RV2P_PROC2_GRC_DEBUG                       0x00002844
4255 #define BNX2_RV2P_GRC_PROC_DEBUG                        0x00002848
4256 #define BNX2_RV2P_DEBUG_VECT_PEEK                       0x0000284c
4257 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE                (0x7ffL<<0)
4258 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN              (1L<<11)
4259 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL                  (0xfL<<12)
4260 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE                (0x7ffL<<16)
4261 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN              (1L<<27)
4262 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL                  (0xfL<<28)
4263
4264 #define BNX2_RV2P_MPFE_PFE_CTL                          0x00002afc
4265 #define BNX2_RV2P_MPFE_PFE_CTL_INC_USAGE_CNT             (1L<<0)
4266 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE                  (0xfL<<4)
4267 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_0                (0L<<4)
4268 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_1                (1L<<4)
4269 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_2                (2L<<4)
4270 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_3                (3L<<4)
4271 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_4                (4L<<4)
4272 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_5                (5L<<4)
4273 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_6                (6L<<4)
4274 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_7                (7L<<4)
4275 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_8                (8L<<4)
4276 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_9                (9L<<4)
4277 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_10               (10L<<4)
4278 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_11               (11L<<4)
4279 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_12               (12L<<4)
4280 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_13               (13L<<4)
4281 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_14               (14L<<4)
4282 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_15               (15L<<4)
4283 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_COUNT                 (0xfL<<12)
4284 #define BNX2_RV2P_MPFE_PFE_CTL_OFFSET                    (0x1ffL<<16)
4285
4286 #define BNX2_RV2P_RV2PPQ                                0x00002b40
4287 #define BNX2_RV2P_PFTQ_CMD                              0x00002b78
4288 #define BNX2_RV2P_PFTQ_CMD_OFFSET                        (0x3ffL<<0)
4289 #define BNX2_RV2P_PFTQ_CMD_WR_TOP                        (1L<<10)
4290 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_0                      (0L<<10)
4291 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_1                      (1L<<10)
4292 #define BNX2_RV2P_PFTQ_CMD_SFT_RESET                     (1L<<25)
4293 #define BNX2_RV2P_PFTQ_CMD_RD_DATA                       (1L<<26)
4294 #define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN                  (1L<<27)
4295 #define BNX2_RV2P_PFTQ_CMD_ADD_DATA                      (1L<<28)
4296 #define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR                 (1L<<29)
4297 #define BNX2_RV2P_PFTQ_CMD_POP                           (1L<<30)
4298 #define BNX2_RV2P_PFTQ_CMD_BUSY                          (1L<<31)
4299
4300 #define BNX2_RV2P_PFTQ_CTL                              0x00002b7c
4301 #define BNX2_RV2P_PFTQ_CTL_INTERVENE                     (1L<<0)
4302 #define BNX2_RV2P_PFTQ_CTL_OVERFLOW                      (1L<<1)
4303 #define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE               (1L<<2)
4304 #define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
4305 #define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
4306
4307 #define BNX2_RV2P_RV2PTQ                                0x00002b80
4308 #define BNX2_RV2P_TFTQ_CMD                              0x00002bb8
4309 #define BNX2_RV2P_TFTQ_CMD_OFFSET                        (0x3ffL<<0)
4310 #define BNX2_RV2P_TFTQ_CMD_WR_TOP                        (1L<<10)
4311 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_0                      (0L<<10)
4312 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_1                      (1L<<10)
4313 #define BNX2_RV2P_TFTQ_CMD_SFT_RESET                     (1L<<25)
4314 #define BNX2_RV2P_TFTQ_CMD_RD_DATA                       (1L<<26)
4315 #define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN                  (1L<<27)
4316 #define BNX2_RV2P_TFTQ_CMD_ADD_DATA                      (1L<<28)
4317 #define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR                 (1L<<29)
4318 #define BNX2_RV2P_TFTQ_CMD_POP                           (1L<<30)
4319 #define BNX2_RV2P_TFTQ_CMD_BUSY                          (1L<<31)
4320
4321 #define BNX2_RV2P_TFTQ_CTL                              0x00002bbc
4322 #define BNX2_RV2P_TFTQ_CTL_INTERVENE                     (1L<<0)
4323 #define BNX2_RV2P_TFTQ_CTL_OVERFLOW                      (1L<<1)
4324 #define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE               (1L<<2)
4325 #define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
4326 #define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
4327
4328 #define BNX2_RV2P_RV2PMQ                                0x00002bc0
4329 #define BNX2_RV2P_MFTQ_CMD                              0x00002bf8
4330 #define BNX2_RV2P_MFTQ_CMD_OFFSET                        (0x3ffL<<0)
4331 #define BNX2_RV2P_MFTQ_CMD_WR_TOP                        (1L<<10)
4332 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_0                      (0L<<10)
4333 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_1                      (1L<<10)
4334 #define BNX2_RV2P_MFTQ_CMD_SFT_RESET                     (1L<<25)
4335 #define BNX2_RV2P_MFTQ_CMD_RD_DATA                       (1L<<26)
4336 #define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN                  (1L<<27)
4337 #define BNX2_RV2P_MFTQ_CMD_ADD_DATA                      (1L<<28)
4338 #define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR                 (1L<<29)
4339 #define BNX2_RV2P_MFTQ_CMD_POP                           (1L<<30)
4340 #define BNX2_RV2P_MFTQ_CMD_BUSY                          (1L<<31)
4341
4342 #define BNX2_RV2P_MFTQ_CTL                              0x00002bfc
4343 #define BNX2_RV2P_MFTQ_CTL_INTERVENE                     (1L<<0)
4344 #define BNX2_RV2P_MFTQ_CTL_OVERFLOW                      (1L<<1)
4345 #define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE               (1L<<2)
4346 #define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
4347 #define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
4348
4349
4350
4351 /*
4352  *  mq_reg definition
4353  *  offset: 0x3c00
4354  */
4355 #define BNX2_MQ_COMMAND                                 0x00003c00
4356 #define BNX2_MQ_COMMAND_ENABLED                          (1L<<0)
4357 #define BNX2_MQ_COMMAND_INIT                             (1L<<1)
4358 #define BNX2_MQ_COMMAND_OVERFLOW                         (1L<<4)
4359 #define BNX2_MQ_COMMAND_WR_ERROR                         (1L<<5)
4360 #define BNX2_MQ_COMMAND_RD_ERROR                         (1L<<6)
4361 #define BNX2_MQ_COMMAND_IDB_CFG_ERROR                    (1L<<7)
4362 #define BNX2_MQ_COMMAND_IDB_OVERFLOW                     (1L<<10)
4363 #define BNX2_MQ_COMMAND_NO_BIN_ERROR                     (1L<<11)
4364 #define BNX2_MQ_COMMAND_NO_MAP_ERROR                     (1L<<12)
4365
4366 #define BNX2_MQ_STATUS                                  0x00003c04
4367 #define BNX2_MQ_STATUS_CTX_ACCESS_STAT                   (1L<<16)
4368 #define BNX2_MQ_STATUS_CTX_ACCESS64_STAT                 (1L<<17)
4369 #define BNX2_MQ_STATUS_PCI_STALL_STAT                    (1L<<18)
4370 #define BNX2_MQ_STATUS_IDB_OFLOW_STAT                    (1L<<19)
4371
4372 #define BNX2_MQ_CONFIG                                  0x00003c08
4373 #define BNX2_MQ_CONFIG_TX_HIGH_PRI                       (1L<<0)
4374 #define BNX2_MQ_CONFIG_HALT_DIS                          (1L<<1)
4375 #define BNX2_MQ_CONFIG_BIN_MQ_MODE                       (1L<<2)
4376 #define BNX2_MQ_CONFIG_DIS_IDB_DROP                      (1L<<3)
4377 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE                  (0x7L<<4)
4378 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256              (0L<<4)
4379 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512              (1L<<4)
4380 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K               (2L<<4)
4381 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K               (3L<<4)
4382 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K               (4L<<4)
4383 #define BNX2_MQ_CONFIG_MAX_DEPTH                         (0x7fL<<8)
4384 #define BNX2_MQ_CONFIG_CUR_DEPTH                         (0x7fL<<20)
4385
4386 #define BNX2_MQ_ENQUEUE1                                0x00003c0c
4387 #define BNX2_MQ_ENQUEUE1_OFFSET                          (0x3fL<<2)
4388 #define BNX2_MQ_ENQUEUE1_CID                             (0x3fffL<<8)
4389 #define BNX2_MQ_ENQUEUE1_BYTE_MASK                       (0xfL<<24)
4390 #define BNX2_MQ_ENQUEUE1_KNL_MODE                        (1L<<28)
4391
4392 #define BNX2_MQ_ENQUEUE2                                0x00003c10
4393 #define BNX2_MQ_BAD_WR_ADDR                             0x00003c14
4394 #define BNX2_MQ_BAD_RD_ADDR                             0x00003c18
4395 #define BNX2_MQ_KNL_BYP_WIND_START                      0x00003c1c
4396 #define BNX2_MQ_KNL_BYP_WIND_START_VALUE                 (0xfffffL<<12)
4397
4398 #define BNX2_MQ_KNL_WIND_END                            0x00003c20
4399 #define BNX2_MQ_KNL_WIND_END_VALUE                       (0xffffffL<<8)
4400
4401 #define BNX2_MQ_KNL_WRITE_MASK1                         0x00003c24
4402 #define BNX2_MQ_KNL_TX_MASK1                            0x00003c28
4403 #define BNX2_MQ_KNL_CMD_MASK1                           0x00003c2c
4404 #define BNX2_MQ_KNL_COND_ENQUEUE_MASK1                  0x00003c30
4405 #define BNX2_MQ_KNL_RX_V2P_MASK1                        0x00003c34
4406 #define BNX2_MQ_KNL_WRITE_MASK2                         0x00003c38
4407 #define BNX2_MQ_KNL_TX_MASK2                            0x00003c3c
4408 #define BNX2_MQ_KNL_CMD_MASK2                           0x00003c40
4409 #define BNX2_MQ_KNL_COND_ENQUEUE_MASK2                  0x00003c44
4410 #define BNX2_MQ_KNL_RX_V2P_MASK2                        0x00003c48
4411 #define BNX2_MQ_KNL_BYP_WRITE_MASK1                     0x00003c4c
4412 #define BNX2_MQ_KNL_BYP_TX_MASK1                        0x00003c50
4413 #define BNX2_MQ_KNL_BYP_CMD_MASK1                       0x00003c54
4414 #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1              0x00003c58
4415 #define BNX2_MQ_KNL_BYP_RX_V2P_MASK1                    0x00003c5c
4416 #define BNX2_MQ_KNL_BYP_WRITE_MASK2                     0x00003c60
4417 #define BNX2_MQ_KNL_BYP_TX_MASK2                        0x00003c64
4418 #define BNX2_MQ_KNL_BYP_CMD_MASK2                       0x00003c68
4419 #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2              0x00003c6c
4420 #define BNX2_MQ_KNL_BYP_RX_V2P_MASK2                    0x00003c70
4421 #define BNX2_MQ_MEM_WR_ADDR                             0x00003c74
4422 #define BNX2_MQ_MEM_WR_ADDR_VALUE                        (0x3fL<<0)
4423
4424 #define BNX2_MQ_MEM_WR_DATA0                            0x00003c78
4425 #define BNX2_MQ_MEM_WR_DATA0_VALUE                       (0xffffffffL<<0)
4426
4427 #define BNX2_MQ_MEM_WR_DATA1                            0x00003c7c
4428 #define BNX2_MQ_MEM_WR_DATA1_VALUE                       (0xffffffffL<<0)
4429
4430 #define BNX2_MQ_MEM_WR_DATA2                            0x00003c80
4431 #define BNX2_MQ_MEM_WR_DATA2_VALUE                       (0x3fffffffL<<0)
4432 #define BNX2_MQ_MEM_WR_DATA2_VALUE_XI                    (0x7fffffffL<<0)
4433
4434 #define BNX2_MQ_MEM_RD_ADDR                             0x00003c84
4435 #define BNX2_MQ_MEM_RD_ADDR_VALUE                        (0x3fL<<0)
4436
4437 #define BNX2_MQ_MEM_RD_DATA0                            0x00003c88
4438 #define BNX2_MQ_MEM_RD_DATA0_VALUE                       (0xffffffffL<<0)
4439
4440 #define BNX2_MQ_MEM_RD_DATA1                            0x00003c8c
4441 #define BNX2_MQ_MEM_RD_DATA1_VALUE                       (0xffffffffL<<0)
4442
4443 #define BNX2_MQ_MEM_RD_DATA2                            0x00003c90
4444 #define BNX2_MQ_MEM_RD_DATA2_VALUE                       (0x3fffffffL<<0)
4445 #define BNX2_MQ_MEM_RD_DATA2_VALUE_XI                    (0x7fffffffL<<0)
4446
4447
4448 /*
4449  *  tsch_reg definition
4450  *  offset: 0x4c00
4451  */
4452 #define BNX2_TSCH_TSS_CFG                               0x00004c1c
4453 #define BNX2_TSCH_TSS_CFG_TSS_START_CID                  (0x7ffL<<8)
4454 #define BNX2_TSCH_TSS_CFG_NUM_OF_TSS_CON                 (0xfL<<24)
4455
4456
4457
4458 /*
4459  *  tbdr_reg definition
4460  *  offset: 0x5000
4461  */
4462 #define BNX2_TBDR_COMMAND                               0x00005000
4463 #define BNX2_TBDR_COMMAND_ENABLE                         (1L<<0)
4464 #define BNX2_TBDR_COMMAND_SOFT_RST                       (1L<<1)
4465 #define BNX2_TBDR_COMMAND_MSTR_ABORT                     (1L<<4)
4466
4467 #define BNX2_TBDR_STATUS                                0x00005004
4468 #define BNX2_TBDR_STATUS_DMA_WAIT                        (1L<<0)
4469 #define BNX2_TBDR_STATUS_FTQ_WAIT                        (1L<<1)
4470 #define BNX2_TBDR_STATUS_FIFO_OVERFLOW                   (1L<<2)
4471 #define BNX2_TBDR_STATUS_FIFO_UNDERFLOW                  (1L<<3)
4472 #define BNX2_TBDR_STATUS_SEARCHMISS_ERROR                (1L<<4)
4473 #define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT                   (1L<<5)
4474 #define BNX2_TBDR_STATUS_BURST_CNT                       (1L<<6)
4475
4476 #define BNX2_TBDR_CONFIG                                0x00005008
4477 #define BNX2_TBDR_CONFIG_MAX_BDS                         (0xffL<<0)
4478 #define BNX2_TBDR_CONFIG_SWAP_MODE                       (1L<<8)
4479 #define BNX2_TBDR_CONFIG_PRIORITY                        (1L<<9)
4480 #define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS            (1L<<10)
4481 #define BNX2_TBDR_CONFIG_PAGE_SIZE                       (0xfL<<24)
4482 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256                   (0L<<24)
4483 #define BNX2_TBDR_CONFIG_PAGE_SIZE_512                   (1L<<24)
4484 #define BNX2_TBDR_CONFIG_PAGE_SIZE_1K                    (2L<<24)
4485 #define BNX2_TBDR_CONFIG_PAGE_SIZE_2K                    (3L<<24)
4486 #define BNX2_TBDR_CONFIG_PAGE_SIZE_4K                    (4L<<24)
4487 #define BNX2_TBDR_CONFIG_PAGE_SIZE_8K                    (5L<<24)
4488 #define BNX2_TBDR_CONFIG_PAGE_SIZE_16K                   (6L<<24)
4489 #define BNX2_TBDR_CONFIG_PAGE_SIZE_32K                   (7L<<24)
4490 #define BNX2_TBDR_CONFIG_PAGE_SIZE_64K                   (8L<<24)
4491 #define BNX2_TBDR_CONFIG_PAGE_SIZE_128K                  (9L<<24)
4492 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256K                  (10L<<24)
4493 #define BNX2_TBDR_CONFIG_PAGE_SIZE_512K                  (11L<<24)
4494 #define BNX2_TBDR_CONFIG_PAGE_SIZE_1M                    (12L<<24)
4495
4496 #define BNX2_TBDR_DEBUG_VECT_PEEK                       0x0000500c
4497 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE                (0x7ffL<<0)
4498 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN              (1L<<11)
4499 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL                  (0xfL<<12)
4500 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE                (0x7ffL<<16)
4501 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN              (1L<<27)
4502 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL                  (0xfL<<28)
4503
4504 #define BNX2_TBDR_CKSUM_ERROR_STATUS                    0x00005010
4505 #define BNX2_TBDR_CKSUM_ERROR_STATUS_CALCULATED          (0xffffL<<0)
4506 #define BNX2_TBDR_CKSUM_ERROR_STATUS_EXPECTED            (0xffffL<<16)
4507
4508 #define BNX2_TBDR_TBDRQ                                 0x000053c0
4509 #define BNX2_TBDR_FTQ_CMD                               0x000053f8
4510 #define BNX2_TBDR_FTQ_CMD_OFFSET                         (0x3ffL<<0)
4511 #define BNX2_TBDR_FTQ_CMD_WR_TOP                         (1L<<10)
4512 #define BNX2_TBDR_FTQ_CMD_WR_TOP_0                       (0L<<10)
4513 #define BNX2_TBDR_FTQ_CMD_WR_TOP_1                       (1L<<10)
4514 #define BNX2_TBDR_FTQ_CMD_SFT_RESET                      (1L<<25)
4515 #define BNX2_TBDR_FTQ_CMD_RD_DATA                        (1L<<26)
4516 #define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN                   (1L<<27)
4517 #define BNX2_TBDR_FTQ_CMD_ADD_DATA                       (1L<<28)
4518 #define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR                  (1L<<29)
4519 #define BNX2_TBDR_FTQ_CMD_POP                            (1L<<30)
4520 #define BNX2_TBDR_FTQ_CMD_BUSY                           (1L<<31)
4521
4522 #define BNX2_TBDR_FTQ_CTL                               0x000053fc
4523 #define BNX2_TBDR_FTQ_CTL_INTERVENE                      (1L<<0)
4524 #define BNX2_TBDR_FTQ_CTL_OVERFLOW                       (1L<<1)
4525 #define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE                (1L<<2)
4526 #define BNX2_TBDR_FTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
4527 #define BNX2_TBDR_FTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
4528
4529
4530
4531 /*
4532  *  tdma_reg definition
4533  *  offset: 0x5c00
4534  */
4535 #define BNX2_TDMA_COMMAND                               0x00005c00
4536 #define BNX2_TDMA_COMMAND_ENABLED                        (1L<<0)
4537 #define BNX2_TDMA_COMMAND_MASTER_ABORT                   (1L<<4)
4538 #define BNX2_TDMA_COMMAND_CS16_ERR                       (1L<<5)
4539 #define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT            (1L<<7)
4540 #define BNX2_TDMA_COMMAND_MASK_CS1                       (1L<<20)
4541 #define BNX2_TDMA_COMMAND_MASK_CS2                       (1L<<21)
4542 #define BNX2_TDMA_COMMAND_MASK_CS3                       (1L<<22)
4543 #define BNX2_TDMA_COMMAND_MASK_CS4                       (1L<<23)
4544 #define BNX2_TDMA_COMMAND_FORCE_ILOCK_CKERR              (1L<<24)
4545 #define BNX2_TDMA_COMMAND_OFIFO_CLR                      (1L<<30)
4546 #define BNX2_TDMA_COMMAND_IFIFO_CLR                      (1L<<31)
4547
4548 #define BNX2_TDMA_STATUS                                0x00005c04
4549 #define BNX2_TDMA_STATUS_DMA_WAIT                        (1L<<0)
4550 #define BNX2_TDMA_STATUS_PAYLOAD_WAIT                    (1L<<1)
4551 #define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT                  (1L<<2)
4552 #define BNX2_TDMA_STATUS_LOCK_WAIT                       (1L<<3)
4553 #define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT                   (1L<<16)
4554 #define BNX2_TDMA_STATUS_BURST_CNT                       (1L<<17)
4555 #define BNX2_TDMA_STATUS_MAX_IFIFO_DEPTH                 (0x3fL<<20)
4556 #define BNX2_TDMA_STATUS_OFIFO_OVERFLOW                  (1L<<30)
4557 #define BNX2_TDMA_STATUS_IFIFO_OVERFLOW                  (1L<<31)
4558
4559 #define BNX2_TDMA_CONFIG                                0x00005c08
4560 #define BNX2_TDMA_CONFIG_ONE_DMA                         (1L<<0)
4561 #define BNX2_TDMA_CONFIG_ONE_RECORD                      (1L<<1)
4562 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN                    (0x3L<<2)
4563 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_0                  (0L<<2)
4564 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_1                  (1L<<2)
4565 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_2                  (2L<<2)
4566 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_3                  (3L<<2)
4567 #define BNX2_TDMA_CONFIG_LIMIT_SZ                        (0xfL<<4)
4568 #define BNX2_TDMA_CONFIG_LIMIT_SZ_64                     (0L<<4)
4569 #define BNX2_TDMA_CONFIG_LIMIT_SZ_128                    (0x4L<<4)
4570 #define BNX2_TDMA_CONFIG_LIMIT_SZ_256                    (0x6L<<4)
4571 #define BNX2_TDMA_CONFIG_LIMIT_SZ_512                    (0x8L<<4)
4572 #define BNX2_TDMA_CONFIG_LINE_SZ                         (0xfL<<8)
4573 #define BNX2_TDMA_CONFIG_LINE_SZ_64                      (0L<<8)
4574 #define BNX2_TDMA_CONFIG_LINE_SZ_128                     (4L<<8)
4575 #define BNX2_TDMA_CONFIG_LINE_SZ_256                     (6L<<8)
4576 #define BNX2_TDMA_CONFIG_LINE_SZ_512                     (8L<<8)
4577 #define BNX2_TDMA_CONFIG_ALIGN_ENA                       (1L<<15)
4578 #define BNX2_TDMA_CONFIG_CHK_L2_BD                       (1L<<16)
4579 #define BNX2_TDMA_CONFIG_CMPL_ENTRY                      (1L<<17)
4580 #define BNX2_TDMA_CONFIG_OFIFO_CMP                       (1L<<19)
4581 #define BNX2_TDMA_CONFIG_OFIFO_CMP_3                     (0L<<19)
4582 #define BNX2_TDMA_CONFIG_OFIFO_CMP_2                     (1L<<19)
4583 #define BNX2_TDMA_CONFIG_FIFO_CMP                        (0xfL<<20)
4584 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_XI                  (0x7L<<20)
4585 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_0_XI                (0L<<20)
4586 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_4_XI                (1L<<20)
4587 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_8_XI                (2L<<20)
4588 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_16_XI               (3L<<20)
4589 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_32_XI               (4L<<20)
4590 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_64_XI               (5L<<20)
4591 #define BNX2_TDMA_CONFIG_FIFO_CMP_EN_XI                  (1L<<23)
4592 #define BNX2_TDMA_CONFIG_BYTES_OST_XI                    (0x7L<<24)
4593 #define BNX2_TDMA_CONFIG_BYTES_OST_512_XI                (0L<<24)
4594 #define BNX2_TDMA_CONFIG_BYTES_OST_1024_XI               (1L<<24)
4595 #define BNX2_TDMA_CONFIG_BYTES_OST_2048_XI               (2L<<24)
4596 #define BNX2_TDMA_CONFIG_BYTES_OST_4096_XI               (3L<<24)
4597 #define BNX2_TDMA_CONFIG_BYTES_OST_8192_XI               (4L<<24)
4598 #define BNX2_TDMA_CONFIG_BYTES_OST_16384_XI              (5L<<24)
4599 #define BNX2_TDMA_CONFIG_HC_BYPASS_XI                    (1L<<27)
4600 #define BNX2_TDMA_CONFIG_LCL_MRRS_XI                     (0x7L<<28)
4601 #define BNX2_TDMA_CONFIG_LCL_MRRS_128_XI                 (0L<<28)
4602 #define BNX2_TDMA_CONFIG_LCL_MRRS_256_XI                 (1L<<28)
4603 #define BNX2_TDMA_CONFIG_LCL_MRRS_512_XI                 (2L<<28)
4604 #define BNX2_TDMA_CONFIG_LCL_MRRS_1024_XI                (3L<<28)
4605 #define BNX2_TDMA_CONFIG_LCL_MRRS_2048_XI                (4L<<28)
4606 #define BNX2_TDMA_CONFIG_LCL_MRRS_4096_XI                (5L<<28)
4607 #define BNX2_TDMA_CONFIG_LCL_MRRS_EN_XI                  (1L<<31)
4608
4609 #define BNX2_TDMA_PAYLOAD_PROD                          0x00005c0c
4610 #define BNX2_TDMA_PAYLOAD_PROD_VALUE                     (0x1fffL<<3)
4611
4612 #define BNX2_TDMA_DBG_WATCHDOG                          0x00005c10
4613 #define BNX2_TDMA_DBG_TRIGGER                           0x00005c14
4614 #define BNX2_TDMA_DMAD_FSM                              0x00005c80
4615 #define BNX2_TDMA_DMAD_FSM_BD_INVLD                      (1L<<0)
4616 #define BNX2_TDMA_DMAD_FSM_PUSH                          (0xfL<<4)
4617 #define BNX2_TDMA_DMAD_FSM_ARB_TBDC                      (0x3L<<8)
4618 #define BNX2_TDMA_DMAD_FSM_ARB_CTX                       (1L<<12)
4619 #define BNX2_TDMA_DMAD_FSM_DR_INTF                       (1L<<16)
4620 #define BNX2_TDMA_DMAD_FSM_DMAD                          (0x7L<<20)
4621 #define BNX2_TDMA_DMAD_FSM_BD                            (0xfL<<24)
4622
4623 #define BNX2_TDMA_DMAD_STATUS                           0x00005c84
4624 #define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY           (0x3L<<0)
4625 #define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY           (0x3L<<4)
4626 #define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY             (0x3L<<8)
4627 #define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM                  (0xfL<<12)
4628
4629 #define BNX2_TDMA_DR_INTF_FSM                           0x00005c88
4630 #define BNX2_TDMA_DR_INTF_FSM_L2_COMP                    (0x3L<<0)
4631 #define BNX2_TDMA_DR_INTF_FSM_TPATQ                      (0x7L<<4)
4632 #define BNX2_TDMA_DR_INTF_FSM_TPBUF                      (0x3L<<8)
4633 #define BNX2_TDMA_DR_INTF_FSM_DR_BUF                     (0x7L<<12)
4634 #define BNX2_TDMA_DR_INTF_FSM_DMAD                       (0x7L<<16)
4635
4636 #define BNX2_TDMA_DR_INTF_STATUS                        0x00005c8c
4637 #define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE              (0x7L<<0)
4638 #define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL              (0x3L<<4)
4639 #define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR              (0x7L<<8)
4640 #define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR                (0xfL<<12)
4641 #define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT              (0x7L<<16)
4642
4643 #define BNX2_TDMA_PUSH_FSM                              0x00005c90
4644 #define BNX2_TDMA_BD_IF_DEBUG                           0x00005c94
4645 #define BNX2_TDMA_DMAD_IF_DEBUG                         0x00005c98
4646 #define BNX2_TDMA_CTX_IF_DEBUG                          0x00005c9c
4647 #define BNX2_TDMA_TPBUF_IF_DEBUG                        0x00005ca0
4648 #define BNX2_TDMA_DR_IF_DEBUG                           0x00005ca4
4649 #define BNX2_TDMA_TPATQ_IF_DEBUG                        0x00005ca8
4650 #define BNX2_TDMA_TDMA_ILOCK_CKSUM                      0x00005cac
4651 #define BNX2_TDMA_TDMA_ILOCK_CKSUM_CALCULATED            (0xffffL<<0)
4652 #define BNX2_TDMA_TDMA_ILOCK_CKSUM_EXPECTED              (0xffffL<<16)
4653
4654 #define BNX2_TDMA_TDMA_PCIE_CKSUM                       0x00005cb0
4655 #define BNX2_TDMA_TDMA_PCIE_CKSUM_CALCULATED             (0xffffL<<0)
4656 #define BNX2_TDMA_TDMA_PCIE_CKSUM_EXPECTED               (0xffffL<<16)
4657
4658 #define BNX2_TDMA_TDMAQ                                 0x00005fc0
4659 #define BNX2_TDMA_FTQ_CMD                               0x00005ff8
4660 #define BNX2_TDMA_FTQ_CMD_OFFSET                         (0x3ffL<<0)
4661 #define BNX2_TDMA_FTQ_CMD_WR_TOP                         (1L<<10)
4662 #define BNX2_TDMA_FTQ_CMD_WR_TOP_0                       (0L<<10)
4663 #define BNX2_TDMA_FTQ_CMD_WR_TOP_1                       (1L<<10)
4664 #define BNX2_TDMA_FTQ_CMD_SFT_RESET                      (1L<<25)
4665 #define BNX2_TDMA_FTQ_CMD_RD_DATA                        (1L<<26)
4666 #define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN                   (1L<<27)
4667 #define BNX2_TDMA_FTQ_CMD_ADD_DATA                       (1L<<28)
4668 #define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR                  (1L<<29)
4669 #define BNX2_TDMA_FTQ_CMD_POP                            (1L<<30)
4670 #define BNX2_TDMA_FTQ_CMD_BUSY                           (1L<<31)
4671
4672 #define BNX2_TDMA_FTQ_CTL                               0x00005ffc
4673 #define BNX2_TDMA_FTQ_CTL_INTERVENE                      (1L<<0)
4674 #define BNX2_TDMA_FTQ_CTL_OVERFLOW                       (1L<<1)
4675 #define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE                (1L<<2)
4676 #define BNX2_TDMA_FTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
4677 #define BNX2_TDMA_FTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
4678
4679
4680
4681 /*
4682  *  hc_reg definition
4683  *  offset: 0x6800
4684  */
4685 #define BNX2_HC_COMMAND                                 0x00006800
4686 #define BNX2_HC_COMMAND_ENABLE                           (1L<<0)
4687 #define BNX2_HC_COMMAND_SKIP_ABORT                       (1L<<4)
4688 #define BNX2_HC_COMMAND_COAL_NOW                         (1L<<16)
4689 #define BNX2_HC_COMMAND_COAL_NOW_WO_INT                  (1L<<17)
4690 #define BNX2_HC_COMMAND_STATS_NOW                        (1L<<18)
4691 #define BNX2_HC_COMMAND_FORCE_INT                        (0x3L<<19)
4692 #define BNX2_HC_COMMAND_FORCE_INT_NULL                   (0L<<19)
4693 #define BNX2_HC_COMMAND_FORCE_INT_HIGH                   (1L<<19)
4694 #define BNX2_HC_COMMAND_FORCE_INT_LOW                    (2L<<19)
4695 #define BNX2_HC_COMMAND_FORCE_INT_FREE                   (3L<<19)
4696 #define BNX2_HC_COMMAND_CLR_STAT_NOW                     (1L<<21)
4697 #define BNX2_HC_COMMAND_MAIN_PWR_INT                     (1L<<22)
4698 #define BNX2_HC_COMMAND_COAL_ON_NEXT_EVENT               (1L<<27)
4699
4700 #define BNX2_HC_STATUS                                  0x00006804
4701 #define BNX2_HC_STATUS_MASTER_ABORT                      (1L<<0)
4702 #define BNX2_HC_STATUS_PARITY_ERROR_STATE                (1L<<1)
4703 #define BNX2_HC_STATUS_PCI_CLK_CNT_STAT                  (1L<<16)
4704 #define BNX2_HC_STATUS_CORE_CLK_CNT_STAT                 (1L<<17)
4705 #define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT            (1L<<18)
4706 #define BNX2_HC_STATUS_NUM_INT_GEN_STAT                  (1L<<19)
4707 #define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT              (1L<<20)
4708 #define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT       (1L<<23)
4709 #define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT       (1L<<24)
4710 #define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT   (1L<<25)
4711
4712 #define BNX2_HC_CONFIG                                  0x00006808
4713 #define BNX2_HC_CONFIG_COLLECT_STATS                     (1L<<0)
4714 #define BNX2_HC_CONFIG_RX_TMR_MODE                       (1L<<1)
4715 #define BNX2_HC_CONFIG_TX_TMR_MODE                       (1L<<2)
4716 #define BNX2_HC_CONFIG_COM_TMR_MODE                      (1L<<3)
4717 #define BNX2_HC_CONFIG_CMD_TMR_MODE                      (1L<<4)
4718 #define BNX2_HC_CONFIG_STATISTIC_PRIORITY                (1L<<5)
4719 #define BNX2_HC_CONFIG_STATUS_PRIORITY                   (1L<<6)
4720 #define BNX2_HC_CONFIG_STAT_MEM_ADDR                     (0xffL<<8)
4721 #define BNX2_HC_CONFIG_PER_MODE                          (1L<<16)
4722 #define BNX2_HC_CONFIG_ONE_SHOT                          (1L<<17)
4723 #define BNX2_HC_CONFIG_USE_INT_PARAM                     (1L<<18)
4724 #define BNX2_HC_CONFIG_SET_MASK_AT_RD                    (1L<<19)
4725 #define BNX2_HC_CONFIG_PER_COLLECT_LIMIT                 (0xfL<<20)
4726 #define BNX2_HC_CONFIG_SB_ADDR_INC                       (0x7L<<24)
4727 #define BNX2_HC_CONFIG_SB_ADDR_INC_64B                   (0L<<24)
4728 #define BNX2_HC_CONFIG_SB_ADDR_INC_128B                  (1L<<24)
4729 #define BNX2_HC_CONFIG_SB_ADDR_INC_256B                  (2L<<24)
4730 #define BNX2_HC_CONFIG_SB_ADDR_INC_512B                  (3L<<24)
4731 #define BNX2_HC_CONFIG_SB_ADDR_INC_1024B                 (4L<<24)
4732 #define BNX2_HC_CONFIG_SB_ADDR_INC_2048B                 (5L<<24)
4733 #define BNX2_HC_CONFIG_SB_ADDR_INC_4096B                 (6L<<24)
4734 #define BNX2_HC_CONFIG_SB_ADDR_INC_8192B                 (7L<<24)
4735 #define BNX2_HC_CONFIG_GEN_STAT_AVG_INTR                 (1L<<29)
4736 #define BNX2_HC_CONFIG_UNMASK_ALL                        (1L<<30)
4737 #define BNX2_HC_CONFIG_TX_SEL                            (1L<<31)
4738
4739 #define BNX2_HC_ATTN_BITS_ENABLE                        0x0000680c
4740 #define BNX2_HC_STATUS_ADDR_L                           0x00006810
4741 #define BNX2_HC_STATUS_ADDR_H                           0x00006814
4742 #define BNX2_HC_STATISTICS_ADDR_L                       0x00006818
4743 #define BNX2_HC_STATISTICS_ADDR_H                       0x0000681c
4744 #define BNX2_HC_TX_QUICK_CONS_TRIP                      0x00006820
4745 #define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE                 (0xffL<<0)
4746 #define BNX2_HC_TX_QUICK_CONS_TRIP_INT                   (0xffL<<16)
4747
4748 #define BNX2_HC_COMP_PROD_TRIP                          0x00006824
4749 #define BNX2_HC_COMP_PROD_TRIP_VALUE                     (0xffL<<0)
4750 #define BNX2_HC_COMP_PROD_TRIP_INT                       (0xffL<<16)
4751
4752 #define BNX2_HC_RX_QUICK_CONS_TRIP                      0x00006828
4753 #define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE                 (0xffL<<0)
4754 #define BNX2_HC_RX_QUICK_CONS_TRIP_INT                   (0xffL<<16)
4755
4756 #define BNX2_HC_RX_TICKS                                0x0000682c
4757 #define BNX2_HC_RX_TICKS_VALUE                           (0x3ffL<<0)
4758 #define BNX2_HC_RX_TICKS_INT                             (0x3ffL<<16)
4759
4760 #define BNX2_HC_TX_TICKS                                0x00006830
4761 #define BNX2_HC_TX_TICKS_VALUE                           (0x3ffL<<0)
4762 #define BNX2_HC_TX_TICKS_INT                             (0x3ffL<<16)
4763
4764 #define BNX2_HC_COM_TICKS                               0x00006834
4765 #define BNX2_HC_COM_TICKS_VALUE                          (0x3ffL<<0)
4766 #define BNX2_HC_COM_TICKS_INT                            (0x3ffL<<16)
4767
4768 #define BNX2_HC_CMD_TICKS                               0x00006838
4769 #define BNX2_HC_CMD_TICKS_VALUE                          (0x3ffL<<0)
4770 #define BNX2_HC_CMD_TICKS_INT                            (0x3ffL<<16)
4771
4772 #define BNX2_HC_PERIODIC_TICKS                          0x0000683c
4773 #define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS         (0xffffL<<0)
4774 #define BNX2_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS     (0xffffL<<16)
4775
4776 #define BNX2_HC_STAT_COLLECT_TICKS                      0x00006840
4777 #define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS    (0xffL<<4)
4778
4779 #define BNX2_HC_STATS_TICKS                             0x00006844
4780 #define BNX2_HC_STATS_TICKS_HC_STAT_TICKS                (0xffffL<<8)
4781
4782 #define BNX2_HC_STATS_INTERRUPT_STATUS                  0x00006848
4783 #define BNX2_HC_STATS_INTERRUPT_STATUS_SB_STATUS         (0x1ffL<<0)
4784 #define BNX2_HC_STATS_INTERRUPT_STATUS_INT_STATUS        (0x1ffL<<16)
4785
4786 #define BNX2_HC_STAT_MEM_DATA                           0x0000684c
4787 #define BNX2_HC_STAT_GEN_SEL_0                          0x00006850
4788 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0                 (0x7fL<<0)
4789 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0       (0L<<0)
4790 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1       (1L<<0)
4791 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2       (2L<<0)
4792 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3       (3L<<0)
4793 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4       (4L<<0)
4794 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5       (5L<<0)
4795 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6       (6L<<0)
4796 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7       (7L<<0)
4797 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8       (8L<<0)
4798 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9       (9L<<0)
4799 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10      (10L<<0)
4800 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11      (11L<<0)
4801 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0       (12L<<0)
4802 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1       (13L<<0)
4803 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2       (14L<<0)
4804 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3       (15L<<0)
4805 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4       (16L<<0)
4806 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5       (17L<<0)
4807 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6       (18L<<0)
4808 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7       (19L<<0)
4809 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0       (20L<<0)
4810 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1       (21L<<0)
4811 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2       (22L<<0)
4812 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3       (23L<<0)
4813 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4       (24L<<0)
4814 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5       (25L<<0)
4815 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6       (26L<<0)
4816 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7       (27L<<0)
4817 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8       (28L<<0)
4818 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9       (29L<<0)
4819 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10      (30L<<0)
4820 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11      (31L<<0)
4821 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0      (32L<<0)
4822 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1      (33L<<0)
4823 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2      (34L<<0)
4824 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3      (35L<<0)
4825 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0        (36L<<0)
4826 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1        (37L<<0)
4827 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2        (38L<<0)
4828 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3        (39L<<0)
4829 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4        (40L<<0)
4830 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5        (41L<<0)
4831 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6        (42L<<0)
4832 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7        (43L<<0)
4833 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0       (44L<<0)
4834 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1       (45L<<0)
4835 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2       (46L<<0)
4836 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3       (47L<<0)
4837 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4       (48L<<0)
4838 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5       (49L<<0)
4839 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6       (50L<<0)
4840 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7       (51L<<0)
4841 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT     (52L<<0)
4842 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT    (53L<<0)
4843 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS    (54L<<0)
4844 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN  (55L<<0)
4845 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR      (56L<<0)
4846 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK       (59L<<0)
4847 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK       (60L<<0)
4848 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK   (61L<<0)
4849 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT    (62L<<0)
4850 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT   (63L<<0)
4851 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT    (64L<<0)
4852 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT   (65L<<0)
4853 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT         (66L<<0)
4854 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT  (67L<<0)
4855 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT         (68L<<0)
4856 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT        (69L<<0)
4857 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT        (70L<<0)
4858 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT        (71L<<0)
4859 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT         (72L<<0)
4860 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT         (73L<<0)
4861 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT         (74L<<0)
4862 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT  (75L<<0)
4863 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT         (76L<<0)
4864 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT         (77L<<0)
4865 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT  (78L<<0)
4866 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT   (79L<<0)
4867 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT   (80L<<0)
4868 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT         (81L<<0)
4869 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT         (82L<<0)
4870 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT  (83L<<0)
4871 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT  (84L<<0)
4872 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT         (85L<<0)
4873 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT    (86L<<0)
4874 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT     (87L<<0)
4875 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT        (88L<<0)
4876 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT      (89L<<0)
4877 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT        (90L<<0)
4878 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT   (91L<<0)
4879 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT    (92L<<0)
4880 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT       (93L<<0)
4881 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT     (94L<<0)
4882 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64    (95L<<0)
4883 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64    (96L<<0)
4884 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS      (97L<<0)
4885 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS     (98L<<0)
4886 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT     (99L<<0)
4887 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT   (100L<<0)
4888 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT      (101L<<0)
4889 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT      (102L<<0)
4890 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT  (103L<<0)
4891 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT      (104L<<0)
4892 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT  (105L<<0)
4893 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT      (106L<<0)
4894 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT  (107L<<0)
4895 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT  (108L<<0)
4896 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT       (109L<<0)
4897 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT    (110L<<0)
4898 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT    (111L<<0)
4899 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT    (112L<<0)
4900 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT    (113L<<0)
4901 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT    (114L<<0)
4902 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0      (115L<<0)
4903 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1      (116L<<0)
4904 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2      (117L<<0)
4905 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3      (118L<<0)
4906 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4      (119L<<0)
4907 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5      (120L<<0)
4908 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS         (121L<<0)
4909 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS         (122L<<0)
4910 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT  (127L<<0)
4911 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1                 (0x7fL<<8)
4912 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2                 (0x7fL<<16)
4913 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3                 (0x7fL<<24)
4914 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI              (0xffL<<0)
4915 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI    (52L<<0)
4916 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI    (57L<<0)
4917 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI    (58L<<0)
4918 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI    (85L<<0)
4919 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI    (86L<<0)
4920 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI    (87L<<0)
4921 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI    (88L<<0)
4922 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI    (89L<<0)
4923 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI    (90L<<0)
4924 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI    (91L<<0)
4925 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI    (92L<<0)
4926 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI   (93L<<0)
4927 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI         (94L<<0)
4928 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI       (123L<<0)
4929 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI       (124L<<0)
4930 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI     (125L<<0)
4931 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI   (126L<<0)
4932 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI    (128L<<0)
4933 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI  (129L<<0)
4934 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI      (130L<<0)
4935 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI       (131L<<0)
4936 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI       (132L<<0)
4937 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI   (133L<<0)
4938 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI    (134L<<0)
4939 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI  (135L<<0)
4940 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI      (136L<<0)
4941 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI       (137L<<0)
4942 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI       (138L<<0)
4943 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI   (139L<<0)
4944 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI    (140L<<0)
4945 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI  (141L<<0)
4946 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI      (142L<<0)
4947 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI       (143L<<0)
4948 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI       (144L<<0)
4949 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI   (145L<<0)
4950 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI    (146L<<0)
4951 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI  (147L<<0)
4952 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI      (148L<<0)
4953 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI       (149L<<0)
4954 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI       (150L<<0)
4955 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI   (151L<<0)
4956 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI    (152L<<0)
4957 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI  (153L<<0)
4958 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI      (154L<<0)
4959 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI       (155L<<0)
4960 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI       (156L<<0)
4961 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI   (157L<<0)
4962 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI    (158L<<0)
4963 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI  (159L<<0)
4964 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI      (160L<<0)
4965 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI       (161L<<0)
4966 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI       (162L<<0)
4967 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI   (163L<<0)
4968 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI    (164L<<0)
4969 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI  (165L<<0)
4970 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI      (166L<<0)
4971 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI       (167L<<0)
4972 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI       (168L<<0)
4973 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI   (169L<<0)
4974 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI    (170L<<0)
4975 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI  (171L<<0)
4976 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI      (172L<<0)
4977 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI       (173L<<0)
4978 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI       (174L<<0)
4979 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI   (175L<<0)
4980 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI       (176L<<0)
4981 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI      (177L<<0)
4982 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI    (178L<<0)
4983 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI              (0xffL<<8)
4984 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI              (0xffL<<16)
4985 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI              (0xffL<<24)
4986
4987 #define BNX2_HC_STAT_GEN_SEL_1                          0x00006854
4988 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4                 (0x7fL<<0)
4989 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5                 (0x7fL<<8)
4990 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6                 (0x7fL<<16)
4991 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7                 (0x7fL<<24)
4992 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI              (0xffL<<0)
4993 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI              (0xffL<<8)
4994 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI              (0xffL<<16)
4995 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI              (0xffL<<24)
4996
4997 #define BNX2_HC_STAT_GEN_SEL_2                          0x00006858
4998 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8                 (0x7fL<<0)
4999 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9                 (0x7fL<<8)
5000 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10                (0x7fL<<16)
5001 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11                (0x7fL<<24)
5002 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI              (0xffL<<0)
5003 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI              (0xffL<<8)
5004 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI             (0xffL<<16)
5005 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI             (0xffL<<24)
5006
5007 #define BNX2_HC_STAT_GEN_SEL_3                          0x0000685c
5008 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12                (0x7fL<<0)
5009 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13                (0x7fL<<8)
5010 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14                (0x7fL<<16)
5011 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15                (0x7fL<<24)
5012 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI             (0xffL<<0)
5013 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI             (0xffL<<8)
5014 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI             (0xffL<<16)
5015 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI             (0xffL<<24)
5016
5017 #define BNX2_HC_STAT_GEN_STAT0                          0x00006888
5018 #define BNX2_HC_STAT_GEN_STAT1                          0x0000688c
5019 #define BNX2_HC_STAT_GEN_STAT2                          0x00006890
5020 #define BNX2_HC_STAT_GEN_STAT3                          0x00006894
5021 #define BNX2_HC_STAT_GEN_STAT4                          0x00006898
5022 #define BNX2_HC_STAT_GEN_STAT5                          0x0000689c
5023 #define BNX2_HC_STAT_GEN_STAT6                          0x000068a0
5024 #define BNX2_HC_STAT_GEN_STAT7                          0x000068a4
5025 #define BNX2_HC_STAT_GEN_STAT8                          0x000068a8
5026 #define BNX2_HC_STAT_GEN_STAT9                          0x000068ac
5027 #define BNX2_HC_STAT_GEN_STAT10                         0x000068b0
5028 #define BNX2_HC_STAT_GEN_STAT11                         0x000068b4
5029 #define BNX2_HC_STAT_GEN_STAT12                         0x000068b8
5030 #define BNX2_HC_STAT_GEN_STAT13                         0x000068bc
5031 #define BNX2_HC_STAT_GEN_STAT14                         0x000068c0
5032 #define BNX2_HC_STAT_GEN_STAT15                         0x000068c4
5033 #define BNX2_HC_STAT_GEN_STAT_AC0                       0x000068c8
5034 #define BNX2_HC_STAT_GEN_STAT_AC1                       0x000068cc
5035 #define BNX2_HC_STAT_GEN_STAT_AC2                       0x000068d0
5036 #define BNX2_HC_STAT_GEN_STAT_AC3                       0x000068d4
5037 #define BNX2_HC_STAT_GEN_STAT_AC4                       0x000068d8
5038 #define BNX2_HC_STAT_GEN_STAT_AC5                       0x000068dc
5039 #define BNX2_HC_STAT_GEN_STAT_AC6                       0x000068e0
5040 #define BNX2_HC_STAT_GEN_STAT_AC7                       0x000068e4
5041 #define BNX2_HC_STAT_GEN_STAT_AC8                       0x000068e8
5042 #define BNX2_HC_STAT_GEN_STAT_AC9                       0x000068ec
5043 #define BNX2_HC_STAT_GEN_STAT_AC10                      0x000068f0
5044 #define BNX2_HC_STAT_GEN_STAT_AC11                      0x000068f4
5045 #define BNX2_HC_STAT_GEN_STAT_AC12                      0x000068f8
5046 #define BNX2_HC_STAT_GEN_STAT_AC13                      0x000068fc
5047 #define BNX2_HC_STAT_GEN_STAT_AC14                      0x00006900
5048 #define BNX2_HC_STAT_GEN_STAT_AC15                      0x00006904
5049 #define BNX2_HC_STAT_GEN_STAT_AC                        0x000068c8
5050 #define BNX2_HC_VIS                                     0x00006908
5051 #define BNX2_HC_VIS_STAT_BUILD_STATE                     (0xfL<<0)
5052 #define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE                (0L<<0)
5053 #define BNX2_HC_VIS_STAT_BUILD_STATE_START               (1L<<0)
5054 #define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST             (2L<<0)
5055 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64            (3L<<0)
5056 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32            (4L<<0)
5057 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE         (5L<<0)
5058 #define BNX2_HC_VIS_STAT_BUILD_STATE_DMA                 (6L<<0)
5059 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL         (7L<<0)
5060 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW             (8L<<0)
5061 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH            (9L<<0)
5062 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA            (10L<<0)
5063 #define BNX2_HC_VIS_DMA_STAT_STATE                       (0xfL<<8)
5064 #define BNX2_HC_VIS_DMA_STAT_STATE_IDLE                  (0L<<8)
5065 #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM          (1L<<8)
5066 #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA            (2L<<8)
5067 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP            (3L<<8)
5068 #define BNX2_HC_VIS_DMA_STAT_STATE_COMP                  (4L<<8)
5069 #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM       (5L<<8)
5070 #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA         (6L<<8)
5071 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1          (7L<<8)
5072 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2          (8L<<8)
5073 #define BNX2_HC_VIS_DMA_STAT_STATE_WAIT                  (9L<<8)
5074 #define BNX2_HC_VIS_DMA_STAT_STATE_ABORT                 (15L<<8)
5075 #define BNX2_HC_VIS_DMA_MSI_STATE                        (0x7L<<12)
5076 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE               (0x3L<<15)
5077 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE          (0L<<15)
5078 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT         (1L<<15)
5079 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START         (2L<<15)
5080
5081 #define BNX2_HC_VIS_1                                   0x0000690c
5082 #define BNX2_HC_VIS_1_HW_INTACK_STATE                    (1L<<4)
5083 #define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE               (0L<<4)
5084 #define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT              (1L<<4)
5085 #define BNX2_HC_VIS_1_SW_INTACK_STATE                    (1L<<5)
5086 #define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE               (0L<<5)
5087 #define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT              (1L<<5)
5088 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE             (1L<<6)
5089 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE        (0L<<6)
5090 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT       (1L<<6)
5091 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE                (1L<<7)
5092 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE           (0L<<7)
5093 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT          (1L<<7)
5094 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE                   (0xfL<<17)
5095 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE              (0L<<17)
5096 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA               (1L<<17)
5097 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE            (2L<<17)
5098 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN            (3L<<17)
5099 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT              (4L<<17)
5100 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE        (5L<<17)
5101 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN        (6L<<17)
5102 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT          (7L<<17)
5103 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE                   (0x3L<<21)
5104 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL            (0L<<21)
5105 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR             (1L<<21)
5106 #define BNX2_HC_VIS_1_INT_GEN_STATE                      (1L<<23)
5107 #define BNX2_HC_VIS_1_INT_GEN_STATE_DLE                  (0L<<23)
5108 #define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT             (1L<<23)
5109 #define BNX2_HC_VIS_1_STAT_CHAN_ID                       (0x7L<<24)
5110 #define BNX2_HC_VIS_1_INT_B                              (1L<<27)
5111
5112 #define BNX2_HC_DEBUG_VECT_PEEK                         0x00006910
5113 #define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE                  (0x7ffL<<0)
5114 #define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN                (1L<<11)
5115 #define BNX2_HC_DEBUG_VECT_PEEK_1_SEL                    (0xfL<<12)
5116 #define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE                  (0x7ffL<<16)
5117 #define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN                (1L<<27)
5118 #define BNX2_HC_DEBUG_VECT_PEEK_2_SEL                    (0xfL<<28)
5119
5120 #define BNX2_HC_COALESCE_NOW                            0x00006914
5121 #define BNX2_HC_COALESCE_NOW_COAL_NOW                    (0x1ffL<<1)
5122 #define BNX2_HC_COALESCE_NOW_COAL_NOW_WO_INT             (0x1ffL<<11)
5123 #define BNX2_HC_COALESCE_NOW_COAL_ON_NXT_EVENT           (0x1ffL<<21)
5124
5125 #define BNX2_HC_MSIX_BIT_VECTOR                         0x00006918
5126 #define BNX2_HC_MSIX_BIT_VECTOR_VAL                      (0x1ffL<<0)
5127
5128 #define BNX2_HC_SB_CONFIG_1                             0x00006a00
5129 #define BNX2_HC_SB_CONFIG_1_RX_TMR_MODE                  (1L<<1)
5130 #define BNX2_HC_SB_CONFIG_1_TX_TMR_MODE                  (1L<<2)
5131 #define BNX2_HC_SB_CONFIG_1_COM_TMR_MODE                 (1L<<3)
5132 #define BNX2_HC_SB_CONFIG_1_CMD_TMR_MODE                 (1L<<4)
5133 #define BNX2_HC_SB_CONFIG_1_PER_MODE                     (1L<<16)
5134 #define BNX2_HC_SB_CONFIG_1_ONE_SHOT                     (1L<<17)
5135 #define BNX2_HC_SB_CONFIG_1_USE_INT_PARAM                (1L<<18)
5136 #define BNX2_HC_SB_CONFIG_1_PER_COLLECT_LIMIT            (0xfL<<20)
5137
5138 #define BNX2_HC_TX_QUICK_CONS_TRIP_1                    0x00006a04
5139 #define BNX2_HC_TX_QUICK_CONS_TRIP_1_VALUE               (0xffL<<0)
5140 #define BNX2_HC_TX_QUICK_CONS_TRIP_1_INT                 (0xffL<<16)
5141
5142 #define BNX2_HC_COMP_PROD_TRIP_1                        0x00006a08
5143 #define BNX2_HC_COMP_PROD_TRIP_1_VALUE                   (0xffL<<0)
5144 #define BNX2_HC_COMP_PROD_TRIP_1_INT                     (0xffL<<16)
5145
5146 #define BNX2_HC_RX_QUICK_CONS_TRIP_1                    0x00006a0c
5147 #define BNX2_HC_RX_QUICK_CONS_TRIP_1_VALUE               (0xffL<<0)
5148 #define BNX2_HC_RX_QUICK_CONS_TRIP_1_INT                 (0xffL<<16)
5149
5150 #define BNX2_HC_RX_TICKS_1                              0x00006a10
5151 #define BNX2_HC_RX_TICKS_1_VALUE                         (0x3ffL<<0)
5152 #define BNX2_HC_RX_TICKS_1_INT                           (0x3ffL<<16)
5153
5154 #define BNX2_HC_TX_TICKS_1                              0x00006a14
5155 #define BNX2_HC_TX_TICKS_1_VALUE                         (0x3ffL<<0)
5156 #define BNX2_HC_TX_TICKS_1_INT                           (0x3ffL<<16)
5157
5158 #define BNX2_HC_COM_TICKS_1                             0x00006a18
5159 #define BNX2_HC_COM_TICKS_1_VALUE                        (0x3ffL<<0)
5160 #define BNX2_HC_COM_TICKS_1_INT                          (0x3ffL<<16)
5161
5162 #define BNX2_HC_CMD_TICKS_1                             0x00006a1c
5163 #define BNX2_HC_CMD_TICKS_1_VALUE                        (0x3ffL<<0)
5164 #define BNX2_HC_CMD_TICKS_1_INT                          (0x3ffL<<16)
5165
5166 #define BNX2_HC_PERIODIC_TICKS_1                        0x00006a20
5167 #define BNX2_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS       (0xffffL<<0)
5168 #define BNX2_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
5169
5170 #define BNX2_HC_SB_CONFIG_2                             0x00006a24
5171 #define BNX2_HC_SB_CONFIG_2_RX_TMR_MODE                  (1L<<1)
5172 #define BNX2_HC_SB_CONFIG_2_TX_TMR_MODE                  (1L<<2)
5173 #define BNX2_HC_SB_CONFIG_2_COM_TMR_MODE                 (1L<<3)
5174 #define BNX2_HC_SB_CONFIG_2_CMD_TMR_MODE                 (1L<<4)
5175 #define BNX2_HC_SB_CONFIG_2_PER_MODE                     (1L<<16)
5176 #define BNX2_HC_SB_CONFIG_2_ONE_SHOT                     (1L<<17)
5177 #define BNX2_HC_SB_CONFIG_2_USE_INT_PARAM                (1L<<18)
5178 #define BNX2_HC_SB_CONFIG_2_PER_COLLECT_LIMIT            (0xfL<<20)
5179
5180 #define BNX2_HC_TX_QUICK_CONS_TRIP_2                    0x00006a28
5181 #define BNX2_HC_TX_QUICK_CONS_TRIP_2_VALUE               (0xffL<<0)
5182 #define BNX2_HC_TX_QUICK_CONS_TRIP_2_INT                 (0xffL<<16)
5183
5184 #define BNX2_HC_COMP_PROD_TRIP_2                        0x00006a2c
5185 #define BNX2_HC_COMP_PROD_TRIP_2_VALUE                   (0xffL<<0)
5186 #define BNX2_HC_COMP_PROD_TRIP_2_INT                     (0xffL<<16)
5187
5188 #define BNX2_HC_RX_QUICK_CONS_TRIP_2                    0x00006a30
5189 #define BNX2_HC_RX_QUICK_CONS_TRIP_2_VALUE               (0xffL<<0)
5190 #define BNX2_HC_RX_QUICK_CONS_TRIP_2_INT                 (0xffL<<16)
5191
5192 #define BNX2_HC_RX_TICKS_2                              0x00006a34
5193 #define BNX2_HC_RX_TICKS_2_VALUE                         (0x3ffL<<0)
5194 #define BNX2_HC_RX_TICKS_2_INT                           (0x3ffL<<16)
5195
5196 #define BNX2_HC_TX_TICKS_2                              0x00006a38
5197 #define BNX2_HC_TX_TICKS_2_VALUE                         (0x3ffL<<0)
5198 #define BNX2_HC_TX_TICKS_2_INT                           (0x3ffL<<16)
5199
5200 #define BNX2_HC_COM_TICKS_2                             0x00006a3c
5201 #define BNX2_HC_COM_TICKS_2_VALUE                        (0x3ffL<<0)
5202 #define BNX2_HC_COM_TICKS_2_INT                          (0x3ffL<<16)
5203
5204 #define BNX2_HC_CMD_TICKS_2                             0x00006a40
5205 #define BNX2_HC_CMD_TICKS_2_VALUE                        (0x3ffL<<0)
5206 #define BNX2_HC_CMD_TICKS_2_INT                          (0x3ffL<<16)
5207
5208 #define BNX2_HC_PERIODIC_TICKS_2                        0x00006a44
5209 #define BNX2_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS       (0xffffL<<0)
5210 #define BNX2_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
5211
5212 #define BNX2_HC_SB_CONFIG_3                             0x00006a48
5213 #define BNX2_HC_SB_CONFIG_3_RX_TMR_MODE                  (1L<<1)
5214 #define BNX2_HC_SB_CONFIG_3_TX_TMR_MODE                  (1L<<2)
5215 #define BNX2_HC_SB_CONFIG_3_COM_TMR_MODE                 (1L<<3)
5216 #define BNX2_HC_SB_CONFIG_3_CMD_TMR_MODE                 (1L<<4)
5217 #define BNX2_HC_SB_CONFIG_3_PER_MODE                     (1L<<16)
5218 #define BNX2_HC_SB_CONFIG_3_ONE_SHOT                     (1L<<17)
5219 #define BNX2_HC_SB_CONFIG_3_USE_INT_PARAM                (1L<<18)
5220 #define BNX2_HC_SB_CONFIG_3_PER_COLLECT_LIMIT            (0xfL<<20)
5221
5222 #define BNX2_HC_TX_QUICK_CONS_TRIP_3                    0x00006a4c
5223 #define BNX2_HC_TX_QUICK_CONS_TRIP_3_VALUE               (0xffL<<0)
5224 #define BNX2_HC_TX_QUICK_CONS_TRIP_3_INT                 (0xffL<<16)
5225
5226 #define BNX2_HC_COMP_PROD_TRIP_3                        0x00006a50
5227 #define BNX2_HC_COMP_PROD_TRIP_3_VALUE                   (0xffL<<0)
5228 #define BNX2_HC_COMP_PROD_TRIP_3_INT                     (0xffL<<16)
5229
5230 #define BNX2_HC_RX_QUICK_CONS_TRIP_3                    0x00006a54
5231 #define BNX2_HC_RX_QUICK_CONS_TRIP_3_VALUE               (0xffL<<0)
5232 #define BNX2_HC_RX_QUICK_CONS_TRIP_3_INT                 (0xffL<<16)
5233
5234 #define BNX2_HC_RX_TICKS_3                              0x00006a58
5235 #define BNX2_HC_RX_TICKS_3_VALUE                         (0x3ffL<<0)
5236 #define BNX2_HC_RX_TICKS_3_INT                           (0x3ffL<<16)
5237
5238 #define BNX2_HC_TX_TICKS_3                              0x00006a5c
5239 #define BNX2_HC_TX_TICKS_3_VALUE                         (0x3ffL<<0)
5240 #define BNX2_HC_TX_TICKS_3_INT                           (0x3ffL<<16)
5241
5242 #define BNX2_HC_COM_TICKS_3                             0x00006a60
5243 #define BNX2_HC_COM_TICKS_3_VALUE                        (0x3ffL<<0)
5244 #define BNX2_HC_COM_TICKS_3_INT                          (0x3ffL<<16)
5245
5246 #define BNX2_HC_CMD_TICKS_3                             0x00006a64
5247 #define BNX2_HC_CMD_TICKS_3_VALUE                        (0x3ffL<<0)
5248 #define BNX2_HC_CMD_TICKS_3_INT                          (0x3ffL<<16)
5249
5250 #define BNX2_HC_PERIODIC_TICKS_3                        0x00006a68
5251 #define BNX2_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS       (0xffffL<<0)
5252 #define BNX2_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
5253
5254 #define BNX2_HC_SB_CONFIG_4                             0x00006a6c
5255 #define BNX2_HC_SB_CONFIG_4_RX_TMR_MODE                  (1L<<1)
5256 #define BNX2_HC_SB_CONFIG_4_TX_TMR_MODE                  (1L<<2)
5257 #define BNX2_HC_SB_CONFIG_4_COM_TMR_MODE                 (1L<<3)
5258 #define BNX2_HC_SB_CONFIG_4_CMD_TMR_MODE                 (1L<<4)
5259 #define BNX2_HC_SB_CONFIG_4_PER_MODE                     (1L<<16)
5260 #define BNX2_HC_SB_CONFIG_4_ONE_SHOT                     (1L<<17)
5261 #define BNX2_HC_SB_CONFIG_4_USE_INT_PARAM                (1L<<18)
5262 #define BNX2_HC_SB_CONFIG_4_PER_COLLECT_LIMIT            (0xfL<<20)
5263
5264 #define BNX2_HC_TX_QUICK_CONS_TRIP_4                    0x00006a70
5265 #define BNX2_HC_TX_QUICK_CONS_TRIP_4_VALUE               (0xffL<<0)
5266 #define BNX2_HC_TX_QUICK_CONS_TRIP_4_INT                 (0xffL<<16)
5267
5268 #define BNX2_HC_COMP_PROD_TRIP_4                        0x00006a74
5269 #define BNX2_HC_COMP_PROD_TRIP_4_VALUE                   (0xffL<<0)
5270 #define BNX2_HC_COMP_PROD_TRIP_4_INT                     (0xffL<<16)
5271
5272 #define BNX2_HC_RX_QUICK_CONS_TRIP_4                    0x00006a78
5273 #define BNX2_HC_RX_QUICK_CONS_TRIP_4_VALUE               (0xffL<<0)
5274 #define BNX2_HC_RX_QUICK_CONS_TRIP_4_INT                 (0xffL<<16)
5275
5276 #define BNX2_HC_RX_TICKS_4                              0x00006a7c
5277 #define BNX2_HC_RX_TICKS_4_VALUE                         (0x3ffL<<0)
5278 #define BNX2_HC_RX_TICKS_4_INT                           (0x3ffL<<16)
5279
5280 #define BNX2_HC_TX_TICKS_4                              0x00006a80
5281 #define BNX2_HC_TX_TICKS_4_VALUE                         (0x3ffL<<0)
5282 #define BNX2_HC_TX_TICKS_4_INT                           (0x3ffL<<16)
5283
5284 #define BNX2_HC_COM_TICKS_4                             0x00006a84
5285 #define BNX2_HC_COM_TICKS_4_VALUE                        (0x3ffL<<0)
5286 #define BNX2_HC_COM_TICKS_4_INT                          (0x3ffL<<16)
5287
5288 #define BNX2_HC_CMD_TICKS_4                             0x00006a88
5289 #define BNX2_HC_CMD_TICKS_4_VALUE                        (0x3ffL<<0)
5290 #define BNX2_HC_CMD_TICKS_4_INT                          (0x3ffL<<16)
5291
5292 #define BNX2_HC_PERIODIC_TICKS_4                        0x00006a8c
5293 #define BNX2_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS       (0xffffL<<0)
5294 #define BNX2_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
5295
5296 #define BNX2_HC_SB_CONFIG_5                             0x00006a90
5297 #define BNX2_HC_SB_CONFIG_5_RX_TMR_MODE                  (1L<<1)
5298 #define BNX2_HC_SB_CONFIG_5_TX_TMR_MODE                  (1L<<2)
5299 #define BNX2_HC_SB_CONFIG_5_COM_TMR_MODE                 (1L<<3)
5300 #define BNX2_HC_SB_CONFIG_5_CMD_TMR_MODE                 (1L<<4)
5301 #define BNX2_HC_SB_CONFIG_5_PER_MODE                     (1L<<16)
5302 #define BNX2_HC_SB_CONFIG_5_ONE_SHOT                     (1L<<17)
5303 #define BNX2_HC_SB_CONFIG_5_USE_INT_PARAM                (1L<<18)
5304 #define BNX2_HC_SB_CONFIG_5_PER_COLLECT_LIMIT            (0xfL<<20)
5305
5306 #define BNX2_HC_TX_QUICK_CONS_TRIP_5                    0x00006a94
5307 #define BNX2_HC_TX_QUICK_CONS_TRIP_5_VALUE               (0xffL<<0)
5308 #define BNX2_HC_TX_QUICK_CONS_TRIP_5_INT                 (0xffL<<16)
5309
5310 #define BNX2_HC_COMP_PROD_TRIP_5                        0x00006a98
5311 #define BNX2_HC_COMP_PROD_TRIP_5_VALUE                   (0xffL<<0)
5312 #define BNX2_HC_COMP_PROD_TRIP_5_INT                     (0xffL<<16)
5313
5314 #define BNX2_HC_RX_QUICK_CONS_TRIP_5                    0x00006a9c
5315 #define BNX2_HC_RX_QUICK_CONS_TRIP_5_VALUE               (0xffL<<0)
5316 #define BNX2_HC_RX_QUICK_CONS_TRIP_5_INT                 (0xffL<<16)
5317
5318 #define BNX2_HC_RX_TICKS_5                              0x00006aa0
5319 #define BNX2_HC_RX_TICKS_5_VALUE                         (0x3ffL<<0)
5320 #define BNX2_HC_RX_TICKS_5_INT                           (0x3ffL<<16)
5321
5322 #define BNX2_HC_TX_TICKS_5                              0x00006aa4
5323 #define BNX2_HC_TX_TICKS_5_VALUE                         (0x3ffL<<0)
5324 #define BNX2_HC_TX_TICKS_5_INT                           (0x3ffL<<16)
5325
5326 #define BNX2_HC_COM_TICKS_5                             0x00006aa8
5327 #define BNX2_HC_COM_TICKS_5_VALUE                        (0x3ffL<<0)
5328 #define BNX2_HC_COM_TICKS_5_INT                          (0x3ffL<<16)
5329
5330 #define BNX2_HC_CMD_TICKS_5                             0x00006aac
5331 #define BNX2_HC_CMD_TICKS_5_VALUE                        (0x3ffL<<0)
5332 #define BNX2_HC_CMD_TICKS_5_INT                          (0x3ffL<<16)
5333
5334 #define BNX2_HC_PERIODIC_TICKS_5                        0x00006ab0
5335 #define BNX2_HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS       (0xffffL<<0)
5336 #define BNX2_HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
5337
5338 #define BNX2_HC_SB_CONFIG_6                             0x00006ab4
5339 #define BNX2_HC_SB_CONFIG_6_RX_TMR_MODE                  (1L<<1)
5340 #define BNX2_HC_SB_CONFIG_6_TX_TMR_MODE                  (1L<<2)
5341 #define BNX2_HC_SB_CONFIG_6_COM_TMR_MODE                 (1L<<3)
5342 #define BNX2_HC_SB_CONFIG_6_CMD_TMR_MODE                 (1L<<4)
5343 #define BNX2_HC_SB_CONFIG_6_PER_MODE                     (1L<<16)
5344 #define BNX2_HC_SB_CONFIG_6_ONE_SHOT                     (1L<<17)
5345 #define BNX2_HC_SB_CONFIG_6_USE_INT_PARAM                (1L<<18)
5346 #define BNX2_HC_SB_CONFIG_6_PER_COLLECT_LIMIT            (0xfL<<20)
5347
5348 #define BNX2_HC_TX_QUICK_CONS_TRIP_6                    0x00006ab8
5349 #define BNX2_HC_TX_QUICK_CONS_TRIP_6_VALUE               (0xffL<<0)
5350 #define BNX2_HC_TX_QUICK_CONS_TRIP_6_INT                 (0xffL<<16)
5351
5352 #define BNX2_HC_COMP_PROD_TRIP_6                        0x00006abc
5353 #define BNX2_HC_COMP_PROD_TRIP_6_VALUE                   (0xffL<<0)
5354 #define BNX2_HC_COMP_PROD_TRIP_6_INT                     (0xffL<<16)
5355
5356 #define BNX2_HC_RX_QUICK_CONS_TRIP_6                    0x00006ac0
5357 #define BNX2_HC_RX_QUICK_CONS_TRIP_6_VALUE               (0xffL<<0)
5358 #define BNX2_HC_RX_QUICK_CONS_TRIP_6_INT                 (0xffL<<16)
5359
5360 #define BNX2_HC_RX_TICKS_6                              0x00006ac4
5361 #define BNX2_HC_RX_TICKS_6_VALUE                         (0x3ffL<<0)
5362 #define BNX2_HC_RX_TICKS_6_INT                           (0x3ffL<<16)
5363
5364 #define BNX2_HC_TX_TICKS_6                              0x00006ac8
5365 #define BNX2_HC_TX_TICKS_6_VALUE                         (0x3ffL<<0)
5366 #define BNX2_HC_TX_TICKS_6_INT                           (0x3ffL<<16)
5367
5368 #define BNX2_HC_COM_TICKS_6                             0x00006acc
5369 #define BNX2_HC_COM_TICKS_6_VALUE                        (0x3ffL<<0)
5370 #define BNX2_HC_COM_TICKS_6_INT                          (0x3ffL<<16)
5371
5372 #define BNX2_HC_CMD_TICKS_6                             0x00006ad0
5373 #define BNX2_HC_CMD_TICKS_6_VALUE                        (0x3ffL<<0)
5374 #define BNX2_HC_CMD_TICKS_6_INT                          (0x3ffL<<16)
5375
5376 #define BNX2_HC_PERIODIC_TICKS_6                        0x00006ad4
5377 #define BNX2_HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS       (0xffffL<<0)
5378 #define BNX2_HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
5379
5380 #define BNX2_HC_SB_CONFIG_7                             0x00006ad8
5381 #define BNX2_HC_SB_CONFIG_7_RX_TMR_MODE                  (1L<<1)
5382 #define BNX2_HC_SB_CONFIG_7_TX_TMR_MODE                  (1L<<2)
5383 #define BNX2_HC_SB_CONFIG_7_COM_TMR_MODE                 (1L<<3)
5384 #define BNX2_HC_SB_CONFIG_7_CMD_TMR_MODE                 (1L<<4)
5385 #define BNX2_HC_SB_CONFIG_7_PER_MODE                     (1L<<16)
5386 #define BNX2_HC_SB_CONFIG_7_ONE_SHOT                     (1L<<17)
5387 #define BNX2_HC_SB_CONFIG_7_USE_INT_PARAM                (1L<<18)
5388 #define BNX2_HC_SB_CONFIG_7_PER_COLLECT_LIMIT            (0xfL<<20)
5389
5390 #define BNX2_HC_TX_QUICK_CONS_TRIP_7                    0x00006adc
5391 #define BNX2_HC_TX_QUICK_CONS_TRIP_7_VALUE               (0xffL<<0)
5392 #define BNX2_HC_TX_QUICK_CONS_TRIP_7_INT                 (0xffL<<16)
5393
5394 #define BNX2_HC_COMP_PROD_TRIP_7                        0x00006ae0
5395 #define BNX2_HC_COMP_PROD_TRIP_7_VALUE                   (0xffL<<0)
5396 #define BNX2_HC_COMP_PROD_TRIP_7_INT                     (0xffL<<16)
5397
5398 #define BNX2_HC_RX_QUICK_CONS_TRIP_7                    0x00006ae4
5399 #define BNX2_HC_RX_QUICK_CONS_TRIP_7_VALUE               (0xffL<<0)
5400 #define BNX2_HC_RX_QUICK_CONS_TRIP_7_INT                 (0xffL<<16)
5401
5402 #define BNX2_HC_RX_TICKS_7                              0x00006ae8
5403 #define BNX2_HC_RX_TICKS_7_VALUE                         (0x3ffL<<0)
5404 #define BNX2_HC_RX_TICKS_7_INT                           (0x3ffL<<16)
5405
5406 #define BNX2_HC_TX_TICKS_7                              0x00006aec
5407 #define BNX2_HC_TX_TICKS_7_VALUE                         (0x3ffL<<0)
5408 #define BNX2_HC_TX_TICKS_7_INT                           (0x3ffL<<16)
5409
5410 #define BNX2_HC_COM_TICKS_7                             0x00006af0
5411 #define BNX2_HC_COM_TICKS_7_VALUE                        (0x3ffL<<0)
5412 #define BNX2_HC_COM_TICKS_7_INT                          (0x3ffL<<16)
5413
5414 #define BNX2_HC_CMD_TICKS_7                             0x00006af4
5415 #define BNX2_HC_CMD_TICKS_7_VALUE                        (0x3ffL<<0)
5416 #define BNX2_HC_CMD_TICKS_7_INT                          (0x3ffL<<16)
5417
5418 #define BNX2_HC_PERIODIC_TICKS_7                        0x00006af8
5419 #define BNX2_HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS       (0xffffL<<0)
5420 #define BNX2_HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
5421
5422 #define BNX2_HC_SB_CONFIG_8                             0x00006afc
5423 #define BNX2_HC_SB_CONFIG_8_RX_TMR_MODE                  (1L<<1)
5424 #define BNX2_HC_SB_CONFIG_8_TX_TMR_MODE                  (1L<<2)
5425 #define BNX2_HC_SB_CONFIG_8_COM_TMR_MODE                 (1L<<3)
5426 #define BNX2_HC_SB_CONFIG_8_CMD_TMR_MODE                 (1L<<4)
5427 #define BNX2_HC_SB_CONFIG_8_PER_MODE                     (1L<<16)
5428 #define BNX2_HC_SB_CONFIG_8_ONE_SHOT                     (1L<<17)
5429 #define BNX2_HC_SB_CONFIG_8_USE_INT_PARAM                (1L<<18)
5430 #define BNX2_HC_SB_CONFIG_8_PER_COLLECT_LIMIT            (0xfL<<20)
5431
5432 #define BNX2_HC_TX_QUICK_CONS_TRIP_8                    0x00006b00
5433 #define BNX2_HC_TX_QUICK_CONS_TRIP_8_VALUE               (0xffL<<0)
5434 #define BNX2_HC_TX_QUICK_CONS_TRIP_8_INT                 (0xffL<<16)
5435
5436 #define BNX2_HC_COMP_PROD_TRIP_8                        0x00006b04
5437 #define BNX2_HC_COMP_PROD_TRIP_8_VALUE                   (0xffL<<0)
5438 #define BNX2_HC_COMP_PROD_TRIP_8_INT                     (0xffL<<16)
5439
5440 #define BNX2_HC_RX_QUICK_CONS_TRIP_8                    0x00006b08
5441 #define BNX2_HC_RX_QUICK_CONS_TRIP_8_VALUE               (0xffL<<0)
5442 #define BNX2_HC_RX_QUICK_CONS_TRIP_8_INT                 (0xffL<<16)
5443
5444 #define BNX2_HC_RX_TICKS_8                              0x00006b0c
5445 #define BNX2_HC_RX_TICKS_8_VALUE                         (0x3ffL<<0)
5446 #define BNX2_HC_RX_TICKS_8_INT                           (0x3ffL<<16)
5447
5448 #define BNX2_HC_TX_TICKS_8                              0x00006b10
5449 #define BNX2_HC_TX_TICKS_8_VALUE                         (0x3ffL<<0)
5450 #define BNX2_HC_TX_TICKS_8_INT                           (0x3ffL<<16)
5451
5452 #define BNX2_HC_COM_TICKS_8                             0x00006b14
5453 #define BNX2_HC_COM_TICKS_8_VALUE                        (0x3ffL<<0)
5454 #define BNX2_HC_COM_TICKS_8_INT                          (0x3ffL<<16)
5455
5456 #define BNX2_HC_CMD_TICKS_8                             0x00006b18
5457 #define BNX2_HC_CMD_TICKS_8_VALUE                        (0x3ffL<<0)
5458 #define BNX2_HC_CMD_TICKS_8_INT                          (0x3ffL<<16)
5459
5460 #define BNX2_HC_PERIODIC_TICKS_8                        0x00006b1c
5461 #define BNX2_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS       (0xffffL<<0)
5462 #define BNX2_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
5463
5464
5465 /*
5466  *  txp_reg definition
5467  *  offset: 0x40000
5468  */
5469 #define BNX2_TXP_CPU_MODE                               0x00045000
5470 #define BNX2_TXP_CPU_MODE_LOCAL_RST                      (1L<<0)
5471 #define BNX2_TXP_CPU_MODE_STEP_ENA                       (1L<<1)
5472 #define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA                (1L<<2)
5473 #define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA                (1L<<3)
5474 #define BNX2_TXP_CPU_MODE_MSG_BIT1                       (1L<<6)
5475 #define BNX2_TXP_CPU_MODE_INTERRUPT_ENA                  (1L<<7)
5476 #define BNX2_TXP_CPU_MODE_SOFT_HALT                      (1L<<10)
5477 #define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA              (1L<<11)
5478 #define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA              (1L<<12)
5479 #define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA             (1L<<13)
5480 #define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA        (1L<<15)
5481
5482 #define BNX2_TXP_CPU_STATE                              0x00045004
5483 #define BNX2_TXP_CPU_STATE_BREAKPOINT                    (1L<<0)
5484 #define BNX2_TXP_CPU_STATE_BAD_INST_HALTED               (1L<<2)
5485 #define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
5486 #define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
5487 #define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
5488 #define BNX2_TXP_CPU_STATE_BAD_PC_HALTED                 (1L<<6)
5489 #define BNX2_TXP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
5490 #define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
5491 #define BNX2_TXP_CPU_STATE_SOFT_HALTED                   (1L<<10)
5492 #define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW                (1L<<11)
5493 #define BNX2_TXP_CPU_STATE_INTERRRUPT                    (1L<<12)
5494 #define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL             (1L<<14)
5495 #define BNX2_TXP_CPU_STATE_INST_FETCH_STALL              (1L<<15)
5496 #define BNX2_TXP_CPU_STATE_BLOCKED_READ                  (1L<<31)
5497
5498 #define BNX2_TXP_CPU_EVENT_MASK                         0x00045008
5499 #define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK          (1L<<0)
5500 #define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK     (1L<<2)
5501 #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK  (1L<<3)
5502 #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK  (1L<<4)
5503 #define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK        (1L<<5)
5504 #define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK       (1L<<6)
5505 #define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK        (1L<<7)
5506 #define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK           (1L<<8)
5507 #define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK         (1L<<10)
5508 #define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK      (1L<<11)
5509 #define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK           (1L<<12)
5510
5511 #define BNX2_TXP_CPU_PROGRAM_COUNTER                    0x0004501c
5512 #define BNX2_TXP_CPU_INSTRUCTION                        0x00045020
5513 #define BNX2_TXP_CPU_DATA_ACCESS                        0x00045024
5514 #define BNX2_TXP_CPU_INTERRUPT_ENABLE                   0x00045028
5515 #define BNX2_TXP_CPU_INTERRUPT_VECTOR                   0x0004502c
5516 #define BNX2_TXP_CPU_INTERRUPT_SAVED_PC                 0x00045030
5517 #define BNX2_TXP_CPU_HW_BREAKPOINT                      0x00045034
5518 #define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE               (1L<<0)
5519 #define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS               (0x3fffffffL<<2)
5520
5521 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK                    0x00045038
5522 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE             (0x7ffL<<0)
5523 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN           (1L<<11)
5524 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL               (0xfL<<12)
5525 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE             (0x7ffL<<16)
5526 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN           (1L<<27)
5527 #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL               (0xfL<<28)
5528
5529 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR                   0x00045048
5530 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE               (1L<<1)
5531 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP          (0L<<1)
5532 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH        (1L<<1)
5533 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
5534
5535 #define BNX2_TXP_CPU_REG_FILE                           0x00045200
5536 #define BNX2_TXP_TXPQ                                   0x000453c0
5537 #define BNX2_TXP_FTQ_CMD                                0x000453f8
5538 #define BNX2_TXP_FTQ_CMD_OFFSET                          (0x3ffL<<0)
5539 #define BNX2_TXP_FTQ_CMD_WR_TOP                          (1L<<10)
5540 #define BNX2_TXP_FTQ_CMD_WR_TOP_0                        (0L<<10)
5541 #define BNX2_TXP_FTQ_CMD_WR_TOP_1                        (1L<<10)
5542 #define BNX2_TXP_FTQ_CMD_SFT_RESET                       (1L<<25)
5543 #define BNX2_TXP_FTQ_CMD_RD_DATA                         (1L<<26)
5544 #define BNX2_TXP_FTQ_CMD_ADD_INTERVEN                    (1L<<27)
5545 #define BNX2_TXP_FTQ_CMD_ADD_DATA                        (1L<<28)
5546 #define BNX2_TXP_FTQ_CMD_INTERVENE_CLR                   (1L<<29)
5547 #define BNX2_TXP_FTQ_CMD_POP                             (1L<<30)
5548 #define BNX2_TXP_FTQ_CMD_BUSY                            (1L<<31)
5549
5550 #define BNX2_TXP_FTQ_CTL                                0x000453fc
5551 #define BNX2_TXP_FTQ_CTL_INTERVENE                       (1L<<0)
5552 #define BNX2_TXP_FTQ_CTL_OVERFLOW                        (1L<<1)
5553 #define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE                 (1L<<2)
5554 #define BNX2_TXP_FTQ_CTL_MAX_DEPTH                       (0x3ffL<<12)
5555 #define BNX2_TXP_FTQ_CTL_CUR_DEPTH                       (0x3ffL<<22)
5556
5557 #define BNX2_TXP_SCRATCH                                0x00060000
5558
5559
5560 /*
5561  *  tpat_reg definition
5562  *  offset: 0x80000
5563  */
5564 #define BNX2_TPAT_CPU_MODE                              0x00085000
5565 #define BNX2_TPAT_CPU_MODE_LOCAL_RST                     (1L<<0)
5566 #define BNX2_TPAT_CPU_MODE_STEP_ENA                      (1L<<1)
5567 #define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA               (1L<<2)
5568 #define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA               (1L<<3)
5569 #define BNX2_TPAT_CPU_MODE_MSG_BIT1                      (1L<<6)
5570 #define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA                 (1L<<7)
5571 #define BNX2_TPAT_CPU_MODE_SOFT_HALT                     (1L<<10)
5572 #define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA             (1L<<11)
5573 #define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA             (1L<<12)
5574 #define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA            (1L<<13)
5575 #define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA       (1L<<15)
5576
5577 #define BNX2_TPAT_CPU_STATE                             0x00085004
5578 #define BNX2_TPAT_CPU_STATE_BREAKPOINT                   (1L<<0)
5579 #define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED              (1L<<2)
5580 #define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED           (1L<<3)
5581 #define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED           (1L<<4)
5582 #define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED         (1L<<5)
5583 #define BNX2_TPAT_CPU_STATE_BAD_PC_HALTED                (1L<<6)
5584 #define BNX2_TPAT_CPU_STATE_ALIGN_HALTED                 (1L<<7)
5585 #define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED             (1L<<8)
5586 #define BNX2_TPAT_CPU_STATE_SOFT_HALTED                  (1L<<10)
5587 #define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW               (1L<<11)
5588 #define BNX2_TPAT_CPU_STATE_INTERRRUPT                   (1L<<12)
5589 #define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL            (1L<<14)
5590 #define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL             (1L<<15)
5591 #define BNX2_TPAT_CPU_STATE_BLOCKED_READ                 (1L<<31)
5592
5593 #define BNX2_TPAT_CPU_EVENT_MASK                        0x00085008
5594 #define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK         (1L<<0)
5595 #define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK    (1L<<2)
5596 #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK         (1L<<3)
5597 #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK         (1L<<4)
5598 #define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK       (1L<<5)
5599 #define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK      (1L<<6)
5600 #define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK       (1L<<7)
5601 #define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK          (1L<<8)
5602 #define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK        (1L<<10)
5603 #define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK     (1L<<11)
5604 #define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK          (1L<<12)
5605
5606 #define BNX2_TPAT_CPU_PROGRAM_COUNTER                   0x0008501c
5607 #define BNX2_TPAT_CPU_INSTRUCTION                       0x00085020
5608 #define BNX2_TPAT_CPU_DATA_ACCESS                       0x00085024
5609 #define BNX2_TPAT_CPU_INTERRUPT_ENABLE                  0x00085028
5610 #define BNX2_TPAT_CPU_INTERRUPT_VECTOR                  0x0008502c
5611 #define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC                0x00085030
5612 #define BNX2_TPAT_CPU_HW_BREAKPOINT                     0x00085034
5613 #define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE              (1L<<0)
5614 #define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS              (0x3fffffffL<<2)
5615
5616 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK                   0x00085038
5617 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE            (0x7ffL<<0)
5618 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN          (1L<<11)
5619 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL              (0xfL<<12)
5620 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE            (0x7ffL<<16)
5621 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN          (1L<<27)
5622 #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL              (0xfL<<28)
5623
5624 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR                  0x00085048
5625 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE              (1L<<1)
5626 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP         (0L<<1)
5627 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH       (1L<<1)
5628 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA               (0x3fffffffL<<2)
5629
5630 #define BNX2_TPAT_CPU_REG_FILE                          0x00085200
5631 #define BNX2_TPAT_TPATQ                                 0x000853c0
5632 #define BNX2_TPAT_FTQ_CMD                               0x000853f8
5633 #define BNX2_TPAT_FTQ_CMD_OFFSET                         (0x3ffL<<0)
5634 #define BNX2_TPAT_FTQ_CMD_WR_TOP                         (1L<<10)
5635 #define BNX2_TPAT_FTQ_CMD_WR_TOP_0                       (0L<<10)
5636 #define BNX2_TPAT_FTQ_CMD_WR_TOP_1                       (1L<<10)
5637 #define BNX2_TPAT_FTQ_CMD_SFT_RESET                      (1L<<25)
5638 #define BNX2_TPAT_FTQ_CMD_RD_DATA                        (1L<<26)
5639 #define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN                   (1L<<27)
5640 #define BNX2_TPAT_FTQ_CMD_ADD_DATA                       (1L<<28)
5641 #define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR                  (1L<<29)
5642 #define BNX2_TPAT_FTQ_CMD_POP                            (1L<<30)
5643 #define BNX2_TPAT_FTQ_CMD_BUSY                           (1L<<31)
5644
5645 #define BNX2_TPAT_FTQ_CTL                               0x000853fc
5646 #define BNX2_TPAT_FTQ_CTL_INTERVENE                      (1L<<0)
5647 #define BNX2_TPAT_FTQ_CTL_OVERFLOW                       (1L<<1)
5648 #define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE                (1L<<2)
5649 #define BNX2_TPAT_FTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
5650 #define BNX2_TPAT_FTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
5651
5652 #define BNX2_TPAT_SCRATCH                               0x000a0000
5653
5654
5655 /*
5656  *  rxp_reg definition
5657  *  offset: 0xc0000
5658  */
5659 #define BNX2_RXP_CPU_MODE                               0x000c5000
5660 #define BNX2_RXP_CPU_MODE_LOCAL_RST                      (1L<<0)
5661 #define BNX2_RXP_CPU_MODE_STEP_ENA                       (1L<<1)
5662 #define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA                (1L<<2)
5663 #define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA                (1L<<3)
5664 #define BNX2_RXP_CPU_MODE_MSG_BIT1                       (1L<<6)
5665 #define BNX2_RXP_CPU_MODE_INTERRUPT_ENA                  (1L<<7)
5666 #define BNX2_RXP_CPU_MODE_SOFT_HALT                      (1L<<10)
5667 #define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA              (1L<<11)
5668 #define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA              (1L<<12)
5669 #define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA             (1L<<13)
5670 #define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA        (1L<<15)
5671
5672 #define BNX2_RXP_CPU_STATE                              0x000c5004
5673 #define BNX2_RXP_CPU_STATE_BREAKPOINT                    (1L<<0)
5674 #define BNX2_RXP_CPU_STATE_BAD_INST_HALTED               (1L<<2)
5675 #define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
5676 #define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
5677 #define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
5678 #define BNX2_RXP_CPU_STATE_BAD_PC_HALTED                 (1L<<6)
5679 #define BNX2_RXP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
5680 #define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
5681 #define BNX2_RXP_CPU_STATE_SOFT_HALTED                   (1L<<10)
5682 #define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW                (1L<<11)
5683 #define BNX2_RXP_CPU_STATE_INTERRRUPT                    (1L<<12)
5684 #define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL             (1L<<14)
5685 #define BNX2_RXP_CPU_STATE_INST_FETCH_STALL              (1L<<15)
5686 #define BNX2_RXP_CPU_STATE_BLOCKED_READ                  (1L<<31)
5687
5688 #define BNX2_RXP_CPU_EVENT_MASK                         0x000c5008
5689 #define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK          (1L<<0)
5690 #define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK     (1L<<2)
5691 #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK  (1L<<3)
5692 #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK  (1L<<4)
5693 #define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK        (1L<<5)
5694 #define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK       (1L<<6)
5695 #define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK        (1L<<7)
5696 #define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK           (1L<<8)
5697 #define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK         (1L<<10)
5698 #define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK      (1L<<11)
5699 #define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK           (1L<<12)
5700
5701 #define BNX2_RXP_CPU_PROGRAM_COUNTER                    0x000c501c
5702 #define BNX2_RXP_CPU_INSTRUCTION                        0x000c5020
5703 #define BNX2_RXP_CPU_DATA_ACCESS                        0x000c5024
5704 #define BNX2_RXP_CPU_INTERRUPT_ENABLE                   0x000c5028
5705 #define BNX2_RXP_CPU_INTERRUPT_VECTOR                   0x000c502c
5706 #define BNX2_RXP_CPU_INTERRUPT_SAVED_PC                 0x000c5030
5707 #define BNX2_RXP_CPU_HW_BREAKPOINT                      0x000c5034
5708 #define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE               (1L<<0)
5709 #define BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS               (0x3fffffffL<<2)
5710
5711 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK                    0x000c5038
5712 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE             (0x7ffL<<0)
5713 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN           (1L<<11)
5714 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL               (0xfL<<12)
5715 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE             (0x7ffL<<16)
5716 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN           (1L<<27)
5717 #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL               (0xfL<<28)
5718
5719 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR                   0x000c5048
5720 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE               (1L<<1)
5721 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP          (0L<<1)
5722 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH        (1L<<1)
5723 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
5724
5725 #define BNX2_RXP_CPU_REG_FILE                           0x000c5200
5726 #define BNX2_RXP_PFE_PFE_CTL                            0x000c537c
5727 #define BNX2_RXP_PFE_PFE_CTL_INC_USAGE_CNT               (1L<<0)
5728 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE                    (0xfL<<4)
5729 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_0                  (0L<<4)
5730 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_1                  (1L<<4)
5731 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_2                  (2L<<4)
5732 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_3                  (3L<<4)
5733 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_4                  (4L<<4)
5734 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_5                  (5L<<4)
5735 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_6                  (6L<<4)
5736 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_7                  (7L<<4)
5737 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_8                  (8L<<4)
5738 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_9                  (9L<<4)
5739 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_10                 (10L<<4)
5740 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_11                 (11L<<4)
5741 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_12                 (12L<<4)
5742 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_13                 (13L<<4)
5743 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_14                 (14L<<4)
5744 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_15                 (15L<<4)
5745 #define BNX2_RXP_PFE_PFE_CTL_PFE_COUNT                   (0xfL<<12)
5746 #define BNX2_RXP_PFE_PFE_CTL_OFFSET                      (0x1ffL<<16)
5747
5748 #define BNX2_RXP_RXPCQ                                  0x000c5380
5749 #define BNX2_RXP_CFTQ_CMD                               0x000c53b8
5750 #define BNX2_RXP_CFTQ_CMD_OFFSET                         (0x3ffL<<0)
5751 #define BNX2_RXP_CFTQ_CMD_WR_TOP                         (1L<<10)
5752 #define BNX2_RXP_CFTQ_CMD_WR_TOP_0                       (0L<<10)
5753 #define BNX2_RXP_CFTQ_CMD_WR_TOP_1                       (1L<<10)
5754 #define BNX2_RXP_CFTQ_CMD_SFT_RESET                      (1L<<25)
5755 #define BNX2_RXP_CFTQ_CMD_RD_DATA                        (1L<<26)
5756 #define BNX2_RXP_CFTQ_CMD_ADD_INTERVEN                   (1L<<27)
5757 #define BNX2_RXP_CFTQ_CMD_ADD_DATA                       (1L<<28)
5758 #define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR                  (1L<<29)
5759 #define BNX2_RXP_CFTQ_CMD_POP                            (1L<<30)
5760 #define BNX2_RXP_CFTQ_CMD_BUSY                           (1L<<31)
5761
5762 #define BNX2_RXP_CFTQ_CTL                               0x000c53bc
5763 #define BNX2_RXP_CFTQ_CTL_INTERVENE                      (1L<<0)
5764 #define BNX2_RXP_CFTQ_CTL_OVERFLOW                       (1L<<1)
5765 #define BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE                (1L<<2)
5766 #define BNX2_RXP_CFTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
5767 #define BNX2_RXP_CFTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
5768
5769 #define BNX2_RXP_RXPQ                                   0x000c53c0
5770 #define BNX2_RXP_FTQ_CMD                                0x000c53f8
5771 #define BNX2_RXP_FTQ_CMD_OFFSET                          (0x3ffL<<0)
5772 #define BNX2_RXP_FTQ_CMD_WR_TOP                          (1L<<10)
5773 #define BNX2_RXP_FTQ_CMD_WR_TOP_0                        (0L<<10)
5774 #define BNX2_RXP_FTQ_CMD_WR_TOP_1                        (1L<<10)
5775 #define BNX2_RXP_FTQ_CMD_SFT_RESET                       (1L<<25)
5776 #define BNX2_RXP_FTQ_CMD_RD_DATA                         (1L<<26)
5777 #define BNX2_RXP_FTQ_CMD_ADD_INTERVEN                    (1L<<27)
5778 #define BNX2_RXP_FTQ_CMD_ADD_DATA                        (1L<<28)
5779 #define BNX2_RXP_FTQ_CMD_INTERVENE_CLR                   (1L<<29)
5780 #define BNX2_RXP_FTQ_CMD_POP                             (1L<<30)
5781 #define BNX2_RXP_FTQ_CMD_BUSY                            (1L<<31)
5782
5783 #define BNX2_RXP_FTQ_CTL                                0x000c53fc
5784 #define BNX2_RXP_FTQ_CTL_INTERVENE                       (1L<<0)
5785 #define BNX2_RXP_FTQ_CTL_OVERFLOW                        (1L<<1)
5786 #define BNX2_RXP_FTQ_CTL_FORCE_INTERVENE                 (1L<<2)
5787 #define BNX2_RXP_FTQ_CTL_MAX_DEPTH                       (0x3ffL<<12)
5788 #define BNX2_RXP_FTQ_CTL_CUR_DEPTH                       (0x3ffL<<22)
5789
5790 #define BNX2_RXP_SCRATCH                                0x000e0000
5791
5792
5793 /*
5794  *  com_reg definition
5795  *  offset: 0x100000
5796  */
5797 #define BNX2_COM_CKSUM_ERROR_STATUS                     0x00100000
5798 #define BNX2_COM_CKSUM_ERROR_STATUS_CALCULATED           (0xffffL<<0)
5799 #define BNX2_COM_CKSUM_ERROR_STATUS_EXPECTED             (0xffffL<<16)
5800
5801 #define BNX2_COM_CPU_MODE                               0x00105000
5802 #define BNX2_COM_CPU_MODE_LOCAL_RST                      (1L<<0)
5803 #define BNX2_COM_CPU_MODE_STEP_ENA                       (1L<<1)
5804 #define BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA                (1L<<2)
5805 #define BNX2_COM_CPU_MODE_PAGE_0_INST_ENA                (1L<<3)
5806 #define BNX2_COM_CPU_MODE_MSG_BIT1                       (1L<<6)
5807 #define BNX2_COM_CPU_MODE_INTERRUPT_ENA                  (1L<<7)
5808 #define BNX2_COM_CPU_MODE_SOFT_HALT                      (1L<<10)
5809 #define BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA              (1L<<11)
5810 #define BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA              (1L<<12)
5811 #define BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA             (1L<<13)
5812 #define BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA        (1L<<15)
5813
5814 #define BNX2_COM_CPU_STATE                              0x00105004
5815 #define BNX2_COM_CPU_STATE_BREAKPOINT                    (1L<<0)
5816 #define BNX2_COM_CPU_STATE_BAD_INST_HALTED               (1L<<2)
5817 #define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
5818 #define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
5819 #define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
5820 #define BNX2_COM_CPU_STATE_BAD_PC_HALTED                 (1L<<6)
5821 #define BNX2_COM_CPU_STATE_ALIGN_HALTED                  (1L<<7)
5822 #define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
5823 #define BNX2_COM_CPU_STATE_SOFT_HALTED                   (1L<<10)
5824 #define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW                (1L<<11)
5825 #define BNX2_COM_CPU_STATE_INTERRRUPT                    (1L<<12)
5826 #define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL             (1L<<14)
5827 #define BNX2_COM_CPU_STATE_INST_FETCH_STALL              (1L<<15)
5828 #define BNX2_COM_CPU_STATE_BLOCKED_READ                  (1L<<31)
5829
5830 #define BNX2_COM_CPU_EVENT_MASK                         0x00105008
5831 #define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK          (1L<<0)
5832 #define BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK     (1L<<2)
5833 #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK  (1L<<3)
5834 #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK  (1L<<4)
5835 #define BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK        (1L<<5)
5836 #define BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK       (1L<<6)
5837 #define BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK        (1L<<7)
5838 #define BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK           (1L<<8)
5839 #define BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK         (1L<<10)
5840 #define BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK      (1L<<11)
5841 #define BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK           (1L<<12)
5842
5843 #define BNX2_COM_CPU_PROGRAM_COUNTER                    0x0010501c
5844 #define BNX2_COM_CPU_INSTRUCTION                        0x00105020
5845 #define BNX2_COM_CPU_DATA_ACCESS                        0x00105024
5846 #define BNX2_COM_CPU_INTERRUPT_ENABLE                   0x00105028
5847 #define BNX2_COM_CPU_INTERRUPT_VECTOR                   0x0010502c
5848 #define BNX2_COM_CPU_INTERRUPT_SAVED_PC                 0x00105030
5849 #define BNX2_COM_CPU_HW_BREAKPOINT                      0x00105034
5850 #define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE               (1L<<0)
5851 #define BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS               (0x3fffffffL<<2)
5852
5853 #define BNX2_COM_CPU_DEBUG_VECT_PEEK                    0x00105038
5854 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE             (0x7ffL<<0)
5855 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN           (1L<<11)
5856 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL               (0xfL<<12)
5857 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE             (0x7ffL<<16)
5858 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN           (1L<<27)
5859 #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL               (0xfL<<28)
5860
5861 #define BNX2_COM_CPU_LAST_BRANCH_ADDR                   0x00105048
5862 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE               (1L<<1)
5863 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP          (0L<<1)
5864 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH        (1L<<1)
5865 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
5866
5867 #define BNX2_COM_CPU_REG_FILE                           0x00105200
5868 #define BNX2_COM_COMTQ_PFE_PFE_CTL                      0x001052bc
5869 #define BNX2_COM_COMTQ_PFE_PFE_CTL_INC_USAGE_CNT         (1L<<0)
5870 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE              (0xfL<<4)
5871 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_0            (0L<<4)
5872 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_1            (1L<<4)
5873 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_2            (2L<<4)
5874 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_3            (3L<<4)
5875 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_4            (4L<<4)
5876 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_5            (5L<<4)
5877 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_6            (6L<<4)
5878 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_7            (7L<<4)
5879 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_8            (8L<<4)
5880 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_9            (9L<<4)
5881 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_10           (10L<<4)
5882 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_11           (11L<<4)
5883 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_12           (12L<<4)
5884 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_13           (13L<<4)
5885 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_14           (14L<<4)
5886 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_15           (15L<<4)
5887 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_COUNT             (0xfL<<12)
5888 #define BNX2_COM_COMTQ_PFE_PFE_CTL_OFFSET                (0x1ffL<<16)
5889
5890 #define BNX2_COM_COMXQ                                  0x00105340
5891 #define BNX2_COM_COMXQ_FTQ_CMD                          0x00105378
5892 #define BNX2_COM_COMXQ_FTQ_CMD_OFFSET                    (0x3ffL<<0)
5893 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP                    (1L<<10)
5894 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0                  (0L<<10)
5895 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1                  (1L<<10)
5896 #define BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET                 (1L<<25)
5897 #define BNX2_COM_COMXQ_FTQ_CMD_RD_DATA                   (1L<<26)
5898 #define BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN              (1L<<27)
5899 #define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA                  (1L<<28)
5900 #define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR             (1L<<29)
5901 #define BNX2_COM_COMXQ_FTQ_CMD_POP                       (1L<<30)
5902 #define BNX2_COM_COMXQ_FTQ_CMD_BUSY                      (1L<<31)
5903
5904 #define BNX2_COM_COMXQ_FTQ_CTL                          0x0010537c
5905 #define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE                 (1L<<0)
5906 #define BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW                  (1L<<1)
5907 #define BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE           (1L<<2)
5908 #define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH                 (0x3ffL<<12)
5909 #define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH                 (0x3ffL<<22)
5910
5911 #define BNX2_COM_COMTQ                                  0x00105380
5912 #define BNX2_COM_COMTQ_FTQ_CMD                          0x001053b8
5913 #define BNX2_COM_COMTQ_FTQ_CMD_OFFSET                    (0x3ffL<<0)
5914 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP                    (1L<<10)
5915 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0                  (0L<<10)
5916 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1                  (1L<<10)
5917 #define BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET                 (1L<<25)
5918 #define BNX2_COM_COMTQ_FTQ_CMD_RD_DATA                   (1L<<26)
5919 #define BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN              (1L<<27)
5920 #define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA                  (1L<<28)
5921 #define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR             (1L<<29)
5922 #define BNX2_COM_COMTQ_FTQ_CMD_POP                       (1L<<30)
5923 #define BNX2_COM_COMTQ_FTQ_CMD_BUSY                      (1L<<31)
5924
5925 #define BNX2_COM_COMTQ_FTQ_CTL                          0x001053bc
5926 #define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE                 (1L<<0)
5927 #define BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW                  (1L<<1)
5928 #define BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE           (1L<<2)
5929 #define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH                 (0x3ffL<<12)
5930 #define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH                 (0x3ffL<<22)
5931
5932 #define BNX2_COM_COMQ                                   0x001053c0
5933 #define BNX2_COM_COMQ_FTQ_CMD                           0x001053f8
5934 #define BNX2_COM_COMQ_FTQ_CMD_OFFSET                     (0x3ffL<<0)
5935 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP                     (1L<<10)
5936 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0                   (0L<<10)
5937 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1                   (1L<<10)
5938 #define BNX2_COM_COMQ_FTQ_CMD_SFT_RESET                  (1L<<25)
5939 #define BNX2_COM_COMQ_FTQ_CMD_RD_DATA                    (1L<<26)
5940 #define BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN               (1L<<27)
5941 #define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA                   (1L<<28)
5942 #define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR              (1L<<29)
5943 #define BNX2_COM_COMQ_FTQ_CMD_POP                        (1L<<30)
5944 #define BNX2_COM_COMQ_FTQ_CMD_BUSY                       (1L<<31)
5945
5946 #define BNX2_COM_COMQ_FTQ_CTL                           0x001053fc
5947 #define BNX2_COM_COMQ_FTQ_CTL_INTERVENE                  (1L<<0)
5948 #define BNX2_COM_COMQ_FTQ_CTL_OVERFLOW                   (1L<<1)
5949 #define BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE            (1L<<2)
5950 #define BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH                  (0x3ffL<<12)
5951 #define BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH                  (0x3ffL<<22)
5952
5953 #define BNX2_COM_SCRATCH                                0x00120000
5954
5955 #define BNX2_FW_RX_DROP_COUNT                            0x00120084
5956
5957
5958 /*
5959  *  cp_reg definition
5960  *  offset: 0x180000
5961  */
5962 #define BNX2_CP_CKSUM_ERROR_STATUS                      0x00180000
5963 #define BNX2_CP_CKSUM_ERROR_STATUS_CALCULATED            (0xffffL<<0)
5964 #define BNX2_CP_CKSUM_ERROR_STATUS_EXPECTED              (0xffffL<<16)
5965
5966 #define BNX2_CP_CPU_MODE                                0x00185000
5967 #define BNX2_CP_CPU_MODE_LOCAL_RST                       (1L<<0)
5968 #define BNX2_CP_CPU_MODE_STEP_ENA                        (1L<<1)
5969 #define BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA                 (1L<<2)
5970 #define BNX2_CP_CPU_MODE_PAGE_0_INST_ENA                 (1L<<3)
5971 #define BNX2_CP_CPU_MODE_MSG_BIT1                        (1L<<6)
5972 #define BNX2_CP_CPU_MODE_INTERRUPT_ENA                   (1L<<7)
5973 #define BNX2_CP_CPU_MODE_SOFT_HALT                       (1L<<10)
5974 #define BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA               (1L<<11)
5975 #define BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA               (1L<<12)
5976 #define BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA              (1L<<13)
5977 #define BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA         (1L<<15)
5978
5979 #define BNX2_CP_CPU_STATE                               0x00185004
5980 #define BNX2_CP_CPU_STATE_BREAKPOINT                     (1L<<0)
5981 #define BNX2_CP_CPU_STATE_BAD_INST_HALTED                (1L<<2)
5982 #define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED             (1L<<3)
5983 #define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED             (1L<<4)
5984 #define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED           (1L<<5)
5985 #define BNX2_CP_CPU_STATE_BAD_PC_HALTED                  (1L<<6)
5986 #define BNX2_CP_CPU_STATE_ALIGN_HALTED                   (1L<<7)
5987 #define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED               (1L<<8)
5988 #define BNX2_CP_CPU_STATE_SOFT_HALTED                    (1L<<10)
5989 #define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW                 (1L<<11)
5990 #define BNX2_CP_CPU_STATE_INTERRRUPT                     (1L<<12)
5991 #define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL              (1L<<14)
5992 #define BNX2_CP_CPU_STATE_INST_FETCH_STALL               (1L<<15)
5993 #define BNX2_CP_CPU_STATE_BLOCKED_READ                   (1L<<31)
5994
5995 #define BNX2_CP_CPU_EVENT_MASK                          0x00185008
5996 #define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK           (1L<<0)
5997 #define BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK      (1L<<2)
5998 #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK   (1L<<3)
5999 #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK   (1L<<4)
6000 #define BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK         (1L<<5)
6001 #define BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK        (1L<<6)
6002 #define BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK         (1L<<7)
6003 #define BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK            (1L<<8)
6004 #define BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK          (1L<<10)
6005 #define BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK       (1L<<11)
6006 #define BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK            (1L<<12)
6007
6008 #define BNX2_CP_CPU_PROGRAM_COUNTER                     0x0018501c
6009 #define BNX2_CP_CPU_INSTRUCTION                         0x00185020
6010 #define BNX2_CP_CPU_DATA_ACCESS                         0x00185024
6011 #define BNX2_CP_CPU_INTERRUPT_ENABLE                    0x00185028
6012 #define BNX2_CP_CPU_INTERRUPT_VECTOR                    0x0018502c
6013 #define BNX2_CP_CPU_INTERRUPT_SAVED_PC                  0x00185030
6014 #define BNX2_CP_CPU_HW_BREAKPOINT                       0x00185034
6015 #define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE                (1L<<0)
6016 #define BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS                (0x3fffffffL<<2)
6017
6018 #define BNX2_CP_CPU_DEBUG_VECT_PEEK                     0x00185038
6019 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE              (0x7ffL<<0)
6020 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN            (1L<<11)
6021 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL                (0xfL<<12)
6022 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE              (0x7ffL<<16)
6023 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN            (1L<<27)
6024 #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL                (0xfL<<28)
6025
6026 #define BNX2_CP_CPU_LAST_BRANCH_ADDR                    0x00185048
6027 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE                (1L<<1)
6028 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP           (0L<<1)
6029 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH         (1L<<1)
6030 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA                 (0x3fffffffL<<2)
6031
6032 #define BNX2_CP_CPU_REG_FILE                            0x00185200
6033 #define BNX2_CP_CPQ_PFE_PFE_CTL                         0x001853bc
6034 #define BNX2_CP_CPQ_PFE_PFE_CTL_INC_USAGE_CNT            (1L<<0)
6035 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE                 (0xfL<<4)
6036 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_0               (0L<<4)
6037 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_1               (1L<<4)
6038 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_2               (2L<<4)
6039 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_3               (3L<<4)
6040 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_4               (4L<<4)
6041 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_5               (5L<<4)
6042 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_6               (6L<<4)
6043 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_7               (7L<<4)
6044 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_8               (8L<<4)
6045 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_9               (9L<<4)
6046 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_10              (10L<<4)
6047 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_11              (11L<<4)
6048 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_12              (12L<<4)
6049 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_13              (13L<<4)
6050 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_14              (14L<<4)
6051 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_15              (15L<<4)
6052 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_COUNT                (0xfL<<12)
6053 #define BNX2_CP_CPQ_PFE_PFE_CTL_OFFSET                   (0x1ffL<<16)
6054
6055 #define BNX2_CP_CPQ                                     0x001853c0
6056 #define BNX2_CP_CPQ_FTQ_CMD                             0x001853f8
6057 #define BNX2_CP_CPQ_FTQ_CMD_OFFSET                       (0x3ffL<<0)
6058 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP                       (1L<<10)
6059 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0                     (0L<<10)
6060 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1                     (1L<<10)
6061 #define BNX2_CP_CPQ_FTQ_CMD_SFT_RESET                    (1L<<25)
6062 #define BNX2_CP_CPQ_FTQ_CMD_RD_DATA                      (1L<<26)
6063 #define BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN                 (1L<<27)
6064 #define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA                     (1L<<28)
6065 #define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR                (1L<<29)
6066 #define BNX2_CP_CPQ_FTQ_CMD_POP                          (1L<<30)
6067 #define BNX2_CP_CPQ_FTQ_CMD_BUSY                         (1L<<31)
6068
6069 #define BNX2_CP_CPQ_FTQ_CTL                             0x001853fc
6070 #define BNX2_CP_CPQ_FTQ_CTL_INTERVENE                    (1L<<0)
6071 #define BNX2_CP_CPQ_FTQ_CTL_OVERFLOW                     (1L<<1)
6072 #define BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE              (1L<<2)
6073 #define BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH                    (0x3ffL<<12)
6074 #define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH                    (0x3ffL<<22)
6075
6076 #define BNX2_CP_SCRATCH                                 0x001a0000
6077
6078
6079 /*
6080  *  mcp_reg definition
6081  *  offset: 0x140000
6082  */
6083 #define BNX2_MCP_MCP_CONTROL                            0x00140080
6084 #define BNX2_MCP_MCP_CONTROL_SMBUS_SEL                   (1L<<30)
6085 #define BNX2_MCP_MCP_CONTROL_MCP_ISOLATE                 (1L<<31)
6086
6087 #define BNX2_MCP_MCP_ATTENTION_STATUS                   0x00140084
6088 #define BNX2_MCP_MCP_ATTENTION_STATUS_DRV_DOORBELL       (1L<<29)
6089 #define BNX2_MCP_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT   (1L<<30)
6090 #define BNX2_MCP_MCP_ATTENTION_STATUS_CPU_EVENT          (1L<<31)
6091
6092 #define BNX2_MCP_MCP_HEARTBEAT_CONTROL                  0x00140088
6093 #define BNX2_MCP_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE      (1L<<31)
6094
6095 #define BNX2_MCP_MCP_HEARTBEAT_STATUS                   0x0014008c
6096 #define BNX2_MCP_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD       (0x7ffL<<0)
6097 #define BNX2_MCP_MCP_HEARTBEAT_STATUS_VALID              (1L<<31)
6098
6099 #define BNX2_MCP_MCP_HEARTBEAT                          0x00140090
6100 #define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT       (0x3fffffffL<<0)
6101 #define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_INC         (1L<<30)
6102 #define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET       (1L<<31)
6103
6104 #define BNX2_MCP_WATCHDOG_RESET                         0x00140094
6105 #define BNX2_MCP_WATCHDOG_RESET_WATCHDOG_RESET           (1L<<31)
6106
6107 #define BNX2_MCP_WATCHDOG_CONTROL                       0x00140098
6108 #define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_TIMEOUT       (0xfffffffL<<0)
6109 #define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ATTN          (1L<<29)
6110 #define BNX2_MCP_WATCHDOG_CONTROL_MCP_RST_ENABLE         (1L<<30)
6111 #define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ENABLE        (1L<<31)
6112
6113 #define BNX2_MCP_ACCESS_LOCK                            0x0014009c
6114 #define BNX2_MCP_ACCESS_LOCK_LOCK                        (1L<<31)
6115
6116 #define BNX2_MCP_TOE_ID                                 0x001400a0
6117 #define BNX2_MCP_TOE_ID_FUNCTION_ID                      (1L<<31)
6118
6119 #define BNX2_MCP_MAILBOX_CFG                            0x001400a4
6120 #define BNX2_MCP_MAILBOX_CFG_MAILBOX_OFFSET              (0x3fffL<<0)
6121 #define BNX2_MCP_MAILBOX_CFG_MAILBOX_SIZE                (0xfffL<<20)
6122
6123 #define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC                 0x001400a8
6124 #define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET   (0x3fffL<<0)
6125 #define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE     (0xfffL<<20)
6126
6127 #define BNX2_MCP_MCP_DOORBELL                           0x001400ac
6128 #define BNX2_MCP_MCP_DOORBELL_MCP_DOORBELL               (1L<<31)
6129
6130 #define BNX2_MCP_DRIVER_DOORBELL                        0x001400b0
6131 #define BNX2_MCP_DRIVER_DOORBELL_DRIVER_DOORBELL         (1L<<31)
6132
6133 #define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC             0x001400b4
6134 #define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC_DRIVER_DOORBELL      (1L<<31)
6135
6136 #define BNX2_MCP_CPU_MODE                               0x00145000
6137 #define BNX2_MCP_CPU_MODE_LOCAL_RST                      (1L<<0)
6138 #define BNX2_MCP_CPU_MODE_STEP_ENA                       (1L<<1)
6139 #define BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA                (1L<<2)
6140 #define BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA                (1L<<3)
6141 #define BNX2_MCP_CPU_MODE_MSG_BIT1                       (1L<<6)
6142 #define BNX2_MCP_CPU_MODE_INTERRUPT_ENA                  (1L<<7)
6143 #define BNX2_MCP_CPU_MODE_SOFT_HALT                      (1L<<10)
6144 #define BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA              (1L<<11)
6145 #define BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA              (1L<<12)
6146 #define BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA             (1L<<13)
6147 #define BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA        (1L<<15)
6148
6149 #define BNX2_MCP_CPU_STATE                              0x00145004
6150 #define BNX2_MCP_CPU_STATE_BREAKPOINT                    (1L<<0)
6151 #define BNX2_MCP_CPU_STATE_BAD_INST_HALTED               (1L<<2)
6152 #define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
6153 #define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
6154 #define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
6155 #define BNX2_MCP_CPU_STATE_BAD_PC_HALTED                 (1L<<6)
6156 #define BNX2_MCP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
6157 #define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
6158 #define BNX2_MCP_CPU_STATE_SOFT_HALTED                   (1L<<10)
6159 #define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW                (1L<<11)
6160 #define BNX2_MCP_CPU_STATE_INTERRRUPT                    (1L<<12)
6161 #define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL             (1L<<14)
6162 #define BNX2_MCP_CPU_STATE_INST_FETCH_STALL              (1L<<15)
6163 #define BNX2_MCP_CPU_STATE_BLOCKED_READ                  (1L<<31)
6164
6165 #define BNX2_MCP_CPU_EVENT_MASK                         0x00145008
6166 #define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK          (1L<<0)
6167 #define BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK     (1L<<2)
6168 #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK  (1L<<3)
6169 #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK  (1L<<4)
6170 #define BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK        (1L<<5)
6171 #define BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK       (1L<<6)
6172 #define BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK        (1L<<7)
6173 #define BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK           (1L<<8)
6174 #define BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK         (1L<<10)
6175 #define BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK      (1L<<11)
6176 #define BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK           (1L<<12)
6177
6178 #define BNX2_MCP_CPU_PROGRAM_COUNTER                    0x0014501c
6179 #define BNX2_MCP_CPU_INSTRUCTION                        0x00145020
6180 #define BNX2_MCP_CPU_DATA_ACCESS                        0x00145024
6181 #define BNX2_MCP_CPU_INTERRUPT_ENABLE                   0x00145028
6182 #define BNX2_MCP_CPU_INTERRUPT_VECTOR                   0x0014502c
6183 #define BNX2_MCP_CPU_INTERRUPT_SAVED_PC                 0x00145030
6184 #define BNX2_MCP_CPU_HW_BREAKPOINT                      0x00145034
6185 #define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE               (1L<<0)
6186 #define BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS               (0x3fffffffL<<2)
6187
6188 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK                    0x00145038
6189 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE             (0x7ffL<<0)
6190 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN           (1L<<11)
6191 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL               (0xfL<<12)
6192 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE             (0x7ffL<<16)
6193 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN           (1L<<27)
6194 #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL               (0xfL<<28)
6195
6196 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR                   0x00145048
6197 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE               (1L<<1)
6198 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP          (0L<<1)
6199 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH        (1L<<1)
6200 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
6201
6202 #define BNX2_MCP_CPU_REG_FILE                           0x00145200
6203 #define BNX2_MCP_MCPQ                                   0x001453c0
6204 #define BNX2_MCP_MCPQ_FTQ_CMD                           0x001453f8
6205 #define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET                     (0x3ffL<<0)
6206 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP                     (1L<<10)
6207 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0                   (0L<<10)
6208 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1                   (1L<<10)
6209 #define BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET                  (1L<<25)
6210 #define BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA                    (1L<<26)
6211 #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN               (1L<<27)
6212 #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA                   (1L<<28)
6213 #define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR              (1L<<29)
6214 #define BNX2_MCP_MCPQ_FTQ_CMD_POP                        (1L<<30)
6215 #define BNX2_MCP_MCPQ_FTQ_CMD_BUSY                       (1L<<31)
6216
6217 #define BNX2_MCP_MCPQ_FTQ_CTL                           0x001453fc
6218 #define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE                  (1L<<0)
6219 #define BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW                   (1L<<1)
6220 #define BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE            (1L<<2)
6221 #define BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH                  (0x3ffL<<12)
6222 #define BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH                  (0x3ffL<<22)
6223
6224 #define BNX2_MCP_ROM                                    0x00150000
6225 #define BNX2_MCP_SCRATCH                                0x00160000
6226
6227 #define BNX2_SHM_HDR_SIGNATURE                          BNX2_MCP_SCRATCH
6228 #define BNX2_SHM_HDR_SIGNATURE_SIG_MASK                  0xffff0000
6229 #define BNX2_SHM_HDR_SIGNATURE_SIG                       0x53530000
6230 #define BNX2_SHM_HDR_SIGNATURE_VER_MASK                  0x000000ff
6231 #define BNX2_SHM_HDR_SIGNATURE_VER_ONE                   0x00000001
6232
6233 #define BNX2_SHM_HDR_ADDR_0                             BNX2_MCP_SCRATCH + 4
6234 #define BNX2_SHM_HDR_ADDR_1                             BNX2_MCP_SCRATCH + 8
6235
6236
6237 #define NUM_MC_HASH_REGISTERS   8
6238
6239
6240 /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0.  */
6241 #define PHY_BCM5706_PHY_ID                          0x00206160
6242
6243 #define PHY_ID(id)                                  ((id) & 0xfffffff0)
6244 #define PHY_REV_ID(id)                              ((id) & 0xf)
6245
6246 /* 5708 Serdes PHY registers */
6247
6248 #define BCM5708S_BMCR_FORCE_2500                0x20
6249
6250 #define BCM5708S_UP1                            0xb
6251
6252 #define BCM5708S_UP1_2G5                        0x1
6253
6254 #define BCM5708S_BLK_ADDR                       0x1f
6255
6256 #define BCM5708S_BLK_ADDR_DIG                   0x0000
6257 #define BCM5708S_BLK_ADDR_DIG3                  0x0002
6258 #define BCM5708S_BLK_ADDR_TX_MISC               0x0005
6259
6260 /* Digital Block */
6261 #define BCM5708S_1000X_CTL1                     0x10
6262
6263 #define BCM5708S_1000X_CTL1_FIBER_MODE          0x0001
6264 #define BCM5708S_1000X_CTL1_AUTODET_EN          0x0010
6265
6266 #define BCM5708S_1000X_CTL2                     0x11
6267
6268 #define BCM5708S_1000X_CTL2_PLLEL_DET_EN        0x0001
6269
6270 #define BCM5708S_1000X_STAT1                    0x14
6271
6272 #define BCM5708S_1000X_STAT1_SGMII              0x0001
6273 #define BCM5708S_1000X_STAT1_LINK               0x0002
6274 #define BCM5708S_1000X_STAT1_FD                 0x0004
6275 #define BCM5708S_1000X_STAT1_SPEED_MASK         0x0018
6276 #define BCM5708S_1000X_STAT1_SPEED_10           0x0000
6277 #define BCM5708S_1000X_STAT1_SPEED_100          0x0008
6278 #define BCM5708S_1000X_STAT1_SPEED_1G           0x0010
6279 #define BCM5708S_1000X_STAT1_SPEED_2G5          0x0018
6280 #define BCM5708S_1000X_STAT1_TX_PAUSE           0x0020
6281 #define BCM5708S_1000X_STAT1_RX_PAUSE           0x0040
6282
6283 /* Digital3 Block */
6284 #define BCM5708S_DIG_3_0                        0x10
6285
6286 #define BCM5708S_DIG_3_0_USE_IEEE               0x0001
6287
6288 /* Tx/Misc Block */
6289 #define BCM5708S_TX_ACTL1                       0x15
6290
6291 #define BCM5708S_TX_ACTL1_DRIVER_VCM            0x30
6292
6293 #define BCM5708S_TX_ACTL3                       0x17
6294
6295 #define MII_BNX2_DSP_RW_PORT                    0x15
6296 #define MII_BNX2_DSP_ADDRESS                    0x17
6297 #define MII_BNX2_DSP_EXPAND_REG                  0x0f00
6298
6299 #define MII_BNX2_BLK_ADDR                       0x1f
6300 #define MII_BNX2_BLK_ADDR_IEEE0                  0x0000
6301 #define MII_BNX2_BLK_ADDR_GP_STATUS              0x8120
6302 #define MII_BNX2_GP_TOP_AN_STATUS1                0x1b
6303 #define MII_BNX2_GP_TOP_AN_SPEED_MSK               0x3f00
6304 #define MII_BNX2_GP_TOP_AN_SPEED_10                0x0000
6305 #define MII_BNX2_GP_TOP_AN_SPEED_100               0x0100
6306 #define MII_BNX2_GP_TOP_AN_SPEED_1G                0x0200
6307 #define MII_BNX2_GP_TOP_AN_SPEED_2_5G              0x0300
6308 #define MII_BNX2_GP_TOP_AN_SPEED_1GKV              0x0d00
6309 #define MII_BNX2_GP_TOP_AN_FD                      0x8
6310 #define MII_BNX2_BLK_ADDR_SERDES_DIG             0x8300
6311 #define MII_BNX2_SERDES_DIG_1000XCTL1             0x10
6312 #define MII_BNX2_SD_1000XCTL1_FIBER                0x01
6313 #define MII_BNX2_SD_1000XCTL1_AUTODET              0x10
6314 #define MII_BNX2_SERDES_DIG_MISC1                 0x18
6315 #define MII_BNX2_SD_MISC1_FORCE_MSK                0xf
6316 #define MII_BNX2_SD_MISC1_FORCE_2_5G               0x0
6317 #define MII_BNX2_SD_MISC1_FORCE                    0x10
6318 #define MII_BNX2_BLK_ADDR_OVER1G                 0x8320
6319 #define MII_BNX2_OVER1G_UP1                       0x19
6320 #define MII_BNX2_BLK_ADDR_BAM_NXTPG              0x8350
6321 #define MII_BNX2_BAM_NXTPG_CTL                    0x10
6322 #define MII_BNX2_NXTPG_CTL_BAM                     0x1
6323 #define MII_BNX2_NXTPG_CTL_T2                      0x2
6324 #define MII_BNX2_BLK_ADDR_CL73_USERB0            0x8370
6325 #define MII_BNX2_CL73_BAM_CTL1                    0x12
6326 #define MII_BNX2_CL73_BAM_EN                       0x8000
6327 #define MII_BNX2_CL73_BAM_STA_MGR_EN               0x4000
6328 #define MII_BNX2_CL73_BAM_NP_AFT_BP_EN             0x2000
6329 #define MII_BNX2_BLK_ADDR_AER                    0xffd0
6330 #define MII_BNX2_AER_AER                          0x1e
6331 #define MII_BNX2_AER_AER_AN_MMD                    0x3800
6332 #define MII_BNX2_BLK_ADDR_COMBO_IEEEB0           0xffe0
6333
6334 #define MIN_ETHERNET_PACKET_SIZE        60
6335 #define MAX_ETHERNET_PACKET_SIZE        1514
6336 #define MAX_ETHERNET_JUMBO_PACKET_SIZE  9014
6337
6338 #define RX_COPY_THRESH                  92
6339
6340 #define DMA_READ_CHANS  5
6341 #define DMA_WRITE_CHANS 3
6342
6343 /* Use CPU native page size up to 16K for the ring sizes.  */
6344 #if (PAGE_SHIFT > 14)
6345 #define BCM_PAGE_BITS   14
6346 #else
6347 #define BCM_PAGE_BITS   PAGE_SHIFT
6348 #endif
6349 #define BCM_PAGE_SIZE   (1 << BCM_PAGE_BITS)
6350
6351 #define TX_DESC_CNT  (BCM_PAGE_SIZE / sizeof(struct tx_bd))
6352 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
6353
6354 #define MAX_RX_RINGS    4
6355 #define RX_DESC_CNT  (BCM_PAGE_SIZE / sizeof(struct rx_bd))
6356 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 1)
6357 #define MAX_TOTAL_RX_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_RINGS)
6358
6359 #define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) ==                 \
6360                 (MAX_TX_DESC_CNT - 1)) ?                                \
6361         (x) + 2 : (x) + 1
6362
6363 #define TX_RING_IDX(x) ((x) & MAX_TX_DESC_CNT)
6364
6365 #define NEXT_RX_BD(x) (((x) & (MAX_RX_DESC_CNT - 1)) ==                 \
6366                 (MAX_RX_DESC_CNT - 1)) ?                                \
6367         (x) + 2 : (x) + 1
6368
6369 #define RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx)
6370
6371 #define RX_RING(x) (((x) & ~MAX_RX_DESC_CNT) >> (BCM_PAGE_BITS - 4))
6372 #define RX_IDX(x) ((x) & MAX_RX_DESC_CNT)
6373
6374 /* Context size. */
6375 #define CTX_SHIFT                   7
6376 #define CTX_SIZE                    (1 << CTX_SHIFT)
6377 #define CTX_MASK                    (CTX_SIZE - 1)
6378 #define GET_CID_ADDR(_cid)          ((_cid) << CTX_SHIFT)
6379 #define GET_CID(_cid_addr)          ((_cid_addr) >> CTX_SHIFT)
6380
6381 #define PHY_CTX_SHIFT               6
6382 #define PHY_CTX_SIZE                (1 << PHY_CTX_SHIFT)
6383 #define PHY_CTX_MASK                (PHY_CTX_SIZE - 1)
6384 #define GET_PCID_ADDR(_pcid)        ((_pcid) << PHY_CTX_SHIFT)
6385 #define GET_PCID(_pcid_addr)        ((_pcid_addr) >> PHY_CTX_SHIFT)
6386
6387 #define MB_KERNEL_CTX_SHIFT         8
6388 #define MB_KERNEL_CTX_SIZE          (1 << MB_KERNEL_CTX_SHIFT)
6389 #define MB_KERNEL_CTX_MASK          (MB_KERNEL_CTX_SIZE - 1)
6390 #define MB_GET_CID_ADDR(_cid)       (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
6391
6392 #define MAX_CID_CNT                 0x4000
6393 #define MAX_CID_ADDR                (GET_CID_ADDR(MAX_CID_CNT))
6394 #define INVALID_CID_ADDR            0xffffffff
6395
6396 #define TX_CID          16
6397 #define TX_TSS_CID      32
6398 #define RX_CID          0
6399
6400 #define MB_TX_CID_ADDR  MB_GET_CID_ADDR(TX_CID)
6401 #define MB_RX_CID_ADDR  MB_GET_CID_ADDR(RX_CID)
6402
6403 struct sw_bd {
6404         struct sk_buff          *skb;
6405         DECLARE_PCI_UNMAP_ADDR(mapping)
6406 };
6407
6408 /* Buffered flash (Atmel: AT45DB011B) specific information */
6409 #define SEEPROM_PAGE_BITS                       2
6410 #define SEEPROM_PHY_PAGE_SIZE                   (1 << SEEPROM_PAGE_BITS)
6411 #define SEEPROM_BYTE_ADDR_MASK                  (SEEPROM_PHY_PAGE_SIZE-1)
6412 #define SEEPROM_PAGE_SIZE                       4
6413 #define SEEPROM_TOTAL_SIZE                      65536
6414
6415 #define BUFFERED_FLASH_PAGE_BITS                9
6416 #define BUFFERED_FLASH_PHY_PAGE_SIZE            (1 << BUFFERED_FLASH_PAGE_BITS)
6417 #define BUFFERED_FLASH_BYTE_ADDR_MASK           (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
6418 #define BUFFERED_FLASH_PAGE_SIZE                264
6419 #define BUFFERED_FLASH_TOTAL_SIZE               0x21000
6420
6421 #define SAIFUN_FLASH_PAGE_BITS                  8
6422 #define SAIFUN_FLASH_PHY_PAGE_SIZE              (1 << SAIFUN_FLASH_PAGE_BITS)
6423 #define SAIFUN_FLASH_BYTE_ADDR_MASK             (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
6424 #define SAIFUN_FLASH_PAGE_SIZE                  256
6425 #define SAIFUN_FLASH_BASE_TOTAL_SIZE            65536
6426
6427 #define ST_MICRO_FLASH_PAGE_BITS                8
6428 #define ST_MICRO_FLASH_PHY_PAGE_SIZE            (1 << ST_MICRO_FLASH_PAGE_BITS)
6429 #define ST_MICRO_FLASH_BYTE_ADDR_MASK           (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
6430 #define ST_MICRO_FLASH_PAGE_SIZE                256
6431 #define ST_MICRO_FLASH_BASE_TOTAL_SIZE          65536
6432
6433 #define NVRAM_TIMEOUT_COUNT                     30000
6434
6435
6436 #define FLASH_STRAP_MASK                        (BNX2_NVM_CFG1_FLASH_MODE   | \
6437                                                  BNX2_NVM_CFG1_BUFFER_MODE  | \
6438                                                  BNX2_NVM_CFG1_PROTECT_MODE | \
6439                                                  BNX2_NVM_CFG1_FLASH_SIZE)
6440
6441 #define FLASH_BACKUP_STRAP_MASK                 (0xf << 26)
6442
6443 struct flash_spec {
6444         u32 strapping;
6445         u32 config1;
6446         u32 config2;
6447         u32 config3;
6448         u32 write1;
6449         u32 buffered;
6450         u32 page_bits;
6451         u32 page_size;
6452         u32 addr_mask;
6453         u32 total_size;
6454         u8  *name;
6455 };
6456
6457 struct bnx2 {
6458         /* Fields used in the tx and intr/napi performance paths are grouped */
6459         /* together in the beginning of the structure. */
6460         void __iomem            *regview;
6461
6462         struct net_device       *dev;
6463         struct pci_dev          *pdev;
6464
6465         atomic_t                intr_sem;
6466
6467         struct status_block     *status_blk;
6468         u32                     last_status_idx;
6469
6470         u32                     flags;
6471 #define PCIX_FLAG                       0x00000001
6472 #define PCI_32BIT_FLAG                  0x00000002
6473 #define ONE_TDMA_FLAG                   0x00000004      /* no longer used */
6474 #define NO_WOL_FLAG                     0x00000008
6475 #define USING_MSI_FLAG                  0x00000020
6476 #define ASF_ENABLE_FLAG                 0x00000040
6477 #define MSI_CAP_FLAG                    0x00000080
6478 #define ONE_SHOT_MSI_FLAG               0x00000100
6479 #define PCIE_FLAG                       0x00000200
6480
6481         /* Put tx producer and consumer fields in separate cache lines. */
6482
6483         u32             tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
6484         u16             tx_prod;
6485         u32             tx_bidx_addr;
6486         u32             tx_bseq_addr;
6487
6488         u16             tx_cons __attribute__((aligned(L1_CACHE_BYTES)));
6489         u16             hw_tx_cons;
6490
6491 #ifdef BCM_VLAN
6492         struct                  vlan_group *vlgrp;
6493 #endif
6494
6495         u32                     rx_offset;
6496         u32                     rx_buf_use_size;        /* useable size */
6497         u32                     rx_buf_size;            /* with alignment */
6498         u32                     rx_max_ring_idx;
6499
6500         u32                     rx_prod_bseq;
6501         u16                     rx_prod;
6502         u16                     rx_cons;
6503         u16                     hw_rx_cons;
6504
6505         u32                     rx_csum;
6506
6507         struct sw_bd            *rx_buf_ring;
6508         struct rx_bd            *rx_desc_ring[MAX_RX_RINGS];
6509
6510         /* TX constants */
6511         struct tx_bd    *tx_desc_ring;
6512         struct sw_bd    *tx_buf_ring;
6513         int             tx_ring_size;
6514         u32             tx_wake_thresh;
6515
6516         /* End of fields used in the performance code paths. */
6517
6518         char                    *name;
6519
6520         int                     timer_interval;
6521         int                     current_interval;
6522         struct                  timer_list timer;
6523         struct work_struct      reset_task;
6524         int                     in_reset_task;
6525
6526         /* Used to synchronize phy accesses. */
6527         spinlock_t              phy_lock;
6528         spinlock_t              indirect_lock;
6529
6530         u32                     phy_flags;
6531 #define PHY_SERDES_FLAG                 1
6532 #define PHY_CRC_FIX_FLAG                2
6533 #define PHY_PARALLEL_DETECT_FLAG        4
6534 #define PHY_2_5G_CAPABLE_FLAG           8
6535 #define PHY_INT_MODE_MASK_FLAG          0x300
6536 #define PHY_INT_MODE_AUTO_POLLING_FLAG  0x100
6537 #define PHY_INT_MODE_LINK_READY_FLAG    0x200
6538 #define PHY_DIS_EARLY_DAC_FLAG          0x400
6539
6540         u32                     mii_bmcr;
6541         u32                     mii_bmsr;
6542         u32                     mii_bmsr1;
6543         u32                     mii_adv;
6544         u32                     mii_lpa;
6545         u32                     mii_up1;
6546
6547         u32                     chip_id;
6548         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
6549 #define CHIP_NUM(bp)                    (((bp)->chip_id) & 0xffff0000)
6550 #define CHIP_NUM_5706                   0x57060000
6551 #define CHIP_NUM_5708                   0x57080000
6552 #define CHIP_NUM_5709                   0x57090000
6553
6554 #define CHIP_REV(bp)                    (((bp)->chip_id) & 0x0000f000)
6555 #define CHIP_REV_Ax                     0x00000000
6556 #define CHIP_REV_Bx                     0x00001000
6557 #define CHIP_REV_Cx                     0x00002000
6558
6559 #define CHIP_METAL(bp)                  (((bp)->chip_id) & 0x00000ff0)
6560 #define CHIP_BONDING(bp)                (((bp)->chip_id) & 0x0000000f)
6561
6562 #define CHIP_ID(bp)                     (((bp)->chip_id) & 0xfffffff0)
6563 #define CHIP_ID_5706_A0                 0x57060000
6564 #define CHIP_ID_5706_A1                 0x57060010
6565 #define CHIP_ID_5706_A2                 0x57060020
6566 #define CHIP_ID_5708_A0                 0x57080000
6567 #define CHIP_ID_5708_B0                 0x57081000
6568 #define CHIP_ID_5708_B1                 0x57081010
6569 #define CHIP_ID_5709_A0                 0x57090000
6570 #define CHIP_ID_5709_A1                 0x57090010
6571
6572 #define CHIP_BOND_ID(bp)                (((bp)->chip_id) & 0xf)
6573
6574 /* A serdes chip will have the first bit of the bond id set. */
6575 #define CHIP_BOND_ID_SERDES_BIT         0x01
6576
6577         u32                     phy_addr;
6578         u32                     phy_id;
6579
6580         u16                     bus_speed_mhz;
6581         u8                      wol;
6582
6583         u8                      pad;
6584
6585         u16                     fw_wr_seq;
6586         u16                     fw_drv_pulse_wr_seq;
6587
6588         dma_addr_t              tx_desc_mapping;
6589
6590
6591         int                     rx_max_ring;
6592         int                     rx_ring_size;
6593         dma_addr_t              rx_desc_mapping[MAX_RX_RINGS];
6594
6595         u16                     tx_quick_cons_trip;
6596         u16                     tx_quick_cons_trip_int;
6597         u16                     rx_quick_cons_trip;
6598         u16                     rx_quick_cons_trip_int;
6599         u16                     comp_prod_trip;
6600         u16                     comp_prod_trip_int;
6601         u16                     tx_ticks;
6602         u16                     tx_ticks_int;
6603         u16                     com_ticks;
6604         u16                     com_ticks_int;
6605         u16                     cmd_ticks;
6606         u16                     cmd_ticks_int;
6607         u16                     rx_ticks;
6608         u16                     rx_ticks_int;
6609
6610         u32                     stats_ticks;
6611
6612         dma_addr_t              status_blk_mapping;
6613
6614         struct statistics_block *stats_blk;
6615         dma_addr_t              stats_blk_mapping;
6616
6617         int                     ctx_pages;
6618         void                    *ctx_blk[4];
6619         dma_addr_t              ctx_blk_mapping[4];
6620
6621         u32                     hc_cmd;
6622         u32                     rx_mode;
6623
6624         u16                     req_line_speed;
6625         u8                      req_duplex;
6626
6627         u8                      link_up;
6628
6629         u16                     line_speed;
6630         u8                      duplex;
6631         u8                      flow_ctrl;      /* actual flow ctrl settings */
6632                                                 /* may be different from     */
6633                                                 /* req_flow_ctrl if autoneg  */
6634 #define FLOW_CTRL_TX            1
6635 #define FLOW_CTRL_RX            2
6636
6637         u32                     advertising;
6638
6639         u8                      req_flow_ctrl;  /* flow ctrl advertisement */
6640                                                 /* settings or forced      */
6641                                                 /* settings                */
6642         u8                      autoneg;
6643 #define AUTONEG_SPEED           1
6644 #define AUTONEG_FLOW_CTRL       2
6645
6646         u8                      loopback;
6647 #define MAC_LOOPBACK            1
6648 #define PHY_LOOPBACK            2
6649
6650         u8                      serdes_an_pending;
6651 #define SERDES_AN_TIMEOUT       (HZ / 3)
6652 #define SERDES_FORCED_TIMEOUT   (HZ / 10)
6653
6654         u8                      mac_addr[8];
6655
6656         u32                     shmem_base;
6657
6658         u32                     fw_ver;
6659
6660         int                     pm_cap;
6661         int                     pcix_cap;
6662
6663         struct net_device_stats net_stats;
6664
6665         struct flash_spec       *flash_info;
6666         u32                     flash_size;
6667
6668         int                     status_stats_size;
6669
6670         struct z_stream_s       *strm;
6671         void                    *gunzip_buf;
6672 };
6673
6674 static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset);
6675 static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val);
6676
6677 #define REG_RD(bp, offset)                                      \
6678         readl(bp->regview + offset)
6679
6680 #define REG_WR(bp, offset, val)                                 \
6681         writel(val, bp->regview + offset)
6682
6683 #define REG_WR16(bp, offset, val)                               \
6684         writew(val, bp->regview + offset)
6685
6686 #define REG_RD_IND(bp, offset)                                  \
6687         bnx2_reg_rd_ind(bp, offset)
6688
6689 #define REG_WR_IND(bp, offset, val)                             \
6690         bnx2_reg_wr_ind(bp, offset, val)
6691
6692 /* Indirect context access.  Unlike the MBQ_WR, these macros will not
6693  * trigger a chip event. */
6694 static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val);
6695
6696 #define CTX_WR(bp, cid_addr, offset, val)                       \
6697         bnx2_ctx_wr(bp, cid_addr, offset, val)
6698
6699 struct cpu_reg {
6700         u32 mode;
6701         u32 mode_value_halt;
6702         u32 mode_value_sstep;
6703
6704         u32 state;
6705         u32 state_value_clear;
6706
6707         u32 gpr0;
6708         u32 evmask;
6709         u32 pc;
6710         u32 inst;
6711         u32 bp;
6712
6713         u32 spad_base;
6714
6715         u32 mips_view_base;
6716 };
6717
6718 struct fw_info {
6719         const u32 ver_major;
6720         const u32 ver_minor;
6721         const u32 ver_fix;
6722
6723         const u32 start_addr;
6724
6725         /* Text section. */
6726         const u32 text_addr;
6727         const u32 text_len;
6728         const u32 text_index;
6729         u32 *text;
6730         u8 *gz_text;
6731         const u32 gz_text_len;
6732
6733         /* Data section. */
6734         const u32 data_addr;
6735         const u32 data_len;
6736         const u32 data_index;
6737         const u32 *data;
6738
6739         /* SBSS section. */
6740         const u32 sbss_addr;
6741         const u32 sbss_len;
6742         const u32 sbss_index;
6743         const u32 *sbss;
6744
6745         /* BSS section. */
6746         const u32 bss_addr;
6747         const u32 bss_len;
6748         const u32 bss_index;
6749         const u32 *bss;
6750
6751         /* Read-only section. */
6752         const u32 rodata_addr;
6753         const u32 rodata_len;
6754         const u32 rodata_index;
6755         const u32 *rodata;
6756 };
6757
6758 #define RV2P_PROC1                              0
6759 #define RV2P_PROC2                              1
6760
6761
6762 /* This value (in milliseconds) determines the frequency of the driver
6763  * issuing the PULSE message code.  The firmware monitors this periodic
6764  * pulse to determine when to switch to an OS-absent mode. */
6765 #define DRV_PULSE_PERIOD_MS                 250
6766
6767 /* This value (in milliseconds) determines how long the driver should
6768  * wait for an acknowledgement from the firmware before timing out.  Once
6769  * the firmware has timed out, the driver will assume there is no firmware
6770  * running and there won't be any firmware-driver synchronization during a
6771  * driver reset. */
6772 #define FW_ACK_TIME_OUT_MS                  100
6773
6774
6775 #define BNX2_DRV_RESET_SIGNATURE                0x00000000
6776 #define BNX2_DRV_RESET_SIGNATURE_MAGIC           0x4841564b /* HAVK */
6777 //#define DRV_RESET_SIGNATURE_MAGIC              0x47495352 /* RSIG */
6778
6779 #define BNX2_DRV_MB                             0x00000004
6780 #define BNX2_DRV_MSG_CODE                        0xff000000
6781 #define BNX2_DRV_MSG_CODE_RESET                  0x01000000
6782 #define BNX2_DRV_MSG_CODE_UNLOAD                 0x02000000
6783 #define BNX2_DRV_MSG_CODE_SHUTDOWN               0x03000000
6784 #define BNX2_DRV_MSG_CODE_SUSPEND_WOL            0x04000000
6785 #define BNX2_DRV_MSG_CODE_FW_TIMEOUT             0x05000000
6786 #define BNX2_DRV_MSG_CODE_PULSE                  0x06000000
6787 #define BNX2_DRV_MSG_CODE_DIAG                   0x07000000
6788 #define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL         0x09000000
6789 #define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN          0x0b000000
6790
6791 #define BNX2_DRV_MSG_DATA                        0x00ff0000
6792 #define BNX2_DRV_MSG_DATA_WAIT0                  0x00010000
6793 #define BNX2_DRV_MSG_DATA_WAIT1                  0x00020000
6794 #define BNX2_DRV_MSG_DATA_WAIT2                  0x00030000
6795 #define BNX2_DRV_MSG_DATA_WAIT3                  0x00040000
6796
6797 #define BNX2_DRV_MSG_SEQ                         0x0000ffff
6798
6799 #define BNX2_FW_MB                              0x00000008
6800 #define BNX2_FW_MSG_ACK                          0x0000ffff
6801 #define BNX2_FW_MSG_STATUS_MASK                  0x00ff0000
6802 #define BNX2_FW_MSG_STATUS_OK                    0x00000000
6803 #define BNX2_FW_MSG_STATUS_FAILURE               0x00ff0000
6804
6805 #define BNX2_LINK_STATUS                        0x0000000c
6806 #define BNX2_LINK_STATUS_INIT_VALUE              0xffffffff
6807 #define BNX2_LINK_STATUS_LINK_UP                 0x1
6808 #define BNX2_LINK_STATUS_LINK_DOWN               0x0
6809 #define BNX2_LINK_STATUS_SPEED_MASK              0x1e
6810 #define BNX2_LINK_STATUS_AN_INCOMPLETE           (0<<1)
6811 #define BNX2_LINK_STATUS_10HALF                  (1<<1)
6812 #define BNX2_LINK_STATUS_10FULL                  (2<<1)
6813 #define BNX2_LINK_STATUS_100HALF                 (3<<1)
6814 #define BNX2_LINK_STATUS_100BASE_T4              (4<<1)
6815 #define BNX2_LINK_STATUS_100FULL                 (5<<1)
6816 #define BNX2_LINK_STATUS_1000HALF                (6<<1)
6817 #define BNX2_LINK_STATUS_1000FULL                (7<<1)
6818 #define BNX2_LINK_STATUS_2500HALF                (8<<1)
6819 #define BNX2_LINK_STATUS_2500FULL                (9<<1)
6820 #define BNX2_LINK_STATUS_AN_ENABLED              (1<<5)
6821 #define BNX2_LINK_STATUS_AN_COMPLETE             (1<<6)
6822 #define BNX2_LINK_STATUS_PARALLEL_DET            (1<<7)
6823 #define BNX2_LINK_STATUS_RESERVED                (1<<8)
6824 #define BNX2_LINK_STATUS_PARTNER_AD_1000FULL     (1<<9)
6825 #define BNX2_LINK_STATUS_PARTNER_AD_1000HALF     (1<<10)
6826 #define BNX2_LINK_STATUS_PARTNER_AD_100BT4       (1<<11)
6827 #define BNX2_LINK_STATUS_PARTNER_AD_100FULL      (1<<12)
6828 #define BNX2_LINK_STATUS_PARTNER_AD_100HALF      (1<<13)
6829 #define BNX2_LINK_STATUS_PARTNER_AD_10FULL       (1<<14)
6830 #define BNX2_LINK_STATUS_PARTNER_AD_10HALF       (1<<15)
6831 #define BNX2_LINK_STATUS_TX_FC_ENABLED           (1<<16)
6832 #define BNX2_LINK_STATUS_RX_FC_ENABLED           (1<<17)
6833 #define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP   (1<<18)
6834 #define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP  (1<<19)
6835 #define BNX2_LINK_STATUS_SERDES_LINK             (1<<20)
6836 #define BNX2_LINK_STATUS_PARTNER_AD_2500FULL     (1<<21)
6837 #define BNX2_LINK_STATUS_PARTNER_AD_2500HALF     (1<<22)
6838
6839 #define BNX2_DRV_PULSE_MB                       0x00000010
6840 #define BNX2_DRV_PULSE_SEQ_MASK                  0x00007fff
6841
6842 /* Indicate to the firmware not to go into the
6843  * OS absent when it is not getting driver pulse.
6844  * This is used for debugging. */
6845 #define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE        0x00080000
6846
6847 #define BNX2_DEV_INFO_SIGNATURE                 0x00000020
6848 #define BNX2_DEV_INFO_SIGNATURE_MAGIC            0x44564900
6849 #define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK       0xffffff00
6850 #define BNX2_DEV_INFO_FEATURE_CFG_VALID          0x01
6851 #define BNX2_DEV_INFO_SECONDARY_PORT             0x80
6852 #define BNX2_DEV_INFO_DRV_ALWAYS_ALIVE           0x40
6853
6854 #define BNX2_SHARED_HW_CFG_PART_NUM             0x00000024
6855
6856 #define BNX2_SHARED_HW_CFG_POWER_DISSIPATED     0x00000034
6857 #define BNX2_SHARED_HW_CFG_POWER_STATE_D3_MASK   0xff000000
6858 #define BNX2_SHARED_HW_CFG_POWER_STATE_D2_MASK   0xff0000
6859 #define BNX2_SHARED_HW_CFG_POWER_STATE_D1_MASK   0xff00
6860 #define BNX2_SHARED_HW_CFG_POWER_STATE_D0_MASK   0xff
6861
6862 #define BNX2_SHARED_HW_CFG POWER_CONSUMED       0x00000038
6863 #define BNX2_SHARED_HW_CFG_CONFIG               0x0000003c
6864 #define BNX2_SHARED_HW_CFG_DESIGN_NIC            0
6865 #define BNX2_SHARED_HW_CFG_DESIGN_LOM            0x1
6866 #define BNX2_SHARED_HW_CFG_PHY_COPPER            0
6867 #define BNX2_SHARED_HW_CFG_PHY_FIBER             0x2
6868 #define BNX2_SHARED_HW_CFG_PHY_2_5G              0x20
6869 #define BNX2_SHARED_HW_CFG_PHY_BACKPLANE         0x40
6870 #define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS   8
6871 #define BNX2_SHARED_HW_CFG_LED_MODE_MASK         0x300
6872 #define BNX2_SHARED_HW_CFG_LED_MODE_MAC          0
6873 #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1        0x100
6874 #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2        0x200
6875
6876 #define BNX2_SHARED_HW_CFG_CONFIG2              0x00000040
6877 #define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK        0x00fff000
6878
6879 #define BNX2_DEV_INFO_BC_REV                    0x0000004c
6880
6881 #define BNX2_PORT_HW_CFG_MAC_UPPER              0x00000050
6882 #define BNX2_PORT_HW_CFG_UPPERMAC_MASK           0xffff
6883
6884 #define BNX2_PORT_HW_CFG_MAC_LOWER              0x00000054
6885 #define BNX2_PORT_HW_CFG_CONFIG                 0x00000058
6886 #define BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK         0x0000ffff
6887 #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK      0x001f0000
6888 #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN        0x00000000
6889 #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G        0x00030000
6890 #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_2_5G      0x00040000
6891
6892 #define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER        0x00000068
6893 #define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER        0x0000006c
6894 #define BNX2_PORT_HW_CFG_IMD_MAC_B_UPPER        0x00000070
6895 #define BNX2_PORT_HW_CFG_IMD_MAC_B_LOWER        0x00000074
6896 #define BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER        0x00000078
6897 #define BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER        0x0000007c
6898
6899 #define BNX2_DEV_INFO_PER_PORT_HW_CONFIG2       0x000000b4
6900
6901 #define BNX2_DEV_INFO_FORMAT_REV                0x000000c4
6902 #define BNX2_DEV_INFO_FORMAT_REV_MASK            0xff000000
6903 #define BNX2_DEV_INFO_FORMAT_REV_ID              ('A' << 24)
6904
6905 #define BNX2_SHARED_FEATURE                     0x000000c8
6906 #define BNX2_SHARED_FEATURE_MASK                 0xffffffff
6907
6908 #define BNX2_PORT_FEATURE                       0x000000d8
6909 #define BNX2_PORT2_FEATURE                      0x00000014c
6910 #define BNX2_PORT_FEATURE_WOL_ENABLED            0x01000000
6911 #define BNX2_PORT_FEATURE_MBA_ENABLED            0x02000000
6912 #define BNX2_PORT_FEATURE_ASF_ENABLED            0x04000000
6913 #define BNX2_PORT_FEATURE_IMD_ENABLED            0x08000000
6914 #define BNX2_PORT_FEATURE_BAR1_SIZE_MASK         0xf
6915 #define BNX2_PORT_FEATURE_BAR1_SIZE_DISABLED     0x0
6916 #define BNX2_PORT_FEATURE_BAR1_SIZE_64K          0x1
6917 #define BNX2_PORT_FEATURE_BAR1_SIZE_128K         0x2
6918 #define BNX2_PORT_FEATURE_BAR1_SIZE_256K         0x3
6919 #define BNX2_PORT_FEATURE_BAR1_SIZE_512K         0x4
6920 #define BNX2_PORT_FEATURE_BAR1_SIZE_1M           0x5
6921 #define BNX2_PORT_FEATURE_BAR1_SIZE_2M           0x6
6922 #define BNX2_PORT_FEATURE_BAR1_SIZE_4M           0x7
6923 #define BNX2_PORT_FEATURE_BAR1_SIZE_8M           0x8
6924 #define BNX2_PORT_FEATURE_BAR1_SIZE_16M          0x9
6925 #define BNX2_PORT_FEATURE_BAR1_SIZE_32M          0xa
6926 #define BNX2_PORT_FEATURE_BAR1_SIZE_64M          0xb
6927 #define BNX2_PORT_FEATURE_BAR1_SIZE_128M         0xc
6928 #define BNX2_PORT_FEATURE_BAR1_SIZE_256M         0xd
6929 #define BNX2_PORT_FEATURE_BAR1_SIZE_512M         0xe
6930 #define BNX2_PORT_FEATURE_BAR1_SIZE_1G           0xf
6931
6932 #define BNX2_PORT_FEATURE_WOL                   0xdc
6933 #define BNX2_PORT2_FEATURE_WOL                  0x150
6934 #define BNX2_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS         4
6935 #define BNX2_PORT_FEATURE_WOL_DEFAULT_MASK       0x30
6936 #define BNX2_PORT_FEATURE_WOL_DEFAULT_DISABLE    0
6937 #define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC      0x10
6938 #define BNX2_PORT_FEATURE_WOL_DEFAULT_ACPI       0x20
6939 #define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI     0x30
6940 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_MASK    0xf
6941 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG         0
6942 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10HALF  1
6943 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10FULL  2
6944 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3
6945 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4
6946 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000HALF        5
6947 #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000FULL        6
6948 #define BNX2_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000     0x40
6949 #define BNX2_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
6950 #define BNX2_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP    0x800
6951
6952 #define BNX2_PORT_FEATURE_MBA                   0xe0
6953 #define BNX2_PORT2_FEATURE_MBA                  0x154
6954 #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS         0
6955 #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x3
6956 #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE        0
6957 #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL        1
6958 #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP      2
6959 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS      2
6960 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_MASK    0x3c
6961 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG         0
6962 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10HALF  0x4
6963 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10FULL  0x8
6964 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100HALF         0xc
6965 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100FULL         0x10
6966 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000HALF        0x14
6967 #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000FULL        0x18
6968 #define BNX2_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x40
6969 #define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_S      0
6970 #define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_B      0x80
6971 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS    8
6972 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK  0xff00
6973 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED      0
6974 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K    0x100
6975 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K    0x200
6976 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K    0x300
6977 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K    0x400
6978 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K   0x500
6979 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K   0x600
6980 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K   0x700
6981 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K  0x800
6982 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K  0x900
6983 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K  0xa00
6984 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M    0xb00
6985 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M    0xc00
6986 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M    0xd00
6987 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M    0xe00
6988 #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M   0xf00
6989 #define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS     16
6990 #define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK   0xf0000
6991 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS  20
6992 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x300000
6993 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO        0
6994 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS         0x100000
6995 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H      0x200000
6996 #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H      0x300000
6997
6998 #define BNX2_PORT_FEATURE_IMD                   0xe4
6999 #define BNX2_PORT2_FEATURE_IMD                  0x158
7000 #define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT      0
7001 #define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE       1
7002
7003 #define BNX2_PORT_FEATURE_VLAN                  0xe8
7004 #define BNX2_PORT2_FEATURE_VLAN                 0x15c
7005 #define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK      0xffff
7006 #define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE        0x10000
7007
7008 #define BNX2_BC_STATE_RESET_TYPE                0x000001c0
7009 #define BNX2_BC_STATE_RESET_TYPE_SIG             0x00005254
7010 #define BNX2_BC_STATE_RESET_TYPE_SIG_MASK        0x0000ffff
7011 #define BNX2_BC_STATE_RESET_TYPE_NONE    (BNX2_BC_STATE_RESET_TYPE_SIG | \
7012                                           0x00010000)
7013 #define BNX2_BC_STATE_RESET_TYPE_PCI     (BNX2_BC_STATE_RESET_TYPE_SIG | \
7014                                           0x00020000)
7015 #define BNX2_BC_STATE_RESET_TYPE_VAUX    (BNX2_BC_STATE_RESET_TYPE_SIG | \
7016                                           0x00030000)
7017 #define BNX2_BC_STATE_RESET_TYPE_DRV_MASK        DRV_MSG_CODE
7018 #define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \
7019                                             DRV_MSG_CODE_RESET)
7020 #define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \
7021                                              DRV_MSG_CODE_UNLOAD)
7022 #define BNX2_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX2_BC_STATE_RESET_TYPE_SIG | \
7023                                                DRV_MSG_CODE_SHUTDOWN)
7024 #define BNX2_BC_STATE_RESET_TYPE_DRV_WOL (BNX2_BC_STATE_RESET_TYPE_SIG | \
7025                                           DRV_MSG_CODE_WOL)
7026 #define BNX2_BC_STATE_RESET_TYPE_DRV_DIAG (BNX2_BC_STATE_RESET_TYPE_SIG | \
7027                                            DRV_MSG_CODE_DIAG)
7028 #define BNX2_BC_STATE_RESET_TYPE_VALUE(msg) (BNX2_BC_STATE_RESET_TYPE_SIG | \
7029                                              (msg))
7030
7031 #define BNX2_BC_STATE                           0x000001c4
7032 #define BNX2_BC_STATE_ERR_MASK                   0x0000ff00
7033 #define BNX2_BC_STATE_SIGN                       0x42530000
7034 #define BNX2_BC_STATE_SIGN_MASK                  0xffff0000
7035 #define BNX2_BC_STATE_BC1_START                  (BNX2_BC_STATE_SIGN | 0x1)
7036 #define BNX2_BC_STATE_GET_NVM_CFG1               (BNX2_BC_STATE_SIGN | 0x2)
7037 #define BNX2_BC_STATE_PROG_BAR                   (BNX2_BC_STATE_SIGN | 0x3)
7038 #define BNX2_BC_STATE_INIT_VID                   (BNX2_BC_STATE_SIGN | 0x4)
7039 #define BNX2_BC_STATE_GET_NVM_CFG2               (BNX2_BC_STATE_SIGN | 0x5)
7040 #define BNX2_BC_STATE_APPLY_WKARND               (BNX2_BC_STATE_SIGN | 0x6)
7041 #define BNX2_BC_STATE_LOAD_BC2                   (BNX2_BC_STATE_SIGN | 0x7)
7042 #define BNX2_BC_STATE_GOING_BC2                  (BNX2_BC_STATE_SIGN | 0x8)
7043 #define BNX2_BC_STATE_GOING_DIAG                 (BNX2_BC_STATE_SIGN | 0x9)
7044 #define BNX2_BC_STATE_RT_FINAL_INIT              (BNX2_BC_STATE_SIGN | 0x81)
7045 #define BNX2_BC_STATE_RT_WKARND                  (BNX2_BC_STATE_SIGN | 0x82)
7046 #define BNX2_BC_STATE_RT_DRV_PULSE               (BNX2_BC_STATE_SIGN | 0x83)
7047 #define BNX2_BC_STATE_RT_FIOEVTS                 (BNX2_BC_STATE_SIGN | 0x84)
7048 #define BNX2_BC_STATE_RT_DRV_CMD                 (BNX2_BC_STATE_SIGN | 0x85)
7049 #define BNX2_BC_STATE_RT_LOW_POWER               (BNX2_BC_STATE_SIGN | 0x86)
7050 #define BNX2_BC_STATE_RT_SET_WOL                 (BNX2_BC_STATE_SIGN | 0x87)
7051 #define BNX2_BC_STATE_RT_OTHER_FW                (BNX2_BC_STATE_SIGN | 0x88)
7052 #define BNX2_BC_STATE_RT_GOING_D3                (BNX2_BC_STATE_SIGN | 0x89)
7053 #define BNX2_BC_STATE_ERR_BAD_VERSION            (BNX2_BC_STATE_SIGN | 0x0100)
7054 #define BNX2_BC_STATE_ERR_BAD_BC2_CRC            (BNX2_BC_STATE_SIGN | 0x0200)
7055 #define BNX2_BC_STATE_ERR_BC1_LOOP               (BNX2_BC_STATE_SIGN | 0x0300)
7056 #define BNX2_BC_STATE_ERR_UNKNOWN_CMD            (BNX2_BC_STATE_SIGN | 0x0400)
7057 #define BNX2_BC_STATE_ERR_DRV_DEAD               (BNX2_BC_STATE_SIGN | 0x0500)
7058 #define BNX2_BC_STATE_ERR_NO_RXP                 (BNX2_BC_STATE_SIGN | 0x0600)
7059 #define BNX2_BC_STATE_ERR_TOO_MANY_RBUF          (BNX2_BC_STATE_SIGN | 0x0700)
7060
7061 #define BNX2_BC_STATE_DEBUG_CMD                 0x1dc
7062 #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE       0x42440000
7063 #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK  0xffff0000
7064 #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK   0xffff
7065 #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE   0xffff
7066
7067 #define HOST_VIEW_SHMEM_BASE                    0x167c00
7068
7069 #endif