54ce11afd9fe829a889648154f0e5c807a5c75c6
[sfrench/cifs-2.6.git] / drivers / net / bnx2.h
1 /* bnx2.h: Broadcom NX2 network driver.
2  *
3  * Copyright (c) 2004-2007 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Written by: Michael Chan  (mchan@broadcom.com)
10  */
11
12
13 #ifndef BNX2_H
14 #define BNX2_H
15
16 /* Hardware data structures and register definitions automatically
17  * generated from RTL code. Do not modify.
18  */
19
20 /*
21  *  tx_bd definition
22  */
23 struct tx_bd {
24         u32 tx_bd_haddr_hi;
25         u32 tx_bd_haddr_lo;
26         u32 tx_bd_mss_nbytes;
27                 #define TX_BD_TCP6_OFF2_SHL             (14)
28         u32 tx_bd_vlan_tag_flags;
29                 #define TX_BD_FLAGS_CONN_FAULT          (1<<0)
30                 #define TX_BD_FLAGS_TCP6_OFF0_MSK       (3<<1)
31                 #define TX_BD_FLAGS_TCP6_OFF0_SHL       (1)
32                 #define TX_BD_FLAGS_TCP_UDP_CKSUM       (1<<1)
33                 #define TX_BD_FLAGS_IP_CKSUM            (1<<2)
34                 #define TX_BD_FLAGS_VLAN_TAG            (1<<3)
35                 #define TX_BD_FLAGS_COAL_NOW            (1<<4)
36                 #define TX_BD_FLAGS_DONT_GEN_CRC        (1<<5)
37                 #define TX_BD_FLAGS_END                 (1<<6)
38                 #define TX_BD_FLAGS_START               (1<<7)
39                 #define TX_BD_FLAGS_SW_OPTION_WORD      (0x1f<<8)
40                 #define TX_BD_FLAGS_TCP6_OFF4_SHL       (12)
41                 #define TX_BD_FLAGS_SW_FLAGS            (1<<13)
42                 #define TX_BD_FLAGS_SW_SNAP             (1<<14)
43                 #define TX_BD_FLAGS_SW_LSO              (1<<15)
44
45 };
46
47
48 /*
49  *  rx_bd definition
50  */
51 struct rx_bd {
52         u32 rx_bd_haddr_hi;
53         u32 rx_bd_haddr_lo;
54         u32 rx_bd_len;
55         u32 rx_bd_flags;
56                 #define RX_BD_FLAGS_NOPUSH              (1<<0)
57                 #define RX_BD_FLAGS_DUMMY               (1<<1)
58                 #define RX_BD_FLAGS_END                 (1<<2)
59                 #define RX_BD_FLAGS_START               (1<<3)
60
61 };
62
63 #define BNX2_RX_ALIGN                   16
64
65 /*
66  *  status_block definition
67  */
68 struct status_block {
69         u32 status_attn_bits;
70                 #define STATUS_ATTN_BITS_LINK_STATE             (1L<<0)
71                 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT     (1L<<1)
72                 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT       (1L<<2)
73                 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT      (1L<<3)
74                 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT     (1L<<4)
75                 #define STATUS_ATTN_BITS_TX_DMA_ABORT           (1L<<5)
76                 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT       (1L<<6)
77                 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT     (1L<<7)
78                 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT    (1L<<8)
79                 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT        (1L<<9)
80                 #define STATUS_ATTN_BITS_RX_MBUF_ABORT          (1L<<10)
81                 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT        (1L<<11)
82                 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT     (1L<<12)
83                 #define STATUS_ATTN_BITS_RX_V2P_ABORT           (1L<<13)
84                 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT      (1L<<14)
85                 #define STATUS_ATTN_BITS_RX_DMA_ABORT           (1L<<15)
86                 #define STATUS_ATTN_BITS_COMPLETION_ABORT       (1L<<16)
87                 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT    (1L<<17)
88                 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT    (1L<<18)
89                 #define STATUS_ATTN_BITS_CONTEXT_ABORT          (1L<<19)
90                 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT    (1L<<20)
91                 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT    (1L<<21)
92                 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT   (1L<<22)
93                 #define STATUS_ATTN_BITS_MAC_ABORT              (1L<<23)
94                 #define STATUS_ATTN_BITS_TIMER_ABORT            (1L<<24)
95                 #define STATUS_ATTN_BITS_DMAE_ABORT             (1L<<25)
96                 #define STATUS_ATTN_BITS_FLSH_ABORT             (1L<<26)
97                 #define STATUS_ATTN_BITS_GRC_ABORT              (1L<<27)
98                 #define STATUS_ATTN_BITS_EPB_ERROR              (1L<<30)
99                 #define STATUS_ATTN_BITS_PARITY_ERROR           (1L<<31)
100
101         u32 status_attn_bits_ack;
102 #if defined(__BIG_ENDIAN)
103         u16 status_tx_quick_consumer_index0;
104         u16 status_tx_quick_consumer_index1;
105         u16 status_tx_quick_consumer_index2;
106         u16 status_tx_quick_consumer_index3;
107         u16 status_rx_quick_consumer_index0;
108         u16 status_rx_quick_consumer_index1;
109         u16 status_rx_quick_consumer_index2;
110         u16 status_rx_quick_consumer_index3;
111         u16 status_rx_quick_consumer_index4;
112         u16 status_rx_quick_consumer_index5;
113         u16 status_rx_quick_consumer_index6;
114         u16 status_rx_quick_consumer_index7;
115         u16 status_rx_quick_consumer_index8;
116         u16 status_rx_quick_consumer_index9;
117         u16 status_rx_quick_consumer_index10;
118         u16 status_rx_quick_consumer_index11;
119         u16 status_rx_quick_consumer_index12;
120         u16 status_rx_quick_consumer_index13;
121         u16 status_rx_quick_consumer_index14;
122         u16 status_rx_quick_consumer_index15;
123         u16 status_completion_producer_index;
124         u16 status_cmd_consumer_index;
125         u16 status_idx;
126         u8 status_unused;
127         u8 status_blk_num;
128 #elif defined(__LITTLE_ENDIAN)
129         u16 status_tx_quick_consumer_index1;
130         u16 status_tx_quick_consumer_index0;
131         u16 status_tx_quick_consumer_index3;
132         u16 status_tx_quick_consumer_index2;
133         u16 status_rx_quick_consumer_index1;
134         u16 status_rx_quick_consumer_index0;
135         u16 status_rx_quick_consumer_index3;
136         u16 status_rx_quick_consumer_index2;
137         u16 status_rx_quick_consumer_index5;
138         u16 status_rx_quick_consumer_index4;
139         u16 status_rx_quick_consumer_index7;
140         u16 status_rx_quick_consumer_index6;
141         u16 status_rx_quick_consumer_index9;
142         u16 status_rx_quick_consumer_index8;
143         u16 status_rx_quick_consumer_index11;
144         u16 status_rx_quick_consumer_index10;
145         u16 status_rx_quick_consumer_index13;
146         u16 status_rx_quick_consumer_index12;
147         u16 status_rx_quick_consumer_index15;
148         u16 status_rx_quick_consumer_index14;
149         u16 status_cmd_consumer_index;
150         u16 status_completion_producer_index;
151         u8 status_blk_num;
152         u8 status_unused;
153         u16 status_idx;
154 #endif
155 };
156
157 /*
158  *  status_block definition
159  */
160 struct status_block_msix {
161 #if defined(__BIG_ENDIAN)
162         u16 status_tx_quick_consumer_index;
163         u16 status_rx_quick_consumer_index;
164         u16 status_completion_producer_index;
165         u16 status_cmd_consumer_index;
166         u32 status_unused;
167         u16 status_idx;
168         u8 status_unused2;
169         u8 status_blk_num;
170 #elif defined(__LITTLE_ENDIAN)
171         u16 status_rx_quick_consumer_index;
172         u16 status_tx_quick_consumer_index;
173         u16 status_cmd_consumer_index;
174         u16 status_completion_producer_index;
175         u32 status_unused;
176         u8 status_blk_num;
177         u8 status_unused2;
178         u16 status_idx;
179 #endif
180 };
181
182 #define BNX2_SBLK_MSIX_ALIGN_SIZE       128
183
184
185 /*
186  *  statistics_block definition
187  */
188 struct statistics_block {
189         u32 stat_IfHCInOctets_hi;
190         u32 stat_IfHCInOctets_lo;
191         u32 stat_IfHCInBadOctets_hi;
192         u32 stat_IfHCInBadOctets_lo;
193         u32 stat_IfHCOutOctets_hi;
194         u32 stat_IfHCOutOctets_lo;
195         u32 stat_IfHCOutBadOctets_hi;
196         u32 stat_IfHCOutBadOctets_lo;
197         u32 stat_IfHCInUcastPkts_hi;
198         u32 stat_IfHCInUcastPkts_lo;
199         u32 stat_IfHCInMulticastPkts_hi;
200         u32 stat_IfHCInMulticastPkts_lo;
201         u32 stat_IfHCInBroadcastPkts_hi;
202         u32 stat_IfHCInBroadcastPkts_lo;
203         u32 stat_IfHCOutUcastPkts_hi;
204         u32 stat_IfHCOutUcastPkts_lo;
205         u32 stat_IfHCOutMulticastPkts_hi;
206         u32 stat_IfHCOutMulticastPkts_lo;
207         u32 stat_IfHCOutBroadcastPkts_hi;
208         u32 stat_IfHCOutBroadcastPkts_lo;
209         u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
210         u32 stat_Dot3StatsCarrierSenseErrors;
211         u32 stat_Dot3StatsFCSErrors;
212         u32 stat_Dot3StatsAlignmentErrors;
213         u32 stat_Dot3StatsSingleCollisionFrames;
214         u32 stat_Dot3StatsMultipleCollisionFrames;
215         u32 stat_Dot3StatsDeferredTransmissions;
216         u32 stat_Dot3StatsExcessiveCollisions;
217         u32 stat_Dot3StatsLateCollisions;
218         u32 stat_EtherStatsCollisions;
219         u32 stat_EtherStatsFragments;
220         u32 stat_EtherStatsJabbers;
221         u32 stat_EtherStatsUndersizePkts;
222         u32 stat_EtherStatsOverrsizePkts;
223         u32 stat_EtherStatsPktsRx64Octets;
224         u32 stat_EtherStatsPktsRx65Octetsto127Octets;
225         u32 stat_EtherStatsPktsRx128Octetsto255Octets;
226         u32 stat_EtherStatsPktsRx256Octetsto511Octets;
227         u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
228         u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
229         u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
230         u32 stat_EtherStatsPktsTx64Octets;
231         u32 stat_EtherStatsPktsTx65Octetsto127Octets;
232         u32 stat_EtherStatsPktsTx128Octetsto255Octets;
233         u32 stat_EtherStatsPktsTx256Octetsto511Octets;
234         u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
235         u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
236         u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
237         u32 stat_XonPauseFramesReceived;
238         u32 stat_XoffPauseFramesReceived;
239         u32 stat_OutXonSent;
240         u32 stat_OutXoffSent;
241         u32 stat_FlowControlDone;
242         u32 stat_MacControlFramesReceived;
243         u32 stat_XoffStateEntered;
244         u32 stat_IfInFramesL2FilterDiscards;
245         u32 stat_IfInRuleCheckerDiscards;
246         u32 stat_IfInFTQDiscards;
247         u32 stat_IfInMBUFDiscards;
248         u32 stat_IfInRuleCheckerP4Hit;
249         u32 stat_CatchupInRuleCheckerDiscards;
250         u32 stat_CatchupInFTQDiscards;
251         u32 stat_CatchupInMBUFDiscards;
252         u32 stat_CatchupInRuleCheckerP4Hit;
253         u32 stat_GenStat00;
254         u32 stat_GenStat01;
255         u32 stat_GenStat02;
256         u32 stat_GenStat03;
257         u32 stat_GenStat04;
258         u32 stat_GenStat05;
259         u32 stat_GenStat06;
260         u32 stat_GenStat07;
261         u32 stat_GenStat08;
262         u32 stat_GenStat09;
263         u32 stat_GenStat10;
264         u32 stat_GenStat11;
265         u32 stat_GenStat12;
266         u32 stat_GenStat13;
267         u32 stat_GenStat14;
268         u32 stat_GenStat15;
269         u32 stat_FwRxDrop;
270 };
271
272
273 /*
274  *  l2_fhdr definition
275  */
276 struct l2_fhdr {
277         u32 l2_fhdr_status;
278                 #define L2_FHDR_STATUS_RULE_CLASS       (0x7<<0)
279                 #define L2_FHDR_STATUS_RULE_P2          (1<<3)
280                 #define L2_FHDR_STATUS_RULE_P3          (1<<4)
281                 #define L2_FHDR_STATUS_RULE_P4          (1<<5)
282                 #define L2_FHDR_STATUS_L2_VLAN_TAG      (1<<6)
283                 #define L2_FHDR_STATUS_L2_LLC_SNAP      (1<<7)
284                 #define L2_FHDR_STATUS_RSS_HASH         (1<<8)
285                 #define L2_FHDR_STATUS_IP_DATAGRAM      (1<<13)
286                 #define L2_FHDR_STATUS_TCP_SEGMENT      (1<<14)
287                 #define L2_FHDR_STATUS_UDP_DATAGRAM     (1<<15)
288
289                 #define L2_FHDR_STATUS_SPLIT            (1<<16)
290                 #define L2_FHDR_ERRORS_BAD_CRC          (1<<17)
291                 #define L2_FHDR_ERRORS_PHY_DECODE       (1<<18)
292                 #define L2_FHDR_ERRORS_ALIGNMENT        (1<<19)
293                 #define L2_FHDR_ERRORS_TOO_SHORT        (1<<20)
294                 #define L2_FHDR_ERRORS_GIANT_FRAME      (1<<21)
295                 #define L2_FHDR_ERRORS_TCP_XSUM         (1<<28)
296                 #define L2_FHDR_ERRORS_UDP_XSUM         (1<<31)
297
298         u32 l2_fhdr_hash;
299 #if defined(__BIG_ENDIAN)
300         u16 l2_fhdr_pkt_len;
301         u16 l2_fhdr_vlan_tag;
302         u16 l2_fhdr_ip_xsum;
303         u16 l2_fhdr_tcp_udp_xsum;
304 #elif defined(__LITTLE_ENDIAN)
305         u16 l2_fhdr_vlan_tag;
306         u16 l2_fhdr_pkt_len;
307         u16 l2_fhdr_tcp_udp_xsum;
308         u16 l2_fhdr_ip_xsum;
309 #endif
310 };
311
312
313 /*
314  *  l2_context definition
315  */
316 #define BNX2_L2CTX_TYPE                                 0x00000000
317 #define BNX2_L2CTX_TYPE_SIZE_L2                          ((0xc0/0x20)<<16)
318 #define BNX2_L2CTX_TYPE_TYPE                             (0xf<<28)
319 #define BNX2_L2CTX_TYPE_TYPE_EMPTY                       (0<<28)
320 #define BNX2_L2CTX_TYPE_TYPE_L2                          (1<<28)
321
322 #define BNX2_L2CTX_TX_HOST_BIDX                         0x00000088
323 #define BNX2_L2CTX_EST_NBD                              0x00000088
324 #define BNX2_L2CTX_CMD_TYPE                             0x00000088
325 #define BNX2_L2CTX_CMD_TYPE_TYPE                         (0xf<<24)
326 #define BNX2_L2CTX_CMD_TYPE_TYPE_L2                      (0<<24)
327 #define BNX2_L2CTX_CMD_TYPE_TYPE_TCP                     (1<<24)
328
329 #define BNX2_L2CTX_TX_HOST_BSEQ                         0x00000090
330 #define BNX2_L2CTX_TSCH_BSEQ                            0x00000094
331 #define BNX2_L2CTX_TBDR_BSEQ                            0x00000098
332 #define BNX2_L2CTX_TBDR_BOFF                            0x0000009c
333 #define BNX2_L2CTX_TBDR_BIDX                            0x0000009c
334 #define BNX2_L2CTX_TBDR_BHADDR_HI                       0x000000a0
335 #define BNX2_L2CTX_TBDR_BHADDR_LO                       0x000000a4
336 #define BNX2_L2CTX_TXP_BOFF                             0x000000a8
337 #define BNX2_L2CTX_TXP_BIDX                             0x000000a8
338 #define BNX2_L2CTX_TXP_BSEQ                             0x000000ac
339
340 #define BNX2_L2CTX_TYPE_XI                              0x00000080
341 #define BNX2_L2CTX_CMD_TYPE_XI                          0x00000240
342 #define BNX2_L2CTX_TBDR_BHADDR_HI_XI                    0x00000258
343 #define BNX2_L2CTX_TBDR_BHADDR_LO_XI                    0x0000025c
344
345 /*
346  *  l2_bd_chain_context definition
347  */
348 #define BNX2_L2CTX_BD_PRE_READ                          0x00000000
349 #define BNX2_L2CTX_CTX_SIZE                             0x00000000
350 #define BNX2_L2CTX_CTX_TYPE                             0x00000000
351 #define BNX2_L2CTX_CTX_TYPE_SIZE_L2                      ((0x20/20)<<16)
352 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE              (0xf<<28)
353 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED    (0<<28)
354 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE        (1<<28)
355
356 #define BNX2_L2CTX_HOST_BDIDX                           0x00000004
357 #define BNX2_L2CTX_HOST_BSEQ                            0x00000008
358 #define BNX2_L2CTX_NX_BSEQ                              0x0000000c
359 #define BNX2_L2CTX_NX_BDHADDR_HI                        0x00000010
360 #define BNX2_L2CTX_NX_BDHADDR_LO                        0x00000014
361 #define BNX2_L2CTX_NX_BDIDX                             0x00000018
362
363 #define BNX2_L2CTX_HOST_PG_BDIDX                        0x00000044
364 #define BNX2_L2CTX_PG_BUF_SIZE                          0x00000048
365 #define BNX2_L2CTX_RBDC_KEY                             0x0000004c
366 #define BNX2_L2CTX_RBDC_JUMBO_KEY                        0x3ffe
367 #define BNX2_L2CTX_NX_PG_BDHADDR_HI                     0x00000050
368 #define BNX2_L2CTX_NX_PG_BDHADDR_LO                     0x00000054
369
370 /*
371  *  pci_config_l definition
372  *  offset: 0000
373  */
374 #define BNX2_PCICFG_MISC_CONFIG                         0x00000068
375 #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP         (1L<<2)
376 #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP      (1L<<3)
377 #define BNX2_PCICFG_MISC_CONFIG_RESERVED1                (1L<<4)
378 #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA            (1L<<5)
379 #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP     (1L<<6)
380 #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA           (1L<<7)
381 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ             (1L<<8)
382 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY             (1L<<9)
383 #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN         (1L<<10)
384 #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN         (1L<<11)
385 #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN         (1L<<12)
386 #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV           (0xffL<<16)
387 #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV            (0xfL<<24)
388 #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID                  (0xfL<<28)
389
390 #define BNX2_PCICFG_MISC_STATUS                         0x0000006c
391 #define BNX2_PCICFG_MISC_STATUS_INTA_VALUE               (1L<<0)
392 #define BNX2_PCICFG_MISC_STATUS_32BIT_DET                (1L<<1)
393 #define BNX2_PCICFG_MISC_STATUS_M66EN                    (1L<<2)
394 #define BNX2_PCICFG_MISC_STATUS_PCIX_DET                 (1L<<3)
395 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED               (0x3L<<4)
396 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66            (0L<<4)
397 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100           (1L<<4)
398 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133           (2L<<4)
399 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE      (3L<<4)
400 #define BNX2_PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE         (1L<<8)
401
402 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS              0x00000070
403 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET       (0xfL<<0)
404 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ         (0L<<0)
405 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ         (1L<<0)
406 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ         (2L<<0)
407 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ         (3L<<0)
408 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ         (4L<<0)
409 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ         (5L<<0)
410 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ         (6L<<0)
411 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ        (7L<<0)
412 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW   (0xfL<<0)
413 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE      (1L<<6)
414 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT  (1L<<7)
415 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC      (0x7L<<8)
416 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF        (0L<<8)
417 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12   (1L<<8)
418 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6    (2L<<8)
419 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62   (4L<<8)
420 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER     (1L<<11)
421 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED    (0xfL<<12)
422 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100        (0L<<12)
423 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80         (1L<<12)
424 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50         (2L<<12)
425 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40         (4L<<12)
426 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25         (8L<<12)
427 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP     (1L<<16)
428 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17   (1L<<17)
429 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18   (1L<<18)
430 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19   (1L<<19)
431 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED      (0xfffL<<20)
432
433 #define BNX2_PCICFG_REG_WINDOW_ADDRESS                  0x00000078
434 #define BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL               (0xfffffL<<2)
435
436 #define BNX2_PCICFG_REG_WINDOW                          0x00000080
437 #define BNX2_PCICFG_INT_ACK_CMD                         0x00000084
438 #define BNX2_PCICFG_INT_ACK_CMD_INDEX                    (0xffffL<<0)
439 #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID              (1L<<16)
440 #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM         (1L<<17)
441 #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT                 (1L<<18)
442 #define BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM            (0xfL<<24)
443 #define BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT            24
444
445 #define BNX2_PCICFG_STATUS_BIT_SET_CMD                  0x00000088
446 #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD                0x0000008c
447 #define BNX2_PCICFG_MAILBOX_QUEUE_ADDR                  0x00000090
448 #define BNX2_PCICFG_MAILBOX_QUEUE_DATA                  0x00000094
449
450
451 /*
452  *  pci_reg definition
453  *  offset: 0x400
454  */
455 #define BNX2_PCI_GRC_WINDOW_ADDR                        0x00000400
456 #define BNX2_PCI_GRC_WINDOW_ADDR_VALUE                   (0x1ffL<<13)
457 #define BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN                 (1L<<31)
458
459 #define BNX2_PCI_GRC_WINDOW2_BASE                        0xc000
460 #define BNX2_PCI_GRC_WINDOW3_BASE                        0xe000
461
462 #define BNX2_PCI_CONFIG_1                               0x00000404
463 #define BNX2_PCI_CONFIG_1_RESERVED0                      (0xffL<<0)
464 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY                  (0x7L<<8)
465 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF              (0L<<8)
466 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16               (1L<<8)
467 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32               (2L<<8)
468 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64               (3L<<8)
469 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128              (4L<<8)
470 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256              (5L<<8)
471 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512              (6L<<8)
472 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024             (7L<<8)
473 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY                 (0x7L<<11)
474 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF             (0L<<11)
475 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16              (1L<<11)
476 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32              (2L<<11)
477 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64              (3L<<11)
478 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128             (4L<<11)
479 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256             (5L<<11)
480 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512             (6L<<11)
481 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024            (7L<<11)
482 #define BNX2_PCI_CONFIG_1_RESERVED1                      (0x3ffffL<<14)
483
484 #define BNX2_PCI_CONFIG_2                               0x00000408
485 #define BNX2_PCI_CONFIG_2_BAR1_SIZE                      (0xfL<<0)
486 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED             (0L<<0)
487 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K                  (1L<<0)
488 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K                 (2L<<0)
489 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K                 (3L<<0)
490 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K                 (4L<<0)
491 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M                   (5L<<0)
492 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M                   (6L<<0)
493 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M                   (7L<<0)
494 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M                   (8L<<0)
495 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M                  (9L<<0)
496 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M                  (10L<<0)
497 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M                  (11L<<0)
498 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M                 (12L<<0)
499 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M                 (13L<<0)
500 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M                 (14L<<0)
501 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G                   (15L<<0)
502 #define BNX2_PCI_CONFIG_2_BAR1_64ENA                     (1L<<4)
503 #define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY                  (1L<<5)
504 #define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY                (1L<<6)
505 #define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE                 (1L<<7)
506 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE                   (0xffL<<8)
507 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED          (0L<<8)
508 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K                (1L<<8)
509 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K                (2L<<8)
510 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K                (3L<<8)
511 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K                (4L<<8)
512 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K               (5L<<8)
513 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K               (6L<<8)
514 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K               (7L<<8)
515 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K              (8L<<8)
516 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K              (9L<<8)
517 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K              (10L<<8)
518 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M                (11L<<8)
519 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M                (12L<<8)
520 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M                (13L<<8)
521 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M                (14L<<8)
522 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M               (15L<<8)
523 #define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT                (0x1fL<<16)
524 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT                 (0x3L<<21)
525 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512             (0L<<21)
526 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K              (1L<<21)
527 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K              (2L<<21)
528 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K              (3L<<21)
529 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR              (1L<<23)
530 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT               (1L<<24)
531 #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT                (1L<<25)
532 #define BNX2_PCI_CONFIG_2_RESERVED0                      (0x3fL<<26)
533 #define BNX2_PCI_CONFIG_2_BAR_PREFETCH_XI                (1L<<16)
534 #define BNX2_PCI_CONFIG_2_RESERVED0_XI                   (0x7fffL<<17)
535
536 #define BNX2_PCI_CONFIG_3                               0x0000040c
537 #define BNX2_PCI_CONFIG_3_STICKY_BYTE                    (0xffL<<0)
538 #define BNX2_PCI_CONFIG_3_REG_STICKY_BYTE                (0xffL<<8)
539 #define BNX2_PCI_CONFIG_3_FORCE_PME                      (1L<<24)
540 #define BNX2_PCI_CONFIG_3_PME_STATUS                     (1L<<25)
541 #define BNX2_PCI_CONFIG_3_PME_ENABLE                     (1L<<26)
542 #define BNX2_PCI_CONFIG_3_PM_STATE                       (0x3L<<27)
543 #define BNX2_PCI_CONFIG_3_VAUX_PRESET                    (1L<<30)
544 #define BNX2_PCI_CONFIG_3_PCI_POWER                      (1L<<31)
545
546 #define BNX2_PCI_PM_DATA_A                              0x00000410
547 #define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG                 (0xffL<<0)
548 #define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG                 (0xffL<<8)
549 #define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG                 (0xffL<<16)
550 #define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG                 (0xffL<<24)
551
552 #define BNX2_PCI_PM_DATA_B                              0x00000414
553 #define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG                 (0xffL<<0)
554 #define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG                 (0xffL<<8)
555 #define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG                 (0xffL<<16)
556 #define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG                 (0xffL<<24)
557
558 #define BNX2_PCI_SWAP_DIAG0                             0x00000418
559 #define BNX2_PCI_SWAP_DIAG1                             0x0000041c
560 #define BNX2_PCI_EXP_ROM_ADDR                           0x00000420
561 #define BNX2_PCI_EXP_ROM_ADDR_ADDRESS                    (0x3fffffL<<2)
562 #define BNX2_PCI_EXP_ROM_ADDR_REQ                        (1L<<31)
563
564 #define BNX2_PCI_EXP_ROM_DATA                           0x00000424
565 #define BNX2_PCI_VPD_INTF                               0x00000428
566 #define BNX2_PCI_VPD_INTF_INTF_REQ                       (1L<<0)
567
568 #define BNX2_PCI_VPD_ADDR_FLAG                          0x0000042c
569 #define BNX2_PCI_VPD_ADDR_FLAG_MSK                      0x0000ffff
570 #define BNX2_PCI_VPD_ADDR_FLAG_SL                       0L
571 #define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS                   (0x1fffL<<2)
572 #define BNX2_PCI_VPD_ADDR_FLAG_WR                        (1L<<15)
573
574 #define BNX2_PCI_VPD_DATA                               0x00000430
575 #define BNX2_PCI_ID_VAL1                                0x00000434
576 #define BNX2_PCI_ID_VAL1_DEVICE_ID                       (0xffffL<<0)
577 #define BNX2_PCI_ID_VAL1_VENDOR_ID                       (0xffffL<<16)
578
579 #define BNX2_PCI_ID_VAL2                                0x00000438
580 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID             (0xffffL<<0)
581 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID                    (0xffffL<<16)
582
583 #define BNX2_PCI_ID_VAL3                                0x0000043c
584 #define BNX2_PCI_ID_VAL3_CLASS_CODE                      (0xffffffL<<0)
585 #define BNX2_PCI_ID_VAL3_REVISION_ID                     (0xffL<<24)
586
587 #define BNX2_PCI_ID_VAL4                                0x00000440
588 #define BNX2_PCI_ID_VAL4_CAP_ENA                         (0xfL<<0)
589 #define BNX2_PCI_ID_VAL4_CAP_ENA_0                       (0L<<0)
590 #define BNX2_PCI_ID_VAL4_CAP_ENA_1                       (1L<<0)
591 #define BNX2_PCI_ID_VAL4_CAP_ENA_2                       (2L<<0)
592 #define BNX2_PCI_ID_VAL4_CAP_ENA_3                       (3L<<0)
593 #define BNX2_PCI_ID_VAL4_CAP_ENA_4                       (4L<<0)
594 #define BNX2_PCI_ID_VAL4_CAP_ENA_5                       (5L<<0)
595 #define BNX2_PCI_ID_VAL4_CAP_ENA_6                       (6L<<0)
596 #define BNX2_PCI_ID_VAL4_CAP_ENA_7                       (7L<<0)
597 #define BNX2_PCI_ID_VAL4_CAP_ENA_8                       (8L<<0)
598 #define BNX2_PCI_ID_VAL4_CAP_ENA_9                       (9L<<0)
599 #define BNX2_PCI_ID_VAL4_CAP_ENA_10                      (10L<<0)
600 #define BNX2_PCI_ID_VAL4_CAP_ENA_11                      (11L<<0)
601 #define BNX2_PCI_ID_VAL4_CAP_ENA_12                      (12L<<0)
602 #define BNX2_PCI_ID_VAL4_CAP_ENA_13                      (13L<<0)
603 #define BNX2_PCI_ID_VAL4_CAP_ENA_14                      (14L<<0)
604 #define BNX2_PCI_ID_VAL4_CAP_ENA_15                      (15L<<0)
605 #define BNX2_PCI_ID_VAL4_RESERVED0                       (0x3L<<4)
606 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG                    (0x3L<<6)
607 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0                  (0L<<6)
608 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1                  (1L<<6)
609 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2                  (2L<<6)
610 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3                  (3L<<6)
611 #define BNX2_PCI_ID_VAL4_MSI_PV_MASK_CAP                 (1L<<8)
612 #define BNX2_PCI_ID_VAL4_MSI_LIMIT                       (0x7L<<9)
613 #define BNX2_PCI_ID_VAL4_MULTI_MSG_CAP                   (0x7L<<12)
614 #define BNX2_PCI_ID_VAL4_MSI_ENABLE                      (1L<<15)
615 #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE                (1L<<16)
616 #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE               (1L<<17)
617 #define BNX2_PCI_ID_VAL4_RESERVED2                       (0x7L<<18)
618 #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21         (0x3L<<21)
619 #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B21              (0x3L<<23)
620 #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0          (1L<<25)
621 #define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10           (0x3L<<26)
622 #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B0               (1L<<28)
623 #define BNX2_PCI_ID_VAL4_RESERVED3                       (0x7L<<29)
624 #define BNX2_PCI_ID_VAL4_RESERVED3_XI                    (0xffffL<<16)
625
626 #define BNX2_PCI_ID_VAL5                                0x00000444
627 #define BNX2_PCI_ID_VAL5_D1_SUPPORT                      (1L<<0)
628 #define BNX2_PCI_ID_VAL5_D2_SUPPORT                      (1L<<1)
629 #define BNX2_PCI_ID_VAL5_PME_IN_D0                       (1L<<2)
630 #define BNX2_PCI_ID_VAL5_PME_IN_D1                       (1L<<3)
631 #define BNX2_PCI_ID_VAL5_PME_IN_D2                       (1L<<4)
632 #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT                   (1L<<5)
633 #define BNX2_PCI_ID_VAL5_RESERVED0_TE                    (0x3ffffffL<<6)
634 #define BNX2_PCI_ID_VAL5_PM_VERSION_XI                   (0x7L<<6)
635 #define BNX2_PCI_ID_VAL5_NO_SOFT_RESET_XI                (1L<<9)
636 #define BNX2_PCI_ID_VAL5_RESERVED0_XI                    (0x3fffffL<<10)
637
638 #define BNX2_PCI_PCIX_EXTENDED_STATUS                   0x00000448
639 #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP           (1L<<8)
640 #define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST         (1L<<9)
641 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS       (0xfL<<16)
642 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX         (0xffL<<24)
643
644 #define BNX2_PCI_ID_VAL6                                0x0000044c
645 #define BNX2_PCI_ID_VAL6_MAX_LAT                         (0xffL<<0)
646 #define BNX2_PCI_ID_VAL6_MIN_GNT                         (0xffL<<8)
647 #define BNX2_PCI_ID_VAL6_BIST                            (0xffL<<16)
648 #define BNX2_PCI_ID_VAL6_RESERVED0                       (0xffL<<24)
649
650 #define BNX2_PCI_MSI_DATA                               0x00000450
651 #define BNX2_PCI_MSI_DATA_MSI_DATA                       (0xffffL<<0)
652
653 #define BNX2_PCI_MSI_ADDR_H                             0x00000454
654 #define BNX2_PCI_MSI_ADDR_L                             0x00000458
655 #define BNX2_PCI_MSI_ADDR_L_VAL                          (0x3fffffffL<<2)
656
657 #define BNX2_PCI_CFG_ACCESS_CMD                         0x0000045c
658 #define BNX2_PCI_CFG_ACCESS_CMD_ADR                      (0x3fL<<2)
659 #define BNX2_PCI_CFG_ACCESS_CMD_RD_REQ                   (1L<<27)
660 #define BNX2_PCI_CFG_ACCESS_CMD_WR_REQ                   (0xfL<<28)
661
662 #define BNX2_PCI_CFG_ACCESS_DATA                        0x00000460
663 #define BNX2_PCI_MSI_MASK                               0x00000464
664 #define BNX2_PCI_MSI_MASK_MSI_MASK                       (0xffffffffL<<0)
665
666 #define BNX2_PCI_MSI_PEND                               0x00000468
667 #define BNX2_PCI_MSI_PEND_MSI_PEND                       (0xffffffffL<<0)
668
669 #define BNX2_PCI_PM_DATA_C                              0x0000046c
670 #define BNX2_PCI_PM_DATA_C_PM_DATA_8_PRG                 (0xffL<<0)
671 #define BNX2_PCI_PM_DATA_C_RESERVED0                     (0xffffffL<<8)
672
673 #define BNX2_PCI_MSIX_CONTROL                           0x000004c0
674 #define BNX2_PCI_MSIX_CONTROL_MSIX_TBL_SIZ               (0x7ffL<<0)
675 #define BNX2_PCI_MSIX_CONTROL_RESERVED0                  (0x1fffffL<<11)
676
677 #define BNX2_PCI_MSIX_TBL_OFF_BIR                       0x000004c4
678 #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR           (0x7L<<0)
679 #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF           (0x1fffffffL<<3)
680
681 #define BNX2_PCI_MSIX_PBA_OFF_BIT                       0x000004c8
682 #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR           (0x7L<<0)
683 #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF           (0x1fffffffL<<3)
684
685 #define BNX2_PCI_PCIE_CAPABILITY                        0x000004d0
686 #define BNX2_PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM       (0x1fL<<0)
687 #define BNX2_PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1         (1L<<5)
688
689 #define BNX2_PCI_DEVICE_CAPABILITY                      0x000004d4
690 #define BNX2_PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED  (0x7L<<0)
691 #define BNX2_PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT  (1L<<5)
692 #define BNX2_PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY        (0x7L<<6)
693 #define BNX2_PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY         (0x7L<<9)
694 #define BNX2_PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT    (1L<<15)
695
696 #define BNX2_PCI_LINK_CAPABILITY                        0x000004dc
697 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED          (0xfL<<0)
698 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001     (1L<<0)
699 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010     (1L<<0)
700 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_WIDTH          (0x1fL<<4)
701 #define BNX2_PCI_LINK_CAPABILITY_CLK_POWER_MGMT          (1L<<9)
702 #define BNX2_PCI_LINK_CAPABILITY_ASPM_SUPPORT            (0x3L<<10)
703 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT            (0x7L<<12)
704 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101        (5L<<12)
705 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110        (6L<<12)
706 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT             (0x7L<<15)
707 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_001         (1L<<15)
708 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_010         (2L<<15)
709 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT       (0x7L<<18)
710 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101   (5L<<18)
711 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110   (6L<<18)
712 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT        (0x7L<<21)
713 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001    (1L<<21)
714 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010    (2L<<21)
715 #define BNX2_PCI_LINK_CAPABILITY_PORT_NUM                (0xffL<<24)
716
717 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2               0x000004e4
718 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP     (0xfL<<0)
719 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP    (1L<<4)
720 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED       (0x7ffffffL<<5)
721
722 #define BNX2_PCI_PCIE_LINK_CAPABILITY_2                 0x000004e8
723 #define BNX2_PCI_PCIE_LINK_CAPABILITY_2_RESERVED         (0xffffffffL<<0)
724
725 #define BNX2_PCI_GRC_WINDOW1_ADDR                       0x00000610
726 #define BNX2_PCI_GRC_WINDOW1_ADDR_VALUE                  (0x1ffL<<13)
727
728 #define BNX2_PCI_GRC_WINDOW2_ADDR                       0x00000614
729 #define BNX2_PCI_GRC_WINDOW2_ADDR_VALUE                  (0x1ffL<<13)
730
731 #define BNX2_PCI_GRC_WINDOW3_ADDR                       0x00000618
732 #define BNX2_PCI_GRC_WINDOW3_ADDR_VALUE                  (0x1ffL<<13)
733
734 #define BNX2_MSIX_TABLE_ADDR                             0x318000
735 #define BNX2_MSIX_PBA_ADDR                               0x31c000
736
737 /*
738  *  misc_reg definition
739  *  offset: 0x800
740  */
741 #define BNX2_MISC_COMMAND                               0x00000800
742 #define BNX2_MISC_COMMAND_ENABLE_ALL                     (1L<<0)
743 #define BNX2_MISC_COMMAND_DISABLE_ALL                    (1L<<1)
744 #define BNX2_MISC_COMMAND_SW_RESET                       (1L<<4)
745 #define BNX2_MISC_COMMAND_POR_RESET                      (1L<<5)
746 #define BNX2_MISC_COMMAND_HD_RESET                       (1L<<6)
747 #define BNX2_MISC_COMMAND_CMN_SW_RESET                   (1L<<7)
748 #define BNX2_MISC_COMMAND_PAR_ERROR                      (1L<<8)
749 #define BNX2_MISC_COMMAND_CS16_ERR                       (1L<<9)
750 #define BNX2_MISC_COMMAND_CS16_ERR_LOC                   (0xfL<<12)
751 #define BNX2_MISC_COMMAND_PAR_ERR_RAM                    (0x7fL<<16)
752 #define BNX2_MISC_COMMAND_POWERDOWN_EVENT                (1L<<23)
753 #define BNX2_MISC_COMMAND_SW_SHUTDOWN                    (1L<<24)
754 #define BNX2_MISC_COMMAND_SHUTDOWN_EN                    (1L<<25)
755 #define BNX2_MISC_COMMAND_DINTEG_ATTN_EN                 (1L<<26)
756 #define BNX2_MISC_COMMAND_PCIE_LINK_IN_L23               (1L<<27)
757 #define BNX2_MISC_COMMAND_PCIE_DIS                       (1L<<28)
758
759 #define BNX2_MISC_CFG                                   0x00000804
760 #define BNX2_MISC_CFG_GRC_TMOUT                          (1L<<0)
761 #define BNX2_MISC_CFG_NVM_WR_EN                          (0x3L<<1)
762 #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT                  (0L<<1)
763 #define BNX2_MISC_CFG_NVM_WR_EN_PCI                      (1L<<1)
764 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW                    (2L<<1)
765 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2                   (3L<<1)
766 #define BNX2_MISC_CFG_BIST_EN                            (1L<<3)
767 #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC                   (1L<<4)
768 #define BNX2_MISC_CFG_RESERVED5_TE                       (1L<<5)
769 #define BNX2_MISC_CFG_RESERVED6_TE                       (1L<<6)
770 #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE                   (1L<<7)
771 #define BNX2_MISC_CFG_LEDMODE                            (0x7L<<8)
772 #define BNX2_MISC_CFG_LEDMODE_MAC                        (0L<<8)
773 #define BNX2_MISC_CFG_LEDMODE_PHY1_TE                    (1L<<8)
774 #define BNX2_MISC_CFG_LEDMODE_PHY2_TE                    (2L<<8)
775 #define BNX2_MISC_CFG_LEDMODE_PHY3_TE                    (3L<<8)
776 #define BNX2_MISC_CFG_LEDMODE_PHY4_TE                    (4L<<8)
777 #define BNX2_MISC_CFG_LEDMODE_PHY5_TE                    (5L<<8)
778 #define BNX2_MISC_CFG_LEDMODE_PHY6_TE                    (6L<<8)
779 #define BNX2_MISC_CFG_LEDMODE_PHY7_TE                    (7L<<8)
780 #define BNX2_MISC_CFG_MCP_GRC_TMOUT_TE                   (1L<<11)
781 #define BNX2_MISC_CFG_DBU_GRC_TMOUT_TE                   (1L<<12)
782 #define BNX2_MISC_CFG_LEDMODE_XI                         (0xfL<<8)
783 #define BNX2_MISC_CFG_LEDMODE_MAC_XI                     (0L<<8)
784 #define BNX2_MISC_CFG_LEDMODE_PHY1_XI                    (1L<<8)
785 #define BNX2_MISC_CFG_LEDMODE_PHY2_XI                    (2L<<8)
786 #define BNX2_MISC_CFG_LEDMODE_PHY3_XI                    (3L<<8)
787 #define BNX2_MISC_CFG_LEDMODE_MAC2_XI                    (4L<<8)
788 #define BNX2_MISC_CFG_LEDMODE_PHY4_XI                    (5L<<8)
789 #define BNX2_MISC_CFG_LEDMODE_PHY5_XI                    (6L<<8)
790 #define BNX2_MISC_CFG_LEDMODE_PHY6_XI                    (7L<<8)
791 #define BNX2_MISC_CFG_LEDMODE_MAC3_XI                    (8L<<8)
792 #define BNX2_MISC_CFG_LEDMODE_PHY7_XI                    (9L<<8)
793 #define BNX2_MISC_CFG_LEDMODE_PHY8_XI                    (10L<<8)
794 #define BNX2_MISC_CFG_LEDMODE_PHY9_XI                    (11L<<8)
795 #define BNX2_MISC_CFG_LEDMODE_MAC4_XI                    (12L<<8)
796 #define BNX2_MISC_CFG_LEDMODE_PHY10_XI                   (13L<<8)
797 #define BNX2_MISC_CFG_LEDMODE_PHY11_XI                   (14L<<8)
798 #define BNX2_MISC_CFG_LEDMODE_UNUSED_XI                  (15L<<8)
799 #define BNX2_MISC_CFG_PORT_SELECT_XI                     (1L<<13)
800 #define BNX2_MISC_CFG_PARITY_MODE_XI                     (1L<<14)
801
802 #define BNX2_MISC_ID                                    0x00000808
803 #define BNX2_MISC_ID_BOND_ID                             (0xfL<<0)
804 #define BNX2_MISC_ID_BOND_ID_X                           (0L<<0)
805 #define BNX2_MISC_ID_BOND_ID_C                           (3L<<0)
806 #define BNX2_MISC_ID_BOND_ID_S                           (12L<<0)
807 #define BNX2_MISC_ID_CHIP_METAL                          (0xffL<<4)
808 #define BNX2_MISC_ID_CHIP_REV                            (0xfL<<12)
809 #define BNX2_MISC_ID_CHIP_NUM                            (0xffffL<<16)
810
811 #define BNX2_MISC_ENABLE_STATUS_BITS                    0x0000080c
812 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE         (1L<<0)
813 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE   (1L<<1)
814 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE  (1L<<2)
815 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE         (1L<<3)
816 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE       (1L<<4)
817 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE   (1L<<5)
818 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE         (1L<<6)
819 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE  (1L<<7)
820 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE         (1L<<8)
821 #define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE         (1L<<9)
822 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE        (1L<<10)
823 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE    (1L<<11)
824 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE      (1L<<12)
825 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE    (1L<<13)
826 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE         (1L<<14)
827 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE       (1L<<15)
828 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE  (1L<<16)
829 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE       (1L<<17)
830 #define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE   (1L<<18)
831 #define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE        (1L<<19)
832 #define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE        (1L<<20)
833 #define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE      (1L<<21)
834 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE        (1L<<22)
835 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE        (1L<<23)
836 #define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE       (1L<<24)
837 #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE        (1L<<25)
838 #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE   (1L<<26)
839 #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE          (1L<<27)
840 #define BNX2_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE   (1L<<28)
841 #define BNX2_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE  (0x7L<<29)
842
843 #define BNX2_MISC_ENABLE_SET_BITS                       0x00000810
844 #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
845 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE      (1L<<1)
846 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE     (1L<<2)
847 #define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE    (1L<<3)
848 #define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE          (1L<<4)
849 #define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE      (1L<<5)
850 #define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE    (1L<<6)
851 #define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE     (1L<<7)
852 #define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE    (1L<<8)
853 #define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE            (1L<<9)
854 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE   (1L<<10)
855 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE       (1L<<11)
856 #define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE         (1L<<12)
857 #define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE       (1L<<13)
858 #define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE    (1L<<14)
859 #define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE          (1L<<15)
860 #define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE     (1L<<16)
861 #define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE          (1L<<17)
862 #define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE      (1L<<18)
863 #define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE   (1L<<19)
864 #define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE   (1L<<20)
865 #define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE         (1L<<21)
866 #define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE   (1L<<22)
867 #define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE   (1L<<23)
868 #define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE  (1L<<24)
869 #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE           (1L<<25)
870 #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE      (1L<<26)
871 #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE             (1L<<27)
872 #define BNX2_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE      (1L<<28)
873 #define BNX2_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE     (0x7L<<29)
874
875 #define BNX2_MISC_ENABLE_CLR_BITS                       0x00000814
876 #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
877 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE      (1L<<1)
878 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE     (1L<<2)
879 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE    (1L<<3)
880 #define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE          (1L<<4)
881 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE      (1L<<5)
882 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE    (1L<<6)
883 #define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE     (1L<<7)
884 #define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE    (1L<<8)
885 #define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE            (1L<<9)
886 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE   (1L<<10)
887 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE       (1L<<11)
888 #define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE         (1L<<12)
889 #define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE       (1L<<13)
890 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE    (1L<<14)
891 #define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE          (1L<<15)
892 #define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE     (1L<<16)
893 #define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE          (1L<<17)
894 #define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE      (1L<<18)
895 #define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE   (1L<<19)
896 #define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE   (1L<<20)
897 #define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE         (1L<<21)
898 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE   (1L<<22)
899 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE   (1L<<23)
900 #define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE  (1L<<24)
901 #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE           (1L<<25)
902 #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE      (1L<<26)
903 #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE             (1L<<27)
904 #define BNX2_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE      (1L<<28)
905 #define BNX2_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE     (0x7L<<29)
906
907 #define BNX2_MISC_CLOCK_CONTROL_BITS                    0x00000818
908 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET     (0xfL<<0)
909 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ       (0L<<0)
910 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ       (1L<<0)
911 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ       (2L<<0)
912 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ       (3L<<0)
913 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ       (4L<<0)
914 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ       (5L<<0)
915 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ       (6L<<0)
916 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ      (7L<<0)
917 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW         (0xfL<<0)
918 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE    (1L<<6)
919 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT        (1L<<7)
920 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC    (0x7L<<8)
921 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF      (0L<<8)
922 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12         (1L<<8)
923 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6  (2L<<8)
924 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62         (4L<<8)
925 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI        (0x7L<<8)
926 #define BNX2_MISC_CLOCK_CONTROL_BITS_MIN_POWER           (1L<<11)
927 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED  (0xfL<<12)
928 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100      (0L<<12)
929 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80       (1L<<12)
930 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50       (2L<<12)
931 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40       (4L<<12)
932 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25       (8L<<12)
933 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI        (0xfL<<12)
934 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP   (1L<<16)
935 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE      (1L<<17)
936 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE      (1L<<18)
937 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE      (1L<<19)
938 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_TE         (0xfffL<<20)
939 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI        (1L<<17)
940 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI        (0x3fL<<18)
941 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI         (0x7L<<24)
942 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI        (1L<<27)
943 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI       (0xfL<<28)
944
945 #define BNX2_MISC_SPIO                                  0x0000081c
946 #define BNX2_MISC_SPIO_VALUE                             (0xffL<<0)
947 #define BNX2_MISC_SPIO_SET                               (0xffL<<8)
948 #define BNX2_MISC_SPIO_CLR                               (0xffL<<16)
949 #define BNX2_MISC_SPIO_FLOAT                             (0xffL<<24)
950
951 #define BNX2_MISC_SPIO_INT                              0x00000820
952 #define BNX2_MISC_SPIO_INT_INT_STATE_TE                  (0xfL<<0)
953 #define BNX2_MISC_SPIO_INT_OLD_VALUE_TE                  (0xfL<<8)
954 #define BNX2_MISC_SPIO_INT_OLD_SET_TE                    (0xfL<<16)
955 #define BNX2_MISC_SPIO_INT_OLD_CLR_TE                    (0xfL<<24)
956 #define BNX2_MISC_SPIO_INT_INT_STATE_XI                  (0xffL<<0)
957 #define BNX2_MISC_SPIO_INT_OLD_VALUE_XI                  (0xffL<<8)
958 #define BNX2_MISC_SPIO_INT_OLD_SET_XI                    (0xffL<<16)
959 #define BNX2_MISC_SPIO_INT_OLD_CLR_XI                    (0xffL<<24)
960
961 #define BNX2_MISC_CONFIG_LFSR                           0x00000824
962 #define BNX2_MISC_CONFIG_LFSR_DIV                        (0xffffL<<0)
963
964 #define BNX2_MISC_LFSR_MASK_BITS                        0x00000828
965 #define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE     (1L<<0)
966 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE       (1L<<1)
967 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE      (1L<<2)
968 #define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE     (1L<<3)
969 #define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE           (1L<<4)
970 #define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE       (1L<<5)
971 #define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE     (1L<<6)
972 #define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE      (1L<<7)
973 #define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE     (1L<<8)
974 #define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE             (1L<<9)
975 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE    (1L<<10)
976 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE        (1L<<11)
977 #define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE          (1L<<12)
978 #define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE        (1L<<13)
979 #define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE     (1L<<14)
980 #define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE           (1L<<15)
981 #define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE      (1L<<16)
982 #define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE           (1L<<17)
983 #define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE       (1L<<18)
984 #define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE    (1L<<19)
985 #define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE    (1L<<20)
986 #define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE          (1L<<21)
987 #define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE    (1L<<22)
988 #define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE    (1L<<23)
989 #define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE   (1L<<24)
990 #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE            (1L<<25)
991 #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE       (1L<<26)
992 #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE              (1L<<27)
993 #define BNX2_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE       (1L<<28)
994 #define BNX2_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE      (0x7L<<29)
995
996 #define BNX2_MISC_ARB_REQ0                              0x0000082c
997 #define BNX2_MISC_ARB_REQ1                              0x00000830
998 #define BNX2_MISC_ARB_REQ2                              0x00000834
999 #define BNX2_MISC_ARB_REQ3                              0x00000838
1000 #define BNX2_MISC_ARB_REQ4                              0x0000083c
1001 #define BNX2_MISC_ARB_FREE0                             0x00000840
1002 #define BNX2_MISC_ARB_FREE1                             0x00000844
1003 #define BNX2_MISC_ARB_FREE2                             0x00000848
1004 #define BNX2_MISC_ARB_FREE3                             0x0000084c
1005 #define BNX2_MISC_ARB_FREE4                             0x00000850
1006 #define BNX2_MISC_ARB_REQ_STATUS0                       0x00000854
1007 #define BNX2_MISC_ARB_REQ_STATUS1                       0x00000858
1008 #define BNX2_MISC_ARB_REQ_STATUS2                       0x0000085c
1009 #define BNX2_MISC_ARB_REQ_STATUS3                       0x00000860
1010 #define BNX2_MISC_ARB_REQ_STATUS4                       0x00000864
1011 #define BNX2_MISC_ARB_GNT0                              0x00000868
1012 #define BNX2_MISC_ARB_GNT0_0                             (0x7L<<0)
1013 #define BNX2_MISC_ARB_GNT0_1                             (0x7L<<4)
1014 #define BNX2_MISC_ARB_GNT0_2                             (0x7L<<8)
1015 #define BNX2_MISC_ARB_GNT0_3                             (0x7L<<12)
1016 #define BNX2_MISC_ARB_GNT0_4                             (0x7L<<16)
1017 #define BNX2_MISC_ARB_GNT0_5                             (0x7L<<20)
1018 #define BNX2_MISC_ARB_GNT0_6                             (0x7L<<24)
1019 #define BNX2_MISC_ARB_GNT0_7                             (0x7L<<28)
1020
1021 #define BNX2_MISC_ARB_GNT1                              0x0000086c
1022 #define BNX2_MISC_ARB_GNT1_8                             (0x7L<<0)
1023 #define BNX2_MISC_ARB_GNT1_9                             (0x7L<<4)
1024 #define BNX2_MISC_ARB_GNT1_10                            (0x7L<<8)
1025 #define BNX2_MISC_ARB_GNT1_11                            (0x7L<<12)
1026 #define BNX2_MISC_ARB_GNT1_12                            (0x7L<<16)
1027 #define BNX2_MISC_ARB_GNT1_13                            (0x7L<<20)
1028 #define BNX2_MISC_ARB_GNT1_14                            (0x7L<<24)
1029 #define BNX2_MISC_ARB_GNT1_15                            (0x7L<<28)
1030
1031 #define BNX2_MISC_ARB_GNT2                              0x00000870
1032 #define BNX2_MISC_ARB_GNT2_16                            (0x7L<<0)
1033 #define BNX2_MISC_ARB_GNT2_17                            (0x7L<<4)
1034 #define BNX2_MISC_ARB_GNT2_18                            (0x7L<<8)
1035 #define BNX2_MISC_ARB_GNT2_19                            (0x7L<<12)
1036 #define BNX2_MISC_ARB_GNT2_20                            (0x7L<<16)
1037 #define BNX2_MISC_ARB_GNT2_21                            (0x7L<<20)
1038 #define BNX2_MISC_ARB_GNT2_22                            (0x7L<<24)
1039 #define BNX2_MISC_ARB_GNT2_23                            (0x7L<<28)
1040
1041 #define BNX2_MISC_ARB_GNT3                              0x00000874
1042 #define BNX2_MISC_ARB_GNT3_24                            (0x7L<<0)
1043 #define BNX2_MISC_ARB_GNT3_25                            (0x7L<<4)
1044 #define BNX2_MISC_ARB_GNT3_26                            (0x7L<<8)
1045 #define BNX2_MISC_ARB_GNT3_27                            (0x7L<<12)
1046 #define BNX2_MISC_ARB_GNT3_28                            (0x7L<<16)
1047 #define BNX2_MISC_ARB_GNT3_29                            (0x7L<<20)
1048 #define BNX2_MISC_ARB_GNT3_30                            (0x7L<<24)
1049 #define BNX2_MISC_ARB_GNT3_31                            (0x7L<<28)
1050
1051 #define BNX2_MISC_RESERVED1                             0x00000878
1052 #define BNX2_MISC_RESERVED1_MISC_RESERVED1_VALUE         (0x3fL<<0)
1053
1054 #define BNX2_MISC_RESERVED2                             0x0000087c
1055 #define BNX2_MISC_RESERVED2_PCIE_DIS                     (1L<<0)
1056 #define BNX2_MISC_RESERVED2_LINK_IN_L23                  (1L<<1)
1057
1058 #define BNX2_MISC_SM_ASF_CONTROL                        0x00000880
1059 #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST                 (1L<<0)
1060 #define BNX2_MISC_SM_ASF_CONTROL_TSC_EN                  (1L<<1)
1061 #define BNX2_MISC_SM_ASF_CONTROL_WG_TO                   (1L<<2)
1062 #define BNX2_MISC_SM_ASF_CONTROL_HB_TO                   (1L<<3)
1063 #define BNX2_MISC_SM_ASF_CONTROL_PA_TO                   (1L<<4)
1064 #define BNX2_MISC_SM_ASF_CONTROL_PL_TO                   (1L<<5)
1065 #define BNX2_MISC_SM_ASF_CONTROL_RT_TO                   (1L<<6)
1066 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT               (1L<<7)
1067 #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_EN              (1L<<8)
1068 #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_PULSE           (1L<<9)
1069 #define BNX2_MISC_SM_ASF_CONTROL_RES                     (0x3L<<10)
1070 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN                  (1L<<12)
1071 #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN               (1L<<13)
1072 #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT        (1L<<14)
1073 #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD            (1L<<15)
1074 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1           (0x7fL<<16)
1075 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2           (0x7fL<<23)
1076 #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0       (1L<<30)
1077 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN          (1L<<31)
1078
1079 #define BNX2_MISC_SMB_IN                                0x00000884
1080 #define BNX2_MISC_SMB_IN_DAT_IN                          (0xffL<<0)
1081 #define BNX2_MISC_SMB_IN_RDY                             (1L<<8)
1082 #define BNX2_MISC_SMB_IN_DONE                            (1L<<9)
1083 #define BNX2_MISC_SMB_IN_FIRSTBYTE                       (1L<<10)
1084 #define BNX2_MISC_SMB_IN_STATUS                          (0x7L<<11)
1085 #define BNX2_MISC_SMB_IN_STATUS_OK                       (0x0L<<11)
1086 #define BNX2_MISC_SMB_IN_STATUS_PEC                      (0x1L<<11)
1087 #define BNX2_MISC_SMB_IN_STATUS_OFLOW                    (0x2L<<11)
1088 #define BNX2_MISC_SMB_IN_STATUS_STOP                     (0x3L<<11)
1089 #define BNX2_MISC_SMB_IN_STATUS_TIMEOUT                  (0x4L<<11)
1090
1091 #define BNX2_MISC_SMB_OUT                               0x00000888
1092 #define BNX2_MISC_SMB_OUT_DAT_OUT                        (0xffL<<0)
1093 #define BNX2_MISC_SMB_OUT_RDY                            (1L<<8)
1094 #define BNX2_MISC_SMB_OUT_START                          (1L<<9)
1095 #define BNX2_MISC_SMB_OUT_LAST                           (1L<<10)
1096 #define BNX2_MISC_SMB_OUT_ACC_TYPE                       (1L<<11)
1097 #define BNX2_MISC_SMB_OUT_ENB_PEC                        (1L<<12)
1098 #define BNX2_MISC_SMB_OUT_GET_RX_LEN                     (1L<<13)
1099 #define BNX2_MISC_SMB_OUT_SMB_READ_LEN                   (0x3fL<<14)
1100 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS                 (0xfL<<20)
1101 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK              (0L<<20)
1102 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK      (1L<<20)
1103 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW           (2L<<20)
1104 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP            (3L<<20)
1105 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT         (4L<<20)
1106 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST      (5L<<20)
1107 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK          (6L<<20)
1108 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK        (9L<<20)
1109 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST        (0xdL<<20)
1110 #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE              (1L<<24)
1111 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN                 (1L<<25)
1112 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN                 (1L<<26)
1113 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN                 (1L<<27)
1114 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN                 (1L<<28)
1115
1116 #define BNX2_MISC_SMB_WATCHDOG                          0x0000088c
1117 #define BNX2_MISC_SMB_WATCHDOG_WATCHDOG                  (0xffffL<<0)
1118
1119 #define BNX2_MISC_SMB_HEARTBEAT                         0x00000890
1120 #define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT                (0xffffL<<0)
1121
1122 #define BNX2_MISC_SMB_POLL_ASF                          0x00000894
1123 #define BNX2_MISC_SMB_POLL_ASF_POLL_ASF                  (0xffffL<<0)
1124
1125 #define BNX2_MISC_SMB_POLL_LEGACY                       0x00000898
1126 #define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY            (0xffffL<<0)
1127
1128 #define BNX2_MISC_SMB_RETRAN                            0x0000089c
1129 #define BNX2_MISC_SMB_RETRAN_RETRAN                      (0xffL<<0)
1130
1131 #define BNX2_MISC_SMB_TIMESTAMP                         0x000008a0
1132 #define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP                (0xffffffffL<<0)
1133
1134 #define BNX2_MISC_PERR_ENA0                             0x000008a4
1135 #define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC                (1L<<0)
1136 #define BNX2_MISC_PERR_ENA0_COM_MISC_REGF                (1L<<1)
1137 #define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD               (1L<<2)
1138 #define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC                 (1L<<3)
1139 #define BNX2_MISC_PERR_ENA0_CP_MISC_REGF                 (1L<<4)
1140 #define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD                (1L<<5)
1141 #define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM                 (1L<<6)
1142 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0               (1L<<7)
1143 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1               (1L<<8)
1144 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2               (1L<<9)
1145 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3               (1L<<10)
1146 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4               (1L<<11)
1147 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5               (1L<<12)
1148 #define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL               (1L<<13)
1149 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0                (1L<<14)
1150 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1                (1L<<15)
1151 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2                (1L<<16)
1152 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3                (1L<<17)
1153 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4                (1L<<18)
1154 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0                (1L<<19)
1155 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1                (1L<<20)
1156 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2                (1L<<21)
1157 #define BNX2_MISC_PERR_ENA0_HC_MISC_DMA                  (1L<<22)
1158 #define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF                (1L<<23)
1159 #define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD               (1L<<24)
1160 #define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX                  (1L<<25)
1161 #define BNX2_MISC_PERR_ENA0_RBDC_MISC                    (1L<<26)
1162 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB                 (1L<<27)
1163 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR                (1L<<28)
1164 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC                 (1L<<29)
1165 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM                 (1L<<30)
1166 #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS            (1L<<31)
1167 #define BNX2_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI          (1L<<0)
1168 #define BNX2_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI           (1L<<1)
1169 #define BNX2_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI     (1L<<2)
1170 #define BNX2_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI     (1L<<3)
1171 #define BNX2_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI         (1L<<4)
1172 #define BNX2_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI         (1L<<5)
1173 #define BNX2_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI        (1L<<6)
1174 #define BNX2_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI          (1L<<7)
1175 #define BNX2_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI         (1L<<8)
1176 #define BNX2_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI           (1L<<9)
1177 #define BNX2_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI          (1L<<10)
1178 #define BNX2_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI         (1L<<11)
1179 #define BNX2_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI          (1L<<12)
1180 #define BNX2_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI         (1L<<13)
1181 #define BNX2_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI        (1L<<14)
1182 #define BNX2_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI          (1L<<15)
1183 #define BNX2_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI         (1L<<16)
1184 #define BNX2_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI           (1L<<17)
1185 #define BNX2_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI            (1L<<18)
1186 #define BNX2_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI      (1L<<19)
1187 #define BNX2_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI      (1L<<20)
1188 #define BNX2_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI       (1L<<21)
1189 #define BNX2_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI      (1L<<22)
1190 #define BNX2_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI       (1L<<23)
1191 #define BNX2_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI       (1L<<24)
1192 #define BNX2_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI      (1L<<25)
1193 #define BNX2_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI      (1L<<26)
1194 #define BNX2_MISC_PERR_ENA0_TPBUF_PERR_EN_XI             (1L<<27)
1195 #define BNX2_MISC_PERR_ENA0_THBUF_PERR_EN_XI             (1L<<28)
1196 #define BNX2_MISC_PERR_ENA0_TDMA_PERR_EN_XI              (1L<<29)
1197 #define BNX2_MISC_PERR_ENA0_TBDC_PERR_EN_XI              (1L<<30)
1198 #define BNX2_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI           (1L<<31)
1199
1200 #define BNX2_MISC_PERR_ENA1                             0x000008a8
1201 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS            (1L<<0)
1202 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM             (1L<<1)
1203 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM             (1L<<2)
1204 #define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC                (1L<<3)
1205 #define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF                (1L<<4)
1206 #define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD               (1L<<5)
1207 #define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC               (1L<<6)
1208 #define BNX2_MISC_PERR_ENA1_TBDC_MISC                    (1L<<7)
1209 #define BNX2_MISC_PERR_ENA1_TDMA_MISC                    (1L<<8)
1210 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0               (1L<<9)
1211 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1               (1L<<10)
1212 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF               (1L<<11)
1213 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD              (1L<<12)
1214 #define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB                (1L<<13)
1215 #define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR                 (1L<<14)
1216 #define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC                (1L<<15)
1217 #define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF                (1L<<16)
1218 #define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD               (1L<<17)
1219 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX               (1L<<18)
1220 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX               (1L<<19)
1221 #define BNX2_MISC_PERR_ENA1_UMP_MISC_RX                  (1L<<20)
1222 #define BNX2_MISC_PERR_ENA1_UMP_MISC_TX                  (1L<<21)
1223 #define BNX2_MISC_PERR_ENA1_RDMAQ_MISC                   (1L<<22)
1224 #define BNX2_MISC_PERR_ENA1_CSQ_MISC                     (1L<<23)
1225 #define BNX2_MISC_PERR_ENA1_CPQ_MISC                     (1L<<24)
1226 #define BNX2_MISC_PERR_ENA1_MCPQ_MISC                    (1L<<25)
1227 #define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC                  (1L<<26)
1228 #define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC                  (1L<<27)
1229 #define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC                  (1L<<28)
1230 #define BNX2_MISC_PERR_ENA1_RXPQ_MISC                    (1L<<29)
1231 #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC                   (1L<<30)
1232 #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC                   (1L<<31)
1233 #define BNX2_MISC_PERR_ENA1_RBDC_PERR_EN_XI              (1L<<0)
1234 #define BNX2_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI        (1L<<2)
1235 #define BNX2_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI          (1L<<3)
1236 #define BNX2_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI           (1L<<4)
1237 #define BNX2_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI      (1L<<5)
1238 #define BNX2_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI      (1L<<6)
1239 #define BNX2_MISC_PERR_ENA1_TPATQ_PERR_EN_XI             (1L<<7)
1240 #define BNX2_MISC_PERR_ENA1_MCPQ_PERR_EN_XI              (1L<<8)
1241 #define BNX2_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI             (1L<<9)
1242 #define BNX2_MISC_PERR_ENA1_TXPQ_PERR_EN_XI              (1L<<10)
1243 #define BNX2_MISC_PERR_ENA1_COMTQ_PERR_EN_XI             (1L<<11)
1244 #define BNX2_MISC_PERR_ENA1_COMQ_PERR_EN_XI              (1L<<12)
1245 #define BNX2_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI             (1L<<13)
1246 #define BNX2_MISC_PERR_ENA1_RXPQ_PERR_EN_XI              (1L<<14)
1247 #define BNX2_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI            (1L<<15)
1248 #define BNX2_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI             (1L<<16)
1249 #define BNX2_MISC_PERR_ENA1_TASQ_PERR_EN_XI              (1L<<17)
1250 #define BNX2_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI             (1L<<18)
1251 #define BNX2_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI             (1L<<19)
1252 #define BNX2_MISC_PERR_ENA1_COMXQ_PERR_EN_XI             (1L<<20)
1253 #define BNX2_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI             (1L<<21)
1254 #define BNX2_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI            (1L<<22)
1255 #define BNX2_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI            (1L<<23)
1256 #define BNX2_MISC_PERR_ENA1_CPQ_PERR_EN_XI               (1L<<24)
1257 #define BNX2_MISC_PERR_ENA1_CSQ_PERR_EN_XI               (1L<<25)
1258 #define BNX2_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI          (1L<<26)
1259 #define BNX2_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI       (1L<<27)
1260 #define BNX2_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI           (1L<<28)
1261 #define BNX2_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI            (1L<<29)
1262
1263 #define BNX2_MISC_PERR_ENA2                             0x000008ac
1264 #define BNX2_MISC_PERR_ENA2_COMQ_MISC                    (1L<<0)
1265 #define BNX2_MISC_PERR_ENA2_COMXQ_MISC                   (1L<<1)
1266 #define BNX2_MISC_PERR_ENA2_COMTQ_MISC                   (1L<<2)
1267 #define BNX2_MISC_PERR_ENA2_TSCHQ_MISC                   (1L<<3)
1268 #define BNX2_MISC_PERR_ENA2_TBDRQ_MISC                   (1L<<4)
1269 #define BNX2_MISC_PERR_ENA2_TXPQ_MISC                    (1L<<5)
1270 #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC                   (1L<<6)
1271 #define BNX2_MISC_PERR_ENA2_TPATQ_MISC                   (1L<<7)
1272 #define BNX2_MISC_PERR_ENA2_TASQ_MISC                    (1L<<8)
1273 #define BNX2_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI          (1L<<0)
1274 #define BNX2_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI            (1L<<1)
1275 #define BNX2_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI            (1L<<2)
1276 #define BNX2_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI           (1L<<3)
1277 #define BNX2_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI         (1L<<4)
1278 #define BNX2_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI            (1L<<5)
1279 #define BNX2_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI       (1L<<6)
1280
1281 #define BNX2_MISC_DEBUG_VECTOR_SEL                      0x000008b0
1282 #define BNX2_MISC_DEBUG_VECTOR_SEL_0                     (0xfffL<<0)
1283 #define BNX2_MISC_DEBUG_VECTOR_SEL_1                     (0xfffL<<12)
1284 #define BNX2_MISC_DEBUG_VECTOR_SEL_1_XI                  (0xfffL<<15)
1285
1286 #define BNX2_MISC_VREG_CONTROL                          0x000008b4
1287 #define BNX2_MISC_VREG_CONTROL_1_2                       (0xfL<<0)
1288 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_XI               (0xfL<<0)
1289 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI        (0L<<0)
1290 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI        (1L<<0)
1291 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI        (2L<<0)
1292 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI         (3L<<0)
1293 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI         (4L<<0)
1294 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI         (5L<<0)
1295 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI         (6L<<0)
1296 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI           (7L<<0)
1297 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI        (8L<<0)
1298 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI        (9L<<0)
1299 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI        (10L<<0)
1300 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI        (11L<<0)
1301 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI       (12L<<0)
1302 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI       (13L<<0)
1303 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI       (14L<<0)
1304 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI       (15L<<0)
1305 #define BNX2_MISC_VREG_CONTROL_2_5                       (0xfL<<4)
1306 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS14                (0L<<4)
1307 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS12                (1L<<4)
1308 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS10                (2L<<4)
1309 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS8                 (3L<<4)
1310 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS6                 (4L<<4)
1311 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS4                 (5L<<4)
1312 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS2                 (6L<<4)
1313 #define BNX2_MISC_VREG_CONTROL_2_5_NOM                   (7L<<4)
1314 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS2                (8L<<4)
1315 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS4                (9L<<4)
1316 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS6                (10L<<4)
1317 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS8                (11L<<4)
1318 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS10               (12L<<4)
1319 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS12               (13L<<4)
1320 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS14               (14L<<4)
1321 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS16               (15L<<4)
1322 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT                  (0xfL<<8)
1323 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14           (0L<<8)
1324 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS12           (1L<<8)
1325 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS10           (2L<<8)
1326 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS8            (3L<<8)
1327 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS6            (4L<<8)
1328 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS4            (5L<<8)
1329 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS2            (6L<<8)
1330 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_NOM              (7L<<8)
1331 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS2           (8L<<8)
1332 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS4           (9L<<8)
1333 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS6           (10L<<8)
1334 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS8           (11L<<8)
1335 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS10          (12L<<8)
1336 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS12          (13L<<8)
1337 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS14          (14L<<8)
1338 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS16          (15L<<8)
1339
1340 #define BNX2_MISC_FINAL_CLK_CTL_VAL                     0x000008b8
1341 #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL       (0x3ffffffL<<6)
1342
1343 #define BNX2_MISC_GP_HW_CTL0                            0x000008bc
1344 #define BNX2_MISC_GP_HW_CTL0_TX_DRIVE                    (1L<<0)
1345 #define BNX2_MISC_GP_HW_CTL0_RMII_MODE                   (1L<<1)
1346 #define BNX2_MISC_GP_HW_CTL0_RMII_CRSDV_SEL              (1L<<2)
1347 #define BNX2_MISC_GP_HW_CTL0_RVMII_MODE                  (1L<<3)
1348 #define BNX2_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE  (1L<<4)
1349 #define BNX2_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE       (1L<<5)
1350 #define BNX2_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE    (1L<<6)
1351 #define BNX2_MISC_GP_HW_CTL0_RESERVED1_XI                (0x7L<<4)
1352 #define BNX2_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY         (1L<<7)
1353 #define BNX2_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE     (1L<<8)
1354 #define BNX2_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE         (1L<<9)
1355 #define BNX2_MISC_GP_HW_CTL0_LED_ACT_SEL_TE              (1L<<10)
1356 #define BNX2_MISC_GP_HW_CTL0_RESERVED2_XI                (0x7L<<8)
1357 #define BNX2_MISC_GP_HW_CTL0_UP1_DEF0                    (1L<<11)
1358 #define BNX2_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF          (1L<<12)
1359 #define BNX2_MISC_GP_HW_CTL0_FORCE2500_DEF               (1L<<13)
1360 #define BNX2_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF          (1L<<14)
1361 #define BNX2_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF         (1L<<15)
1362 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI                 (0xfL<<16)
1363 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA             (0L<<16)
1364 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA           (1L<<16)
1365 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA           (3L<<16)
1366 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA           (5L<<16)
1367 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA           (7L<<16)
1368 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN           (15L<<16)
1369 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS             (1L<<20)
1370 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS             (1L<<21)
1371 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT                (0x3L<<22)
1372 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P            (0L<<22)
1373 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P            (1L<<22)
1374 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P            (2L<<22)
1375 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P            (3L<<22)
1376 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT                (0x3L<<24)
1377 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P            (0L<<24)
1378 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P            (1L<<24)
1379 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P            (2L<<24)
1380 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P            (3L<<24)
1381 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ            (0x3L<<26)
1382 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA      (0L<<26)
1383 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA      (1L<<26)
1384 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA      (2L<<26)
1385 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA      (3L<<26)
1386 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ           (0x3L<<28)
1387 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA     (0L<<28)
1388 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA     (1L<<28)
1389 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA     (2L<<28)
1390 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA     (3L<<28)
1391 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ            (0x3L<<30)
1392 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57       (0L<<30)
1393 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45       (1L<<30)
1394 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62       (2L<<30)
1395 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66       (3L<<30)
1396
1397 #define BNX2_MISC_GP_HW_CTL1                            0x000008c0
1398 #define BNX2_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE         (1L<<0)
1399 #define BNX2_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE         (1L<<1)
1400 #define BNX2_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE          (1L<<2)
1401 #define BNX2_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE          (1L<<3)
1402 #define BNX2_MISC_GP_HW_CTL1_RESERVED_SOFT_XI            (0xffffL<<0)
1403 #define BNX2_MISC_GP_HW_CTL1_RESERVED_HARD_XI            (0xffffL<<16)
1404
1405 #define BNX2_MISC_NEW_HW_CTL                            0x000008c4
1406 #define BNX2_MISC_NEW_HW_CTL_MAIN_POR_BYPASS             (1L<<0)
1407 #define BNX2_MISC_NEW_HW_CTL_RINGOSC_ENABLE              (1L<<1)
1408 #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL0                (1L<<2)
1409 #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL1                (1L<<3)
1410 #define BNX2_MISC_NEW_HW_CTL_RESERVED_SHARED             (0xfffL<<4)
1411 #define BNX2_MISC_NEW_HW_CTL_RESERVED_SPLIT              (0xffffL<<16)
1412
1413 #define BNX2_MISC_NEW_CORE_CTL                          0x000008c8
1414 #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS      (1L<<0)
1415 #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ          (1L<<1)
1416 #define BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE                (1L<<16)
1417 #define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN              (0x3fffL<<2)
1418 #define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC               (0xffffL<<16)
1419
1420 #define BNX2_MISC_ECO_HW_CTL                            0x000008cc
1421 #define BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN          (1L<<0)
1422 #define BNX2_MISC_ECO_HW_CTL_RESERVED_SOFT               (0x7fffL<<1)
1423 #define BNX2_MISC_ECO_HW_CTL_RESERVED_HARD               (0xffffL<<16)
1424
1425 #define BNX2_MISC_ECO_CORE_CTL                          0x000008d0
1426 #define BNX2_MISC_ECO_CORE_CTL_RESERVED_SOFT             (0xffffL<<0)
1427 #define BNX2_MISC_ECO_CORE_CTL_RESERVED_HARD             (0xffffL<<16)
1428
1429 #define BNX2_MISC_PPIO                                  0x000008d4
1430 #define BNX2_MISC_PPIO_VALUE                             (0xfL<<0)
1431 #define BNX2_MISC_PPIO_SET                               (0xfL<<8)
1432 #define BNX2_MISC_PPIO_CLR                               (0xfL<<16)
1433 #define BNX2_MISC_PPIO_FLOAT                             (0xfL<<24)
1434
1435 #define BNX2_MISC_PPIO_INT                              0x000008d8
1436 #define BNX2_MISC_PPIO_INT_INT_STATE                     (0xfL<<0)
1437 #define BNX2_MISC_PPIO_INT_OLD_VALUE                     (0xfL<<8)
1438 #define BNX2_MISC_PPIO_INT_OLD_SET                       (0xfL<<16)
1439 #define BNX2_MISC_PPIO_INT_OLD_CLR                       (0xfL<<24)
1440
1441 #define BNX2_MISC_RESET_NUMS                            0x000008dc
1442 #define BNX2_MISC_RESET_NUMS_NUM_HARD_RESETS             (0x7L<<0)
1443 #define BNX2_MISC_RESET_NUMS_NUM_PCIE_RESETS             (0x7L<<4)
1444 #define BNX2_MISC_RESET_NUMS_NUM_PERSTB_RESETS           (0x7L<<8)
1445 #define BNX2_MISC_RESET_NUMS_NUM_CMN_RESETS              (0x7L<<12)
1446 #define BNX2_MISC_RESET_NUMS_NUM_PORT_RESETS             (0x7L<<16)
1447
1448 #define BNX2_MISC_CS16_ERR                              0x000008e0
1449 #define BNX2_MISC_CS16_ERR_ENA_PCI                       (1L<<0)
1450 #define BNX2_MISC_CS16_ERR_ENA_RDMA                      (1L<<1)
1451 #define BNX2_MISC_CS16_ERR_ENA_TDMA                      (1L<<2)
1452 #define BNX2_MISC_CS16_ERR_ENA_EMAC                      (1L<<3)
1453 #define BNX2_MISC_CS16_ERR_ENA_CTX                       (1L<<4)
1454 #define BNX2_MISC_CS16_ERR_ENA_TBDR                      (1L<<5)
1455 #define BNX2_MISC_CS16_ERR_ENA_RBDC                      (1L<<6)
1456 #define BNX2_MISC_CS16_ERR_ENA_COM                       (1L<<7)
1457 #define BNX2_MISC_CS16_ERR_ENA_CP                        (1L<<8)
1458 #define BNX2_MISC_CS16_ERR_STA_PCI                       (1L<<16)
1459 #define BNX2_MISC_CS16_ERR_STA_RDMA                      (1L<<17)
1460 #define BNX2_MISC_CS16_ERR_STA_TDMA                      (1L<<18)
1461 #define BNX2_MISC_CS16_ERR_STA_EMAC                      (1L<<19)
1462 #define BNX2_MISC_CS16_ERR_STA_CTX                       (1L<<20)
1463 #define BNX2_MISC_CS16_ERR_STA_TBDR                      (1L<<21)
1464 #define BNX2_MISC_CS16_ERR_STA_RBDC                      (1L<<22)
1465 #define BNX2_MISC_CS16_ERR_STA_COM                       (1L<<23)
1466 #define BNX2_MISC_CS16_ERR_STA_CP                        (1L<<24)
1467
1468 #define BNX2_MISC_SPIO_EVENT                            0x000008e4
1469 #define BNX2_MISC_SPIO_EVENT_ENABLE                      (0xffL<<0)
1470
1471 #define BNX2_MISC_PPIO_EVENT                            0x000008e8
1472 #define BNX2_MISC_PPIO_EVENT_ENABLE                      (0xfL<<0)
1473
1474 #define BNX2_MISC_DUAL_MEDIA_CTRL                       0x000008ec
1475 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID                (0xffL<<0)
1476 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X              (0L<<0)
1477 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C              (3L<<0)
1478 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S              (12L<<0)
1479 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP         (0x7L<<8)
1480 #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN          (1L<<11)
1481 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET         (1L<<12)
1482 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET         (1L<<13)
1483 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET            (1L<<14)
1484 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET            (1L<<15)
1485 #define BNX2_MISC_DUAL_MEDIA_CTRL_LCPLL_RST              (1L<<16)
1486 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_RST            (1L<<17)
1487 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_RST            (1L<<18)
1488 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_RST               (1L<<19)
1489 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_RST               (1L<<20)
1490 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL               (0x7L<<21)
1491 #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP              (1L<<24)
1492 #define BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE         (1L<<25)
1493 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ        (0xfL<<26)
1494 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ      (1L<<26)
1495 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ      (2L<<26)
1496 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ      (4L<<26)
1497 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ      (8L<<26)
1498
1499 #define BNX2_MISC_OTP_CMD1                              0x000008f0
1500 #define BNX2_MISC_OTP_CMD1_FMODE                         (0x7L<<0)
1501 #define BNX2_MISC_OTP_CMD1_FMODE_IDLE                    (0L<<0)
1502 #define BNX2_MISC_OTP_CMD1_FMODE_WRITE                   (1L<<0)
1503 #define BNX2_MISC_OTP_CMD1_FMODE_INIT                    (2L<<0)
1504 #define BNX2_MISC_OTP_CMD1_FMODE_SET                     (3L<<0)
1505 #define BNX2_MISC_OTP_CMD1_FMODE_RST                     (4L<<0)
1506 #define BNX2_MISC_OTP_CMD1_FMODE_VERIFY                  (5L<<0)
1507 #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED0               (6L<<0)
1508 #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED1               (7L<<0)
1509 #define BNX2_MISC_OTP_CMD1_USEPINS                       (1L<<8)
1510 #define BNX2_MISC_OTP_CMD1_PROGSEL                       (1L<<9)
1511 #define BNX2_MISC_OTP_CMD1_PROGSTART                     (1L<<10)
1512 #define BNX2_MISC_OTP_CMD1_PCOUNT                        (0x7L<<16)
1513 #define BNX2_MISC_OTP_CMD1_PBYP                          (1L<<19)
1514 #define BNX2_MISC_OTP_CMD1_VSEL                          (0xfL<<20)
1515 #define BNX2_MISC_OTP_CMD1_TM                            (0x7L<<27)
1516 #define BNX2_MISC_OTP_CMD1_SADBYP                        (1L<<30)
1517 #define BNX2_MISC_OTP_CMD1_DEBUG                         (1L<<31)
1518
1519 #define BNX2_MISC_OTP_CMD2                              0x000008f4
1520 #define BNX2_MISC_OTP_CMD2_OTP_ROM_ADDR                  (0x3ffL<<0)
1521 #define BNX2_MISC_OTP_CMD2_DOSEL                         (0x7fL<<16)
1522 #define BNX2_MISC_OTP_CMD2_DOSEL_0                       (0L<<16)
1523 #define BNX2_MISC_OTP_CMD2_DOSEL_1                       (1L<<16)
1524 #define BNX2_MISC_OTP_CMD2_DOSEL_127                     (127L<<16)
1525
1526 #define BNX2_MISC_OTP_STATUS                            0x000008f8
1527 #define BNX2_MISC_OTP_STATUS_DATA                        (0xffL<<0)
1528 #define BNX2_MISC_OTP_STATUS_VALID                       (1L<<8)
1529 #define BNX2_MISC_OTP_STATUS_BUSY                        (1L<<9)
1530 #define BNX2_MISC_OTP_STATUS_BUSYSM                      (1L<<10)
1531 #define BNX2_MISC_OTP_STATUS_DONE                        (1L<<11)
1532
1533 #define BNX2_MISC_OTP_SHIFT1_CMD                        0x000008fc
1534 #define BNX2_MISC_OTP_SHIFT1_CMD_RESET_MODE_N            (1L<<0)
1535 #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_DONE              (1L<<1)
1536 #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_START             (1L<<2)
1537 #define BNX2_MISC_OTP_SHIFT1_CMD_LOAD_DATA               (1L<<3)
1538 #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT            (0x1fL<<8)
1539
1540 #define BNX2_MISC_OTP_SHIFT1_DATA                       0x00000900
1541 #define BNX2_MISC_OTP_SHIFT2_CMD                        0x00000904
1542 #define BNX2_MISC_OTP_SHIFT2_CMD_RESET_MODE_N            (1L<<0)
1543 #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_DONE              (1L<<1)
1544 #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_START             (1L<<2)
1545 #define BNX2_MISC_OTP_SHIFT2_CMD_LOAD_DATA               (1L<<3)
1546 #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT            (0x1fL<<8)
1547
1548 #define BNX2_MISC_OTP_SHIFT2_DATA                       0x00000908
1549 #define BNX2_MISC_BIST_CS0                              0x0000090c
1550 #define BNX2_MISC_BIST_CS0_MBIST_EN                      (1L<<0)
1551 #define BNX2_MISC_BIST_CS0_BIST_SETUP                    (0x3L<<1)
1552 #define BNX2_MISC_BIST_CS0_MBIST_ASYNC_RESET             (1L<<3)
1553 #define BNX2_MISC_BIST_CS0_MBIST_DONE                    (1L<<8)
1554 #define BNX2_MISC_BIST_CS0_MBIST_GO                      (1L<<9)
1555 #define BNX2_MISC_BIST_CS0_BIST_OVERRIDE                 (1L<<31)
1556
1557 #define BNX2_MISC_BIST_MEMSTATUS0                       0x00000910
1558 #define BNX2_MISC_BIST_CS1                              0x00000914
1559 #define BNX2_MISC_BIST_CS1_MBIST_EN                      (1L<<0)
1560 #define BNX2_MISC_BIST_CS1_BIST_SETUP                    (0x3L<<1)
1561 #define BNX2_MISC_BIST_CS1_MBIST_ASYNC_RESET             (1L<<3)
1562 #define BNX2_MISC_BIST_CS1_MBIST_DONE                    (1L<<8)
1563 #define BNX2_MISC_BIST_CS1_MBIST_GO                      (1L<<9)
1564
1565 #define BNX2_MISC_BIST_MEMSTATUS1                       0x00000918
1566 #define BNX2_MISC_BIST_CS2                              0x0000091c
1567 #define BNX2_MISC_BIST_CS2_MBIST_EN                      (1L<<0)
1568 #define BNX2_MISC_BIST_CS2_BIST_SETUP                    (0x3L<<1)
1569 #define BNX2_MISC_BIST_CS2_MBIST_ASYNC_RESET             (1L<<3)
1570 #define BNX2_MISC_BIST_CS2_MBIST_DONE                    (1L<<8)
1571 #define BNX2_MISC_BIST_CS2_MBIST_GO                      (1L<<9)
1572
1573 #define BNX2_MISC_BIST_MEMSTATUS2                       0x00000920
1574 #define BNX2_MISC_BIST_CS3                              0x00000924
1575 #define BNX2_MISC_BIST_CS3_MBIST_EN                      (1L<<0)
1576 #define BNX2_MISC_BIST_CS3_BIST_SETUP                    (0x3L<<1)
1577 #define BNX2_MISC_BIST_CS3_MBIST_ASYNC_RESET             (1L<<3)
1578 #define BNX2_MISC_BIST_CS3_MBIST_DONE                    (1L<<8)
1579 #define BNX2_MISC_BIST_CS3_MBIST_GO                      (1L<<9)
1580
1581 #define BNX2_MISC_BIST_MEMSTATUS3                       0x00000928
1582 #define BNX2_MISC_BIST_CS4                              0x0000092c
1583 #define BNX2_MISC_BIST_CS4_MBIST_EN                      (1L<<0)
1584 #define BNX2_MISC_BIST_CS4_BIST_SETUP                    (0x3L<<1)
1585 #define BNX2_MISC_BIST_CS4_MBIST_ASYNC_RESET             (1L<<3)
1586 #define BNX2_MISC_BIST_CS4_MBIST_DONE                    (1L<<8)
1587 #define BNX2_MISC_BIST_CS4_MBIST_GO                      (1L<<9)
1588
1589 #define BNX2_MISC_BIST_MEMSTATUS4                       0x00000930
1590 #define BNX2_MISC_BIST_CS5                              0x00000934
1591 #define BNX2_MISC_BIST_CS5_MBIST_EN                      (1L<<0)
1592 #define BNX2_MISC_BIST_CS5_BIST_SETUP                    (0x3L<<1)
1593 #define BNX2_MISC_BIST_CS5_MBIST_ASYNC_RESET             (1L<<3)
1594 #define BNX2_MISC_BIST_CS5_MBIST_DONE                    (1L<<8)
1595 #define BNX2_MISC_BIST_CS5_MBIST_GO                      (1L<<9)
1596
1597 #define BNX2_MISC_BIST_MEMSTATUS5                       0x00000938
1598 #define BNX2_MISC_MEM_TM0                               0x0000093c
1599 #define BNX2_MISC_MEM_TM0_PCIE_REPLAY_TM                 (0xfL<<0)
1600 #define BNX2_MISC_MEM_TM0_MCP_SCPAD                      (0xfL<<8)
1601 #define BNX2_MISC_MEM_TM0_UMP_TM                         (0xffL<<16)
1602 #define BNX2_MISC_MEM_TM0_HB_MEM_TM                      (0xfL<<24)
1603
1604 #define BNX2_MISC_USPLL_CTRL                            0x00000940
1605 #define BNX2_MISC_USPLL_CTRL_PH_DET_DIS                  (1L<<0)
1606 #define BNX2_MISC_USPLL_CTRL_FREQ_DET_DIS                (1L<<1)
1607 #define BNX2_MISC_USPLL_CTRL_LCPX                        (0x3fL<<2)
1608 #define BNX2_MISC_USPLL_CTRL_RX                          (0x3L<<8)
1609 #define BNX2_MISC_USPLL_CTRL_VC_EN                       (1L<<10)
1610 #define BNX2_MISC_USPLL_CTRL_VCO_MG                      (0x3L<<11)
1611 #define BNX2_MISC_USPLL_CTRL_KVCO_XF                     (0x7L<<13)
1612 #define BNX2_MISC_USPLL_CTRL_KVCO_XS                     (0x7L<<16)
1613 #define BNX2_MISC_USPLL_CTRL_TESTD_EN                    (1L<<19)
1614 #define BNX2_MISC_USPLL_CTRL_TESTD_SEL                   (0x7L<<20)
1615 #define BNX2_MISC_USPLL_CTRL_TESTA_EN                    (1L<<23)
1616 #define BNX2_MISC_USPLL_CTRL_TESTA_SEL                   (0x3L<<24)
1617 #define BNX2_MISC_USPLL_CTRL_ATTEN_FREF                  (1L<<26)
1618 #define BNX2_MISC_USPLL_CTRL_DIGITAL_RST                 (1L<<27)
1619 #define BNX2_MISC_USPLL_CTRL_ANALOG_RST                  (1L<<28)
1620 #define BNX2_MISC_USPLL_CTRL_LOCK                        (1L<<29)
1621
1622 #define BNX2_MISC_PERR_STATUS0                          0x00000944
1623 #define BNX2_MISC_PERR_STATUS0_COM_DMAE_PERR             (1L<<0)
1624 #define BNX2_MISC_PERR_STATUS0_CP_DMAE_PERR              (1L<<1)
1625 #define BNX2_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR        (1L<<2)
1626 #define BNX2_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR        (1L<<3)
1627 #define BNX2_MISC_PERR_STATUS0_CTX_PGTBL_PERR            (1L<<4)
1628 #define BNX2_MISC_PERR_STATUS0_CTX_CACHE_PERR            (1L<<5)
1629 #define BNX2_MISC_PERR_STATUS0_CTX_MIRROR_PERR           (1L<<6)
1630 #define BNX2_MISC_PERR_STATUS0_COM_CTXC_PERR             (1L<<7)
1631 #define BNX2_MISC_PERR_STATUS0_COM_SCPAD_PERR            (1L<<8)
1632 #define BNX2_MISC_PERR_STATUS0_CP_CTXC_PERR              (1L<<9)
1633 #define BNX2_MISC_PERR_STATUS0_CP_SCPAD_PERR             (1L<<10)
1634 #define BNX2_MISC_PERR_STATUS0_RXP_RBUFC_PERR            (1L<<11)
1635 #define BNX2_MISC_PERR_STATUS0_RXP_CTXC_PERR             (1L<<12)
1636 #define BNX2_MISC_PERR_STATUS0_RXP_SCPAD_PERR            (1L<<13)
1637 #define BNX2_MISC_PERR_STATUS0_TPAT_SCPAD_PERR           (1L<<14)
1638 #define BNX2_MISC_PERR_STATUS0_TXP_CTXC_PERR             (1L<<15)
1639 #define BNX2_MISC_PERR_STATUS0_TXP_SCPAD_PERR            (1L<<16)
1640 #define BNX2_MISC_PERR_STATUS0_CS_TMEM_PERR              (1L<<17)
1641 #define BNX2_MISC_PERR_STATUS0_MQ_CTX_PERR               (1L<<18)
1642 #define BNX2_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR         (1L<<19)
1643 #define BNX2_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR         (1L<<20)
1644 #define BNX2_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR          (1L<<21)
1645 #define BNX2_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR         (1L<<22)
1646 #define BNX2_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR          (1L<<23)
1647 #define BNX2_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR          (1L<<24)
1648 #define BNX2_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR         (1L<<25)
1649 #define BNX2_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR         (1L<<26)
1650 #define BNX2_MISC_PERR_STATUS0_TPBUF_PERR                (1L<<27)
1651 #define BNX2_MISC_PERR_STATUS0_THBUF_PERR                (1L<<28)
1652 #define BNX2_MISC_PERR_STATUS0_TDMA_PERR                 (1L<<29)
1653 #define BNX2_MISC_PERR_STATUS0_TBDC_PERR                 (1L<<30)
1654 #define BNX2_MISC_PERR_STATUS0_TSCH_LR_PERR              (1L<<31)
1655
1656 #define BNX2_MISC_PERR_STATUS1                          0x00000948
1657 #define BNX2_MISC_PERR_STATUS1_RBDC_PERR                 (1L<<0)
1658 #define BNX2_MISC_PERR_STATUS1_RDMA_DFIFO_PERR           (1L<<2)
1659 #define BNX2_MISC_PERR_STATUS1_HC_STATS_PERR             (1L<<3)
1660 #define BNX2_MISC_PERR_STATUS1_HC_MSIX_PERR              (1L<<4)
1661 #define BNX2_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR         (1L<<5)
1662 #define BNX2_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR         (1L<<6)
1663 #define BNX2_MISC_PERR_STATUS1_TPATQ_PERR                (1L<<7)
1664 #define BNX2_MISC_PERR_STATUS1_MCPQ_PERR                 (1L<<8)
1665 #define BNX2_MISC_PERR_STATUS1_TDMAQ_PERR                (1L<<9)
1666 #define BNX2_MISC_PERR_STATUS1_TXPQ_PERR                 (1L<<10)
1667 #define BNX2_MISC_PERR_STATUS1_COMTQ_PERR                (1L<<11)
1668 #define BNX2_MISC_PERR_STATUS1_COMQ_PERR                 (1L<<12)
1669 #define BNX2_MISC_PERR_STATUS1_RLUPQ_PERR                (1L<<13)
1670 #define BNX2_MISC_PERR_STATUS1_RXPQ_PERR                 (1L<<14)
1671 #define BNX2_MISC_PERR_STATUS1_RV2PPQ_PERR               (1L<<15)
1672 #define BNX2_MISC_PERR_STATUS1_RDMAQ_PERR                (1L<<16)
1673 #define BNX2_MISC_PERR_STATUS1_TASQ_PERR                 (1L<<17)
1674 #define BNX2_MISC_PERR_STATUS1_TBDRQ_PERR                (1L<<18)
1675 #define BNX2_MISC_PERR_STATUS1_TSCHQ_PERR                (1L<<19)
1676 #define BNX2_MISC_PERR_STATUS1_COMXQ_PERR                (1L<<20)
1677 #define BNX2_MISC_PERR_STATUS1_RXPCQ_PERR                (1L<<21)
1678 #define BNX2_MISC_PERR_STATUS1_RV2PTQ_PERR               (1L<<22)
1679 #define BNX2_MISC_PERR_STATUS1_RV2PMQ_PERR               (1L<<23)
1680 #define BNX2_MISC_PERR_STATUS1_CPQ_PERR                  (1L<<24)
1681 #define BNX2_MISC_PERR_STATUS1_CSQ_PERR                  (1L<<25)
1682 #define BNX2_MISC_PERR_STATUS1_RLUP_CID_PERR             (1L<<26)
1683 #define BNX2_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR          (1L<<27)
1684 #define BNX2_MISC_PERR_STATUS1_RV2PCSQ_PERR              (1L<<28)
1685 #define BNX2_MISC_PERR_STATUS1_MQ_IDX_PERR               (1L<<29)
1686
1687 #define BNX2_MISC_PERR_STATUS2                          0x0000094c
1688 #define BNX2_MISC_PERR_STATUS2_TGT_FIFO_PERR             (1L<<0)
1689 #define BNX2_MISC_PERR_STATUS2_UMP_TX_PERR               (1L<<1)
1690 #define BNX2_MISC_PERR_STATUS2_UMP_RX_PERR               (1L<<2)
1691 #define BNX2_MISC_PERR_STATUS2_MCP_ROM_PERR              (1L<<3)
1692 #define BNX2_MISC_PERR_STATUS2_MCP_SCPAD_PERR            (1L<<4)
1693 #define BNX2_MISC_PERR_STATUS2_HB_MEM_PERR               (1L<<5)
1694 #define BNX2_MISC_PERR_STATUS2_PCIE_REPLAY_PERR          (1L<<6)
1695
1696 #define BNX2_MISC_LCPLL_CTRL0                           0x00000950
1697 #define BNX2_MISC_LCPLL_CTRL0_OAC                        (0x7L<<0)
1698 #define BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY              (0L<<0)
1699 #define BNX2_MISC_LCPLL_CTRL0_OAC_ZERO                   (1L<<0)
1700 #define BNX2_MISC_LCPLL_CTRL0_OAC_TWENTY                 (3L<<0)
1701 #define BNX2_MISC_LCPLL_CTRL0_OAC_FORTY                  (7L<<0)
1702 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL                   (0x7L<<3)
1703 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360               (0L<<3)
1704 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_480               (1L<<3)
1705 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_600               (3L<<3)
1706 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_720               (7L<<3)
1707 #define BNX2_MISC_LCPLL_CTRL0_BIAS_CTRL                  (0x3L<<6)
1708 #define BNX2_MISC_LCPLL_CTRL0_PLL_OBSERVE                (0x7L<<8)
1709 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL                   (0x3L<<11)
1710 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0                 (0L<<11)
1711 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_1                 (1L<<11)
1712 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_2                 (2L<<11)
1713 #define BNX2_MISC_LCPLL_CTRL0_PLLSEQSTART                (1L<<13)
1714 #define BNX2_MISC_LCPLL_CTRL0_RESERVED                   (1L<<14)
1715 #define BNX2_MISC_LCPLL_CTRL0_CAPRETRY_EN                (1L<<15)
1716 #define BNX2_MISC_LCPLL_CTRL0_FREQMONITOR_EN             (1L<<16)
1717 #define BNX2_MISC_LCPLL_CTRL0_FREQDETRESTART_EN          (1L<<17)
1718 #define BNX2_MISC_LCPLL_CTRL0_FREQDETRETRY_EN            (1L<<18)
1719 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN           (1L<<19)
1720 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE              (1L<<20)
1721 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFPASS              (1L<<21)
1722 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN         (1L<<22)
1723 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE            (1L<<23)
1724 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN         (1L<<24)
1725 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS            (1L<<25)
1726 #define BNX2_MISC_LCPLL_CTRL0_CAPRESTART                 (1L<<26)
1727 #define BNX2_MISC_LCPLL_CTRL0_CAPSELECTM_EN              (1L<<27)
1728
1729 #define BNX2_MISC_LCPLL_CTRL1                           0x00000954
1730 #define BNX2_MISC_LCPLL_CTRL1_CAPSELECTM                 (0x1fL<<0)
1731 #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN        (1L<<5)
1732 #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN           (1L<<6)
1733 #define BNX2_MISC_LCPLL_CTRL1_SLOWDN_XOR                 (1L<<7)
1734
1735 #define BNX2_MISC_LCPLL_STATUS                          0x00000958
1736 #define BNX2_MISC_LCPLL_STATUS_FREQDONE_SM               (1L<<0)
1737 #define BNX2_MISC_LCPLL_STATUS_FREQPASS_SM               (1L<<1)
1738 #define BNX2_MISC_LCPLL_STATUS_PLLSEQDONE                (1L<<2)
1739 #define BNX2_MISC_LCPLL_STATUS_PLLSEQPASS                (1L<<3)
1740 #define BNX2_MISC_LCPLL_STATUS_PLLSTATE                  (0x7L<<4)
1741 #define BNX2_MISC_LCPLL_STATUS_CAPSTATE                  (0x7L<<7)
1742 #define BNX2_MISC_LCPLL_STATUS_CAPSELECT                 (0x1fL<<10)
1743 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR          (1L<<15)
1744 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0        (0L<<15)
1745 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1        (1L<<15)
1746
1747 #define BNX2_MISC_OSCFUNDS_CTRL                         0x0000095c
1748 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON                 (1L<<5)
1749 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF             (0L<<5)
1750 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_ON              (1L<<5)
1751 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM               (0x3L<<6)
1752 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0             (0L<<6)
1753 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1             (1L<<6)
1754 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2             (2L<<6)
1755 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3             (3L<<6)
1756 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ                (0x3L<<8)
1757 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0              (0L<<8)
1758 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1              (1L<<8)
1759 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2              (2L<<8)
1760 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3              (3L<<8)
1761 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ                 (0x3L<<10)
1762 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0               (0L<<10)
1763 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1               (1L<<10)
1764 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2               (2L<<10)
1765 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3               (3L<<10)
1766
1767
1768 /*
1769  *  nvm_reg definition
1770  *  offset: 0x6400
1771  */
1772 #define BNX2_NVM_COMMAND                                0x00006400
1773 #define BNX2_NVM_COMMAND_RST                             (1L<<0)
1774 #define BNX2_NVM_COMMAND_DONE                            (1L<<3)
1775 #define BNX2_NVM_COMMAND_DOIT                            (1L<<4)
1776 #define BNX2_NVM_COMMAND_WR                              (1L<<5)
1777 #define BNX2_NVM_COMMAND_ERASE                           (1L<<6)
1778 #define BNX2_NVM_COMMAND_FIRST                           (1L<<7)
1779 #define BNX2_NVM_COMMAND_LAST                            (1L<<8)
1780 #define BNX2_NVM_COMMAND_WREN                            (1L<<16)
1781 #define BNX2_NVM_COMMAND_WRDI                            (1L<<17)
1782 #define BNX2_NVM_COMMAND_EWSR                            (1L<<18)
1783 #define BNX2_NVM_COMMAND_WRSR                            (1L<<19)
1784 #define BNX2_NVM_COMMAND_RD_ID                           (1L<<20)
1785 #define BNX2_NVM_COMMAND_RD_STATUS                       (1L<<21)
1786 #define BNX2_NVM_COMMAND_MODE_256                        (1L<<22)
1787
1788 #define BNX2_NVM_STATUS                                 0x00006404
1789 #define BNX2_NVM_STATUS_PI_FSM_STATE                     (0xfL<<0)
1790 #define BNX2_NVM_STATUS_EE_FSM_STATE                     (0xfL<<4)
1791 #define BNX2_NVM_STATUS_EQ_FSM_STATE                     (0xfL<<8)
1792 #define BNX2_NVM_STATUS_SPI_FSM_STATE_XI                 (0x1fL<<0)
1793 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI        (0L<<0)
1794 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI        (1L<<0)
1795 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI        (2L<<0)
1796 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI         (3L<<0)
1797 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI         (4L<<0)
1798 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI       (5L<<0)
1799 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI         (6L<<0)
1800 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI         (7L<<0)
1801 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI         (8L<<0)
1802 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI  (9L<<0)
1803 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI  (10L<<0)
1804 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI  (11L<<0)
1805 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI   (12L<<0)
1806 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI   (13L<<0)
1807 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI   (14L<<0)
1808 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI   (15L<<0)
1809 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI   (16L<<0)
1810 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI         (17L<<0)
1811 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI     (18L<<0)
1812 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI        (19L<<0)
1813
1814 #define BNX2_NVM_WRITE                                  0x00006408
1815 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE                   (0xffffffffL<<0)
1816 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG          (0L<<0)
1817 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK             (1L<<0)
1818 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA            (2L<<0)
1819 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK              (4L<<0)
1820 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B              (8L<<0)
1821 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO                (16L<<0)
1822 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI                (32L<<0)
1823 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI_XI             (1L<<0)
1824 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO_XI             (2L<<0)
1825 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI           (4L<<0)
1826 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI           (8L<<0)
1827
1828 #define BNX2_NVM_ADDR                                   0x0000640c
1829 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE                     (0xffffffL<<0)
1830 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG            (0L<<0)
1831 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK               (1L<<0)
1832 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA              (2L<<0)
1833 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK                (4L<<0)
1834 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B                (8L<<0)
1835 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO                  (16L<<0)
1836 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI                  (32L<<0)
1837 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI_XI               (1L<<0)
1838 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO_XI               (2L<<0)
1839 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI             (4L<<0)
1840 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI             (8L<<0)
1841
1842 #define BNX2_NVM_READ                                   0x00006410
1843 #define BNX2_NVM_READ_NVM_READ_VALUE                     (0xffffffffL<<0)
1844 #define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG            (0L<<0)
1845 #define BNX2_NVM_READ_NVM_READ_VALUE_EECLK               (1L<<0)
1846 #define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA              (2L<<0)
1847 #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK                (4L<<0)
1848 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B                (8L<<0)
1849 #define BNX2_NVM_READ_NVM_READ_VALUE_SO                  (16L<<0)
1850 #define BNX2_NVM_READ_NVM_READ_VALUE_SI                  (32L<<0)
1851 #define BNX2_NVM_READ_NVM_READ_VALUE_SI_XI               (1L<<0)
1852 #define BNX2_NVM_READ_NVM_READ_VALUE_SO_XI               (2L<<0)
1853 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B_XI             (4L<<0)
1854 #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK_XI             (8L<<0)
1855
1856 #define BNX2_NVM_CFG1                                   0x00006414
1857 #define BNX2_NVM_CFG1_FLASH_MODE                         (1L<<0)
1858 #define BNX2_NVM_CFG1_BUFFER_MODE                        (1L<<1)
1859 #define BNX2_NVM_CFG1_PASS_MODE                          (1L<<2)
1860 #define BNX2_NVM_CFG1_BITBANG_MODE                       (1L<<3)
1861 #define BNX2_NVM_CFG1_STATUS_BIT                         (0x7L<<4)
1862 #define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY               (0L<<4)
1863 #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY              (7L<<4)
1864 #define BNX2_NVM_CFG1_SPI_CLK_DIV                        (0xfL<<7)
1865 #define BNX2_NVM_CFG1_SEE_CLK_DIV                        (0x7ffL<<11)
1866 #define BNX2_NVM_CFG1_STRAP_CONTROL_0                    (1L<<23)
1867 #define BNX2_NVM_CFG1_PROTECT_MODE                       (1L<<24)
1868 #define BNX2_NVM_CFG1_FLASH_SIZE                         (1L<<25)
1869 #define BNX2_NVM_CFG1_FW_USTRAP_1                        (1L<<26)
1870 #define BNX2_NVM_CFG1_FW_USTRAP_0                        (1L<<27)
1871 #define BNX2_NVM_CFG1_FW_USTRAP_2                        (1L<<28)
1872 #define BNX2_NVM_CFG1_FW_USTRAP_3                        (1L<<29)
1873 #define BNX2_NVM_CFG1_FW_FLASH_TYPE_EN                   (1L<<30)
1874 #define BNX2_NVM_CFG1_COMPAT_BYPASSS                     (1L<<31)
1875
1876 #define BNX2_NVM_CFG2                                   0x00006418
1877 #define BNX2_NVM_CFG2_ERASE_CMD                          (0xffL<<0)
1878 #define BNX2_NVM_CFG2_DUMMY                              (0xffL<<8)
1879 #define BNX2_NVM_CFG2_STATUS_CMD                         (0xffL<<16)
1880 #define BNX2_NVM_CFG2_READ_ID                            (0xffL<<24)
1881
1882 #define BNX2_NVM_CFG3                                   0x0000641c
1883 #define BNX2_NVM_CFG3_BUFFER_RD_CMD                      (0xffL<<0)
1884 #define BNX2_NVM_CFG3_WRITE_CMD                          (0xffL<<8)
1885 #define BNX2_NVM_CFG3_BUFFER_WRITE_CMD                   (0xffL<<16)
1886 #define BNX2_NVM_CFG3_READ_CMD                           (0xffL<<24)
1887
1888 #define BNX2_NVM_SW_ARB                                 0x00006420
1889 #define BNX2_NVM_SW_ARB_ARB_REQ_SET0                     (1L<<0)
1890 #define BNX2_NVM_SW_ARB_ARB_REQ_SET1                     (1L<<1)
1891 #define BNX2_NVM_SW_ARB_ARB_REQ_SET2                     (1L<<2)
1892 #define BNX2_NVM_SW_ARB_ARB_REQ_SET3                     (1L<<3)
1893 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR0                     (1L<<4)
1894 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR1                     (1L<<5)
1895 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR2                     (1L<<6)
1896 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR3                     (1L<<7)
1897 #define BNX2_NVM_SW_ARB_ARB_ARB0                         (1L<<8)
1898 #define BNX2_NVM_SW_ARB_ARB_ARB1                         (1L<<9)
1899 #define BNX2_NVM_SW_ARB_ARB_ARB2                         (1L<<10)
1900 #define BNX2_NVM_SW_ARB_ARB_ARB3                         (1L<<11)
1901 #define BNX2_NVM_SW_ARB_REQ0                             (1L<<12)
1902 #define BNX2_NVM_SW_ARB_REQ1                             (1L<<13)
1903 #define BNX2_NVM_SW_ARB_REQ2                             (1L<<14)
1904 #define BNX2_NVM_SW_ARB_REQ3                             (1L<<15)
1905
1906 #define BNX2_NVM_ACCESS_ENABLE                          0x00006424
1907 #define BNX2_NVM_ACCESS_ENABLE_EN                        (1L<<0)
1908 #define BNX2_NVM_ACCESS_ENABLE_WR_EN                     (1L<<1)
1909
1910 #define BNX2_NVM_WRITE1                                 0x00006428
1911 #define BNX2_NVM_WRITE1_WREN_CMD                         (0xffL<<0)
1912 #define BNX2_NVM_WRITE1_WRDI_CMD                         (0xffL<<8)
1913 #define BNX2_NVM_WRITE1_SR_DATA                          (0xffL<<16)
1914
1915 #define BNX2_NVM_CFG4                                   0x0000642c
1916 #define BNX2_NVM_CFG4_FLASH_SIZE                         (0x7L<<0)
1917 #define BNX2_NVM_CFG4_FLASH_SIZE_1MBIT                   (0L<<0)
1918 #define BNX2_NVM_CFG4_FLASH_SIZE_2MBIT                   (1L<<0)
1919 #define BNX2_NVM_CFG4_FLASH_SIZE_4MBIT                   (2L<<0)
1920 #define BNX2_NVM_CFG4_FLASH_SIZE_8MBIT                   (3L<<0)
1921 #define BNX2_NVM_CFG4_FLASH_SIZE_16MBIT                  (4L<<0)
1922 #define BNX2_NVM_CFG4_FLASH_SIZE_32MBIT                  (5L<<0)
1923 #define BNX2_NVM_CFG4_FLASH_SIZE_64MBIT                  (6L<<0)
1924 #define BNX2_NVM_CFG4_FLASH_SIZE_128MBIT                 (7L<<0)
1925 #define BNX2_NVM_CFG4_FLASH_VENDOR                       (1L<<3)
1926 #define BNX2_NVM_CFG4_FLASH_VENDOR_ST                    (0L<<3)
1927 #define BNX2_NVM_CFG4_FLASH_VENDOR_ATMEL                 (1L<<3)
1928 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC             (0x3L<<4)
1929 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8        (0L<<4)
1930 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9        (1L<<4)
1931 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10       (2L<<4)
1932 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11       (3L<<4)
1933 #define BNX2_NVM_CFG4_STATUS_BIT_POLARITY                (1L<<6)
1934 #define BNX2_NVM_CFG4_RESERVED                           (0x1ffffffL<<7)
1935
1936 #define BNX2_NVM_RECONFIG                               0x00006430
1937 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE               (0xfL<<0)
1938 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST            (0L<<0)
1939 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL         (1L<<0)
1940 #define BNX2_NVM_RECONFIG_RECONFIG_STRAP_VALUE           (0xfL<<4)
1941 #define BNX2_NVM_RECONFIG_RESERVED                       (0x7fffffL<<8)
1942 #define BNX2_NVM_RECONFIG_RECONFIG_DONE                  (1L<<31)
1943
1944
1945
1946 /*
1947  *  dma_reg definition
1948  *  offset: 0xc00
1949  */
1950 #define BNX2_DMA_COMMAND                                0x00000c00
1951 #define BNX2_DMA_COMMAND_ENABLE                          (1L<<0)
1952
1953 #define BNX2_DMA_STATUS                                 0x00000c04
1954 #define BNX2_DMA_STATUS_PAR_ERROR_STATE                  (1L<<0)
1955 #define BNX2_DMA_STATUS_READ_TRANSFERS_STAT              (1L<<16)
1956 #define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT         (1L<<17)
1957 #define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT          (1L<<18)
1958 #define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT     (1L<<19)
1959 #define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT   (1L<<20)
1960 #define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT             (1L<<21)
1961 #define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT        (1L<<22)
1962 #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT         (1L<<23)
1963 #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT    (1L<<24)
1964 #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT  (1L<<25)
1965 #define BNX2_DMA_STATUS_GLOBAL_ERR_XI                    (1L<<0)
1966 #define BNX2_DMA_STATUS_BME_XI                           (1L<<4)
1967
1968 #define BNX2_DMA_CONFIG                                 0x00000c08
1969 #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP                   (1L<<0)
1970 #define BNX2_DMA_CONFIG_DATA_WORD_SWAP                   (1L<<1)
1971 #define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP                   (1L<<4)
1972 #define BNX2_DMA_CONFIG_CNTL_WORD_SWAP                   (1L<<5)
1973 #define BNX2_DMA_CONFIG_ONE_DMA                          (1L<<6)
1974 #define BNX2_DMA_CONFIG_CNTL_TWO_DMA                     (1L<<7)
1975 #define BNX2_DMA_CONFIG_CNTL_FPGA_MODE                   (1L<<8)
1976 #define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA               (1L<<10)
1977 #define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY                (1L<<11)
1978 #define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE                 (0xfL<<12)
1979 #define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE                 (0xfL<<16)
1980 #define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS                 (0x7L<<20)
1981 #define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP                 (1L<<23)
1982 #define BNX2_DMA_CONFIG_BIG_SIZE                         (0xfL<<24)
1983 #define BNX2_DMA_CONFIG_BIG_SIZE_NONE                    (0x0L<<24)
1984 #define BNX2_DMA_CONFIG_BIG_SIZE_64                      (0x1L<<24)
1985 #define BNX2_DMA_CONFIG_BIG_SIZE_128                     (0x2L<<24)
1986 #define BNX2_DMA_CONFIG_BIG_SIZE_256                     (0x4L<<24)
1987 #define BNX2_DMA_CONFIG_BIG_SIZE_512                     (0x8L<<24)
1988 #define BNX2_DMA_CONFIG_DAT_WBSWAP_MODE_XI               (0x3L<<0)
1989 #define BNX2_DMA_CONFIG_CTL_WBSWAP_MODE_XI               (0x3L<<4)
1990 #define BNX2_DMA_CONFIG_MAX_PL_XI                        (0x7L<<12)
1991 #define BNX2_DMA_CONFIG_MAX_PL_128B_XI                   (0L<<12)
1992 #define BNX2_DMA_CONFIG_MAX_PL_256B_XI                   (1L<<12)
1993 #define BNX2_DMA_CONFIG_MAX_PL_512B_XI                   (2L<<12)
1994 #define BNX2_DMA_CONFIG_MAX_PL_EN_XI                     (1L<<15)
1995 #define BNX2_DMA_CONFIG_MAX_RRS_XI                       (0x7L<<16)
1996 #define BNX2_DMA_CONFIG_MAX_RRS_128B_XI                  (0L<<16)
1997 #define BNX2_DMA_CONFIG_MAX_RRS_256B_XI                  (1L<<16)
1998 #define BNX2_DMA_CONFIG_MAX_RRS_512B_XI                  (2L<<16)
1999 #define BNX2_DMA_CONFIG_MAX_RRS_1024B_XI                 (3L<<16)
2000 #define BNX2_DMA_CONFIG_MAX_RRS_2048B_XI                 (4L<<16)
2001 #define BNX2_DMA_CONFIG_MAX_RRS_4096B_XI                 (5L<<16)
2002 #define BNX2_DMA_CONFIG_MAX_RRS_EN_XI                    (1L<<19)
2003 #define BNX2_DMA_CONFIG_NO_64SWAP_EN_XI                  (1L<<31)
2004
2005 #define BNX2_DMA_BLACKOUT                               0x00000c0c
2006 #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT              (0xffL<<0)
2007 #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT          (0xffL<<8)
2008 #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT              (0xffL<<16)
2009
2010 #define BNX2_DMA_READ_MASTER_SETTING_0                  0x00000c10
2011 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP     (1L<<0)
2012 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER  (1L<<1)
2013 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY     (1L<<2)
2014 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS        (0x7L<<4)
2015 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN     (1L<<7)
2016 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP     (1L<<8)
2017 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER  (1L<<9)
2018 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY     (1L<<10)
2019 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS        (0x7L<<12)
2020 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN     (1L<<15)
2021 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP     (1L<<16)
2022 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER  (1L<<17)
2023 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY     (1L<<18)
2024 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS        (0x7L<<20)
2025 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN     (1L<<23)
2026 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP      (1L<<24)
2027 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER   (1L<<25)
2028 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PRIORITY      (1L<<26)
2029 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS         (0x7L<<28)
2030 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN      (1L<<31)
2031
2032 #define BNX2_DMA_READ_MASTER_SETTING_1                  0x00000c14
2033 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP      (1L<<0)
2034 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER   (1L<<1)
2035 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PRIORITY      (1L<<2)
2036 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS         (0x7L<<4)
2037 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PARAM_EN      (1L<<7)
2038 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP       (1L<<8)
2039 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER    (1L<<9)
2040 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PRIORITY       (1L<<10)
2041 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS  (0x7L<<12)
2042 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PARAM_EN       (1L<<15)
2043
2044 #define BNX2_DMA_WRITE_MASTER_SETTING_0                 0x00000c18
2045 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP      (1L<<0)
2046 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER   (1L<<1)
2047 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY      (1L<<2)
2048 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD        (1L<<3)
2049 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS         (0x7L<<4)
2050 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN      (1L<<7)
2051 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP    (1L<<8)
2052 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER         (1L<<9)
2053 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY    (1L<<10)
2054 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD      (1L<<11)
2055 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS       (0x7L<<12)
2056 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN    (1L<<15)
2057 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP     (1L<<24)
2058 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER  (1L<<25)
2059 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY     (1L<<26)
2060 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD       (1L<<27)
2061 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS        (0x7L<<28)
2062 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN     (1L<<31)
2063
2064 #define BNX2_DMA_WRITE_MASTER_SETTING_1                 0x00000c1c
2065 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP     (1L<<0)
2066 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER  (1L<<1)
2067 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY     (1L<<2)
2068 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD       (1L<<3)
2069 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS        (0x7L<<4)
2070 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN     (1L<<7)
2071 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP      (1L<<8)
2072 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER   (1L<<9)
2073 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY      (1L<<10)
2074 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD        (1L<<11)
2075 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS         (0x7L<<12)
2076 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN      (1L<<15)
2077
2078 #define BNX2_DMA_ARBITER                                0x00000c20
2079 #define BNX2_DMA_ARBITER_NUM_READS                       (0x7L<<0)
2080 #define BNX2_DMA_ARBITER_WR_ARB_MODE                     (1L<<4)
2081 #define BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT              (0L<<4)
2082 #define BNX2_DMA_ARBITER_WR_ARB_MODE_RND_RBN             (1L<<4)
2083 #define BNX2_DMA_ARBITER_RD_ARB_MODE                     (0x3L<<5)
2084 #define BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT              (0L<<5)
2085 #define BNX2_DMA_ARBITER_RD_ARB_MODE_RND_RBN             (1L<<5)
2086 #define BNX2_DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN         (2L<<5)
2087 #define BNX2_DMA_ARBITER_ALT_MODE_EN                     (1L<<8)
2088 #define BNX2_DMA_ARBITER_RR_MODE                         (1L<<9)
2089 #define BNX2_DMA_ARBITER_TIMER_MODE                      (1L<<10)
2090 #define BNX2_DMA_ARBITER_OUSTD_READ_REQ                  (0xfL<<12)
2091
2092 #define BNX2_DMA_ARB_TIMERS                             0x00000c24
2093 #define BNX2_DMA_ARB_TIMERS_RD_DRR_WAIT_TIME             (0xffL<<0)
2094 #define BNX2_DMA_ARB_TIMERS_TM_MIN_TIMEOUT               (0xffL<<12)
2095 #define BNX2_DMA_ARB_TIMERS_TM_MAX_TIMEOUT               (0xfffL<<20)
2096
2097 #define BNX2_DMA_DEBUG_VECT_PEEK                        0x00000c2c
2098 #define BNX2_DMA_DEBUG_VECT_PEEK_1_VALUE                 (0x7ffL<<0)
2099 #define BNX2_DMA_DEBUG_VECT_PEEK_1_PEEK_EN               (1L<<11)
2100 #define BNX2_DMA_DEBUG_VECT_PEEK_1_SEL                   (0xfL<<12)
2101 #define BNX2_DMA_DEBUG_VECT_PEEK_2_VALUE                 (0x7ffL<<16)
2102 #define BNX2_DMA_DEBUG_VECT_PEEK_2_PEEK_EN               (1L<<27)
2103 #define BNX2_DMA_DEBUG_VECT_PEEK_2_SEL                   (0xfL<<28)
2104
2105 #define BNX2_DMA_TAG_RAM_00                             0x00000c30
2106 #define BNX2_DMA_TAG_RAM_00_CHANNEL                      (0xfL<<0)
2107 #define BNX2_DMA_TAG_RAM_00_MASTER                       (0x7L<<4)
2108 #define BNX2_DMA_TAG_RAM_00_MASTER_CTX                   (0L<<4)
2109 #define BNX2_DMA_TAG_RAM_00_MASTER_RBDC                  (1L<<4)
2110 #define BNX2_DMA_TAG_RAM_00_MASTER_TBDC                  (2L<<4)
2111 #define BNX2_DMA_TAG_RAM_00_MASTER_COM                   (3L<<4)
2112 #define BNX2_DMA_TAG_RAM_00_MASTER_CP                    (4L<<4)
2113 #define BNX2_DMA_TAG_RAM_00_MASTER_TDMA                  (5L<<4)
2114 #define BNX2_DMA_TAG_RAM_00_SWAP                         (0x3L<<7)
2115 #define BNX2_DMA_TAG_RAM_00_SWAP_CONFIG                  (0L<<7)
2116 #define BNX2_DMA_TAG_RAM_00_SWAP_DATA                    (1L<<7)
2117 #define BNX2_DMA_TAG_RAM_00_SWAP_CONTROL                 (2L<<7)
2118 #define BNX2_DMA_TAG_RAM_00_FUNCTION                     (1L<<9)
2119 #define BNX2_DMA_TAG_RAM_00_VALID                        (1L<<10)
2120
2121 #define BNX2_DMA_TAG_RAM_01                             0x00000c34
2122 #define BNX2_DMA_TAG_RAM_01_CHANNEL                      (0xfL<<0)
2123 #define BNX2_DMA_TAG_RAM_01_MASTER                       (0x7L<<4)
2124 #define BNX2_DMA_TAG_RAM_01_MASTER_CTX                   (0L<<4)
2125 #define BNX2_DMA_TAG_RAM_01_MASTER_RBDC                  (1L<<4)
2126 #define BNX2_DMA_TAG_RAM_01_MASTER_TBDC                  (2L<<4)
2127 #define BNX2_DMA_TAG_RAM_01_MASTER_COM                   (3L<<4)
2128 #define BNX2_DMA_TAG_RAM_01_MASTER_CP                    (4L<<4)
2129 #define BNX2_DMA_TAG_RAM_01_MASTER_TDMA                  (5L<<4)
2130 #define BNX2_DMA_TAG_RAM_01_SWAP                         (0x3L<<7)
2131 #define BNX2_DMA_TAG_RAM_01_SWAP_CONFIG                  (0L<<7)
2132 #define BNX2_DMA_TAG_RAM_01_SWAP_DATA                    (1L<<7)
2133 #define BNX2_DMA_TAG_RAM_01_SWAP_CONTROL                 (2L<<7)
2134 #define BNX2_DMA_TAG_RAM_01_FUNCTION                     (1L<<9)
2135 #define BNX2_DMA_TAG_RAM_01_VALID                        (1L<<10)
2136
2137 #define BNX2_DMA_TAG_RAM_02                             0x00000c38
2138 #define BNX2_DMA_TAG_RAM_02_CHANNEL                      (0xfL<<0)
2139 #define BNX2_DMA_TAG_RAM_02_MASTER                       (0x7L<<4)
2140 #define BNX2_DMA_TAG_RAM_02_MASTER_CTX                   (0L<<4)
2141 #define BNX2_DMA_TAG_RAM_02_MASTER_RBDC                  (1L<<4)
2142 #define BNX2_DMA_TAG_RAM_02_MASTER_TBDC                  (2L<<4)
2143 #define BNX2_DMA_TAG_RAM_02_MASTER_COM                   (3L<<4)
2144 #define BNX2_DMA_TAG_RAM_02_MASTER_CP                    (4L<<4)
2145 #define BNX2_DMA_TAG_RAM_02_MASTER_TDMA                  (5L<<4)
2146 #define BNX2_DMA_TAG_RAM_02_SWAP                         (0x3L<<7)
2147 #define BNX2_DMA_TAG_RAM_02_SWAP_CONFIG                  (0L<<7)
2148 #define BNX2_DMA_TAG_RAM_02_SWAP_DATA                    (1L<<7)
2149 #define BNX2_DMA_TAG_RAM_02_SWAP_CONTROL                 (2L<<7)
2150 #define BNX2_DMA_TAG_RAM_02_FUNCTION                     (1L<<9)
2151 #define BNX2_DMA_TAG_RAM_02_VALID                        (1L<<10)
2152
2153 #define BNX2_DMA_TAG_RAM_03                             0x00000c3c
2154 #define BNX2_DMA_TAG_RAM_03_CHANNEL                      (0xfL<<0)
2155 #define BNX2_DMA_TAG_RAM_03_MASTER                       (0x7L<<4)
2156 #define BNX2_DMA_TAG_RAM_03_MASTER_CTX                   (0L<<4)
2157 #define BNX2_DMA_TAG_RAM_03_MASTER_RBDC                  (1L<<4)
2158 #define BNX2_DMA_TAG_RAM_03_MASTER_TBDC                  (2L<<4)
2159 #define BNX2_DMA_TAG_RAM_03_MASTER_COM                   (3L<<4)
2160 #define BNX2_DMA_TAG_RAM_03_MASTER_CP                    (4L<<4)
2161 #define BNX2_DMA_TAG_RAM_03_MASTER_TDMA                  (5L<<4)
2162 #define BNX2_DMA_TAG_RAM_03_SWAP                         (0x3L<<7)
2163 #define BNX2_DMA_TAG_RAM_03_SWAP_CONFIG                  (0L<<7)
2164 #define BNX2_DMA_TAG_RAM_03_SWAP_DATA                    (1L<<7)
2165 #define BNX2_DMA_TAG_RAM_03_SWAP_CONTROL                 (2L<<7)
2166 #define BNX2_DMA_TAG_RAM_03_FUNCTION                     (1L<<9)
2167 #define BNX2_DMA_TAG_RAM_03_VALID                        (1L<<10)
2168
2169 #define BNX2_DMA_TAG_RAM_04                             0x00000c40
2170 #define BNX2_DMA_TAG_RAM_04_CHANNEL                      (0xfL<<0)
2171 #define BNX2_DMA_TAG_RAM_04_MASTER                       (0x7L<<4)
2172 #define BNX2_DMA_TAG_RAM_04_MASTER_CTX                   (0L<<4)
2173 #define BNX2_DMA_TAG_RAM_04_MASTER_RBDC                  (1L<<4)
2174 #define BNX2_DMA_TAG_RAM_04_MASTER_TBDC                  (2L<<4)
2175 #define BNX2_DMA_TAG_RAM_04_MASTER_COM                   (3L<<4)
2176 #define BNX2_DMA_TAG_RAM_04_MASTER_CP                    (4L<<4)
2177 #define BNX2_DMA_TAG_RAM_04_MASTER_TDMA                  (5L<<4)
2178 #define BNX2_DMA_TAG_RAM_04_SWAP                         (0x3L<<7)
2179 #define BNX2_DMA_TAG_RAM_04_SWAP_CONFIG                  (0L<<7)
2180 #define BNX2_DMA_TAG_RAM_04_SWAP_DATA                    (1L<<7)
2181 #define BNX2_DMA_TAG_RAM_04_SWAP_CONTROL                 (2L<<7)
2182 #define BNX2_DMA_TAG_RAM_04_FUNCTION                     (1L<<9)
2183 #define BNX2_DMA_TAG_RAM_04_VALID                        (1L<<10)
2184
2185 #define BNX2_DMA_TAG_RAM_05                             0x00000c44
2186 #define BNX2_DMA_TAG_RAM_05_CHANNEL                      (0xfL<<0)
2187 #define BNX2_DMA_TAG_RAM_05_MASTER                       (0x7L<<4)
2188 #define BNX2_DMA_TAG_RAM_05_MASTER_CTX                   (0L<<4)
2189 #define BNX2_DMA_TAG_RAM_05_MASTER_RBDC                  (1L<<4)
2190 #define BNX2_DMA_TAG_RAM_05_MASTER_TBDC                  (2L<<4)
2191 #define BNX2_DMA_TAG_RAM_05_MASTER_COM                   (3L<<4)
2192 #define BNX2_DMA_TAG_RAM_05_MASTER_CP                    (4L<<4)
2193 #define BNX2_DMA_TAG_RAM_05_MASTER_TDMA                  (5L<<4)
2194 #define BNX2_DMA_TAG_RAM_05_SWAP                         (0x3L<<7)
2195 #define BNX2_DMA_TAG_RAM_05_SWAP_CONFIG                  (0L<<7)
2196 #define BNX2_DMA_TAG_RAM_05_SWAP_DATA                    (1L<<7)
2197 #define BNX2_DMA_TAG_RAM_05_SWAP_CONTROL                 (2L<<7)
2198 #define BNX2_DMA_TAG_RAM_05_FUNCTION                     (1L<<9)
2199 #define BNX2_DMA_TAG_RAM_05_VALID                        (1L<<10)
2200
2201 #define BNX2_DMA_TAG_RAM_06                             0x00000c48
2202 #define BNX2_DMA_TAG_RAM_06_CHANNEL                      (0xfL<<0)
2203 #define BNX2_DMA_TAG_RAM_06_MASTER                       (0x7L<<4)
2204 #define BNX2_DMA_TAG_RAM_06_MASTER_CTX                   (0L<<4)
2205 #define BNX2_DMA_TAG_RAM_06_MASTER_RBDC                  (1L<<4)
2206 #define BNX2_DMA_TAG_RAM_06_MASTER_TBDC                  (2L<<4)
2207 #define BNX2_DMA_TAG_RAM_06_MASTER_COM                   (3L<<4)
2208 #define BNX2_DMA_TAG_RAM_06_MASTER_CP                    (4L<<4)
2209 #define BNX2_DMA_TAG_RAM_06_MASTER_TDMA                  (5L<<4)
2210 #define BNX2_DMA_TAG_RAM_06_SWAP                         (0x3L<<7)
2211 #define BNX2_DMA_TAG_RAM_06_SWAP_CONFIG                  (0L<<7)
2212 #define BNX2_DMA_TAG_RAM_06_SWAP_DATA                    (1L<<7)
2213 #define BNX2_DMA_TAG_RAM_06_SWAP_CONTROL                 (2L<<7)
2214 #define BNX2_DMA_TAG_RAM_06_FUNCTION                     (1L<<9)
2215 #define BNX2_DMA_TAG_RAM_06_VALID                        (1L<<10)
2216
2217 #define BNX2_DMA_TAG_RAM_07                             0x00000c4c
2218 #define BNX2_DMA_TAG_RAM_07_CHANNEL                      (0xfL<<0)
2219 #define BNX2_DMA_TAG_RAM_07_MASTER                       (0x7L<<4)
2220 #define BNX2_DMA_TAG_RAM_07_MASTER_CTX                   (0L<<4)
2221 #define BNX2_DMA_TAG_RAM_07_MASTER_RBDC                  (1L<<4)
2222 #define BNX2_DMA_TAG_RAM_07_MASTER_TBDC                  (2L<<4)
2223 #define BNX2_DMA_TAG_RAM_07_MASTER_COM                   (3L<<4)
2224 #define BNX2_DMA_TAG_RAM_07_MASTER_CP                    (4L<<4)
2225 #define BNX2_DMA_TAG_RAM_07_MASTER_TDMA                  (5L<<4)
2226 #define BNX2_DMA_TAG_RAM_07_SWAP                         (0x3L<<7)
2227 #define BNX2_DMA_TAG_RAM_07_SWAP_CONFIG                  (0L<<7)
2228 #define BNX2_DMA_TAG_RAM_07_SWAP_DATA                    (1L<<7)
2229 #define BNX2_DMA_TAG_RAM_07_SWAP_CONTROL                 (2L<<7)
2230 #define BNX2_DMA_TAG_RAM_07_FUNCTION                     (1L<<9)
2231 #define BNX2_DMA_TAG_RAM_07_VALID                        (1L<<10)
2232
2233 #define BNX2_DMA_TAG_RAM_08                             0x00000c50
2234 #define BNX2_DMA_TAG_RAM_08_CHANNEL                      (0xfL<<0)
2235 #define BNX2_DMA_TAG_RAM_08_MASTER                       (0x7L<<4)
2236 #define BNX2_DMA_TAG_RAM_08_MASTER_CTX                   (0L<<4)
2237 #define BNX2_DMA_TAG_RAM_08_MASTER_RBDC                  (1L<<4)
2238 #define BNX2_DMA_TAG_RAM_08_MASTER_TBDC                  (2L<<4)
2239 #define BNX2_DMA_TAG_RAM_08_MASTER_COM                   (3L<<4)
2240 #define BNX2_DMA_TAG_RAM_08_MASTER_CP                    (4L<<4)
2241 #define BNX2_DMA_TAG_RAM_08_MASTER_TDMA                  (5L<<4)
2242 #define BNX2_DMA_TAG_RAM_08_SWAP                         (0x3L<<7)
2243 #define BNX2_DMA_TAG_RAM_08_SWAP_CONFIG                  (0L<<7)
2244 #define BNX2_DMA_TAG_RAM_08_SWAP_DATA                    (1L<<7)
2245 #define BNX2_DMA_TAG_RAM_08_SWAP_CONTROL                 (2L<<7)
2246 #define BNX2_DMA_TAG_RAM_08_FUNCTION                     (1L<<9)
2247 #define BNX2_DMA_TAG_RAM_08_VALID                        (1L<<10)
2248
2249 #define BNX2_DMA_TAG_RAM_09                             0x00000c54
2250 #define BNX2_DMA_TAG_RAM_09_CHANNEL                      (0xfL<<0)
2251 #define BNX2_DMA_TAG_RAM_09_MASTER                       (0x7L<<4)
2252 #define BNX2_DMA_TAG_RAM_09_MASTER_CTX                   (0L<<4)
2253 #define BNX2_DMA_TAG_RAM_09_MASTER_RBDC                  (1L<<4)
2254 #define BNX2_DMA_TAG_RAM_09_MASTER_TBDC                  (2L<<4)
2255 #define BNX2_DMA_TAG_RAM_09_MASTER_COM                   (3L<<4)
2256 #define BNX2_DMA_TAG_RAM_09_MASTER_CP                    (4L<<4)
2257 #define BNX2_DMA_TAG_RAM_09_MASTER_TDMA                  (5L<<4)
2258 #define BNX2_DMA_TAG_RAM_09_SWAP                         (0x3L<<7)
2259 #define BNX2_DMA_TAG_RAM_09_SWAP_CONFIG                  (0L<<7)
2260 #define BNX2_DMA_TAG_RAM_09_SWAP_DATA                    (1L<<7)
2261 #define BNX2_DMA_TAG_RAM_09_SWAP_CONTROL                 (2L<<7)
2262 #define BNX2_DMA_TAG_RAM_09_FUNCTION                     (1L<<9)
2263 #define BNX2_DMA_TAG_RAM_09_VALID                        (1L<<10)
2264
2265 #define BNX2_DMA_TAG_RAM_10                             0x00000c58
2266 #define BNX2_DMA_TAG_RAM_10_CHANNEL                      (0xfL<<0)
2267 #define BNX2_DMA_TAG_RAM_10_MASTER                       (0x7L<<4)
2268 #define BNX2_DMA_TAG_RAM_10_MASTER_CTX                   (0L<<4)
2269 #define BNX2_DMA_TAG_RAM_10_MASTER_RBDC                  (1L<<4)
2270 #define BNX2_DMA_TAG_RAM_10_MASTER_TBDC                  (2L<<4)
2271 #define BNX2_DMA_TAG_RAM_10_MASTER_COM                   (3L<<4)
2272 #define BNX2_DMA_TAG_RAM_10_MASTER_CP                    (4L<<4)
2273 #define BNX2_DMA_TAG_RAM_10_MASTER_TDMA                  (5L<<4)
2274 #define BNX2_DMA_TAG_RAM_10_SWAP                         (0x3L<<7)
2275 #define BNX2_DMA_TAG_RAM_10_SWAP_CONFIG                  (0L<<7)
2276 #define BNX2_DMA_TAG_RAM_10_SWAP_DATA                    (1L<<7)
2277 #define BNX2_DMA_TAG_RAM_10_SWAP_CONTROL                 (2L<<7)
2278 #define BNX2_DMA_TAG_RAM_10_FUNCTION                     (1L<<9)
2279 #define BNX2_DMA_TAG_RAM_10_VALID                        (1L<<10)
2280
2281 #define BNX2_DMA_TAG_RAM_11                             0x00000c5c
2282 #define BNX2_DMA_TAG_RAM_11_CHANNEL                      (0xfL<<0)
2283 #define BNX2_DMA_TAG_RAM_11_MASTER                       (0x7L<<4)
2284 #define BNX2_DMA_TAG_RAM_11_MASTER_CTX                   (0L<<4)
2285 #define BNX2_DMA_TAG_RAM_11_MASTER_RBDC                  (1L<<4)
2286 #define BNX2_DMA_TAG_RAM_11_MASTER_TBDC                  (2L<<4)
2287 #define BNX2_DMA_TAG_RAM_11_MASTER_COM                   (3L<<4)
2288 #define BNX2_DMA_TAG_RAM_11_MASTER_CP                    (4L<<4)
2289 #define BNX2_DMA_TAG_RAM_11_MASTER_TDMA                  (5L<<4)
2290 #define BNX2_DMA_TAG_RAM_11_SWAP                         (0x3L<<7)
2291 #define BNX2_DMA_TAG_RAM_11_SWAP_CONFIG                  (0L<<7)
2292 #define BNX2_DMA_TAG_RAM_11_SWAP_DATA                    (1L<<7)
2293 #define BNX2_DMA_TAG_RAM_11_SWAP_CONTROL                 (2L<<7)
2294 #define BNX2_DMA_TAG_RAM_11_FUNCTION                     (1L<<9)
2295 #define BNX2_DMA_TAG_RAM_11_VALID                        (1L<<10)
2296
2297 #define BNX2_DMA_RCHAN_STAT_22                          0x00000c60
2298 #define BNX2_DMA_RCHAN_STAT_30                          0x00000c64
2299 #define BNX2_DMA_RCHAN_STAT_31                          0x00000c68
2300 #define BNX2_DMA_RCHAN_STAT_32                          0x00000c6c
2301 #define BNX2_DMA_RCHAN_STAT_40                          0x00000c70
2302 #define BNX2_DMA_RCHAN_STAT_41                          0x00000c74
2303 #define BNX2_DMA_RCHAN_STAT_42                          0x00000c78
2304 #define BNX2_DMA_RCHAN_STAT_50                          0x00000c7c
2305 #define BNX2_DMA_RCHAN_STAT_51                          0x00000c80
2306 #define BNX2_DMA_RCHAN_STAT_52                          0x00000c84
2307 #define BNX2_DMA_RCHAN_STAT_60                          0x00000c88
2308 #define BNX2_DMA_RCHAN_STAT_61                          0x00000c8c
2309 #define BNX2_DMA_RCHAN_STAT_62                          0x00000c90
2310 #define BNX2_DMA_RCHAN_STAT_70                          0x00000c94
2311 #define BNX2_DMA_RCHAN_STAT_71                          0x00000c98
2312 #define BNX2_DMA_RCHAN_STAT_72                          0x00000c9c
2313 #define BNX2_DMA_WCHAN_STAT_00                          0x00000ca0
2314 #define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW   (0xffffffffL<<0)
2315
2316 #define BNX2_DMA_WCHAN_STAT_01                          0x00000ca4
2317 #define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH  (0xffffffffL<<0)
2318
2319 #define BNX2_DMA_WCHAN_STAT_02                          0x00000ca8
2320 #define BNX2_DMA_WCHAN_STAT_02_LENGTH                    (0xffffL<<0)
2321 #define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP                 (1L<<16)
2322 #define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP                 (1L<<17)
2323 #define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL              (1L<<18)
2324
2325 #define BNX2_DMA_WCHAN_STAT_10                          0x00000cac
2326 #define BNX2_DMA_WCHAN_STAT_11                          0x00000cb0
2327 #define BNX2_DMA_WCHAN_STAT_12                          0x00000cb4
2328 #define BNX2_DMA_WCHAN_STAT_20                          0x00000cb8
2329 #define BNX2_DMA_WCHAN_STAT_21                          0x00000cbc
2330 #define BNX2_DMA_WCHAN_STAT_22                          0x00000cc0
2331 #define BNX2_DMA_WCHAN_STAT_30                          0x00000cc4
2332 #define BNX2_DMA_WCHAN_STAT_31                          0x00000cc8
2333 #define BNX2_DMA_WCHAN_STAT_32                          0x00000ccc
2334 #define BNX2_DMA_WCHAN_STAT_40                          0x00000cd0
2335 #define BNX2_DMA_WCHAN_STAT_41                          0x00000cd4
2336 #define BNX2_DMA_WCHAN_STAT_42                          0x00000cd8
2337 #define BNX2_DMA_WCHAN_STAT_50                          0x00000cdc
2338 #define BNX2_DMA_WCHAN_STAT_51                          0x00000ce0
2339 #define BNX2_DMA_WCHAN_STAT_52                          0x00000ce4
2340 #define BNX2_DMA_WCHAN_STAT_60                          0x00000ce8
2341 #define BNX2_DMA_WCHAN_STAT_61                          0x00000cec
2342 #define BNX2_DMA_WCHAN_STAT_62                          0x00000cf0
2343 #define BNX2_DMA_WCHAN_STAT_70                          0x00000cf4
2344 #define BNX2_DMA_WCHAN_STAT_71                          0x00000cf8
2345 #define BNX2_DMA_WCHAN_STAT_72                          0x00000cfc
2346 #define BNX2_DMA_ARB_STAT_00                            0x00000d00
2347 #define BNX2_DMA_ARB_STAT_00_MASTER                      (0xffffL<<0)
2348 #define BNX2_DMA_ARB_STAT_00_MASTER_ENC                  (0xffL<<16)
2349 #define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR                 (0xffL<<24)
2350
2351 #define BNX2_DMA_ARB_STAT_01                            0x00000d04
2352 #define BNX2_DMA_ARB_STAT_01_LPR_RPTR                    (0xfL<<0)
2353 #define BNX2_DMA_ARB_STAT_01_LPR_WPTR                    (0xfL<<4)
2354 #define BNX2_DMA_ARB_STAT_01_LPB_RPTR                    (0xfL<<8)
2355 #define BNX2_DMA_ARB_STAT_01_LPB_WPTR                    (0xfL<<12)
2356 #define BNX2_DMA_ARB_STAT_01_HPR_RPTR                    (0xfL<<16)
2357 #define BNX2_DMA_ARB_STAT_01_HPR_WPTR                    (0xfL<<20)
2358 #define BNX2_DMA_ARB_STAT_01_HPB_RPTR                    (0xfL<<24)
2359 #define BNX2_DMA_ARB_STAT_01_HPB_WPTR                    (0xfL<<28)
2360
2361 #define BNX2_DMA_FUSE_CTRL0_CMD                         0x00000f00
2362 #define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE               (1L<<0)
2363 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE               (1L<<1)
2364 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT                    (1L<<2)
2365 #define BNX2_DMA_FUSE_CTRL0_CMD_LOAD                     (1L<<3)
2366 #define BNX2_DMA_FUSE_CTRL0_CMD_SEL                      (0xfL<<8)
2367
2368 #define BNX2_DMA_FUSE_CTRL0_DATA                        0x00000f04
2369 #define BNX2_DMA_FUSE_CTRL1_CMD                         0x00000f08
2370 #define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE               (1L<<0)
2371 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE               (1L<<1)
2372 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT                    (1L<<2)
2373 #define BNX2_DMA_FUSE_CTRL1_CMD_LOAD                     (1L<<3)
2374 #define BNX2_DMA_FUSE_CTRL1_CMD_SEL                      (0xfL<<8)
2375
2376 #define BNX2_DMA_FUSE_CTRL1_DATA                        0x00000f0c
2377 #define BNX2_DMA_FUSE_CTRL2_CMD                         0x00000f10
2378 #define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE               (1L<<0)
2379 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE               (1L<<1)
2380 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT                    (1L<<2)
2381 #define BNX2_DMA_FUSE_CTRL2_CMD_LOAD                     (1L<<3)
2382 #define BNX2_DMA_FUSE_CTRL2_CMD_SEL                      (0xfL<<8)
2383
2384 #define BNX2_DMA_FUSE_CTRL2_DATA                        0x00000f14
2385
2386
2387 /*
2388  *  context_reg definition
2389  *  offset: 0x1000
2390  */
2391 #define BNX2_CTX_COMMAND                                0x00001000
2392 #define BNX2_CTX_COMMAND_ENABLED                         (1L<<0)
2393 #define BNX2_CTX_COMMAND_DISABLE_USAGE_CNT               (1L<<1)
2394 #define BNX2_CTX_COMMAND_DISABLE_PLRU                    (1L<<2)
2395 #define BNX2_CTX_COMMAND_DISABLE_COMBINE_READ            (1L<<3)
2396 #define BNX2_CTX_COMMAND_FLUSH_AHEAD                     (0x1fL<<8)
2397 #define BNX2_CTX_COMMAND_MEM_INIT                        (1L<<13)
2398 #define BNX2_CTX_COMMAND_PAGE_SIZE                       (0xfL<<16)
2399 #define BNX2_CTX_COMMAND_PAGE_SIZE_256                   (0L<<16)
2400 #define BNX2_CTX_COMMAND_PAGE_SIZE_512                   (1L<<16)
2401 #define BNX2_CTX_COMMAND_PAGE_SIZE_1K                    (2L<<16)
2402 #define BNX2_CTX_COMMAND_PAGE_SIZE_2K                    (3L<<16)
2403 #define BNX2_CTX_COMMAND_PAGE_SIZE_4K                    (4L<<16)
2404 #define BNX2_CTX_COMMAND_PAGE_SIZE_8K                    (5L<<16)
2405 #define BNX2_CTX_COMMAND_PAGE_SIZE_16K                   (6L<<16)
2406 #define BNX2_CTX_COMMAND_PAGE_SIZE_32K                   (7L<<16)
2407 #define BNX2_CTX_COMMAND_PAGE_SIZE_64K                   (8L<<16)
2408 #define BNX2_CTX_COMMAND_PAGE_SIZE_128K                  (9L<<16)
2409 #define BNX2_CTX_COMMAND_PAGE_SIZE_256K                  (10L<<16)
2410 #define BNX2_CTX_COMMAND_PAGE_SIZE_512K                  (11L<<16)
2411 #define BNX2_CTX_COMMAND_PAGE_SIZE_1M                    (12L<<16)
2412
2413 #define BNX2_CTX_STATUS                                 0x00001004
2414 #define BNX2_CTX_STATUS_LOCK_WAIT                        (1L<<0)
2415 #define BNX2_CTX_STATUS_READ_STAT                        (1L<<16)
2416 #define BNX2_CTX_STATUS_WRITE_STAT                       (1L<<17)
2417 #define BNX2_CTX_STATUS_ACC_STALL_STAT                   (1L<<18)
2418 #define BNX2_CTX_STATUS_LOCK_STALL_STAT                  (1L<<19)
2419 #define BNX2_CTX_STATUS_EXT_READ_STAT                    (1L<<20)
2420 #define BNX2_CTX_STATUS_EXT_WRITE_STAT                   (1L<<21)
2421 #define BNX2_CTX_STATUS_MISS_STAT                        (1L<<22)
2422 #define BNX2_CTX_STATUS_HIT_STAT                         (1L<<23)
2423 #define BNX2_CTX_STATUS_DEAD_LOCK                        (1L<<24)
2424 #define BNX2_CTX_STATUS_USAGE_CNT_ERR                    (1L<<25)
2425 #define BNX2_CTX_STATUS_INVALID_PAGE                     (1L<<26)
2426
2427 #define BNX2_CTX_VIRT_ADDR                              0x00001008
2428 #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR                     (0x7fffL<<6)
2429
2430 #define BNX2_CTX_PAGE_TBL                               0x0000100c
2431 #define BNX2_CTX_PAGE_TBL_PAGE_TBL                       (0x3fffL<<6)
2432
2433 #define BNX2_CTX_DATA_ADR                               0x00001010
2434 #define BNX2_CTX_DATA_ADR_DATA_ADR                       (0x7ffffL<<2)
2435
2436 #define BNX2_CTX_DATA                                   0x00001014
2437 #define BNX2_CTX_LOCK                                   0x00001018
2438 #define BNX2_CTX_LOCK_TYPE                               (0x7L<<0)
2439 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID                (0x0L<<0)
2440 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL            (0x1L<<0)
2441 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX                  (0x2L<<0)
2442 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER               (0x4L<<0)
2443 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE            (0x7L<<0)
2444 #define BNX2_CTX_LOCK_TYPE_VOID_XI                       (0L<<0)
2445 #define BNX2_CTX_LOCK_TYPE_PROTOCOL_XI                   (1L<<0)
2446 #define BNX2_CTX_LOCK_TYPE_TX_XI                         (2L<<0)
2447 #define BNX2_CTX_LOCK_TYPE_TIMER_XI                      (4L<<0)
2448 #define BNX2_CTX_LOCK_TYPE_COMPLETE_XI                   (7L<<0)
2449 #define BNX2_CTX_LOCK_CID_VALUE                          (0x3fffL<<7)
2450 #define BNX2_CTX_LOCK_GRANTED                            (1L<<26)
2451 #define BNX2_CTX_LOCK_MODE                               (0x7L<<27)
2452 #define BNX2_CTX_LOCK_MODE_UNLOCK                        (0x0L<<27)
2453 #define BNX2_CTX_LOCK_MODE_IMMEDIATE                     (0x1L<<27)
2454 #define BNX2_CTX_LOCK_MODE_SURE                          (0x2L<<27)
2455 #define BNX2_CTX_LOCK_STATUS                             (1L<<30)
2456 #define BNX2_CTX_LOCK_REQ                                (1L<<31)
2457
2458 #define BNX2_CTX_CTX_CTRL                               0x0000101c
2459 #define BNX2_CTX_CTX_CTRL_CTX_ADDR                       (0x7ffffL<<2)
2460 #define BNX2_CTX_CTX_CTRL_MOD_USAGE_CNT                  (0x3L<<21)
2461 #define BNX2_CTX_CTX_CTRL_NO_RAM_ACC                     (1L<<23)
2462 #define BNX2_CTX_CTX_CTRL_PREFETCH_SIZE                  (0x3L<<24)
2463 #define BNX2_CTX_CTX_CTRL_ATTR                           (1L<<26)
2464 #define BNX2_CTX_CTX_CTRL_WRITE_REQ                      (1L<<30)
2465 #define BNX2_CTX_CTX_CTRL_READ_REQ                       (1L<<31)
2466
2467 #define BNX2_CTX_CTX_DATA                               0x00001020
2468 #define BNX2_CTX_ACCESS_STATUS                          0x00001040
2469 #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED             (0xfL<<0)
2470 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM            (0x3L<<10)
2471 #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM           (0x3L<<12)
2472 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM        (0x3L<<14)
2473 #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST         (0x7ffL<<17)
2474 #define BNX2_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI       (0x1fL<<0)
2475 #define BNX2_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI     (0x1fL<<5)
2476 #define BNX2_CTX_ACCESS_STATUS_REQUEST_XI                (0x3fffffL<<10)
2477
2478 #define BNX2_CTX_DBG_LOCK_STATUS                        0x00001044
2479 #define BNX2_CTX_DBG_LOCK_STATUS_SM                      (0x3ffL<<0)
2480 #define BNX2_CTX_DBG_LOCK_STATUS_MATCH                   (0x3ffL<<22)
2481
2482 #define BNX2_CTX_CACHE_CTRL_STATUS                      0x00001048
2483 #define BNX2_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW        (1L<<0)
2484 #define BNX2_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP     (1L<<1)
2485 #define BNX2_CTX_CACHE_CTRL_STATUS_FLUSH_START           (1L<<6)
2486 #define BNX2_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT        (0x3fL<<7)
2487 #define BNX2_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED    (0x3fL<<13)
2488 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE       (1L<<19)
2489 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE       (1L<<20)
2490 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE       (1L<<21)
2491 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE       (1L<<22)
2492 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE       (1L<<23)
2493 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE       (1L<<24)
2494 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE       (1L<<25)
2495 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE       (1L<<26)
2496 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE       (1L<<27)
2497 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE       (1L<<28)
2498 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE      (1L<<29)
2499
2500 #define BNX2_CTX_CACHE_CTRL_SM_STATUS                   0x0000104c
2501 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_DWC             (0x7L<<0)
2502 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC          (0x7L<<3)
2503 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC           (0x7L<<6)
2504 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC          (0x7L<<9)
2505 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR   (0x7fffL<<16)
2506
2507 #define BNX2_CTX_CACHE_STATUS                           0x00001050
2508 #define BNX2_CTX_CACHE_STATUS_HELD_ENTRIES               (0x3ffL<<0)
2509 #define BNX2_CTX_CACHE_STATUS_MAX_HELD_ENTRIES           (0x3ffL<<16)
2510
2511 #define BNX2_CTX_DMA_STATUS                             0x00001054
2512 #define BNX2_CTX_DMA_STATUS_RD_CHAN0_STATUS              (0x3L<<0)
2513 #define BNX2_CTX_DMA_STATUS_RD_CHAN1_STATUS              (0x3L<<2)
2514 #define BNX2_CTX_DMA_STATUS_RD_CHAN2_STATUS              (0x3L<<4)
2515 #define BNX2_CTX_DMA_STATUS_RD_CHAN3_STATUS              (0x3L<<6)
2516 #define BNX2_CTX_DMA_STATUS_RD_CHAN4_STATUS              (0x3L<<8)
2517 #define BNX2_CTX_DMA_STATUS_RD_CHAN5_STATUS              (0x3L<<10)
2518 #define BNX2_CTX_DMA_STATUS_RD_CHAN6_STATUS              (0x3L<<12)
2519 #define BNX2_CTX_DMA_STATUS_RD_CHAN7_STATUS              (0x3L<<14)
2520 #define BNX2_CTX_DMA_STATUS_RD_CHAN8_STATUS              (0x3L<<16)
2521 #define BNX2_CTX_DMA_STATUS_RD_CHAN9_STATUS              (0x3L<<18)
2522 #define BNX2_CTX_DMA_STATUS_RD_CHAN10_STATUS             (0x3L<<20)
2523
2524 #define BNX2_CTX_REP_STATUS                             0x00001058
2525 #define BNX2_CTX_REP_STATUS_ERROR_ENTRY                  (0x3ffL<<0)
2526 #define BNX2_CTX_REP_STATUS_ERROR_CLIENT_ID              (0x1fL<<10)
2527 #define BNX2_CTX_REP_STATUS_USAGE_CNT_MAX_ERR            (1L<<16)
2528 #define BNX2_CTX_REP_STATUS_USAGE_CNT_MIN_ERR            (1L<<17)
2529 #define BNX2_CTX_REP_STATUS_USAGE_CNT_MISS_ERR           (1L<<18)
2530
2531 #define BNX2_CTX_CKSUM_ERROR_STATUS                     0x0000105c
2532 #define BNX2_CTX_CKSUM_ERROR_STATUS_CALCULATED           (0xffffL<<0)
2533 #define BNX2_CTX_CKSUM_ERROR_STATUS_EXPECTED             (0xffffL<<16)
2534
2535 #define BNX2_CTX_CHNL_LOCK_STATUS_0                     0x00001080
2536 #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID                  (0x3fffL<<0)
2537 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE                 (0x3L<<14)
2538 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE                 (1L<<16)
2539 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE_XI              (1L<<14)
2540 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE_XI              (0x7L<<15)
2541
2542 #define BNX2_CTX_CHNL_LOCK_STATUS_1                     0x00001084
2543 #define BNX2_CTX_CHNL_LOCK_STATUS_2                     0x00001088
2544 #define BNX2_CTX_CHNL_LOCK_STATUS_3                     0x0000108c
2545 #define BNX2_CTX_CHNL_LOCK_STATUS_4                     0x00001090
2546 #define BNX2_CTX_CHNL_LOCK_STATUS_5                     0x00001094
2547 #define BNX2_CTX_CHNL_LOCK_STATUS_6                     0x00001098
2548 #define BNX2_CTX_CHNL_LOCK_STATUS_7                     0x0000109c
2549 #define BNX2_CTX_CHNL_LOCK_STATUS_8                     0x000010a0
2550 #define BNX2_CTX_CHNL_LOCK_STATUS_9                     0x000010a4
2551
2552 #define BNX2_CTX_CACHE_DATA                             0x000010c4
2553 #define BNX2_CTX_HOST_PAGE_TBL_CTRL                     0x000010c8
2554 #define BNX2_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR        (0x1ffL<<0)
2555 #define BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ            (1L<<30)
2556 #define BNX2_CTX_HOST_PAGE_TBL_CTRL_READ_REQ             (1L<<31)
2557
2558 #define BNX2_CTX_HOST_PAGE_TBL_DATA0                    0x000010cc
2559 #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID               (1L<<0)
2560 #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALUE               (0xffffffL<<8)
2561
2562 #define BNX2_CTX_HOST_PAGE_TBL_DATA1                    0x000010d0
2563 #define BNX2_CTX_CAM_CTRL                               0x000010d4
2564 #define BNX2_CTX_CAM_CTRL_CAM_ADDR                       (0x3ffL<<0)
2565 #define BNX2_CTX_CAM_CTRL_RESET                          (1L<<27)
2566 #define BNX2_CTX_CAM_CTRL_INVALIDATE                     (1L<<28)
2567 #define BNX2_CTX_CAM_CTRL_SEARCH                         (1L<<29)
2568 #define BNX2_CTX_CAM_CTRL_WRITE_REQ                      (1L<<30)
2569 #define BNX2_CTX_CAM_CTRL_READ_REQ                       (1L<<31)
2570
2571
2572 /*
2573  *  emac_reg definition
2574  *  offset: 0x1400
2575  */
2576 #define BNX2_EMAC_MODE                                  0x00001400
2577 #define BNX2_EMAC_MODE_RESET                             (1L<<0)
2578 #define BNX2_EMAC_MODE_HALF_DUPLEX                       (1L<<1)
2579 #define BNX2_EMAC_MODE_PORT                              (0x3L<<2)
2580 #define BNX2_EMAC_MODE_PORT_NONE                         (0L<<2)
2581 #define BNX2_EMAC_MODE_PORT_MII                          (1L<<2)
2582 #define BNX2_EMAC_MODE_PORT_GMII                         (2L<<2)
2583 #define BNX2_EMAC_MODE_PORT_MII_10M                      (3L<<2)
2584 #define BNX2_EMAC_MODE_MAC_LOOP                          (1L<<4)
2585 #define BNX2_EMAC_MODE_25G_MODE                          (1L<<5)
2586 #define BNX2_EMAC_MODE_TAGGED_MAC_CTL                    (1L<<7)
2587 #define BNX2_EMAC_MODE_TX_BURST                          (1L<<8)
2588 #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA                (1L<<9)
2589 #define BNX2_EMAC_MODE_EXT_LINK_POL                      (1L<<10)
2590 #define BNX2_EMAC_MODE_FORCE_LINK                        (1L<<11)
2591 #define BNX2_EMAC_MODE_SERDES_MODE                       (1L<<12)
2592 #define BNX2_EMAC_MODE_BOND_OVRD                         (1L<<13)
2593 #define BNX2_EMAC_MODE_MPKT                              (1L<<18)
2594 #define BNX2_EMAC_MODE_MPKT_RCVD                         (1L<<19)
2595 #define BNX2_EMAC_MODE_ACPI_RCVD                         (1L<<20)
2596
2597 #define BNX2_EMAC_STATUS                                0x00001404
2598 #define BNX2_EMAC_STATUS_LINK                            (1L<<11)
2599 #define BNX2_EMAC_STATUS_LINK_CHANGE                     (1L<<12)
2600 #define BNX2_EMAC_STATUS_SERDES_AUTONEG_COMPLETE         (1L<<13)
2601 #define BNX2_EMAC_STATUS_SERDES_AUTONEG_CHANGE           (1L<<14)
2602 #define BNX2_EMAC_STATUS_SERDES_NXT_PG_CHANGE            (1L<<16)
2603 #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0           (1L<<17)
2604 #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE    (1L<<18)
2605 #define BNX2_EMAC_STATUS_MI_COMPLETE                     (1L<<22)
2606 #define BNX2_EMAC_STATUS_MI_INT                          (1L<<23)
2607 #define BNX2_EMAC_STATUS_AP_ERROR                        (1L<<24)
2608 #define BNX2_EMAC_STATUS_PARITY_ERROR_STATE              (1L<<31)
2609
2610 #define BNX2_EMAC_ATTENTION_ENA                         0x00001408
2611 #define BNX2_EMAC_ATTENTION_ENA_LINK                     (1L<<11)
2612 #define BNX2_EMAC_ATTENTION_ENA_AUTONEG_CHANGE           (1L<<14)
2613 #define BNX2_EMAC_ATTENTION_ENA_NXT_PG_CHANGE            (1L<<16)
2614 #define BNX2_EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE     (1L<<18)
2615 #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE              (1L<<22)
2616 #define BNX2_EMAC_ATTENTION_ENA_MI_INT                   (1L<<23)
2617 #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR                 (1L<<24)
2618
2619 #define BNX2_EMAC_LED                                   0x0000140c
2620 #define BNX2_EMAC_LED_OVERRIDE                           (1L<<0)
2621 #define BNX2_EMAC_LED_1000MB_OVERRIDE                    (1L<<1)
2622 #define BNX2_EMAC_LED_100MB_OVERRIDE                     (1L<<2)
2623 #define BNX2_EMAC_LED_10MB_OVERRIDE                      (1L<<3)
2624 #define BNX2_EMAC_LED_TRAFFIC_OVERRIDE                   (1L<<4)
2625 #define BNX2_EMAC_LED_BLNK_TRAFFIC                       (1L<<5)
2626 #define BNX2_EMAC_LED_TRAFFIC                            (1L<<6)
2627 #define BNX2_EMAC_LED_1000MB                             (1L<<7)
2628 #define BNX2_EMAC_LED_100MB                              (1L<<8)
2629 #define BNX2_EMAC_LED_10MB                               (1L<<9)
2630 #define BNX2_EMAC_LED_TRAFFIC_STAT                       (1L<<10)
2631 #define BNX2_EMAC_LED_2500MB                             (1L<<11)
2632 #define BNX2_EMAC_LED_2500MB_OVERRIDE                    (1L<<12)
2633 #define BNX2_EMAC_LED_ACTIVITY_SEL                       (0x3L<<17)
2634 #define BNX2_EMAC_LED_ACTIVITY_SEL_0                     (0L<<17)
2635 #define BNX2_EMAC_LED_ACTIVITY_SEL_1                     (1L<<17)
2636 #define BNX2_EMAC_LED_ACTIVITY_SEL_2                     (2L<<17)
2637 #define BNX2_EMAC_LED_ACTIVITY_SEL_3                     (3L<<17)
2638 #define BNX2_EMAC_LED_BLNK_RATE                          (0xfffL<<19)
2639 #define BNX2_EMAC_LED_BLNK_RATE_ENA                      (1L<<31)
2640
2641 #define BNX2_EMAC_MAC_MATCH0                            0x00001410
2642 #define BNX2_EMAC_MAC_MATCH1                            0x00001414
2643 #define BNX2_EMAC_MAC_MATCH2                            0x00001418
2644 #define BNX2_EMAC_MAC_MATCH3                            0x0000141c
2645 #define BNX2_EMAC_MAC_MATCH4                            0x00001420
2646 #define BNX2_EMAC_MAC_MATCH5                            0x00001424
2647 #define BNX2_EMAC_MAC_MATCH6                            0x00001428
2648 #define BNX2_EMAC_MAC_MATCH7                            0x0000142c
2649 #define BNX2_EMAC_MAC_MATCH8                            0x00001430
2650 #define BNX2_EMAC_MAC_MATCH9                            0x00001434
2651 #define BNX2_EMAC_MAC_MATCH10                           0x00001438
2652 #define BNX2_EMAC_MAC_MATCH11                           0x0000143c
2653 #define BNX2_EMAC_MAC_MATCH12                           0x00001440
2654 #define BNX2_EMAC_MAC_MATCH13                           0x00001444
2655 #define BNX2_EMAC_MAC_MATCH14                           0x00001448
2656 #define BNX2_EMAC_MAC_MATCH15                           0x0000144c
2657 #define BNX2_EMAC_MAC_MATCH16                           0x00001450
2658 #define BNX2_EMAC_MAC_MATCH17                           0x00001454
2659 #define BNX2_EMAC_MAC_MATCH18                           0x00001458
2660 #define BNX2_EMAC_MAC_MATCH19                           0x0000145c
2661 #define BNX2_EMAC_MAC_MATCH20                           0x00001460
2662 #define BNX2_EMAC_MAC_MATCH21                           0x00001464
2663 #define BNX2_EMAC_MAC_MATCH22                           0x00001468
2664 #define BNX2_EMAC_MAC_MATCH23                           0x0000146c
2665 #define BNX2_EMAC_MAC_MATCH24                           0x00001470
2666 #define BNX2_EMAC_MAC_MATCH25                           0x00001474
2667 #define BNX2_EMAC_MAC_MATCH26                           0x00001478
2668 #define BNX2_EMAC_MAC_MATCH27                           0x0000147c
2669 #define BNX2_EMAC_MAC_MATCH28                           0x00001480
2670 #define BNX2_EMAC_MAC_MATCH29                           0x00001484
2671 #define BNX2_EMAC_MAC_MATCH30                           0x00001488
2672 #define BNX2_EMAC_MAC_MATCH31                           0x0000148c
2673 #define BNX2_EMAC_BACKOFF_SEED                          0x00001498
2674 #define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED         (0x3ffL<<0)
2675
2676 #define BNX2_EMAC_RX_MTU_SIZE                           0x0000149c
2677 #define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE                   (0xffffL<<0)
2678 #define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA                  (1L<<31)
2679
2680 #define BNX2_EMAC_SERDES_CNTL                           0x000014a4
2681 #define BNX2_EMAC_SERDES_CNTL_RXR                        (0x7L<<0)
2682 #define BNX2_EMAC_SERDES_CNTL_RXG                        (0x3L<<3)
2683 #define BNX2_EMAC_SERDES_CNTL_RXCKSEL                    (1L<<6)
2684 #define BNX2_EMAC_SERDES_CNTL_TXBIAS                     (0x7L<<7)
2685 #define BNX2_EMAC_SERDES_CNTL_BGMAX                      (1L<<10)
2686 #define BNX2_EMAC_SERDES_CNTL_BGMIN                      (1L<<11)
2687 #define BNX2_EMAC_SERDES_CNTL_TXMODE                     (1L<<12)
2688 #define BNX2_EMAC_SERDES_CNTL_TXEDGE                     (1L<<13)
2689 #define BNX2_EMAC_SERDES_CNTL_SERDES_MODE                (1L<<14)
2690 #define BNX2_EMAC_SERDES_CNTL_PLLTEST                    (1L<<15)
2691 #define BNX2_EMAC_SERDES_CNTL_CDET_EN                    (1L<<16)
2692 #define BNX2_EMAC_SERDES_CNTL_TBI_LBK                    (1L<<17)
2693 #define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK                 (1L<<18)
2694 #define BNX2_EMAC_SERDES_CNTL_REV_PHASE                  (1L<<19)
2695 #define BNX2_EMAC_SERDES_CNTL_REGCTL12                   (0x3L<<20)
2696 #define BNX2_EMAC_SERDES_CNTL_REGCTL25                   (0x3L<<22)
2697
2698 #define BNX2_EMAC_SERDES_STATUS                         0x000014a8
2699 #define BNX2_EMAC_SERDES_STATUS_RX_STAT                  (0xffL<<0)
2700 #define BNX2_EMAC_SERDES_STATUS_COMMA_DET                (1L<<8)
2701
2702 #define BNX2_EMAC_MDIO_COMM                             0x000014ac
2703 #define BNX2_EMAC_MDIO_COMM_DATA                         (0xffffL<<0)
2704 #define BNX2_EMAC_MDIO_COMM_REG_ADDR                     (0x1fL<<16)
2705 #define BNX2_EMAC_MDIO_COMM_PHY_ADDR                     (0x1fL<<21)
2706 #define BNX2_EMAC_MDIO_COMM_COMMAND                      (0x3L<<26)
2707 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0          (0L<<26)
2708 #define BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS              (0L<<26)
2709 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE                (1L<<26)
2710 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ                 (2L<<26)
2711 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_22_XI          (1L<<26)
2712 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_45_XI          (1L<<26)
2713 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_22_XI           (2L<<26)
2714 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI       (2L<<26)
2715 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3          (3L<<26)
2716 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_45              (3L<<26)
2717 #define BNX2_EMAC_MDIO_COMM_FAIL                         (1L<<28)
2718 #define BNX2_EMAC_MDIO_COMM_START_BUSY                   (1L<<29)
2719 #define BNX2_EMAC_MDIO_COMM_DISEXT                       (1L<<30)
2720
2721 #define BNX2_EMAC_MDIO_STATUS                           0x000014b0
2722 #define BNX2_EMAC_MDIO_STATUS_LINK                       (1L<<0)
2723 #define BNX2_EMAC_MDIO_STATUS_10MB                       (1L<<1)
2724
2725 #define BNX2_EMAC_MDIO_MODE                             0x000014b4
2726 #define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE               (1L<<1)
2727 #define BNX2_EMAC_MDIO_MODE_AUTO_POLL                    (1L<<4)
2728 #define BNX2_EMAC_MDIO_MODE_BIT_BANG                     (1L<<8)
2729 #define BNX2_EMAC_MDIO_MODE_MDIO                         (1L<<9)
2730 #define BNX2_EMAC_MDIO_MODE_MDIO_OE                      (1L<<10)
2731 #define BNX2_EMAC_MDIO_MODE_MDC                          (1L<<11)
2732 #define BNX2_EMAC_MDIO_MODE_MDINT                        (1L<<12)
2733 #define BNX2_EMAC_MDIO_MODE_EXT_MDINT                    (1L<<13)
2734 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT                    (0x1fL<<16)
2735 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT_XI                 (0x3fL<<16)
2736 #define BNX2_EMAC_MDIO_MODE_CLAUSE_45_XI                 (1L<<31)
2737
2738 #define BNX2_EMAC_MDIO_AUTO_STATUS                      0x000014b8
2739 #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR              (1L<<0)
2740
2741 #define BNX2_EMAC_TX_MODE                               0x000014bc
2742 #define BNX2_EMAC_TX_MODE_RESET                          (1L<<0)
2743 #define BNX2_EMAC_TX_MODE_CS16_TEST                      (1L<<2)
2744 #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN                   (1L<<3)
2745 #define BNX2_EMAC_TX_MODE_FLOW_EN                        (1L<<4)
2746 #define BNX2_EMAC_TX_MODE_BIG_BACKOFF                    (1L<<5)
2747 #define BNX2_EMAC_TX_MODE_LONG_PAUSE                     (1L<<6)
2748 #define BNX2_EMAC_TX_MODE_LINK_AWARE                     (1L<<7)
2749
2750 #define BNX2_EMAC_TX_STATUS                             0x000014c0
2751 #define BNX2_EMAC_TX_STATUS_XOFFED                       (1L<<0)
2752 #define BNX2_EMAC_TX_STATUS_XOFF_SENT                    (1L<<1)
2753 #define BNX2_EMAC_TX_STATUS_XON_SENT                     (1L<<2)
2754 #define BNX2_EMAC_TX_STATUS_LINK_UP                      (1L<<3)
2755 #define BNX2_EMAC_TX_STATUS_UNDERRUN                     (1L<<4)
2756 #define BNX2_EMAC_TX_STATUS_CS16_ERROR                   (1L<<5)
2757
2758 #define BNX2_EMAC_TX_LENGTHS                            0x000014c4
2759 #define BNX2_EMAC_TX_LENGTHS_SLOT                        (0xffL<<0)
2760 #define BNX2_EMAC_TX_LENGTHS_IPG                         (0xfL<<8)
2761 #define BNX2_EMAC_TX_LENGTHS_IPG_CRS                     (0x3L<<12)
2762
2763 #define BNX2_EMAC_RX_MODE                               0x000014c8
2764 #define BNX2_EMAC_RX_MODE_RESET                          (1L<<0)
2765 #define BNX2_EMAC_RX_MODE_FLOW_EN                        (1L<<2)
2766 #define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL               (1L<<3)
2767 #define BNX2_EMAC_RX_MODE_KEEP_PAUSE                     (1L<<4)
2768 #define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE                (1L<<5)
2769 #define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS                   (1L<<6)
2770 #define BNX2_EMAC_RX_MODE_LLC_CHK                        (1L<<7)
2771 #define BNX2_EMAC_RX_MODE_PROMISCUOUS                    (1L<<8)
2772 #define BNX2_EMAC_RX_MODE_NO_CRC_CHK                     (1L<<9)
2773 #define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG                  (1L<<10)
2774 #define BNX2_EMAC_RX_MODE_FILT_BROADCAST                 (1L<<11)
2775 #define BNX2_EMAC_RX_MODE_SORT_MODE                      (1L<<12)
2776
2777 #define BNX2_EMAC_RX_STATUS                             0x000014cc
2778 #define BNX2_EMAC_RX_STATUS_FFED                         (1L<<0)
2779 #define BNX2_EMAC_RX_STATUS_FF_RECEIVED                  (1L<<1)
2780 #define BNX2_EMAC_RX_STATUS_N_RECEIVED                   (1L<<2)
2781
2782 #define BNX2_EMAC_MULTICAST_HASH0                       0x000014d0
2783 #define BNX2_EMAC_MULTICAST_HASH1                       0x000014d4
2784 #define BNX2_EMAC_MULTICAST_HASH2                       0x000014d8
2785 #define BNX2_EMAC_MULTICAST_HASH3                       0x000014dc
2786 #define BNX2_EMAC_MULTICAST_HASH4                       0x000014e0
2787 #define BNX2_EMAC_MULTICAST_HASH5                       0x000014e4
2788 #define BNX2_EMAC_MULTICAST_HASH6                       0x000014e8
2789 #define BNX2_EMAC_MULTICAST_HASH7                       0x000014ec
2790 #define BNX2_EMAC_CKSUM_ERROR_STATUS                    0x000014f0
2791 #define BNX2_EMAC_CKSUM_ERROR_STATUS_CALCULATED          (0xffffL<<0)
2792 #define BNX2_EMAC_CKSUM_ERROR_STATUS_EXPECTED            (0xffffL<<16)
2793
2794 #define BNX2_EMAC_RX_STAT_IFHCINOCTETS                  0x00001500
2795 #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS               0x00001504
2796 #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS           0x00001508
2797 #define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS               0x0000150c
2798 #define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS           0x00001510
2799 #define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS           0x00001514
2800 #define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS            0x00001518
2801 #define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS      0x0000151c
2802 #define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS   0x00001520
2803 #define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED        0x00001524
2804 #define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED       0x00001528
2805 #define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED      0x0000152c
2806 #define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED              0x00001530
2807 #define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG        0x00001534
2808 #define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS             0x00001538
2809 #define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS       0x0000153c
2810 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS        0x00001540
2811 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS     0x00001544
2812 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS    0x00001548
2813 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x0000154c
2814 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001550
2815 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x00001554
2816 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS  0x00001558
2817 #define BNX2_EMAC_RXMAC_DEBUG0                          0x0000155c
2818 #define BNX2_EMAC_RXMAC_DEBUG1                          0x00001560
2819 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT      (1L<<0)
2820 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE          (1L<<1)
2821 #define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC                   (1L<<2)
2822 #define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR                  (1L<<3)
2823 #define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR               (1L<<4)
2824 #define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA                 (1L<<5)
2825 #define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START            (1L<<6)
2826 #define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT                (0xffffL<<7)
2827 #define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME                 (0xffL<<23)
2828
2829 #define BNX2_EMAC_RXMAC_DEBUG2                          0x00001564
2830 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE                  (0x7L<<0)
2831 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE             (0x0L<<0)
2832 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD              (0x1L<<0)
2833 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA             (0x2L<<0)
2834 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP            (0x3L<<0)
2835 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT              (0x4L<<0)
2836 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP             (0x5L<<0)
2837 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP            (0x6L<<0)
2838 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC               (0x7L<<0)
2839 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE                 (0xfL<<3)
2840 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE            (0x0L<<3)
2841 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0           (0x1L<<3)
2842 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1           (0x2L<<3)
2843 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2           (0x3L<<3)
2844 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3           (0x4L<<3)
2845 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT           (0x5L<<3)
2846 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT            (0x6L<<3)
2847 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS          (0x7L<<3)
2848 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST            (0x8L<<3)
2849 #define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN                   (0xffL<<7)
2850 #define BNX2_EMAC_RXMAC_DEBUG2_FALSEC                    (1L<<15)
2851 #define BNX2_EMAC_RXMAC_DEBUG2_TAGGED                    (1L<<16)
2852 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE               (1L<<18)
2853 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE          (0L<<18)
2854 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED        (1L<<18)
2855 #define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER                (0xfL<<19)
2856 #define BNX2_EMAC_RXMAC_DEBUG2_QUANTA                    (0x1fL<<23)
2857
2858 #define BNX2_EMAC_RXMAC_DEBUG3                          0x00001568
2859 #define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR                 (0xffffL<<0)
2860 #define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR             (0xffffL<<16)
2861
2862 #define BNX2_EMAC_RXMAC_DEBUG4                          0x0000156c
2863 #define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD                (0xffffL<<0)
2864 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE                (0x3fL<<16)
2865 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE           (0x0L<<16)
2866 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2          (0x1L<<16)
2867 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3          (0x2L<<16)
2868 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI            (0x3L<<16)
2869 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3          (0x5L<<16)
2870 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1           (0x6L<<16)
2871 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2          (0x7L<<16)
2872 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2           (0x7L<<16)
2873 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3           (0x8L<<16)
2874 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2            (0x9L<<16)
2875 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3            (0xaL<<16)
2876 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1         (0xeL<<16)
2877 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2         (0xfL<<16)
2878 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK         (0x10L<<16)
2879 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC             (0x11L<<16)
2880 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2            (0x12L<<16)
2881 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3            (0x13L<<16)
2882 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1           (0x14L<<16)
2883 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2           (0x15L<<16)
2884 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3           (0x16L<<16)
2885 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE          (0x17L<<16)
2886 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC             (0x18L<<16)
2887 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE          (0x19L<<16)
2888 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD            (0x1aL<<16)
2889 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC            (0x1bL<<16)
2890 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH          (0x1cL<<16)
2891 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF           (0x1dL<<16)
2892 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON            (0x1eL<<16)
2893 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED         (0x1fL<<16)
2894 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED        (0x20L<<16)
2895 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE          (0x21L<<16)
2896 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL           (0x22L<<16)
2897 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1           (0x23L<<16)
2898 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2           (0x24L<<16)
2899 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3           (0x25L<<16)
2900 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE          (0x26L<<16)
2901 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE         (0x27L<<16)
2902 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL          (0x28L<<16)
2903 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE          (0x29L<<16)
2904 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP           (0x2aL<<16)
2905 #define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT                  (1L<<22)
2906 #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED               (1L<<23)
2907 #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER             (1L<<24)
2908 #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA                 (1L<<25)
2909 #define BNX2_EMAC_RXMAC_DEBUG4_SFD_FOUND                 (1L<<26)
2910 #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE                   (1L<<27)
2911 #define BNX2_EMAC_RXMAC_DEBUG4_START                     (1L<<28)
2912
2913 #define BNX2_EMAC_RXMAC_DEBUG5                          0x00001570
2914 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM                  (0x7L<<0)
2915 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE             (0L<<0)
2916 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF         (1L<<0)
2917 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT        (2L<<0)
2918 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC     (3L<<0)
2919 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE      (4L<<0)
2920 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL      (5L<<0)
2921 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT    (6L<<0)
2922 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1                (0x7L<<4)
2923 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW            (0x0L<<4)
2924 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT           (0x1L<<4)
2925 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF           (0x2L<<4)
2926 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF           (0x3L<<4)
2927 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF            (0x4L<<4)
2928 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF          (0x6L<<4)
2929 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF          (0x7L<<4)
2930 #define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED              (1L<<7)
2931 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0                (0x7L<<8)
2932 #define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL         (1L<<11)
2933 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE                (1L<<12)
2934 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA                 (1L<<13)
2935 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT                 (1L<<14)
2936 #define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT                  (1L<<15)
2937 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE             (0x3L<<16)
2938 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT            (1L<<19)
2939 #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN                     (0xfffL<<20)
2940
2941 #define BNX2_EMAC_RX_STAT_FALSECARRIERERRORS            0x00001574
2942 #define BNX2_EMAC_RX_STAT_AC0                           0x00001580
2943 #define BNX2_EMAC_RX_STAT_AC1                           0x00001584
2944 #define BNX2_EMAC_RX_STAT_AC2                           0x00001588
2945 #define BNX2_EMAC_RX_STAT_AC3                           0x0000158c
2946 #define BNX2_EMAC_RX_STAT_AC4                           0x00001590
2947 #define BNX2_EMAC_RX_STAT_AC5                           0x00001594
2948 #define BNX2_EMAC_RX_STAT_AC6                           0x00001598
2949 #define BNX2_EMAC_RX_STAT_AC7                           0x0000159c
2950 #define BNX2_EMAC_RX_STAT_AC8                           0x000015a0
2951 #define BNX2_EMAC_RX_STAT_AC9                           0x000015a4
2952 #define BNX2_EMAC_RX_STAT_AC10                          0x000015a8
2953 #define BNX2_EMAC_RX_STAT_AC11                          0x000015ac
2954 #define BNX2_EMAC_RX_STAT_AC12                          0x000015b0
2955 #define BNX2_EMAC_RX_STAT_AC13                          0x000015b4
2956 #define BNX2_EMAC_RX_STAT_AC14                          0x000015b8
2957 #define BNX2_EMAC_RX_STAT_AC15                          0x000015bc
2958 #define BNX2_EMAC_RX_STAT_AC16                          0x000015c0
2959 #define BNX2_EMAC_RX_STAT_AC17                          0x000015c4
2960 #define BNX2_EMAC_RX_STAT_AC18                          0x000015c8
2961 #define BNX2_EMAC_RX_STAT_AC19                          0x000015cc
2962 #define BNX2_EMAC_RX_STAT_AC20                          0x000015d0
2963 #define BNX2_EMAC_RX_STAT_AC21                          0x000015d4
2964 #define BNX2_EMAC_RX_STAT_AC22                          0x000015d8
2965 #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC              0x000015dc
2966 #define BNX2_EMAC_RX_STAT_AC_28                         0x000015f4
2967 #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS                 0x00001600
2968 #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS              0x00001604
2969 #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS          0x00001608
2970 #define BNX2_EMAC_TX_STAT_OUTXONSENT                    0x0000160c
2971 #define BNX2_EMAC_TX_STAT_OUTXOFFSENT                   0x00001610
2972 #define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE               0x00001614
2973 #define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES        0x00001618
2974 #define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES      0x0000161c
2975 #define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS        0x00001620
2976 #define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS  0x00001624
2977 #define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS       0x00001628
2978 #define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS              0x0000162c
2979 #define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS          0x00001630
2980 #define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS          0x00001634
2981 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS        0x00001638
2982 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS     0x0000163c
2983 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS    0x00001640
2984 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x00001644
2985 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001648
2986 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x0000164c
2987 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS  0x00001650
2988 #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS    0x00001654
2989 #define BNX2_EMAC_TXMAC_DEBUG0                          0x00001658
2990 #define BNX2_EMAC_TXMAC_DEBUG1                          0x0000165c
2991 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE                 (0xfL<<0)
2992 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE            (0x0L<<0)
2993 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0          (0x1L<<0)
2994 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0           (0x4L<<0)
2995 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1           (0x5L<<0)
2996 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2           (0x6L<<0)
2997 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3           (0x7L<<0)
2998 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0           (0x8L<<0)
2999 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1           (0x9L<<0)
3000 #define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE                (1L<<4)
3001 #define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC                   (1L<<5)
3002 #define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER                (0xfL<<6)
3003 #define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE                (1L<<10)
3004 #define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION            (1L<<11)
3005 #define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER                 (1L<<12)
3006 #define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED                  (1L<<13)
3007 #define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE                  (1L<<14)
3008 #define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME                  (0xfL<<15)
3009 #define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME                 (0xffL<<19)
3010
3011 #define BNX2_EMAC_TXMAC_DEBUG2                          0x00001660
3012 #define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF                  (0x3ffL<<0)
3013 #define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT                (0xffffL<<10)
3014 #define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT                 (0x1fL<<26)
3015 #define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT                   (1L<<31)
3016
3017 #define BNX2_EMAC_TXMAC_DEBUG3                          0x00001664
3018 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE                  (0xfL<<0)
3019 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE             (0x0L<<0)
3020 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1             (0x1L<<0)
3021 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2             (0x2L<<0)
3022 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD              (0x3L<<0)
3023 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA             (0x4L<<0)
3024 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1             (0x5L<<0)
3025 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2             (0x6L<<0)
3026 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT              (0x7L<<0)
3027 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB            (0x8L<<0)
3028 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG            (0x9L<<0)
3029 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM              (0xaL<<0)
3030 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM             (0xbL<<0)
3031 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM             (0xcL<<0)
3032 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT            (0xdL<<0)
3033 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF          (0xeL<<0)
3034 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE                (0x7L<<4)
3035 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE           (0x0L<<4)
3036 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT           (0x1L<<4)
3037 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI            (0x2L<<4)
3038 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC             (0x3L<<4)
3039 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2            (0x4L<<4)
3040 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3            (0x5L<<4)
3041 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC             (0x6L<<4)
3042 #define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE                  (1L<<7)
3043 #define BNX2_EMAC_TXMAC_DEBUG3_XOFF                      (1L<<8)
3044 #define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER                (0xfL<<9)
3045 #define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER            (0x1fL<<13)
3046
3047 #define BNX2_EMAC_TXMAC_DEBUG4                          0x00001668
3048 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER             (0xffffL<<0)
3049 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE               (0xfL<<16)
3050 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE          (0x0L<<16)
3051 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1          (0x2L<<16)
3052 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2          (0x3L<<16)
3053 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3          (0x4L<<16)
3054 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2          (0x5L<<16)
3055 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3          (0x6L<<16)
3056 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1          (0x7L<<16)
3057 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1          (0x8L<<16)
3058 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2          (0x9L<<16)
3059 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME          (0xaL<<16)
3060 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE          (0xcL<<16)
3061 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT          (0xdL<<16)
3062 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD           (0xeL<<16)
3063 #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID              (1L<<20)
3064 #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC                (1L<<21)
3065 #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED               (1L<<22)
3066 #define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER                 (1L<<23)
3067 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND               (1L<<24)
3068 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING              (1L<<25)
3069 #define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC                   (1L<<26)
3070 #define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING                 (1L<<27)
3071 #define BNX2_EMAC_TXMAC_DEBUG4_COL_IN                    (1L<<28)
3072 #define BNX2_EMAC_TXMAC_DEBUG4_BURSTING                  (1L<<29)
3073 #define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE                   (1L<<30)
3074 #define BNX2_EMAC_TXMAC_DEBUG4_GO                        (1L<<31)
3075
3076 #define BNX2_EMAC_TX_STAT_AC0                           0x00001680
3077 #define BNX2_EMAC_TX_STAT_AC1                           0x00001684
3078 #define BNX2_EMAC_TX_STAT_AC2                           0x00001688
3079 #define BNX2_EMAC_TX_STAT_AC3                           0x0000168c
3080 #define BNX2_EMAC_TX_STAT_AC4                           0x00001690
3081 #define BNX2_EMAC_TX_STAT_AC5                           0x00001694
3082 #define BNX2_EMAC_TX_STAT_AC6                           0x00001698
3083 #define BNX2_EMAC_TX_STAT_AC7                           0x0000169c
3084 #define BNX2_EMAC_TX_STAT_AC8                           0x000016a0
3085 #define BNX2_EMAC_TX_STAT_AC9                           0x000016a4
3086 #define BNX2_EMAC_TX_STAT_AC10                          0x000016a8
3087 #define BNX2_EMAC_TX_STAT_AC11                          0x000016ac
3088 #define BNX2_EMAC_TX_STAT_AC12                          0x000016b0
3089 #define BNX2_EMAC_TX_STAT_AC13                          0x000016b4
3090 #define BNX2_EMAC_TX_STAT_AC14                          0x000016b8
3091 #define BNX2_EMAC_TX_STAT_AC15                          0x000016bc
3092 #define BNX2_EMAC_TX_STAT_AC16                          0x000016c0
3093 #define BNX2_EMAC_TX_STAT_AC17                          0x000016c4
3094 #define BNX2_EMAC_TX_STAT_AC18                          0x000016c8
3095 #define BNX2_EMAC_TX_STAT_AC19                          0x000016cc
3096 #define BNX2_EMAC_TX_STAT_AC20                          0x000016d0
3097 #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC              0x000016d8
3098 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL                    0x000016fc
3099 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC     (0x7fL<<0)
3100 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM     (0x7fL<<16)
3101 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN     (1L<<31)
3102
3103
3104 /*
3105  *  rpm_reg definition
3106  *  offset: 0x1800
3107  */
3108 #define BNX2_RPM_COMMAND                                0x00001800
3109 #define BNX2_RPM_COMMAND_ENABLED                         (1L<<0)
3110 #define BNX2_RPM_COMMAND_OVERRUN_ABORT                   (1L<<4)
3111
3112 #define BNX2_RPM_STATUS                                 0x00001804
3113 #define BNX2_RPM_STATUS_MBUF_WAIT                        (1L<<0)
3114 #define BNX2_RPM_STATUS_FREE_WAIT                        (1L<<1)
3115
3116 #define BNX2_RPM_CONFIG                                 0x00001808
3117 #define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM                 (1L<<0)
3118 #define BNX2_RPM_CONFIG_ACPI_ENA                         (1L<<1)
3119 #define BNX2_RPM_CONFIG_ACPI_KEEP                        (1L<<2)
3120 #define BNX2_RPM_CONFIG_MP_KEEP                          (1L<<3)
3121 #define BNX2_RPM_CONFIG_SORT_VECT_VAL                    (0xfL<<4)
3122 #define BNX2_RPM_CONFIG_DISABLE_WOL_ASSERT               (1L<<30)
3123 #define BNX2_RPM_CONFIG_IGNORE_VLAN                      (1L<<31)
3124
3125 #define BNX2_RPM_MGMT_PKT_CTRL                          0x0000180c
3126 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_SORT                 (0xfL<<0)
3127 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_RULE                 (0xfL<<4)
3128 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN           (1L<<30)
3129 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_EN                   (1L<<31)
3130
3131 #define BNX2_RPM_VLAN_MATCH0                            0x00001810
3132 #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE        (0xfffL<<0)
3133
3134 #define BNX2_RPM_VLAN_MATCH1                            0x00001814
3135 #define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE        (0xfffL<<0)
3136
3137 #define BNX2_RPM_VLAN_MATCH2                            0x00001818
3138 #define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE        (0xfffL<<0)
3139
3140 #define BNX2_RPM_VLAN_MATCH3                            0x0000181c
3141 #define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE        (0xfffL<<0)
3142
3143 #define BNX2_RPM_SORT_USER0                             0x00001820
3144 #define BNX2_RPM_SORT_USER0_PM_EN                        (0xffffL<<0)
3145 #define BNX2_RPM_SORT_USER0_BC_EN                        (1L<<16)
3146 #define BNX2_RPM_SORT_USER0_MC_EN                        (1L<<17)
3147 #define BNX2_RPM_SORT_USER0_MC_HSH_EN                    (1L<<18)
3148 #define BNX2_RPM_SORT_USER0_PROM_EN                      (1L<<19)
3149 #define BNX2_RPM_SORT_USER0_VLAN_EN                      (0xfL<<20)
3150 #define BNX2_RPM_SORT_USER0_PROM_VLAN                    (1L<<24)
3151 #define BNX2_RPM_SORT_USER0_VLAN_NOTMATCH                (1L<<25)
3152 #define BNX2_RPM_SORT_USER0_ENA                          (1L<<31)
3153
3154 #define BNX2_RPM_SORT_USER1                             0x00001824
3155 #define BNX2_RPM_SORT_USER1_PM_EN                        (0xffffL<<0)
3156 #define BNX2_RPM_SORT_USER1_BC_EN                        (1L<<16)
3157 #define BNX2_RPM_SORT_USER1_MC_EN                        (1L<<17)
3158 #define BNX2_RPM_SORT_USER1_MC_HSH_EN                    (1L<<18)
3159 #define BNX2_RPM_SORT_USER1_PROM_EN                      (1L<<19)
3160 #define BNX2_RPM_SORT_USER1_VLAN_EN                      (0xfL<<20)
3161 #define BNX2_RPM_SORT_USER1_PROM_VLAN                    (1L<<24)
3162 #define BNX2_RPM_SORT_USER1_ENA                          (1L<<31)
3163
3164 #define BNX2_RPM_SORT_USER2                             0x00001828
3165 #define BNX2_RPM_SORT_USER2_PM_EN                        (0xffffL<<0)
3166 #define BNX2_RPM_SORT_USER2_BC_EN                        (1L<<16)
3167 #define BNX2_RPM_SORT_USER2_MC_EN                        (1L<<17)
3168 #define BNX2_RPM_SORT_USER2_MC_HSH_EN                    (1L<<18)
3169 #define BNX2_RPM_SORT_USER2_PROM_EN                      (1L<<19)
3170 #define BNX2_RPM_SORT_USER2_VLAN_EN                      (0xfL<<20)
3171 #define BNX2_RPM_SORT_USER2_PROM_VLAN                    (1L<<24)
3172 #define BNX2_RPM_SORT_USER2_ENA                          (1L<<31)
3173
3174 #define BNX2_RPM_SORT_USER3                             0x0000182c
3175 #define BNX2_RPM_SORT_USER3_PM_EN                        (0xffffL<<0)
3176 #define BNX2_RPM_SORT_USER3_BC_EN                        (1L<<16)
3177 #define BNX2_RPM_SORT_USER3_MC_EN                        (1L<<17)
3178 #define BNX2_RPM_SORT_USER3_MC_HSH_EN                    (1L<<18)
3179 #define BNX2_RPM_SORT_USER3_PROM_EN                      (1L<<19)
3180 #define BNX2_RPM_SORT_USER3_VLAN_EN                      (0xfL<<20)
3181 #define BNX2_RPM_SORT_USER3_PROM_VLAN                    (1L<<24)
3182 #define BNX2_RPM_SORT_USER3_ENA                          (1L<<31)
3183
3184 #define BNX2_RPM_STAT_L2_FILTER_DISCARDS                0x00001840
3185 #define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS             0x00001844
3186 #define BNX2_RPM_STAT_IFINFTQDISCARDS                   0x00001848
3187 #define BNX2_RPM_STAT_IFINMBUFDISCARD                   0x0000184c
3188 #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT               0x00001850
3189 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0           0x00001854
3190 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN    (0xffL<<0)
3191 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER        (0xffL<<16)
3192 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE       (1L<<30)
3193 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN     (1L<<31)
3194
3195 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1           0x00001858
3196 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN    (0xffL<<0)
3197 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER        (0xffL<<16)
3198 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE       (1L<<30)
3199 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN     (1L<<31)
3200
3201 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2           0x0000185c
3202 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN    (0xffL<<0)
3203 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER        (0xffL<<16)
3204 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE       (1L<<30)
3205 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN     (1L<<31)
3206
3207 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3           0x00001860
3208 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN    (0xffL<<0)
3209 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER        (0xffL<<16)
3210 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE       (1L<<30)
3211 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN     (1L<<31)
3212
3213 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4           0x00001864
3214 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN    (0xffL<<0)
3215 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER        (0xffL<<16)
3216 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE       (1L<<30)
3217 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN     (1L<<31)
3218
3219 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5           0x00001868
3220 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN    (0xffL<<0)
3221 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER        (0xffL<<16)
3222 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE       (1L<<30)
3223 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN     (1L<<31)
3224
3225 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6           0x0000186c
3226 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN    (0xffL<<0)
3227 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER        (0xffL<<16)
3228 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE       (1L<<30)
3229 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN     (1L<<31)
3230
3231 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7           0x00001870
3232 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN    (0xffL<<0)
3233 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER        (0xffL<<16)
3234 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE       (1L<<30)
3235 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN     (1L<<31)
3236
3237 #define BNX2_RPM_STAT_AC0                               0x00001880
3238 #define BNX2_RPM_STAT_AC1                               0x00001884
3239 #define BNX2_RPM_STAT_AC2                               0x00001888
3240 #define BNX2_RPM_STAT_AC3                               0x0000188c
3241 #define BNX2_RPM_STAT_AC4                               0x00001890