[BNX2]: Enable DMA on 5709.
[sfrench/cifs-2.6.git] / drivers / net / bnx2.c
1 /* bnx2.c: Broadcom NX2 network driver.
2  *
3  * Copyright (c) 2004-2007 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Written by: Michael Chan  (mchan@broadcom.com)
10  */
11
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <asm/bitops.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
34 #include <asm/page.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #ifdef NETIF_F_HW_VLAN_TX
39 #include <linux/if_vlan.h>
40 #define BCM_VLAN 1
41 #endif
42 #include <net/ip.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/zlib.h>
50
51 #include "bnx2.h"
52 #include "bnx2_fw.h"
53 #include "bnx2_fw2.h"
54
55 #define DRV_MODULE_NAME         "bnx2"
56 #define PFX DRV_MODULE_NAME     ": "
57 #define DRV_MODULE_VERSION      "1.5.10"
58 #define DRV_MODULE_RELDATE      "May 1, 2007"
59
60 #define RUN_AT(x) (jiffies + (x))
61
62 /* Time in jiffies before concluding the transmitter is hung. */
63 #define TX_TIMEOUT  (5*HZ)
64
65 static const char version[] __devinitdata =
66         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
67
68 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
69 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
70 MODULE_LICENSE("GPL");
71 MODULE_VERSION(DRV_MODULE_VERSION);
72
73 static int disable_msi = 0;
74
75 module_param(disable_msi, int, 0);
76 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
77
78 typedef enum {
79         BCM5706 = 0,
80         NC370T,
81         NC370I,
82         BCM5706S,
83         NC370F,
84         BCM5708,
85         BCM5708S,
86         BCM5709,
87         BCM5709S,
88 } board_t;
89
90 /* indexed by board_t, above */
91 static const struct {
92         char *name;
93 } board_info[] __devinitdata = {
94         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
95         { "HP NC370T Multifunction Gigabit Server Adapter" },
96         { "HP NC370i Multifunction Gigabit Server Adapter" },
97         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
98         { "HP NC370F Multifunction Gigabit Server Adapter" },
99         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
100         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
101         { "Broadcom NetXtreme II BCM5709 1000Base-T" },
102         { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
103         };
104
105 static struct pci_device_id bnx2_pci_tbl[] = {
106         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
107           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
108         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
110         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
111           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
112         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
113           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
114         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
115           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
116         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
117           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
118         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
119           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
120         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
121           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
122         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
123           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
124         { 0, }
125 };
126
127 static struct flash_spec flash_table[] =
128 {
129         /* Slow EEPROM */
130         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
131          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
132          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
133          "EEPROM - slow"},
134         /* Expansion entry 0001 */
135         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
136          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
137          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
138          "Entry 0001"},
139         /* Saifun SA25F010 (non-buffered flash) */
140         /* strap, cfg1, & write1 need updates */
141         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
142          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
143          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
144          "Non-buffered flash (128kB)"},
145         /* Saifun SA25F020 (non-buffered flash) */
146         /* strap, cfg1, & write1 need updates */
147         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
148          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
149          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
150          "Non-buffered flash (256kB)"},
151         /* Expansion entry 0100 */
152         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
153          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
154          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
155          "Entry 0100"},
156         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
157         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
158          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
159          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
160          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
161         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
162         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
163          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
164          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
165          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
166         /* Saifun SA25F005 (non-buffered flash) */
167         /* strap, cfg1, & write1 need updates */
168         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
169          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
170          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
171          "Non-buffered flash (64kB)"},
172         /* Fast EEPROM */
173         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
174          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
175          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
176          "EEPROM - fast"},
177         /* Expansion entry 1001 */
178         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
179          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
180          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
181          "Entry 1001"},
182         /* Expansion entry 1010 */
183         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
184          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
185          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
186          "Entry 1010"},
187         /* ATMEL AT45DB011B (buffered flash) */
188         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
189          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
190          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
191          "Buffered flash (128kB)"},
192         /* Expansion entry 1100 */
193         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
194          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
195          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
196          "Entry 1100"},
197         /* Expansion entry 1101 */
198         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
199          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
200          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
201          "Entry 1101"},
202         /* Ateml Expansion entry 1110 */
203         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
204          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
205          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
206          "Entry 1110 (Atmel)"},
207         /* ATMEL AT45DB021B (buffered flash) */
208         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
209          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
210          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
211          "Buffered flash (256kB)"},
212 };
213
214 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
215
216 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
217 {
218         u32 diff;
219
220         smp_mb();
221
222         /* The ring uses 256 indices for 255 entries, one of them
223          * needs to be skipped.
224          */
225         diff = bp->tx_prod - bp->tx_cons;
226         if (unlikely(diff >= TX_DESC_CNT)) {
227                 diff &= 0xffff;
228                 if (diff == TX_DESC_CNT)
229                         diff = MAX_TX_DESC_CNT;
230         }
231         return (bp->tx_ring_size - diff);
232 }
233
234 static u32
235 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
236 {
237         u32 val;
238
239         spin_lock_bh(&bp->indirect_lock);
240         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
241         val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
242         spin_unlock_bh(&bp->indirect_lock);
243         return val;
244 }
245
246 static void
247 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
248 {
249         spin_lock_bh(&bp->indirect_lock);
250         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
251         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
252         spin_unlock_bh(&bp->indirect_lock);
253 }
254
255 static void
256 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
257 {
258         offset += cid_addr;
259         spin_lock_bh(&bp->indirect_lock);
260         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
261                 int i;
262
263                 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
264                 REG_WR(bp, BNX2_CTX_CTX_CTRL,
265                        offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
266                 for (i = 0; i < 5; i++) {
267                         u32 val;
268                         val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
269                         if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
270                                 break;
271                         udelay(5);
272                 }
273         } else {
274                 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
275                 REG_WR(bp, BNX2_CTX_DATA, val);
276         }
277         spin_unlock_bh(&bp->indirect_lock);
278 }
279
280 static int
281 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
282 {
283         u32 val1;
284         int i, ret;
285
286         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
287                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
288                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
289
290                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
291                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
292
293                 udelay(40);
294         }
295
296         val1 = (bp->phy_addr << 21) | (reg << 16) |
297                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
298                 BNX2_EMAC_MDIO_COMM_START_BUSY;
299         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
300
301         for (i = 0; i < 50; i++) {
302                 udelay(10);
303
304                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
305                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
306                         udelay(5);
307
308                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
309                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
310
311                         break;
312                 }
313         }
314
315         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
316                 *val = 0x0;
317                 ret = -EBUSY;
318         }
319         else {
320                 *val = val1;
321                 ret = 0;
322         }
323
324         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
325                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
326                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
327
328                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
329                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
330
331                 udelay(40);
332         }
333
334         return ret;
335 }
336
337 static int
338 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
339 {
340         u32 val1;
341         int i, ret;
342
343         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
344                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
345                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
346
347                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
348                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
349
350                 udelay(40);
351         }
352
353         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
354                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
355                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
356         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
357
358         for (i = 0; i < 50; i++) {
359                 udelay(10);
360
361                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
362                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
363                         udelay(5);
364                         break;
365                 }
366         }
367
368         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
369                 ret = -EBUSY;
370         else
371                 ret = 0;
372
373         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
374                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
375                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
376
377                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
378                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
379
380                 udelay(40);
381         }
382
383         return ret;
384 }
385
386 static void
387 bnx2_disable_int(struct bnx2 *bp)
388 {
389         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
390                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
391         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
392 }
393
394 static void
395 bnx2_enable_int(struct bnx2 *bp)
396 {
397         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
398                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
399                BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
400
401         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
402                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
403
404         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
405 }
406
407 static void
408 bnx2_disable_int_sync(struct bnx2 *bp)
409 {
410         atomic_inc(&bp->intr_sem);
411         bnx2_disable_int(bp);
412         synchronize_irq(bp->pdev->irq);
413 }
414
415 static void
416 bnx2_netif_stop(struct bnx2 *bp)
417 {
418         bnx2_disable_int_sync(bp);
419         if (netif_running(bp->dev)) {
420                 netif_poll_disable(bp->dev);
421                 netif_tx_disable(bp->dev);
422                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
423         }
424 }
425
426 static void
427 bnx2_netif_start(struct bnx2 *bp)
428 {
429         if (atomic_dec_and_test(&bp->intr_sem)) {
430                 if (netif_running(bp->dev)) {
431                         netif_wake_queue(bp->dev);
432                         netif_poll_enable(bp->dev);
433                         bnx2_enable_int(bp);
434                 }
435         }
436 }
437
438 static void
439 bnx2_free_mem(struct bnx2 *bp)
440 {
441         int i;
442
443         for (i = 0; i < bp->ctx_pages; i++) {
444                 if (bp->ctx_blk[i]) {
445                         pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
446                                             bp->ctx_blk[i],
447                                             bp->ctx_blk_mapping[i]);
448                         bp->ctx_blk[i] = NULL;
449                 }
450         }
451         if (bp->status_blk) {
452                 pci_free_consistent(bp->pdev, bp->status_stats_size,
453                                     bp->status_blk, bp->status_blk_mapping);
454                 bp->status_blk = NULL;
455                 bp->stats_blk = NULL;
456         }
457         if (bp->tx_desc_ring) {
458                 pci_free_consistent(bp->pdev,
459                                     sizeof(struct tx_bd) * TX_DESC_CNT,
460                                     bp->tx_desc_ring, bp->tx_desc_mapping);
461                 bp->tx_desc_ring = NULL;
462         }
463         kfree(bp->tx_buf_ring);
464         bp->tx_buf_ring = NULL;
465         for (i = 0; i < bp->rx_max_ring; i++) {
466                 if (bp->rx_desc_ring[i])
467                         pci_free_consistent(bp->pdev,
468                                             sizeof(struct rx_bd) * RX_DESC_CNT,
469                                             bp->rx_desc_ring[i],
470                                             bp->rx_desc_mapping[i]);
471                 bp->rx_desc_ring[i] = NULL;
472         }
473         vfree(bp->rx_buf_ring);
474         bp->rx_buf_ring = NULL;
475 }
476
477 static int
478 bnx2_alloc_mem(struct bnx2 *bp)
479 {
480         int i, status_blk_size;
481
482         bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
483                                   GFP_KERNEL);
484         if (bp->tx_buf_ring == NULL)
485                 return -ENOMEM;
486
487         bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
488                                                 sizeof(struct tx_bd) *
489                                                 TX_DESC_CNT,
490                                                 &bp->tx_desc_mapping);
491         if (bp->tx_desc_ring == NULL)
492                 goto alloc_mem_err;
493
494         bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
495                                   bp->rx_max_ring);
496         if (bp->rx_buf_ring == NULL)
497                 goto alloc_mem_err;
498
499         memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
500                                    bp->rx_max_ring);
501
502         for (i = 0; i < bp->rx_max_ring; i++) {
503                 bp->rx_desc_ring[i] =
504                         pci_alloc_consistent(bp->pdev,
505                                              sizeof(struct rx_bd) * RX_DESC_CNT,
506                                              &bp->rx_desc_mapping[i]);
507                 if (bp->rx_desc_ring[i] == NULL)
508                         goto alloc_mem_err;
509
510         }
511
512         /* Combine status and statistics blocks into one allocation. */
513         status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
514         bp->status_stats_size = status_blk_size +
515                                 sizeof(struct statistics_block);
516
517         bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
518                                               &bp->status_blk_mapping);
519         if (bp->status_blk == NULL)
520                 goto alloc_mem_err;
521
522         memset(bp->status_blk, 0, bp->status_stats_size);
523
524         bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
525                                   status_blk_size);
526
527         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
528
529         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
530                 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
531                 if (bp->ctx_pages == 0)
532                         bp->ctx_pages = 1;
533                 for (i = 0; i < bp->ctx_pages; i++) {
534                         bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
535                                                 BCM_PAGE_SIZE,
536                                                 &bp->ctx_blk_mapping[i]);
537                         if (bp->ctx_blk[i] == NULL)
538                                 goto alloc_mem_err;
539                 }
540         }
541         return 0;
542
543 alloc_mem_err:
544         bnx2_free_mem(bp);
545         return -ENOMEM;
546 }
547
548 static void
549 bnx2_report_fw_link(struct bnx2 *bp)
550 {
551         u32 fw_link_status = 0;
552
553         if (bp->link_up) {
554                 u32 bmsr;
555
556                 switch (bp->line_speed) {
557                 case SPEED_10:
558                         if (bp->duplex == DUPLEX_HALF)
559                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
560                         else
561                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
562                         break;
563                 case SPEED_100:
564                         if (bp->duplex == DUPLEX_HALF)
565                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
566                         else
567                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
568                         break;
569                 case SPEED_1000:
570                         if (bp->duplex == DUPLEX_HALF)
571                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
572                         else
573                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
574                         break;
575                 case SPEED_2500:
576                         if (bp->duplex == DUPLEX_HALF)
577                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
578                         else
579                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
580                         break;
581                 }
582
583                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
584
585                 if (bp->autoneg) {
586                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
587
588                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
589                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
590
591                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
592                             bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
593                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
594                         else
595                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
596                 }
597         }
598         else
599                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
600
601         REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
602 }
603
604 static void
605 bnx2_report_link(struct bnx2 *bp)
606 {
607         if (bp->link_up) {
608                 netif_carrier_on(bp->dev);
609                 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
610
611                 printk("%d Mbps ", bp->line_speed);
612
613                 if (bp->duplex == DUPLEX_FULL)
614                         printk("full duplex");
615                 else
616                         printk("half duplex");
617
618                 if (bp->flow_ctrl) {
619                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
620                                 printk(", receive ");
621                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
622                                         printk("& transmit ");
623                         }
624                         else {
625                                 printk(", transmit ");
626                         }
627                         printk("flow control ON");
628                 }
629                 printk("\n");
630         }
631         else {
632                 netif_carrier_off(bp->dev);
633                 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
634         }
635
636         bnx2_report_fw_link(bp);
637 }
638
639 static void
640 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
641 {
642         u32 local_adv, remote_adv;
643
644         bp->flow_ctrl = 0;
645         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
646                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
647
648                 if (bp->duplex == DUPLEX_FULL) {
649                         bp->flow_ctrl = bp->req_flow_ctrl;
650                 }
651                 return;
652         }
653
654         if (bp->duplex != DUPLEX_FULL) {
655                 return;
656         }
657
658         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
659             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
660                 u32 val;
661
662                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
663                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
664                         bp->flow_ctrl |= FLOW_CTRL_TX;
665                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
666                         bp->flow_ctrl |= FLOW_CTRL_RX;
667                 return;
668         }
669
670         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
671         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
672
673         if (bp->phy_flags & PHY_SERDES_FLAG) {
674                 u32 new_local_adv = 0;
675                 u32 new_remote_adv = 0;
676
677                 if (local_adv & ADVERTISE_1000XPAUSE)
678                         new_local_adv |= ADVERTISE_PAUSE_CAP;
679                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
680                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
681                 if (remote_adv & ADVERTISE_1000XPAUSE)
682                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
683                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
684                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
685
686                 local_adv = new_local_adv;
687                 remote_adv = new_remote_adv;
688         }
689
690         /* See Table 28B-3 of 802.3ab-1999 spec. */
691         if (local_adv & ADVERTISE_PAUSE_CAP) {
692                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
693                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
694                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
695                         }
696                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
697                                 bp->flow_ctrl = FLOW_CTRL_RX;
698                         }
699                 }
700                 else {
701                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
702                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
703                         }
704                 }
705         }
706         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
707                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
708                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
709
710                         bp->flow_ctrl = FLOW_CTRL_TX;
711                 }
712         }
713 }
714
715 static int
716 bnx2_5709s_linkup(struct bnx2 *bp)
717 {
718         u32 val, speed;
719
720         bp->link_up = 1;
721
722         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
723         bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
724         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
725
726         if ((bp->autoneg & AUTONEG_SPEED) == 0) {
727                 bp->line_speed = bp->req_line_speed;
728                 bp->duplex = bp->req_duplex;
729                 return 0;
730         }
731         speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
732         switch (speed) {
733                 case MII_BNX2_GP_TOP_AN_SPEED_10:
734                         bp->line_speed = SPEED_10;
735                         break;
736                 case MII_BNX2_GP_TOP_AN_SPEED_100:
737                         bp->line_speed = SPEED_100;
738                         break;
739                 case MII_BNX2_GP_TOP_AN_SPEED_1G:
740                 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
741                         bp->line_speed = SPEED_1000;
742                         break;
743                 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
744                         bp->line_speed = SPEED_2500;
745                         break;
746         }
747         if (val & MII_BNX2_GP_TOP_AN_FD)
748                 bp->duplex = DUPLEX_FULL;
749         else
750                 bp->duplex = DUPLEX_HALF;
751         return 0;
752 }
753
754 static int
755 bnx2_5708s_linkup(struct bnx2 *bp)
756 {
757         u32 val;
758
759         bp->link_up = 1;
760         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
761         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
762                 case BCM5708S_1000X_STAT1_SPEED_10:
763                         bp->line_speed = SPEED_10;
764                         break;
765                 case BCM5708S_1000X_STAT1_SPEED_100:
766                         bp->line_speed = SPEED_100;
767                         break;
768                 case BCM5708S_1000X_STAT1_SPEED_1G:
769                         bp->line_speed = SPEED_1000;
770                         break;
771                 case BCM5708S_1000X_STAT1_SPEED_2G5:
772                         bp->line_speed = SPEED_2500;
773                         break;
774         }
775         if (val & BCM5708S_1000X_STAT1_FD)
776                 bp->duplex = DUPLEX_FULL;
777         else
778                 bp->duplex = DUPLEX_HALF;
779
780         return 0;
781 }
782
783 static int
784 bnx2_5706s_linkup(struct bnx2 *bp)
785 {
786         u32 bmcr, local_adv, remote_adv, common;
787
788         bp->link_up = 1;
789         bp->line_speed = SPEED_1000;
790
791         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
792         if (bmcr & BMCR_FULLDPLX) {
793                 bp->duplex = DUPLEX_FULL;
794         }
795         else {
796                 bp->duplex = DUPLEX_HALF;
797         }
798
799         if (!(bmcr & BMCR_ANENABLE)) {
800                 return 0;
801         }
802
803         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
804         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
805
806         common = local_adv & remote_adv;
807         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
808
809                 if (common & ADVERTISE_1000XFULL) {
810                         bp->duplex = DUPLEX_FULL;
811                 }
812                 else {
813                         bp->duplex = DUPLEX_HALF;
814                 }
815         }
816
817         return 0;
818 }
819
820 static int
821 bnx2_copper_linkup(struct bnx2 *bp)
822 {
823         u32 bmcr;
824
825         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
826         if (bmcr & BMCR_ANENABLE) {
827                 u32 local_adv, remote_adv, common;
828
829                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
830                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
831
832                 common = local_adv & (remote_adv >> 2);
833                 if (common & ADVERTISE_1000FULL) {
834                         bp->line_speed = SPEED_1000;
835                         bp->duplex = DUPLEX_FULL;
836                 }
837                 else if (common & ADVERTISE_1000HALF) {
838                         bp->line_speed = SPEED_1000;
839                         bp->duplex = DUPLEX_HALF;
840                 }
841                 else {
842                         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
843                         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
844
845                         common = local_adv & remote_adv;
846                         if (common & ADVERTISE_100FULL) {
847                                 bp->line_speed = SPEED_100;
848                                 bp->duplex = DUPLEX_FULL;
849                         }
850                         else if (common & ADVERTISE_100HALF) {
851                                 bp->line_speed = SPEED_100;
852                                 bp->duplex = DUPLEX_HALF;
853                         }
854                         else if (common & ADVERTISE_10FULL) {
855                                 bp->line_speed = SPEED_10;
856                                 bp->duplex = DUPLEX_FULL;
857                         }
858                         else if (common & ADVERTISE_10HALF) {
859                                 bp->line_speed = SPEED_10;
860                                 bp->duplex = DUPLEX_HALF;
861                         }
862                         else {
863                                 bp->line_speed = 0;
864                                 bp->link_up = 0;
865                         }
866                 }
867         }
868         else {
869                 if (bmcr & BMCR_SPEED100) {
870                         bp->line_speed = SPEED_100;
871                 }
872                 else {
873                         bp->line_speed = SPEED_10;
874                 }
875                 if (bmcr & BMCR_FULLDPLX) {
876                         bp->duplex = DUPLEX_FULL;
877                 }
878                 else {
879                         bp->duplex = DUPLEX_HALF;
880                 }
881         }
882
883         return 0;
884 }
885
886 static int
887 bnx2_set_mac_link(struct bnx2 *bp)
888 {
889         u32 val;
890
891         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
892         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
893                 (bp->duplex == DUPLEX_HALF)) {
894                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
895         }
896
897         /* Configure the EMAC mode register. */
898         val = REG_RD(bp, BNX2_EMAC_MODE);
899
900         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
901                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
902                 BNX2_EMAC_MODE_25G_MODE);
903
904         if (bp->link_up) {
905                 switch (bp->line_speed) {
906                         case SPEED_10:
907                                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
908                                         val |= BNX2_EMAC_MODE_PORT_MII_10M;
909                                         break;
910                                 }
911                                 /* fall through */
912                         case SPEED_100:
913                                 val |= BNX2_EMAC_MODE_PORT_MII;
914                                 break;
915                         case SPEED_2500:
916                                 val |= BNX2_EMAC_MODE_25G_MODE;
917                                 /* fall through */
918                         case SPEED_1000:
919                                 val |= BNX2_EMAC_MODE_PORT_GMII;
920                                 break;
921                 }
922         }
923         else {
924                 val |= BNX2_EMAC_MODE_PORT_GMII;
925         }
926
927         /* Set the MAC to operate in the appropriate duplex mode. */
928         if (bp->duplex == DUPLEX_HALF)
929                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
930         REG_WR(bp, BNX2_EMAC_MODE, val);
931
932         /* Enable/disable rx PAUSE. */
933         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
934
935         if (bp->flow_ctrl & FLOW_CTRL_RX)
936                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
937         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
938
939         /* Enable/disable tx PAUSE. */
940         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
941         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
942
943         if (bp->flow_ctrl & FLOW_CTRL_TX)
944                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
945         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
946
947         /* Acknowledge the interrupt. */
948         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
949
950         return 0;
951 }
952
953 static void
954 bnx2_enable_bmsr1(struct bnx2 *bp)
955 {
956         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
957             (CHIP_NUM(bp) == CHIP_NUM_5709))
958                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
959                                MII_BNX2_BLK_ADDR_GP_STATUS);
960 }
961
962 static void
963 bnx2_disable_bmsr1(struct bnx2 *bp)
964 {
965         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
966             (CHIP_NUM(bp) == CHIP_NUM_5709))
967                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
968                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
969 }
970
971 static int
972 bnx2_test_and_enable_2g5(struct bnx2 *bp)
973 {
974         u32 up1;
975         int ret = 1;
976
977         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
978                 return 0;
979
980         if (bp->autoneg & AUTONEG_SPEED)
981                 bp->advertising |= ADVERTISED_2500baseX_Full;
982
983         if (CHIP_NUM(bp) == CHIP_NUM_5709)
984                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
985
986         bnx2_read_phy(bp, bp->mii_up1, &up1);
987         if (!(up1 & BCM5708S_UP1_2G5)) {
988                 up1 |= BCM5708S_UP1_2G5;
989                 bnx2_write_phy(bp, bp->mii_up1, up1);
990                 ret = 0;
991         }
992
993         if (CHIP_NUM(bp) == CHIP_NUM_5709)
994                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
995                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
996
997         return ret;
998 }
999
1000 static int
1001 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1002 {
1003         u32 up1;
1004         int ret = 0;
1005
1006         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1007                 return 0;
1008
1009         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1010                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1011
1012         bnx2_read_phy(bp, bp->mii_up1, &up1);
1013         if (up1 & BCM5708S_UP1_2G5) {
1014                 up1 &= ~BCM5708S_UP1_2G5;
1015                 bnx2_write_phy(bp, bp->mii_up1, up1);
1016                 ret = 1;
1017         }
1018
1019         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1020                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1021                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1022
1023         return ret;
1024 }
1025
1026 static void
1027 bnx2_enable_forced_2g5(struct bnx2 *bp)
1028 {
1029         u32 bmcr;
1030
1031         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1032                 return;
1033
1034         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1035                 u32 val;
1036
1037                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1038                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1039                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1040                 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1041                 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1042                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1043
1044                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1045                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1046                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1047
1048         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1049                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1050                 bmcr |= BCM5708S_BMCR_FORCE_2500;
1051         }
1052
1053         if (bp->autoneg & AUTONEG_SPEED) {
1054                 bmcr &= ~BMCR_ANENABLE;
1055                 if (bp->req_duplex == DUPLEX_FULL)
1056                         bmcr |= BMCR_FULLDPLX;
1057         }
1058         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1059 }
1060
1061 static void
1062 bnx2_disable_forced_2g5(struct bnx2 *bp)
1063 {
1064         u32 bmcr;
1065
1066         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1067                 return;
1068
1069         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1070                 u32 val;
1071
1072                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1073                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1074                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1075                 val &= ~MII_BNX2_SD_MISC1_FORCE;
1076                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1077
1078                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1079                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1080                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1081
1082         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1083                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1084                 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1085         }
1086
1087         if (bp->autoneg & AUTONEG_SPEED)
1088                 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1089         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1090 }
1091
1092 static int
1093 bnx2_set_link(struct bnx2 *bp)
1094 {
1095         u32 bmsr;
1096         u8 link_up;
1097
1098         if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1099                 bp->link_up = 1;
1100                 return 0;
1101         }
1102
1103         link_up = bp->link_up;
1104
1105         bnx2_enable_bmsr1(bp);
1106         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1107         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1108         bnx2_disable_bmsr1(bp);
1109
1110         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1111             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1112                 u32 val;
1113
1114                 val = REG_RD(bp, BNX2_EMAC_STATUS);
1115                 if (val & BNX2_EMAC_STATUS_LINK)
1116                         bmsr |= BMSR_LSTATUS;
1117                 else
1118                         bmsr &= ~BMSR_LSTATUS;
1119         }
1120
1121         if (bmsr & BMSR_LSTATUS) {
1122                 bp->link_up = 1;
1123
1124                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1125                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1126                                 bnx2_5706s_linkup(bp);
1127                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1128                                 bnx2_5708s_linkup(bp);
1129                         else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1130                                 bnx2_5709s_linkup(bp);
1131                 }
1132                 else {
1133                         bnx2_copper_linkup(bp);
1134                 }
1135                 bnx2_resolve_flow_ctrl(bp);
1136         }
1137         else {
1138                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1139                     (bp->autoneg & AUTONEG_SPEED))
1140                         bnx2_disable_forced_2g5(bp);
1141
1142                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1143                 bp->link_up = 0;
1144         }
1145
1146         if (bp->link_up != link_up) {
1147                 bnx2_report_link(bp);
1148         }
1149
1150         bnx2_set_mac_link(bp);
1151
1152         return 0;
1153 }
1154
1155 static int
1156 bnx2_reset_phy(struct bnx2 *bp)
1157 {
1158         int i;
1159         u32 reg;
1160
1161         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1162
1163 #define PHY_RESET_MAX_WAIT 100
1164         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1165                 udelay(10);
1166
1167                 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1168                 if (!(reg & BMCR_RESET)) {
1169                         udelay(20);
1170                         break;
1171                 }
1172         }
1173         if (i == PHY_RESET_MAX_WAIT) {
1174                 return -EBUSY;
1175         }
1176         return 0;
1177 }
1178
1179 static u32
1180 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1181 {
1182         u32 adv = 0;
1183
1184         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1185                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1186
1187                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1188                         adv = ADVERTISE_1000XPAUSE;
1189                 }
1190                 else {
1191                         adv = ADVERTISE_PAUSE_CAP;
1192                 }
1193         }
1194         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1195                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1196                         adv = ADVERTISE_1000XPSE_ASYM;
1197                 }
1198                 else {
1199                         adv = ADVERTISE_PAUSE_ASYM;
1200                 }
1201         }
1202         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1203                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1204                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1205                 }
1206                 else {
1207                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1208                 }
1209         }
1210         return adv;
1211 }
1212
1213 static int
1214 bnx2_setup_serdes_phy(struct bnx2 *bp)
1215 {
1216         u32 adv, bmcr;
1217         u32 new_adv = 0;
1218
1219         if (!(bp->autoneg & AUTONEG_SPEED)) {
1220                 u32 new_bmcr;
1221                 int force_link_down = 0;
1222
1223                 if (bp->req_line_speed == SPEED_2500) {
1224                         if (!bnx2_test_and_enable_2g5(bp))
1225                                 force_link_down = 1;
1226                 } else if (bp->req_line_speed == SPEED_1000) {
1227                         if (bnx2_test_and_disable_2g5(bp))
1228                                 force_link_down = 1;
1229                 }
1230                 bnx2_read_phy(bp, bp->mii_adv, &adv);
1231                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1232
1233                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1234                 new_bmcr = bmcr & ~BMCR_ANENABLE;
1235                 new_bmcr |= BMCR_SPEED1000;
1236
1237                 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1238                         if (bp->req_line_speed == SPEED_2500)
1239                                 bnx2_enable_forced_2g5(bp);
1240                         else if (bp->req_line_speed == SPEED_1000) {
1241                                 bnx2_disable_forced_2g5(bp);
1242                                 new_bmcr &= ~0x2000;
1243                         }
1244
1245                 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1246                         if (bp->req_line_speed == SPEED_2500)
1247                                 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1248                         else
1249                                 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1250                 }
1251
1252                 if (bp->req_duplex == DUPLEX_FULL) {
1253                         adv |= ADVERTISE_1000XFULL;
1254                         new_bmcr |= BMCR_FULLDPLX;
1255                 }
1256                 else {
1257                         adv |= ADVERTISE_1000XHALF;
1258                         new_bmcr &= ~BMCR_FULLDPLX;
1259                 }
1260                 if ((new_bmcr != bmcr) || (force_link_down)) {
1261                         /* Force a link down visible on the other side */
1262                         if (bp->link_up) {
1263                                 bnx2_write_phy(bp, bp->mii_adv, adv &
1264                                                ~(ADVERTISE_1000XFULL |
1265                                                  ADVERTISE_1000XHALF));
1266                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1267                                         BMCR_ANRESTART | BMCR_ANENABLE);
1268
1269                                 bp->link_up = 0;
1270                                 netif_carrier_off(bp->dev);
1271                                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1272                                 bnx2_report_link(bp);
1273                         }
1274                         bnx2_write_phy(bp, bp->mii_adv, adv);
1275                         bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1276                 } else {
1277                         bnx2_resolve_flow_ctrl(bp);
1278                         bnx2_set_mac_link(bp);
1279                 }
1280                 return 0;
1281         }
1282
1283         bnx2_test_and_enable_2g5(bp);
1284
1285         if (bp->advertising & ADVERTISED_1000baseT_Full)
1286                 new_adv |= ADVERTISE_1000XFULL;
1287
1288         new_adv |= bnx2_phy_get_pause_adv(bp);
1289
1290         bnx2_read_phy(bp, bp->mii_adv, &adv);
1291         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1292
1293         bp->serdes_an_pending = 0;
1294         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1295                 /* Force a link down visible on the other side */
1296                 if (bp->link_up) {
1297                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1298                         spin_unlock_bh(&bp->phy_lock);
1299                         msleep(20);
1300                         spin_lock_bh(&bp->phy_lock);
1301                 }
1302
1303                 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1304                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1305                         BMCR_ANENABLE);
1306                 /* Speed up link-up time when the link partner
1307                  * does not autonegotiate which is very common
1308                  * in blade servers. Some blade servers use
1309                  * IPMI for kerboard input and it's important
1310                  * to minimize link disruptions. Autoneg. involves
1311                  * exchanging base pages plus 3 next pages and
1312                  * normally completes in about 120 msec.
1313                  */
1314                 bp->current_interval = SERDES_AN_TIMEOUT;
1315                 bp->serdes_an_pending = 1;
1316                 mod_timer(&bp->timer, jiffies + bp->current_interval);
1317         } else {
1318                 bnx2_resolve_flow_ctrl(bp);
1319                 bnx2_set_mac_link(bp);
1320         }
1321
1322         return 0;
1323 }
1324
1325 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1326         (ADVERTISED_1000baseT_Full)
1327
1328 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1329         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1330         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1331         ADVERTISED_1000baseT_Full)
1332
1333 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1334         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1335
1336 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1337
1338 static int
1339 bnx2_setup_copper_phy(struct bnx2 *bp)
1340 {
1341         u32 bmcr;
1342         u32 new_bmcr;
1343
1344         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1345
1346         if (bp->autoneg & AUTONEG_SPEED) {
1347                 u32 adv_reg, adv1000_reg;
1348                 u32 new_adv_reg = 0;
1349                 u32 new_adv1000_reg = 0;
1350
1351                 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1352                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1353                         ADVERTISE_PAUSE_ASYM);
1354
1355                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1356                 adv1000_reg &= PHY_ALL_1000_SPEED;
1357
1358                 if (bp->advertising & ADVERTISED_10baseT_Half)
1359                         new_adv_reg |= ADVERTISE_10HALF;
1360                 if (bp->advertising & ADVERTISED_10baseT_Full)
1361                         new_adv_reg |= ADVERTISE_10FULL;
1362                 if (bp->advertising & ADVERTISED_100baseT_Half)
1363                         new_adv_reg |= ADVERTISE_100HALF;
1364                 if (bp->advertising & ADVERTISED_100baseT_Full)
1365                         new_adv_reg |= ADVERTISE_100FULL;
1366                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1367                         new_adv1000_reg |= ADVERTISE_1000FULL;
1368
1369                 new_adv_reg |= ADVERTISE_CSMA;
1370
1371                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1372
1373                 if ((adv1000_reg != new_adv1000_reg) ||
1374                         (adv_reg != new_adv_reg) ||
1375                         ((bmcr & BMCR_ANENABLE) == 0)) {
1376
1377                         bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1378                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1379                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1380                                 BMCR_ANENABLE);
1381                 }
1382                 else if (bp->link_up) {
1383                         /* Flow ctrl may have changed from auto to forced */
1384                         /* or vice-versa. */
1385
1386                         bnx2_resolve_flow_ctrl(bp);
1387                         bnx2_set_mac_link(bp);
1388                 }
1389                 return 0;
1390         }
1391
1392         new_bmcr = 0;
1393         if (bp->req_line_speed == SPEED_100) {
1394                 new_bmcr |= BMCR_SPEED100;
1395         }
1396         if (bp->req_duplex == DUPLEX_FULL) {
1397                 new_bmcr |= BMCR_FULLDPLX;
1398         }
1399         if (new_bmcr != bmcr) {
1400                 u32 bmsr;
1401
1402                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1403                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1404
1405                 if (bmsr & BMSR_LSTATUS) {
1406                         /* Force link down */
1407                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1408                         spin_unlock_bh(&bp->phy_lock);
1409                         msleep(50);
1410                         spin_lock_bh(&bp->phy_lock);
1411
1412                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1413                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1414                 }
1415
1416                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1417
1418                 /* Normally, the new speed is setup after the link has
1419                  * gone down and up again. In some cases, link will not go
1420                  * down so we need to set up the new speed here.
1421                  */
1422                 if (bmsr & BMSR_LSTATUS) {
1423                         bp->line_speed = bp->req_line_speed;
1424                         bp->duplex = bp->req_duplex;
1425                         bnx2_resolve_flow_ctrl(bp);
1426                         bnx2_set_mac_link(bp);
1427                 }
1428         } else {
1429                 bnx2_resolve_flow_ctrl(bp);
1430                 bnx2_set_mac_link(bp);
1431         }
1432         return 0;
1433 }
1434
1435 static int
1436 bnx2_setup_phy(struct bnx2 *bp)
1437 {
1438         if (bp->loopback == MAC_LOOPBACK)
1439                 return 0;
1440
1441         if (bp->phy_flags & PHY_SERDES_FLAG) {
1442                 return (bnx2_setup_serdes_phy(bp));
1443         }
1444         else {
1445                 return (bnx2_setup_copper_phy(bp));
1446         }
1447 }
1448
1449 static int
1450 bnx2_init_5709s_phy(struct bnx2 *bp)
1451 {
1452         u32 val;
1453
1454         bp->mii_bmcr = MII_BMCR + 0x10;
1455         bp->mii_bmsr = MII_BMSR + 0x10;
1456         bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1457         bp->mii_adv = MII_ADVERTISE + 0x10;
1458         bp->mii_lpa = MII_LPA + 0x10;
1459         bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1460
1461         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1462         bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1463
1464         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1465         bnx2_reset_phy(bp);
1466
1467         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1468
1469         bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1470         val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1471         val |= MII_BNX2_SD_1000XCTL1_FIBER;
1472         bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1473
1474         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1475         bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
1476         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
1477                 val |= BCM5708S_UP1_2G5;
1478         else
1479                 val &= ~BCM5708S_UP1_2G5;
1480         bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1481
1482         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1483         bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1484         val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1485         bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1486
1487         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1488
1489         val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1490               MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1491         bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1492
1493         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1494
1495         return 0;
1496 }
1497
1498 static int
1499 bnx2_init_5708s_phy(struct bnx2 *bp)
1500 {
1501         u32 val;
1502
1503         bnx2_reset_phy(bp);
1504
1505         bp->mii_up1 = BCM5708S_UP1;
1506
1507         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1508         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1509         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1510
1511         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1512         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1513         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1514
1515         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1516         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1517         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1518
1519         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1520                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1521                 val |= BCM5708S_UP1_2G5;
1522                 bnx2_write_phy(bp, BCM5708S_UP1, val);
1523         }
1524
1525         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1526             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1527             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1528                 /* increase tx signal amplitude */
1529                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1530                                BCM5708S_BLK_ADDR_TX_MISC);
1531                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1532                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1533                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1534                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1535         }
1536
1537         val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1538               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1539
1540         if (val) {
1541                 u32 is_backplane;
1542
1543                 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1544                                           BNX2_SHARED_HW_CFG_CONFIG);
1545                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1546                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1547                                        BCM5708S_BLK_ADDR_TX_MISC);
1548                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1549                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1550                                        BCM5708S_BLK_ADDR_DIG);
1551                 }
1552         }
1553         return 0;
1554 }
1555
1556 static int
1557 bnx2_init_5706s_phy(struct bnx2 *bp)
1558 {
1559         bnx2_reset_phy(bp);
1560
1561         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1562
1563         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1564                 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
1565
1566         if (bp->dev->mtu > 1500) {
1567                 u32 val;
1568
1569                 /* Set extended packet length bit */
1570                 bnx2_write_phy(bp, 0x18, 0x7);
1571                 bnx2_read_phy(bp, 0x18, &val);
1572                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1573
1574                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1575                 bnx2_read_phy(bp, 0x1c, &val);
1576                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1577         }
1578         else {
1579                 u32 val;
1580
1581                 bnx2_write_phy(bp, 0x18, 0x7);
1582                 bnx2_read_phy(bp, 0x18, &val);
1583                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1584
1585                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1586                 bnx2_read_phy(bp, 0x1c, &val);
1587                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1588         }
1589
1590         return 0;
1591 }
1592
1593 static int
1594 bnx2_init_copper_phy(struct bnx2 *bp)
1595 {
1596         u32 val;
1597
1598         bnx2_reset_phy(bp);
1599
1600         if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1601                 bnx2_write_phy(bp, 0x18, 0x0c00);
1602                 bnx2_write_phy(bp, 0x17, 0x000a);
1603                 bnx2_write_phy(bp, 0x15, 0x310b);
1604                 bnx2_write_phy(bp, 0x17, 0x201f);
1605                 bnx2_write_phy(bp, 0x15, 0x9506);
1606                 bnx2_write_phy(bp, 0x17, 0x401f);
1607                 bnx2_write_phy(bp, 0x15, 0x14e2);
1608                 bnx2_write_phy(bp, 0x18, 0x0400);
1609         }
1610
1611         if (bp->phy_flags & PHY_DIS_EARLY_DAC_FLAG) {
1612                 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
1613                                MII_BNX2_DSP_EXPAND_REG | 0x8);
1614                 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1615                 val &= ~(1 << 8);
1616                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
1617         }
1618
1619         if (bp->dev->mtu > 1500) {
1620                 /* Set extended packet length bit */
1621                 bnx2_write_phy(bp, 0x18, 0x7);
1622                 bnx2_read_phy(bp, 0x18, &val);
1623                 bnx2_write_phy(bp, 0x18, val | 0x4000);
1624
1625                 bnx2_read_phy(bp, 0x10, &val);
1626                 bnx2_write_phy(bp, 0x10, val | 0x1);
1627         }
1628         else {
1629                 bnx2_write_phy(bp, 0x18, 0x7);
1630                 bnx2_read_phy(bp, 0x18, &val);
1631                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1632
1633                 bnx2_read_phy(bp, 0x10, &val);
1634                 bnx2_write_phy(bp, 0x10, val & ~0x1);
1635         }
1636
1637         /* ethernet@wirespeed */
1638         bnx2_write_phy(bp, 0x18, 0x7007);
1639         bnx2_read_phy(bp, 0x18, &val);
1640         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1641         return 0;
1642 }
1643
1644
1645 static int
1646 bnx2_init_phy(struct bnx2 *bp)
1647 {
1648         u32 val;
1649         int rc = 0;
1650
1651         bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1652         bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1653
1654         bp->mii_bmcr = MII_BMCR;
1655         bp->mii_bmsr = MII_BMSR;
1656         bp->mii_bmsr1 = MII_BMSR;
1657         bp->mii_adv = MII_ADVERTISE;
1658         bp->mii_lpa = MII_LPA;
1659
1660         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1661
1662         bnx2_read_phy(bp, MII_PHYSID1, &val);
1663         bp->phy_id = val << 16;
1664         bnx2_read_phy(bp, MII_PHYSID2, &val);
1665         bp->phy_id |= val & 0xffff;
1666
1667         if (bp->phy_flags & PHY_SERDES_FLAG) {
1668                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1669                         rc = bnx2_init_5706s_phy(bp);
1670                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1671                         rc = bnx2_init_5708s_phy(bp);
1672                 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1673                         rc = bnx2_init_5709s_phy(bp);
1674         }
1675         else {
1676                 rc = bnx2_init_copper_phy(bp);
1677         }
1678
1679         bnx2_setup_phy(bp);
1680
1681         return rc;
1682 }
1683
1684 static int
1685 bnx2_set_mac_loopback(struct bnx2 *bp)
1686 {
1687         u32 mac_mode;
1688
1689         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1690         mac_mode &= ~BNX2_EMAC_MODE_PORT;
1691         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1692         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1693         bp->link_up = 1;
1694         return 0;
1695 }
1696
1697 static int bnx2_test_link(struct bnx2 *);
1698
1699 static int
1700 bnx2_set_phy_loopback(struct bnx2 *bp)
1701 {
1702         u32 mac_mode;
1703         int rc, i;
1704
1705         spin_lock_bh(&bp->phy_lock);
1706         rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
1707                             BMCR_SPEED1000);
1708         spin_unlock_bh(&bp->phy_lock);
1709         if (rc)
1710                 return rc;
1711
1712         for (i = 0; i < 10; i++) {
1713                 if (bnx2_test_link(bp) == 0)
1714                         break;
1715                 msleep(100);
1716         }
1717
1718         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1719         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1720                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1721                       BNX2_EMAC_MODE_25G_MODE);
1722
1723         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
1724         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1725         bp->link_up = 1;
1726         return 0;
1727 }
1728
1729 static int
1730 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1731 {
1732         int i;
1733         u32 val;
1734
1735         bp->fw_wr_seq++;
1736         msg_data |= bp->fw_wr_seq;
1737
1738         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1739
1740         /* wait for an acknowledgement. */
1741         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
1742                 msleep(10);
1743
1744                 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1745
1746                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1747                         break;
1748         }
1749         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1750                 return 0;
1751
1752         /* If we timed out, inform the firmware that this is the case. */
1753         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1754                 if (!silent)
1755                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
1756                                             "%x\n", msg_data);
1757
1758                 msg_data &= ~BNX2_DRV_MSG_CODE;
1759                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1760
1761                 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1762
1763                 return -EBUSY;
1764         }
1765
1766         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1767                 return -EIO;
1768
1769         return 0;
1770 }
1771
1772 static int
1773 bnx2_init_5709_context(struct bnx2 *bp)
1774 {
1775         int i, ret = 0;
1776         u32 val;
1777
1778         val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
1779         val |= (BCM_PAGE_BITS - 8) << 16;
1780         REG_WR(bp, BNX2_CTX_COMMAND, val);
1781         for (i = 0; i < 10; i++) {
1782                 val = REG_RD(bp, BNX2_CTX_COMMAND);
1783                 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
1784                         break;
1785                 udelay(2);
1786         }
1787         if (val & BNX2_CTX_COMMAND_MEM_INIT)
1788                 return -EBUSY;
1789
1790         for (i = 0; i < bp->ctx_pages; i++) {
1791                 int j;
1792
1793                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
1794                        (bp->ctx_blk_mapping[i] & 0xffffffff) |
1795                        BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
1796                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
1797                        (u64) bp->ctx_blk_mapping[i] >> 32);
1798                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
1799                        BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
1800                 for (j = 0; j < 10; j++) {
1801
1802                         val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
1803                         if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
1804                                 break;
1805                         udelay(5);
1806                 }
1807                 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
1808                         ret = -EBUSY;
1809                         break;
1810                 }
1811         }
1812         return ret;
1813 }
1814
1815 static void
1816 bnx2_init_context(struct bnx2 *bp)
1817 {
1818         u32 vcid;
1819
1820         vcid = 96;
1821         while (vcid) {
1822                 u32 vcid_addr, pcid_addr, offset;
1823                 int i;
1824
1825                 vcid--;
1826
1827                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1828                         u32 new_vcid;
1829
1830                         vcid_addr = GET_PCID_ADDR(vcid);
1831                         if (vcid & 0x8) {
1832                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1833                         }
1834                         else {
1835                                 new_vcid = vcid;
1836                         }
1837                         pcid_addr = GET_PCID_ADDR(new_vcid);
1838                 }
1839                 else {
1840                         vcid_addr = GET_CID_ADDR(vcid);
1841                         pcid_addr = vcid_addr;
1842                 }
1843
1844                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
1845                         vcid_addr += (i << PHY_CTX_SHIFT);
1846                         pcid_addr += (i << PHY_CTX_SHIFT);
1847
1848                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1849                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1850
1851                         /* Zero out the context. */
1852                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
1853                                 CTX_WR(bp, 0x00, offset, 0);
1854
1855                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1856                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1857                 }
1858         }
1859 }
1860
1861 static int
1862 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1863 {
1864         u16 *good_mbuf;
1865         u32 good_mbuf_cnt;
1866         u32 val;
1867
1868         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1869         if (good_mbuf == NULL) {
1870                 printk(KERN_ERR PFX "Failed to allocate memory in "
1871                                     "bnx2_alloc_bad_rbuf\n");
1872                 return -ENOMEM;
1873         }
1874
1875         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1876                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1877
1878         good_mbuf_cnt = 0;
1879
1880         /* Allocate a bunch of mbufs and save the good ones in an array. */
1881         val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1882         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1883                 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1884
1885                 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1886
1887                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1888
1889                 /* The addresses with Bit 9 set are bad memory blocks. */
1890                 if (!(val & (1 << 9))) {
1891                         good_mbuf[good_mbuf_cnt] = (u16) val;
1892                         good_mbuf_cnt++;
1893                 }
1894
1895                 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1896         }
1897
1898         /* Free the good ones back to the mbuf pool thus discarding
1899          * all the bad ones. */
1900         while (good_mbuf_cnt) {
1901                 good_mbuf_cnt--;
1902
1903                 val = good_mbuf[good_mbuf_cnt];
1904                 val = (val << 9) | val | 1;
1905
1906                 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1907         }
1908         kfree(good_mbuf);
1909         return 0;
1910 }
1911
1912 static void
1913 bnx2_set_mac_addr(struct bnx2 *bp)
1914 {
1915         u32 val;
1916         u8 *mac_addr = bp->dev->dev_addr;
1917
1918         val = (mac_addr[0] << 8) | mac_addr[1];
1919
1920         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1921
1922         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1923                 (mac_addr[4] << 8) | mac_addr[5];
1924
1925         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1926 }
1927
1928 static inline int
1929 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1930 {
1931         struct sk_buff *skb;
1932         struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1933         dma_addr_t mapping;
1934         struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
1935         unsigned long align;
1936
1937         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1938         if (skb == NULL) {
1939                 return -ENOMEM;
1940         }
1941
1942         if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
1943                 skb_reserve(skb, BNX2_RX_ALIGN - align);
1944
1945         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1946                 PCI_DMA_FROMDEVICE);
1947
1948         rx_buf->skb = skb;
1949         pci_unmap_addr_set(rx_buf, mapping, mapping);
1950
1951         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1952         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1953
1954         bp->rx_prod_bseq += bp->rx_buf_use_size;
1955
1956         return 0;
1957 }
1958
1959 static int
1960 bnx2_phy_event_is_set(struct bnx2 *bp, u32 event)
1961 {
1962         struct status_block *sblk = bp->status_blk;
1963         u32 new_link_state, old_link_state;
1964         int is_set = 1;
1965
1966         new_link_state = sblk->status_attn_bits & event;
1967         old_link_state = sblk->status_attn_bits_ack & event;
1968         if (new_link_state != old_link_state) {
1969                 if (new_link_state)
1970                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
1971                 else
1972                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
1973         } else
1974                 is_set = 0;
1975
1976         return is_set;
1977 }
1978
1979 static void
1980 bnx2_phy_int(struct bnx2 *bp)
1981 {
1982         if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_LINK_STATE)) {
1983                 spin_lock(&bp->phy_lock);
1984                 bnx2_set_link(bp);
1985                 spin_unlock(&bp->phy_lock);
1986         }
1987 }
1988
1989 static void
1990 bnx2_tx_int(struct bnx2 *bp)
1991 {
1992         struct status_block *sblk = bp->status_blk;
1993         u16 hw_cons, sw_cons, sw_ring_cons;
1994         int tx_free_bd = 0;
1995
1996         hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
1997         if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1998                 hw_cons++;
1999         }
2000         sw_cons = bp->tx_cons;
2001
2002         while (sw_cons != hw_cons) {
2003                 struct sw_bd *tx_buf;
2004                 struct sk_buff *skb;
2005                 int i, last;
2006
2007                 sw_ring_cons = TX_RING_IDX(sw_cons);
2008
2009                 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2010                 skb = tx_buf->skb;
2011
2012                 /* partial BD completions possible with TSO packets */
2013                 if (skb_is_gso(skb)) {
2014                         u16 last_idx, last_ring_idx;
2015
2016                         last_idx = sw_cons +
2017                                 skb_shinfo(skb)->nr_frags + 1;
2018                         last_ring_idx = sw_ring_cons +
2019                                 skb_shinfo(skb)->nr_frags + 1;
2020                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2021                                 last_idx++;
2022                         }
2023                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2024                                 break;
2025                         }
2026                 }
2027
2028                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2029                         skb_headlen(skb), PCI_DMA_TODEVICE);
2030
2031                 tx_buf->skb = NULL;
2032                 last = skb_shinfo(skb)->nr_frags;
2033
2034                 for (i = 0; i < last; i++) {
2035                         sw_cons = NEXT_TX_BD(sw_cons);
2036
2037                         pci_unmap_page(bp->pdev,
2038                                 pci_unmap_addr(
2039                                         &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2040                                         mapping),
2041                                 skb_shinfo(skb)->frags[i].size,
2042                                 PCI_DMA_TODEVICE);
2043                 }
2044
2045                 sw_cons = NEXT_TX_BD(sw_cons);
2046
2047                 tx_free_bd += last + 1;
2048
2049                 dev_kfree_skb(skb);
2050
2051                 hw_cons = bp->hw_tx_cons =
2052                         sblk->status_tx_quick_consumer_index0;
2053
2054                 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2055                         hw_cons++;
2056                 }
2057         }
2058
2059         bp->tx_cons = sw_cons;
2060         /* Need to make the tx_cons update visible to bnx2_start_xmit()
2061          * before checking for netif_queue_stopped().  Without the
2062          * memory barrier, there is a small possibility that bnx2_start_xmit()
2063          * will miss it and cause the queue to be stopped forever.
2064          */
2065         smp_mb();
2066
2067         if (unlikely(netif_queue_stopped(bp->dev)) &&
2068                      (bnx2_tx_avail(bp) > bp->tx_wake_thresh)) {
2069                 netif_tx_lock(bp->dev);
2070                 if ((netif_queue_stopped(bp->dev)) &&
2071                     (bnx2_tx_avail(bp) > bp->tx_wake_thresh))
2072                         netif_wake_queue(bp->dev);
2073                 netif_tx_unlock(bp->dev);
2074         }
2075 }
2076
2077 static inline void
2078 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
2079         u16 cons, u16 prod)
2080 {
2081         struct sw_bd *cons_rx_buf, *prod_rx_buf;
2082         struct rx_bd *cons_bd, *prod_bd;
2083
2084         cons_rx_buf = &bp->rx_buf_ring[cons];
2085         prod_rx_buf = &bp->rx_buf_ring[prod];
2086
2087         pci_dma_sync_single_for_device(bp->pdev,
2088                 pci_unmap_addr(cons_rx_buf, mapping),
2089                 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2090
2091         bp->rx_prod_bseq += bp->rx_buf_use_size;
2092
2093         prod_rx_buf->skb = skb;
2094
2095         if (cons == prod)
2096                 return;
2097
2098         pci_unmap_addr_set(prod_rx_buf, mapping,
2099                         pci_unmap_addr(cons_rx_buf, mapping));
2100
2101         cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2102         prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2103         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2104         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2105 }
2106
2107 static int
2108 bnx2_rx_int(struct bnx2 *bp, int budget)
2109 {
2110         struct status_block *sblk = bp->status_blk;
2111         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2112         struct l2_fhdr *rx_hdr;
2113         int rx_pkt = 0;
2114
2115         hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
2116         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
2117                 hw_cons++;
2118         }
2119         sw_cons = bp->rx_cons;
2120         sw_prod = bp->rx_prod;
2121
2122         /* Memory barrier necessary as speculative reads of the rx
2123          * buffer can be ahead of the index in the status block
2124          */
2125         rmb();
2126         while (sw_cons != hw_cons) {
2127                 unsigned int len;
2128                 u32 status;
2129                 struct sw_bd *rx_buf;
2130                 struct sk_buff *skb;
2131                 dma_addr_t dma_addr;
2132
2133                 sw_ring_cons = RX_RING_IDX(sw_cons);
2134                 sw_ring_prod = RX_RING_IDX(sw_prod);
2135
2136                 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2137                 skb = rx_buf->skb;
2138
2139                 rx_buf->skb = NULL;
2140
2141                 dma_addr = pci_unmap_addr(rx_buf, mapping);
2142
2143                 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2144                         bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2145
2146                 rx_hdr = (struct l2_fhdr *) skb->data;
2147                 len = rx_hdr->l2_fhdr_pkt_len - 4;
2148
2149                 if ((status = rx_hdr->l2_fhdr_status) &
2150                         (L2_FHDR_ERRORS_BAD_CRC |
2151                         L2_FHDR_ERRORS_PHY_DECODE |
2152                         L2_FHDR_ERRORS_ALIGNMENT |
2153                         L2_FHDR_ERRORS_TOO_SHORT |
2154                         L2_FHDR_ERRORS_GIANT_FRAME)) {
2155
2156                         goto reuse_rx;
2157                 }
2158
2159                 /* Since we don't have a jumbo ring, copy small packets
2160                  * if mtu > 1500
2161                  */
2162                 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
2163                         struct sk_buff *new_skb;
2164
2165                         new_skb = netdev_alloc_skb(bp->dev, len + 2);
2166                         if (new_skb == NULL)
2167                                 goto reuse_rx;
2168
2169                         /* aligned copy */
2170                         skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2,
2171                                       new_skb->data, len + 2);
2172                         skb_reserve(new_skb, 2);
2173                         skb_put(new_skb, len);
2174
2175                         bnx2_reuse_rx_skb(bp, skb,
2176                                 sw_ring_cons, sw_ring_prod);
2177
2178                         skb = new_skb;
2179                 }
2180                 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
2181                         pci_unmap_single(bp->pdev, dma_addr,
2182                                 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
2183
2184                         skb_reserve(skb, bp->rx_offset);
2185                         skb_put(skb, len);
2186                 }
2187                 else {
2188 reuse_rx:
2189                         bnx2_reuse_rx_skb(bp, skb,
2190                                 sw_ring_cons, sw_ring_prod);
2191                         goto next_rx;
2192                 }
2193
2194                 skb->protocol = eth_type_trans(skb, bp->dev);
2195
2196                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2197                         (ntohs(skb->protocol) != 0x8100)) {
2198
2199                         dev_kfree_skb(skb);
2200                         goto next_rx;
2201
2202                 }
2203
2204                 skb->ip_summed = CHECKSUM_NONE;
2205                 if (bp->rx_csum &&
2206                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2207                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
2208
2209                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2210                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2211                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2212                 }
2213
2214 #ifdef BCM_VLAN
2215                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
2216                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2217                                 rx_hdr->l2_fhdr_vlan_tag);
2218                 }
2219                 else
2220 #endif
2221                         netif_receive_skb(skb);
2222
2223                 bp->dev->last_rx = jiffies;
2224                 rx_pkt++;
2225
2226 next_rx:
2227                 sw_cons = NEXT_RX_BD(sw_cons);
2228                 sw_prod = NEXT_RX_BD(sw_prod);
2229
2230                 if ((rx_pkt == budget))
2231                         break;
2232
2233                 /* Refresh hw_cons to see if there is new work */
2234                 if (sw_cons == hw_cons) {
2235                         hw_cons = bp->hw_rx_cons =
2236                                 sblk->status_rx_quick_consumer_index0;
2237                         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
2238                                 hw_cons++;
2239                         rmb();
2240                 }
2241         }
2242         bp->rx_cons = sw_cons;
2243         bp->rx_prod = sw_prod;
2244
2245         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2246
2247         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2248
2249         mmiowb();
2250
2251         return rx_pkt;
2252
2253 }
2254
2255 /* MSI ISR - The only difference between this and the INTx ISR
2256  * is that the MSI interrupt is always serviced.
2257  */
2258 static irqreturn_t
2259 bnx2_msi(int irq, void *dev_instance)
2260 {
2261         struct net_device *dev = dev_instance;
2262         struct bnx2 *bp = netdev_priv(dev);
2263
2264         prefetch(bp->status_blk);
2265         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2266                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2267                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2268
2269         /* Return here if interrupt is disabled. */
2270         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2271                 return IRQ_HANDLED;
2272
2273         netif_rx_schedule(dev);
2274
2275         return IRQ_HANDLED;
2276 }
2277
2278 static irqreturn_t
2279 bnx2_msi_1shot(int irq, void *dev_instance)
2280 {
2281         struct net_device *dev = dev_instance;
2282         struct bnx2 *bp = netdev_priv(dev);
2283
2284         prefetch(bp->status_blk);
2285
2286         /* Return here if interrupt is disabled. */
2287         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2288                 return IRQ_HANDLED;
2289
2290         netif_rx_schedule(dev);
2291
2292         return IRQ_HANDLED;
2293 }
2294
2295 static irqreturn_t
2296 bnx2_interrupt(int irq, void *dev_instance)
2297 {
2298         struct net_device *dev = dev_instance;
2299         struct bnx2 *bp = netdev_priv(dev);
2300
2301         /* When using INTx, it is possible for the interrupt to arrive
2302          * at the CPU before the status block posted prior to the
2303          * interrupt. Reading a register will flush the status block.
2304          * When using MSI, the MSI message will always complete after
2305          * the status block write.
2306          */
2307         if ((bp->status_blk->status_idx == bp->last_status_idx) &&
2308             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2309              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
2310                 return IRQ_NONE;
2311
2312         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2313                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2314                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2315
2316         /* Return here if interrupt is shared and is disabled. */
2317         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2318                 return IRQ_HANDLED;
2319
2320         netif_rx_schedule(dev);
2321
2322         return IRQ_HANDLED;
2323 }
2324
2325 #define STATUS_ATTN_EVENTS      STATUS_ATTN_BITS_LINK_STATE
2326
2327 static inline int
2328 bnx2_has_work(struct bnx2 *bp)
2329 {
2330         struct status_block *sblk = bp->status_blk;
2331
2332         if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
2333             (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
2334                 return 1;
2335
2336         if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
2337             (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
2338                 return 1;
2339
2340         return 0;
2341 }
2342
2343 static int
2344 bnx2_poll(struct net_device *dev, int *budget)
2345 {
2346         struct bnx2 *bp = netdev_priv(dev);
2347         struct status_block *sblk = bp->status_blk;
2348         u32 status_attn_bits = sblk->status_attn_bits;
2349         u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
2350
2351         if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
2352             (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
2353
2354                 bnx2_phy_int(bp);
2355
2356                 /* This is needed to take care of transient status
2357                  * during link changes.
2358                  */
2359                 REG_WR(bp, BNX2_HC_COMMAND,
2360                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2361                 REG_RD(bp, BNX2_HC_COMMAND);
2362         }
2363
2364         if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
2365                 bnx2_tx_int(bp);
2366
2367         if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
2368                 int orig_budget = *budget;
2369                 int work_done;
2370
2371                 if (orig_budget > dev->quota)
2372                         orig_budget = dev->quota;
2373
2374                 work_done = bnx2_rx_int(bp, orig_budget);
2375                 *budget -= work_done;
2376                 dev->quota -= work_done;
2377         }
2378
2379         bp->last_status_idx = bp->status_blk->status_idx;
2380         rmb();
2381
2382         if (!bnx2_has_work(bp)) {
2383                 netif_rx_complete(dev);
2384                 if (likely(bp->flags & USING_MSI_FLAG)) {
2385                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2386                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2387                                bp->last_status_idx);
2388                         return 0;
2389                 }
2390                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2391                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2392                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2393                        bp->last_status_idx);
2394
2395                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2396                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2397                        bp->last_status_idx);
2398                 return 0;
2399         }
2400
2401         return 1;
2402 }
2403
2404 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
2405  * from set_multicast.
2406  */
2407 static void
2408 bnx2_set_rx_mode(struct net_device *dev)
2409 {
2410         struct bnx2 *bp = netdev_priv(dev);
2411         u32 rx_mode, sort_mode;
2412         int i;
2413
2414         spin_lock_bh(&bp->phy_lock);
2415
2416         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
2417                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
2418         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
2419 #ifdef BCM_VLAN
2420         if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
2421                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2422 #else
2423         if (!(bp->flags & ASF_ENABLE_FLAG))
2424                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2425 #endif
2426         if (dev->flags & IFF_PROMISC) {
2427                 /* Promiscuous mode. */
2428                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
2429                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
2430                              BNX2_RPM_SORT_USER0_PROM_VLAN;
2431         }
2432         else if (dev->flags & IFF_ALLMULTI) {
2433                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2434                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2435                                0xffffffff);
2436                 }
2437                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
2438         }
2439         else {
2440                 /* Accept one or more multicast(s). */
2441                 struct dev_mc_list *mclist;
2442                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
2443                 u32 regidx;
2444                 u32 bit;
2445                 u32 crc;
2446
2447                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
2448
2449                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2450                      i++, mclist = mclist->next) {
2451
2452                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
2453                         bit = crc & 0xff;
2454                         regidx = (bit & 0xe0) >> 5;
2455                         bit &= 0x1f;
2456                         mc_filter[regidx] |= (1 << bit);
2457                 }
2458
2459                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2460                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2461                                mc_filter[i]);
2462                 }
2463
2464                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
2465         }
2466
2467         if (rx_mode != bp->rx_mode) {
2468                 bp->rx_mode = rx_mode;
2469                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
2470         }
2471
2472         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2473         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
2474         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
2475
2476         spin_unlock_bh(&bp->phy_lock);
2477 }
2478
2479 #define FW_BUF_SIZE     0x8000
2480
2481 static int
2482 bnx2_gunzip_init(struct bnx2 *bp)
2483 {
2484         if ((bp->gunzip_buf = vmalloc(FW_BUF_SIZE)) == NULL)
2485                 goto gunzip_nomem1;
2486
2487         if ((bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL)) == NULL)
2488                 goto gunzip_nomem2;
2489
2490         bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(), GFP_KERNEL);
2491         if (bp->strm->workspace == NULL)
2492                 goto gunzip_nomem3;
2493
2494         return 0;
2495
2496 gunzip_nomem3:
2497         kfree(bp->strm);
2498         bp->strm = NULL;
2499
2500 gunzip_nomem2:
2501         vfree(bp->gunzip_buf);
2502         bp->gunzip_buf = NULL;
2503
2504 gunzip_nomem1:
2505         printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for "
2506                             "uncompression.\n", bp->dev->name);
2507         return -ENOMEM;
2508 }
2509
2510 static void
2511 bnx2_gunzip_end(struct bnx2 *bp)
2512 {
2513         kfree(bp->strm->workspace);
2514
2515         kfree(bp->strm);
2516         bp->strm = NULL;
2517
2518         if (bp->gunzip_buf) {
2519                 vfree(bp->gunzip_buf);
2520                 bp->gunzip_buf = NULL;
2521         }
2522 }
2523
2524 static int
2525 bnx2_gunzip(struct bnx2 *bp, u8 *zbuf, int len, void **outbuf, int *outlen)
2526 {
2527         int n, rc;
2528
2529         /* check gzip header */
2530         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
2531                 return -EINVAL;
2532
2533         n = 10;
2534
2535 #define FNAME   0x8
2536         if (zbuf[3] & FNAME)
2537                 while ((zbuf[n++] != 0) && (n < len));
2538
2539         bp->strm->next_in = zbuf + n;
2540         bp->strm->avail_in = len - n;
2541         bp->strm->next_out = bp->gunzip_buf;
2542         bp->strm->avail_out = FW_BUF_SIZE;
2543
2544         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
2545         if (rc != Z_OK)
2546                 return rc;
2547
2548         rc = zlib_inflate(bp->strm, Z_FINISH);
2549
2550         *outlen = FW_BUF_SIZE - bp->strm->avail_out;
2551         *outbuf = bp->gunzip_buf;
2552
2553         if ((rc != Z_OK) && (rc != Z_STREAM_END))
2554                 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
2555                        bp->dev->name, bp->strm->msg);
2556
2557         zlib_inflateEnd(bp->strm);
2558
2559         if (rc == Z_STREAM_END)
2560                 return 0;
2561
2562         return rc;
2563 }
2564
2565 static void
2566 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
2567         u32 rv2p_proc)
2568 {
2569         int i;
2570         u32 val;
2571
2572
2573         for (i = 0; i < rv2p_code_len; i += 8) {
2574                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
2575                 rv2p_code++;
2576                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
2577                 rv2p_code++;
2578
2579                 if (rv2p_proc == RV2P_PROC1) {
2580                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2581                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2582                 }
2583                 else {
2584                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2585                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2586                 }
2587         }
2588
2589         /* Reset the processor, un-stall is done later. */
2590         if (rv2p_proc == RV2P_PROC1) {
2591                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2592         }
2593         else {
2594                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2595         }
2596 }
2597
2598 static int
2599 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2600 {
2601         u32 offset;
2602         u32 val;
2603         int rc;
2604
2605         /* Halt the CPU. */
2606         val = REG_RD_IND(bp, cpu_reg->mode);
2607         val |= cpu_reg->mode_value_halt;
2608         REG_WR_IND(bp, cpu_reg->mode, val);
2609         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2610
2611         /* Load the Text area. */
2612         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2613         if (fw->gz_text) {
2614                 u32 text_len;
2615                 void *text;
2616
2617                 rc = bnx2_gunzip(bp, fw->gz_text, fw->gz_text_len, &text,
2618                                  &text_len);
2619                 if (rc)
2620                         return rc;
2621
2622                 fw->text = text;
2623         }
2624         if (fw->gz_text) {
2625                 int j;
2626
2627                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2628                         REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
2629                 }
2630         }
2631
2632         /* Load the Data area. */
2633         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2634         if (fw->data) {
2635                 int j;
2636
2637                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2638                         REG_WR_IND(bp, offset, fw->data[j]);
2639                 }
2640         }
2641
2642         /* Load the SBSS area. */
2643         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2644         if (fw->sbss) {
2645                 int j;
2646
2647                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2648                         REG_WR_IND(bp, offset, fw->sbss[j]);
2649                 }
2650         }
2651
2652         /* Load the BSS area. */
2653         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2654         if (fw->bss) {
2655                 int j;
2656
2657                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2658                         REG_WR_IND(bp, offset, fw->bss[j]);
2659                 }
2660         }
2661
2662         /* Load the Read-Only area. */
2663         offset = cpu_reg->spad_base +
2664                 (fw->rodata_addr - cpu_reg->mips_view_base);
2665         if (fw->rodata) {
2666                 int j;
2667
2668                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2669                         REG_WR_IND(bp, offset, fw->rodata[j]);
2670                 }
2671         }
2672
2673         /* Clear the pre-fetch instruction. */
2674         REG_WR_IND(bp, cpu_reg->inst, 0);
2675         REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2676
2677         /* Start the CPU. */
2678         val = REG_RD_IND(bp, cpu_reg->mode);
2679         val &= ~cpu_reg->mode_value_halt;
2680         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2681         REG_WR_IND(bp, cpu_reg->mode, val);
2682
2683         return 0;
2684 }
2685
2686 static int
2687 bnx2_init_cpus(struct bnx2 *bp)
2688 {
2689         struct cpu_reg cpu_reg;
2690         struct fw_info *fw;
2691         int rc = 0;
2692         void *text;
2693         u32 text_len;
2694
2695         if ((rc = bnx2_gunzip_init(bp)) != 0)
2696                 return rc;
2697
2698         /* Initialize the RV2P processor. */
2699         rc = bnx2_gunzip(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), &text,
2700                          &text_len);
2701         if (rc)
2702                 goto init_cpu_err;
2703
2704         load_rv2p_fw(bp, text, text_len, RV2P_PROC1);
2705
2706         rc = bnx2_gunzip(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), &text,
2707                          &text_len);
2708         if (rc)
2709                 goto init_cpu_err;
2710
2711         load_rv2p_fw(bp, text, text_len, RV2P_PROC2);
2712
2713         /* Initialize the RX Processor. */
2714         cpu_reg.mode = BNX2_RXP_CPU_MODE;
2715         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2716         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2717         cpu_reg.state = BNX2_RXP_CPU_STATE;
2718         cpu_reg.state_value_clear = 0xffffff;
2719         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2720         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2721         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2722         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2723         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2724         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2725         cpu_reg.mips_view_base = 0x8000000;
2726
2727         if (CHIP_NUM(bp) == CHIP_NUM_5709)
2728                 fw = &bnx2_rxp_fw_09;
2729         else
2730                 fw = &bnx2_rxp_fw_06;
2731
2732         rc = load_cpu_fw(bp, &cpu_reg, fw);
2733         if (rc)
2734                 goto init_cpu_err;
2735
2736         /* Initialize the TX Processor. */
2737         cpu_reg.mode = BNX2_TXP_CPU_MODE;
2738         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2739         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2740         cpu_reg.state = BNX2_TXP_CPU_STATE;
2741         cpu_reg.state_value_clear = 0xffffff;
2742         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2743         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2744         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2745         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2746         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2747         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2748         cpu_reg.mips_view_base = 0x8000000;
2749
2750         if (CHIP_NUM(bp) == CHIP_NUM_5709)
2751                 fw = &bnx2_txp_fw_09;
2752         else
2753                 fw = &bnx2_txp_fw_06;
2754
2755         rc = load_cpu_fw(bp, &cpu_reg, fw);
2756         if (rc)
2757                 goto init_cpu_err;
2758
2759         /* Initialize the TX Patch-up Processor. */
2760         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2761         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2762         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2763         cpu_reg.state = BNX2_TPAT_CPU_STATE;
2764         cpu_reg.state_value_clear = 0xffffff;
2765         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2766         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2767         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2768         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2769         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2770         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2771         cpu_reg.mips_view_base = 0x8000000;
2772
2773         if (CHIP_NUM(bp) == CHIP_NUM_5709)
2774                 fw = &bnx2_tpat_fw_09;
2775         else
2776                 fw = &bnx2_tpat_fw_06;
2777
2778         rc = load_cpu_fw(bp, &cpu_reg, fw);
2779         if (rc)
2780                 goto init_cpu_err;
2781
2782         /* Initialize the Completion Processor. */
2783         cpu_reg.mode = BNX2_COM_CPU_MODE;
2784         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2785         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2786         cpu_reg.state = BNX2_COM_CPU_STATE;
2787         cpu_reg.state_value_clear = 0xffffff;
2788         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2789         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2790         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2791         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2792         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2793         cpu_reg.spad_base = BNX2_COM_SCRATCH;
2794         cpu_reg.mips_view_base = 0x8000000;
2795
2796         if (CHIP_NUM(bp) == CHIP_NUM_5709)
2797                 fw = &bnx2_com_fw_09;
2798         else
2799                 fw = &bnx2_com_fw_06;
2800
2801         rc = load_cpu_fw(bp, &cpu_reg, fw);
2802         if (rc)
2803                 goto init_cpu_err;
2804
2805         /* Initialize the Command Processor. */
2806         cpu_reg.mode = BNX2_CP_CPU_MODE;
2807         cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
2808         cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
2809         cpu_reg.state = BNX2_CP_CPU_STATE;
2810         cpu_reg.state_value_clear = 0xffffff;
2811         cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
2812         cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
2813         cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
2814         cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
2815         cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
2816         cpu_reg.spad_base = BNX2_CP_SCRATCH;
2817         cpu_reg.mips_view_base = 0x8000000;
2818
2819         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
2820                 fw = &bnx2_cp_fw_09;
2821
2822                 rc = load_cpu_fw(bp, &cpu_reg, fw);
2823                 if (rc)
2824                         goto init_cpu_err;
2825         }
2826 init_cpu_err:
2827         bnx2_gunzip_end(bp);
2828         return rc;
2829 }
2830
2831 static int
2832 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
2833 {
2834         u16 pmcsr;
2835
2836         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2837
2838         switch (state) {
2839         case PCI_D0: {
2840                 u32 val;
2841
2842                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2843                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2844                         PCI_PM_CTRL_PME_STATUS);
2845
2846                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2847                         /* delay required during transition out of D3hot */
2848                         msleep(20);
2849
2850                 val = REG_RD(bp, BNX2_EMAC_MODE);
2851                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2852                 val &= ~BNX2_EMAC_MODE_MPKT;
2853                 REG_WR(bp, BNX2_EMAC_MODE, val);
2854
2855                 val = REG_RD(bp, BNX2_RPM_CONFIG);
2856                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2857                 REG_WR(bp, BNX2_RPM_CONFIG, val);
2858                 break;
2859         }
2860         case PCI_D3hot: {
2861                 int i;
2862                 u32 val, wol_msg;
2863
2864                 if (bp->wol) {
2865                         u32 advertising;
2866                         u8 autoneg;
2867
2868                         autoneg = bp->autoneg;
2869                         advertising = bp->advertising;
2870
2871                         bp->autoneg = AUTONEG_SPEED;
2872                         bp->advertising = ADVERTISED_10baseT_Half |
2873                                 ADVERTISED_10baseT_Full |
2874                                 ADVERTISED_100baseT_Half |
2875                                 ADVERTISED_100baseT_Full |
2876                                 ADVERTISED_Autoneg;
2877
2878                         bnx2_setup_copper_phy(bp);
2879
2880                         bp->autoneg = autoneg;
2881                         bp->advertising = advertising;
2882
2883                         bnx2_set_mac_addr(bp);
2884
2885                         val = REG_RD(bp, BNX2_EMAC_MODE);
2886
2887                         /* Enable port mode. */
2888                         val &= ~BNX2_EMAC_MODE_PORT;
2889                         val |= BNX2_EMAC_MODE_PORT_MII |
2890                                BNX2_EMAC_MODE_MPKT_RCVD |
2891                                BNX2_EMAC_MODE_ACPI_RCVD |
2892                                BNX2_EMAC_MODE_MPKT;
2893
2894                         REG_WR(bp, BNX2_EMAC_MODE, val);
2895
2896                         /* receive all multicast */
2897                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2898                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2899                                        0xffffffff);
2900                         }
2901                         REG_WR(bp, BNX2_EMAC_RX_MODE,
2902                                BNX2_EMAC_RX_MODE_SORT_MODE);
2903
2904                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2905                               BNX2_RPM_SORT_USER0_MC_EN;
2906                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2907                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2908                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2909                                BNX2_RPM_SORT_USER0_ENA);
2910
2911                         /* Need to enable EMAC and RPM for WOL. */
2912                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2913                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2914                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2915                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2916
2917                         val = REG_RD(bp, BNX2_RPM_CONFIG);
2918                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2919                         REG_WR(bp, BNX2_RPM_CONFIG, val);
2920
2921                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2922                 }
2923                 else {
2924                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2925                 }
2926
2927                 if (!(bp->flags & NO_WOL_FLAG))
2928                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
2929
2930                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2931                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2932                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2933
2934                         if (bp->wol)
2935                                 pmcsr |= 3;
2936                 }
2937                 else {
2938                         pmcsr |= 3;
2939                 }
2940                 if (bp->wol) {
2941                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2942                 }
2943                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2944                                       pmcsr);
2945
2946                 /* No more memory access after this point until
2947                  * device is brought back to D0.
2948                  */
2949                 udelay(50);
2950                 break;
2951         }
2952         default:
2953                 return -EINVAL;
2954         }
2955         return 0;
2956 }
2957
2958 static int
2959 bnx2_acquire_nvram_lock(struct bnx2 *bp)
2960 {
2961         u32 val;
2962         int j;
2963
2964         /* Request access to the flash interface. */
2965         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2966         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2967                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2968                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2969                         break;
2970
2971                 udelay(5);
2972         }
2973
2974         if (j >= NVRAM_TIMEOUT_COUNT)
2975                 return -EBUSY;
2976
2977         return 0;
2978 }
2979
2980 static int
2981 bnx2_release_nvram_lock(struct bnx2 *bp)
2982 {
2983         int j;
2984         u32 val;
2985
2986         /* Relinquish nvram interface. */
2987         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2988
2989         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2990                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2991                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2992                         break;
2993
2994                 udelay(5);
2995         }
2996
2997         if (j >= NVRAM_TIMEOUT_COUNT)
2998                 return -EBUSY;
2999
3000         return 0;
3001 }
3002
3003
3004 static int
3005 bnx2_enable_nvram_write(struct bnx2 *bp)
3006 {
3007         u32 val;
3008
3009         val = REG_RD(bp, BNX2_MISC_CFG);
3010         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3011
3012         if (!bp->flash_info->buffered) {
3013                 int j;
3014
3015                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3016                 REG_WR(bp, BNX2_NVM_COMMAND,
3017                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3018
3019                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3020                         udelay(5);
3021
3022                         val = REG_RD(bp, BNX2_NVM_COMMAND);
3023                         if (val & BNX2_NVM_COMMAND_DONE)
3024                                 break;
3025                 }
3026
3027                 if (j >= NVRAM_TIMEOUT_COUNT)
3028                         return -EBUSY;
3029         }
3030         return 0;
3031 }
3032
3033 static void
3034 bnx2_disable_nvram_write(struct bnx2 *bp)
3035 {
3036         u32 val;
3037
3038         val = REG_RD(bp, BNX2_MISC_CFG);
3039         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3040 }
3041
3042
3043 static void
3044 bnx2_enable_nvram_access(struct bnx2 *bp)
3045 {
3046         u32 val;
3047
3048         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3049         /* Enable both bits, even on read. */
3050         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3051                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3052 }
3053
3054 static void
3055 bnx2_disable_nvram_access(struct bnx2 *bp)
3056 {
3057         u32 val;
3058
3059         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3060         /* Disable both bits, even after read. */
3061         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3062                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3063                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
3064 }
3065
3066 static int
3067 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3068 {
3069         u32 cmd;
3070         int j;
3071
3072         if (bp->flash_info->buffered)
3073                 /* Buffered flash, no erase needed */
3074                 return 0;
3075
3076         /* Build an erase command */
3077         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3078               BNX2_NVM_COMMAND_DOIT;
3079
3080         /* Need to clear DONE bit separately. */
3081         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3082
3083         /* Address of the NVRAM to read from. */
3084         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3085
3086         /* Issue an erase command. */
3087         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3088
3089         /* Wait for completion. */
3090         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3091                 u32 val;
3092
3093                 udelay(5);
3094
3095                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3096                 if (val & BNX2_NVM_COMMAND_DONE)
3097                         break;
3098         }
3099
3100         if (j >= NVRAM_TIMEOUT_COUNT)
3101                 return -EBUSY;
3102
3103         return 0;
3104 }
3105
3106 static int
3107 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3108 {
3109         u32 cmd;
3110         int j;
3111
3112         /* Build the command word. */
3113         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3114
3115         /* Calculate an offset of a buffered flash. */
3116         if (bp->flash_info->buffered) {
3117                 offset = ((offset / bp->flash_info->page_size) <<
3118                            bp->flash_info->page_bits) +
3119                           (offset % bp->flash_info->page_size);
3120         }
3121
3122         /* Need to clear DONE bit separately. */
3123         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3124
3125         /* Address of the NVRAM to read from. */
3126         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3127
3128         /* Issue a read command. */
3129         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3130
3131         /* Wait for completion. */
3132         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3133                 u32 val;
3134
3135                 udelay(5);
3136
3137                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3138                 if (val & BNX2_NVM_COMMAND_DONE) {
3139                         val = REG_RD(bp, BNX2_NVM_READ);
3140
3141                         val = be32_to_cpu(val);
3142                         memcpy(ret_val, &val, 4);
3143                         break;
3144                 }
3145         }
3146         if (j >= NVRAM_TIMEOUT_COUNT)
3147                 return -EBUSY;
3148
3149         return 0;
3150 }
3151
3152
3153 static int
3154 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3155 {
3156         u32 cmd, val32;
3157         int j;
3158
3159         /* Build the command word. */
3160         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3161
3162         /* Calculate an offset of a buffered flash. */
3163         if (bp->flash_info->buffered) {
3164                 offset = ((offset / bp->flash_info->page_size) <<
3165                           bp->flash_info->page_bits) +
3166                          (offset % bp->flash_info->page_size);
3167         }
3168
3169         /* Need to clear DONE bit separately. */
3170         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3171
3172         memcpy(&val32, val, 4);
3173         val32 = cpu_to_be32(val32);
3174
3175         /* Write the data. */
3176         REG_WR(bp, BNX2_NVM_WRITE, val32);
3177
3178         /* Address of the NVRAM to write to. */
3179         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3180
3181         /* Issue the write command. */
3182         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3183
3184         /* Wait for completion. */
3185         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3186                 udelay(5);
3187
3188                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3189                         break;
3190         }
3191         if (j >= NVRAM_TIMEOUT_COUNT)
3192                 return -EBUSY;
3193
3194         return 0;
3195 }
3196
3197 static int
3198 bnx2_init_nvram(struct bnx2 *bp)
3199 {
3200         u32 val;
3201         int j, entry_count, rc;
3202         struct flash_spec *flash;
3203
3204         /* Determine the selected interface. */
3205         val = REG_RD(bp, BNX2_NVM_CFG1);
3206
3207         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
3208
3209         rc = 0;
3210         if (val & 0x40000000) {
3211
3212                 /* Flash interface has been reconfigured */
3213                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3214                      j++, flash++) {
3215                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
3216                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3217                                 bp->flash_info = flash;
3218                                 break;
3219                         }
3220                 }
3221         }
3222         else {
3223                 u32 mask;
3224                 /* Not yet been reconfigured */
3225
3226                 if (val & (1 << 23))
3227                         mask = FLASH_BACKUP_STRAP_MASK;
3228                 else
3229                         mask = FLASH_STRAP_MASK;
3230
3231                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3232                         j++, flash++) {
3233
3234                         if ((val & mask) == (flash->strapping & mask)) {
3235                                 bp->flash_info = flash;
3236
3237                                 /* Request access to the flash interface. */
3238                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3239                                         return rc;
3240
3241                                 /* Enable access to flash interface */
3242                                 bnx2_enable_nvram_access(bp);
3243
3244                                 /* Reconfigure the flash interface */
3245                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3246                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3247                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3248                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3249
3250                                 /* Disable access to flash interface */
3251                                 bnx2_disable_nvram_access(bp);
3252                                 bnx2_release_nvram_lock(bp);
3253
3254                                 break;
3255                         }
3256                 }
3257         } /* if (val & 0x40000000) */
3258
3259         if (j == entry_count) {
3260                 bp->flash_info = NULL;
3261                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
3262                 return -ENODEV;
3263         }
3264
3265         val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
3266         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3267         if (val)
3268                 bp->flash_size = val;
3269         else
3270                 bp->flash_size = bp->flash_info->total_size;
3271
3272         return rc;
3273 }
3274
3275 static int
3276 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3277                 int buf_size)
3278 {