Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6
[sfrench/cifs-2.6.git] / drivers / net / b44.c
1 /* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
2  *
3  * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4  * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
5  * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
6  * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
7  * Copyright (C) 2006 Broadcom Corporation.
8  * Copyright (C) 2007 Michael Buesch <mb@bu3sch.de>
9  *
10  * Distribute under GPL.
11  */
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/types.h>
17 #include <linux/netdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/mii.h>
20 #include <linux/if_ether.h>
21 #include <linux/if_vlan.h>
22 #include <linux/etherdevice.h>
23 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/ssb/ssb.h>
28
29 #include <asm/uaccess.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32
33
34 #include "b44.h"
35
36 #define DRV_MODULE_NAME         "b44"
37 #define PFX DRV_MODULE_NAME     ": "
38 #define DRV_MODULE_VERSION      "2.0"
39
40 #define B44_DEF_MSG_ENABLE        \
41         (NETIF_MSG_DRV          | \
42          NETIF_MSG_PROBE        | \
43          NETIF_MSG_LINK         | \
44          NETIF_MSG_TIMER        | \
45          NETIF_MSG_IFDOWN       | \
46          NETIF_MSG_IFUP         | \
47          NETIF_MSG_RX_ERR       | \
48          NETIF_MSG_TX_ERR)
49
50 /* length of time before we decide the hardware is borked,
51  * and dev->tx_timeout() should be called to fix the problem
52  */
53 #define B44_TX_TIMEOUT                  (5 * HZ)
54
55 /* hardware minimum and maximum for a single frame's data payload */
56 #define B44_MIN_MTU                     60
57 #define B44_MAX_MTU                     1500
58
59 #define B44_RX_RING_SIZE                512
60 #define B44_DEF_RX_RING_PENDING         200
61 #define B44_RX_RING_BYTES       (sizeof(struct dma_desc) * \
62                                  B44_RX_RING_SIZE)
63 #define B44_TX_RING_SIZE                512
64 #define B44_DEF_TX_RING_PENDING         (B44_TX_RING_SIZE - 1)
65 #define B44_TX_RING_BYTES       (sizeof(struct dma_desc) * \
66                                  B44_TX_RING_SIZE)
67
68 #define TX_RING_GAP(BP) \
69         (B44_TX_RING_SIZE - (BP)->tx_pending)
70 #define TX_BUFFS_AVAIL(BP)                                              \
71         (((BP)->tx_cons <= (BP)->tx_prod) ?                             \
72           (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod :            \
73           (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
74 #define NEXT_TX(N)              (((N) + 1) & (B44_TX_RING_SIZE - 1))
75
76 #define RX_PKT_OFFSET           30
77 #define RX_PKT_BUF_SZ           (1536 + RX_PKT_OFFSET + 64)
78
79 /* minimum number of free TX descriptors required to wake up TX process */
80 #define B44_TX_WAKEUP_THRESH            (B44_TX_RING_SIZE / 4)
81
82 /* b44 internal pattern match filter info */
83 #define B44_PATTERN_BASE        0x400
84 #define B44_PATTERN_SIZE        0x80
85 #define B44_PMASK_BASE          0x600
86 #define B44_PMASK_SIZE          0x10
87 #define B44_MAX_PATTERNS        16
88 #define B44_ETHIPV6UDP_HLEN     62
89 #define B44_ETHIPV4UDP_HLEN     42
90
91 static char version[] __devinitdata =
92         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION "\n";
93
94 MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
95 MODULE_DESCRIPTION("Broadcom 44xx/47xx 10/100 PCI ethernet driver");
96 MODULE_LICENSE("GPL");
97 MODULE_VERSION(DRV_MODULE_VERSION);
98
99 static int b44_debug = -1;      /* -1 == use B44_DEF_MSG_ENABLE as value */
100 module_param(b44_debug, int, 0);
101 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
102
103
104 #ifdef CONFIG_B44_PCI
105 static const struct pci_device_id b44_pci_tbl[] = {
106         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
107         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
108         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
109         { 0 } /* terminate list with empty entry */
110 };
111 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
112
113 static struct pci_driver b44_pci_driver = {
114         .name           = DRV_MODULE_NAME,
115         .id_table       = b44_pci_tbl,
116 };
117 #endif /* CONFIG_B44_PCI */
118
119 static const struct ssb_device_id b44_ssb_tbl[] = {
120         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
121         SSB_DEVTABLE_END
122 };
123 MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);
124
125 static void b44_halt(struct b44 *);
126 static void b44_init_rings(struct b44 *);
127
128 #define B44_FULL_RESET          1
129 #define B44_FULL_RESET_SKIP_PHY 2
130 #define B44_PARTIAL_RESET       3
131 #define B44_CHIP_RESET_FULL     4
132 #define B44_CHIP_RESET_PARTIAL  5
133
134 static void b44_init_hw(struct b44 *, int);
135
136 static int dma_desc_align_mask;
137 static int dma_desc_sync_size;
138 static int instance;
139
140 static const char b44_gstrings[][ETH_GSTRING_LEN] = {
141 #define _B44(x...)      # x,
142 B44_STAT_REG_DECLARE
143 #undef _B44
144 };
145
146 static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
147                                                 dma_addr_t dma_base,
148                                                 unsigned long offset,
149                                                 enum dma_data_direction dir)
150 {
151         dma_sync_single_range_for_device(sdev->dma_dev, dma_base,
152                                          offset & dma_desc_align_mask,
153                                          dma_desc_sync_size, dir);
154 }
155
156 static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
157                                              dma_addr_t dma_base,
158                                              unsigned long offset,
159                                              enum dma_data_direction dir)
160 {
161         dma_sync_single_range_for_cpu(sdev->dma_dev, dma_base,
162                                       offset & dma_desc_align_mask,
163                                       dma_desc_sync_size, dir);
164 }
165
166 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
167 {
168         return ssb_read32(bp->sdev, reg);
169 }
170
171 static inline void bw32(const struct b44 *bp,
172                         unsigned long reg, unsigned long val)
173 {
174         ssb_write32(bp->sdev, reg, val);
175 }
176
177 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
178                         u32 bit, unsigned long timeout, const int clear)
179 {
180         unsigned long i;
181
182         for (i = 0; i < timeout; i++) {
183                 u32 val = br32(bp, reg);
184
185                 if (clear && !(val & bit))
186                         break;
187                 if (!clear && (val & bit))
188                         break;
189                 udelay(10);
190         }
191         if (i == timeout) {
192                 printk(KERN_ERR PFX "%s: BUG!  Timeout waiting for bit %08x of register "
193                        "%lx to %s.\n",
194                        bp->dev->name,
195                        bit, reg,
196                        (clear ? "clear" : "set"));
197                 return -ENODEV;
198         }
199         return 0;
200 }
201
202 static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
203 {
204         u32 val;
205
206         bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
207                             (index << CAM_CTRL_INDEX_SHIFT)));
208
209         b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
210
211         val = br32(bp, B44_CAM_DATA_LO);
212
213         data[2] = (val >> 24) & 0xFF;
214         data[3] = (val >> 16) & 0xFF;
215         data[4] = (val >> 8) & 0xFF;
216         data[5] = (val >> 0) & 0xFF;
217
218         val = br32(bp, B44_CAM_DATA_HI);
219
220         data[0] = (val >> 8) & 0xFF;
221         data[1] = (val >> 0) & 0xFF;
222 }
223
224 static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
225 {
226         u32 val;
227
228         val  = ((u32) data[2]) << 24;
229         val |= ((u32) data[3]) << 16;
230         val |= ((u32) data[4]) <<  8;
231         val |= ((u32) data[5]) <<  0;
232         bw32(bp, B44_CAM_DATA_LO, val);
233         val = (CAM_DATA_HI_VALID |
234                (((u32) data[0]) << 8) |
235                (((u32) data[1]) << 0));
236         bw32(bp, B44_CAM_DATA_HI, val);
237         bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
238                             (index << CAM_CTRL_INDEX_SHIFT)));
239         b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
240 }
241
242 static inline void __b44_disable_ints(struct b44 *bp)
243 {
244         bw32(bp, B44_IMASK, 0);
245 }
246
247 static void b44_disable_ints(struct b44 *bp)
248 {
249         __b44_disable_ints(bp);
250
251         /* Flush posted writes. */
252         br32(bp, B44_IMASK);
253 }
254
255 static void b44_enable_ints(struct b44 *bp)
256 {
257         bw32(bp, B44_IMASK, bp->imask);
258 }
259
260 static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
261 {
262         int err;
263
264         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
265         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
266                              (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
267                              (phy_addr << MDIO_DATA_PMD_SHIFT) |
268                              (reg << MDIO_DATA_RA_SHIFT) |
269                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
270         err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
271         *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
272
273         return err;
274 }
275
276 static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
277 {
278         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
279         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
280                              (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
281                              (phy_addr << MDIO_DATA_PMD_SHIFT) |
282                              (reg << MDIO_DATA_RA_SHIFT) |
283                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
284                              (val & MDIO_DATA_DATA)));
285         return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
286 }
287
288 static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
289 {
290         if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
291                 return 0;
292
293         return __b44_readphy(bp, bp->phy_addr, reg, val);
294 }
295
296 static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
297 {
298         if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
299                 return 0;
300
301         return __b44_writephy(bp, bp->phy_addr, reg, val);
302 }
303
304 /* miilib interface */
305 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
306 {
307         u32 val;
308         struct b44 *bp = netdev_priv(dev);
309         int rc = __b44_readphy(bp, phy_id, location, &val);
310         if (rc)
311                 return 0xffffffff;
312         return val;
313 }
314
315 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
316                          int val)
317 {
318         struct b44 *bp = netdev_priv(dev);
319         __b44_writephy(bp, phy_id, location, val);
320 }
321
322 static int b44_phy_reset(struct b44 *bp)
323 {
324         u32 val;
325         int err;
326
327         if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
328                 return 0;
329         err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
330         if (err)
331                 return err;
332         udelay(100);
333         err = b44_readphy(bp, MII_BMCR, &val);
334         if (!err) {
335                 if (val & BMCR_RESET) {
336                         printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
337                                bp->dev->name);
338                         err = -ENODEV;
339                 }
340         }
341
342         return 0;
343 }
344
345 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
346 {
347         u32 val;
348
349         bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
350         bp->flags |= pause_flags;
351
352         val = br32(bp, B44_RXCONFIG);
353         if (pause_flags & B44_FLAG_RX_PAUSE)
354                 val |= RXCONFIG_FLOW;
355         else
356                 val &= ~RXCONFIG_FLOW;
357         bw32(bp, B44_RXCONFIG, val);
358
359         val = br32(bp, B44_MAC_FLOW);
360         if (pause_flags & B44_FLAG_TX_PAUSE)
361                 val |= (MAC_FLOW_PAUSE_ENAB |
362                         (0xc0 & MAC_FLOW_RX_HI_WATER));
363         else
364                 val &= ~MAC_FLOW_PAUSE_ENAB;
365         bw32(bp, B44_MAC_FLOW, val);
366 }
367
368 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
369 {
370         u32 pause_enab = 0;
371
372         /* The driver supports only rx pause by default because
373            the b44 mac tx pause mechanism generates excessive
374            pause frames.
375            Use ethtool to turn on b44 tx pause if necessary.
376          */
377         if ((local & ADVERTISE_PAUSE_CAP) &&
378             (local & ADVERTISE_PAUSE_ASYM)){
379                 if ((remote & LPA_PAUSE_ASYM) &&
380                     !(remote & LPA_PAUSE_CAP))
381                         pause_enab |= B44_FLAG_RX_PAUSE;
382         }
383
384         __b44_set_flow_ctrl(bp, pause_enab);
385 }
386
387 #ifdef SSB_DRIVER_MIPS
388 extern char *nvram_get(char *name);
389 static void b44_wap54g10_workaround(struct b44 *bp)
390 {
391         const char *str;
392         u32 val;
393         int err;
394
395         /*
396          * workaround for bad hardware design in Linksys WAP54G v1.0
397          * see https://dev.openwrt.org/ticket/146
398          * check and reset bit "isolate"
399          */
400         str = nvram_get("boardnum");
401         if (!str)
402                 return;
403         if (simple_strtoul(str, NULL, 0) == 2) {
404                 err = __b44_readphy(bp, 0, MII_BMCR, &val);
405                 if (err)
406                         goto error;
407                 if (!(val & BMCR_ISOLATE))
408                         return;
409                 val &= ~BMCR_ISOLATE;
410                 err = __b44_writephy(bp, 0, MII_BMCR, val);
411                 if (err)
412                         goto error;
413         }
414         return;
415 error:
416         printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
417 }
418 #else
419 static inline void b44_wap54g10_workaround(struct b44 *bp)
420 {
421 }
422 #endif
423
424 static int b44_setup_phy(struct b44 *bp)
425 {
426         u32 val;
427         int err;
428
429         b44_wap54g10_workaround(bp);
430
431         if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
432                 return 0;
433         if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
434                 goto out;
435         if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
436                                 val & MII_ALEDCTRL_ALLMSK)) != 0)
437                 goto out;
438         if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
439                 goto out;
440         if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
441                                 val | MII_TLEDCTRL_ENABLE)) != 0)
442                 goto out;
443
444         if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
445                 u32 adv = ADVERTISE_CSMA;
446
447                 if (bp->flags & B44_FLAG_ADV_10HALF)
448                         adv |= ADVERTISE_10HALF;
449                 if (bp->flags & B44_FLAG_ADV_10FULL)
450                         adv |= ADVERTISE_10FULL;
451                 if (bp->flags & B44_FLAG_ADV_100HALF)
452                         adv |= ADVERTISE_100HALF;
453                 if (bp->flags & B44_FLAG_ADV_100FULL)
454                         adv |= ADVERTISE_100FULL;
455
456                 if (bp->flags & B44_FLAG_PAUSE_AUTO)
457                         adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
458
459                 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
460                         goto out;
461                 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
462                                                        BMCR_ANRESTART))) != 0)
463                         goto out;
464         } else {
465                 u32 bmcr;
466
467                 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
468                         goto out;
469                 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
470                 if (bp->flags & B44_FLAG_100_BASE_T)
471                         bmcr |= BMCR_SPEED100;
472                 if (bp->flags & B44_FLAG_FULL_DUPLEX)
473                         bmcr |= BMCR_FULLDPLX;
474                 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
475                         goto out;
476
477                 /* Since we will not be negotiating there is no safe way
478                  * to determine if the link partner supports flow control
479                  * or not.  So just disable it completely in this case.
480                  */
481                 b44_set_flow_ctrl(bp, 0, 0);
482         }
483
484 out:
485         return err;
486 }
487
488 static void b44_stats_update(struct b44 *bp)
489 {
490         unsigned long reg;
491         u32 *val;
492
493         val = &bp->hw_stats.tx_good_octets;
494         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
495                 *val++ += br32(bp, reg);
496         }
497
498         /* Pad */
499         reg += 8*4UL;
500
501         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
502                 *val++ += br32(bp, reg);
503         }
504 }
505
506 static void b44_link_report(struct b44 *bp)
507 {
508         if (!netif_carrier_ok(bp->dev)) {
509                 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
510         } else {
511                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
512                        bp->dev->name,
513                        (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
514                        (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
515
516                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
517                        "%s for RX.\n",
518                        bp->dev->name,
519                        (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
520                        (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
521         }
522 }
523
524 static void b44_check_phy(struct b44 *bp)
525 {
526         u32 bmsr, aux;
527
528         if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
529                 bp->flags |= B44_FLAG_100_BASE_T;
530                 bp->flags |= B44_FLAG_FULL_DUPLEX;
531                 if (!netif_carrier_ok(bp->dev)) {
532                         u32 val = br32(bp, B44_TX_CTRL);
533                         val |= TX_CTRL_DUPLEX;
534                         bw32(bp, B44_TX_CTRL, val);
535                         netif_carrier_on(bp->dev);
536                         b44_link_report(bp);
537                 }
538                 return;
539         }
540
541         if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
542             !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
543             (bmsr != 0xffff)) {
544                 if (aux & MII_AUXCTRL_SPEED)
545                         bp->flags |= B44_FLAG_100_BASE_T;
546                 else
547                         bp->flags &= ~B44_FLAG_100_BASE_T;
548                 if (aux & MII_AUXCTRL_DUPLEX)
549                         bp->flags |= B44_FLAG_FULL_DUPLEX;
550                 else
551                         bp->flags &= ~B44_FLAG_FULL_DUPLEX;
552
553                 if (!netif_carrier_ok(bp->dev) &&
554                     (bmsr & BMSR_LSTATUS)) {
555                         u32 val = br32(bp, B44_TX_CTRL);
556                         u32 local_adv, remote_adv;
557
558                         if (bp->flags & B44_FLAG_FULL_DUPLEX)
559                                 val |= TX_CTRL_DUPLEX;
560                         else
561                                 val &= ~TX_CTRL_DUPLEX;
562                         bw32(bp, B44_TX_CTRL, val);
563
564                         if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
565                             !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
566                             !b44_readphy(bp, MII_LPA, &remote_adv))
567                                 b44_set_flow_ctrl(bp, local_adv, remote_adv);
568
569                         /* Link now up */
570                         netif_carrier_on(bp->dev);
571                         b44_link_report(bp);
572                 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
573                         /* Link now down */
574                         netif_carrier_off(bp->dev);
575                         b44_link_report(bp);
576                 }
577
578                 if (bmsr & BMSR_RFAULT)
579                         printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
580                                bp->dev->name);
581                 if (bmsr & BMSR_JCD)
582                         printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
583                                bp->dev->name);
584         }
585 }
586
587 static void b44_timer(unsigned long __opaque)
588 {
589         struct b44 *bp = (struct b44 *) __opaque;
590
591         spin_lock_irq(&bp->lock);
592
593         b44_check_phy(bp);
594
595         b44_stats_update(bp);
596
597         spin_unlock_irq(&bp->lock);
598
599         mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
600 }
601
602 static void b44_tx(struct b44 *bp)
603 {
604         u32 cur, cons;
605
606         cur  = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
607         cur /= sizeof(struct dma_desc);
608
609         /* XXX needs updating when NETIF_F_SG is supported */
610         for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
611                 struct ring_info *rp = &bp->tx_buffers[cons];
612                 struct sk_buff *skb = rp->skb;
613
614                 BUG_ON(skb == NULL);
615
616                 dma_unmap_single(bp->sdev->dma_dev,
617                                  rp->mapping,
618                                  skb->len,
619                                  DMA_TO_DEVICE);
620                 rp->skb = NULL;
621                 dev_kfree_skb_irq(skb);
622         }
623
624         bp->tx_cons = cons;
625         if (netif_queue_stopped(bp->dev) &&
626             TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
627                 netif_wake_queue(bp->dev);
628
629         bw32(bp, B44_GPTIMER, 0);
630 }
631
632 /* Works like this.  This chip writes a 'struct rx_header" 30 bytes
633  * before the DMA address you give it.  So we allocate 30 more bytes
634  * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
635  * point the chip at 30 bytes past where the rx_header will go.
636  */
637 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
638 {
639         struct dma_desc *dp;
640         struct ring_info *src_map, *map;
641         struct rx_header *rh;
642         struct sk_buff *skb;
643         dma_addr_t mapping;
644         int dest_idx;
645         u32 ctrl;
646
647         src_map = NULL;
648         if (src_idx >= 0)
649                 src_map = &bp->rx_buffers[src_idx];
650         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
651         map = &bp->rx_buffers[dest_idx];
652         skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
653         if (skb == NULL)
654                 return -ENOMEM;
655
656         mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
657                                  RX_PKT_BUF_SZ,
658                                  DMA_FROM_DEVICE);
659
660         /* Hardware bug work-around, the chip is unable to do PCI DMA
661            to/from anything above 1GB :-( */
662         if (dma_mapping_error(mapping) ||
663                 mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
664                 /* Sigh... */
665                 if (!dma_mapping_error(mapping))
666                         dma_unmap_single(bp->sdev->dma_dev, mapping,
667                                         RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
668                 dev_kfree_skb_any(skb);
669                 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
670                 if (skb == NULL)
671                         return -ENOMEM;
672                 mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
673                                          RX_PKT_BUF_SZ,
674                                          DMA_FROM_DEVICE);
675                 if (dma_mapping_error(mapping) ||
676                         mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
677                         if (!dma_mapping_error(mapping))
678                                 dma_unmap_single(bp->sdev->dma_dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
679                         dev_kfree_skb_any(skb);
680                         return -ENOMEM;
681                 }
682         }
683
684         rh = (struct rx_header *) skb->data;
685         skb_reserve(skb, RX_PKT_OFFSET);
686
687         rh->len = 0;
688         rh->flags = 0;
689
690         map->skb = skb;
691         map->mapping = mapping;
692
693         if (src_map != NULL)
694                 src_map->skb = NULL;
695
696         ctrl  = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - RX_PKT_OFFSET));
697         if (dest_idx == (B44_RX_RING_SIZE - 1))
698                 ctrl |= DESC_CTRL_EOT;
699
700         dp = &bp->rx_ring[dest_idx];
701         dp->ctrl = cpu_to_le32(ctrl);
702         dp->addr = cpu_to_le32((u32) mapping + RX_PKT_OFFSET + bp->dma_offset);
703
704         if (bp->flags & B44_FLAG_RX_RING_HACK)
705                 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
706                                             dest_idx * sizeof(dp),
707                                             DMA_BIDIRECTIONAL);
708
709         return RX_PKT_BUF_SZ;
710 }
711
712 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
713 {
714         struct dma_desc *src_desc, *dest_desc;
715         struct ring_info *src_map, *dest_map;
716         struct rx_header *rh;
717         int dest_idx;
718         __le32 ctrl;
719
720         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
721         dest_desc = &bp->rx_ring[dest_idx];
722         dest_map = &bp->rx_buffers[dest_idx];
723         src_desc = &bp->rx_ring[src_idx];
724         src_map = &bp->rx_buffers[src_idx];
725
726         dest_map->skb = src_map->skb;
727         rh = (struct rx_header *) src_map->skb->data;
728         rh->len = 0;
729         rh->flags = 0;
730         dest_map->mapping = src_map->mapping;
731
732         if (bp->flags & B44_FLAG_RX_RING_HACK)
733                 b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
734                                          src_idx * sizeof(src_desc),
735                                          DMA_BIDIRECTIONAL);
736
737         ctrl = src_desc->ctrl;
738         if (dest_idx == (B44_RX_RING_SIZE - 1))
739                 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
740         else
741                 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
742
743         dest_desc->ctrl = ctrl;
744         dest_desc->addr = src_desc->addr;
745
746         src_map->skb = NULL;
747
748         if (bp->flags & B44_FLAG_RX_RING_HACK)
749                 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
750                                              dest_idx * sizeof(dest_desc),
751                                              DMA_BIDIRECTIONAL);
752
753         dma_sync_single_for_device(bp->sdev->dma_dev, le32_to_cpu(src_desc->addr),
754                                    RX_PKT_BUF_SZ,
755                                    DMA_FROM_DEVICE);
756 }
757
758 static int b44_rx(struct b44 *bp, int budget)
759 {
760         int received;
761         u32 cons, prod;
762
763         received = 0;
764         prod  = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
765         prod /= sizeof(struct dma_desc);
766         cons = bp->rx_cons;
767
768         while (cons != prod && budget > 0) {
769                 struct ring_info *rp = &bp->rx_buffers[cons];
770                 struct sk_buff *skb = rp->skb;
771                 dma_addr_t map = rp->mapping;
772                 struct rx_header *rh;
773                 u16 len;
774
775                 dma_sync_single_for_cpu(bp->sdev->dma_dev, map,
776                                             RX_PKT_BUF_SZ,
777                                             DMA_FROM_DEVICE);
778                 rh = (struct rx_header *) skb->data;
779                 len = le16_to_cpu(rh->len);
780                 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
781                     (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
782                 drop_it:
783                         b44_recycle_rx(bp, cons, bp->rx_prod);
784                 drop_it_no_recycle:
785                         bp->stats.rx_dropped++;
786                         goto next_pkt;
787                 }
788
789                 if (len == 0) {
790                         int i = 0;
791
792                         do {
793                                 udelay(2);
794                                 barrier();
795                                 len = le16_to_cpu(rh->len);
796                         } while (len == 0 && i++ < 5);
797                         if (len == 0)
798                                 goto drop_it;
799                 }
800
801                 /* Omit CRC. */
802                 len -= 4;
803
804                 if (len > RX_COPY_THRESHOLD) {
805                         int skb_size;
806                         skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
807                         if (skb_size < 0)
808                                 goto drop_it;
809                         dma_unmap_single(bp->sdev->dma_dev, map,
810                                          skb_size, DMA_FROM_DEVICE);
811                         /* Leave out rx_header */
812                         skb_put(skb, len + RX_PKT_OFFSET);
813                         skb_pull(skb, RX_PKT_OFFSET);
814                 } else {
815                         struct sk_buff *copy_skb;
816
817                         b44_recycle_rx(bp, cons, bp->rx_prod);
818                         copy_skb = dev_alloc_skb(len + 2);
819                         if (copy_skb == NULL)
820                                 goto drop_it_no_recycle;
821
822                         skb_reserve(copy_skb, 2);
823                         skb_put(copy_skb, len);
824                         /* DMA sync done above, copy just the actual packet */
825                         skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
826                                                          copy_skb->data, len);
827                         skb = copy_skb;
828                 }
829                 skb->ip_summed = CHECKSUM_NONE;
830                 skb->protocol = eth_type_trans(skb, bp->dev);
831                 netif_receive_skb(skb);
832                 bp->dev->last_rx = jiffies;
833                 received++;
834                 budget--;
835         next_pkt:
836                 bp->rx_prod = (bp->rx_prod + 1) &
837                         (B44_RX_RING_SIZE - 1);
838                 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
839         }
840
841         bp->rx_cons = cons;
842         bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
843
844         return received;
845 }
846
847 static int b44_poll(struct napi_struct *napi, int budget)
848 {
849         struct b44 *bp = container_of(napi, struct b44, napi);
850         struct net_device *netdev = bp->dev;
851         int work_done;
852
853         spin_lock_irq(&bp->lock);
854
855         if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
856                 /* spin_lock(&bp->tx_lock); */
857                 b44_tx(bp);
858                 /* spin_unlock(&bp->tx_lock); */
859         }
860         spin_unlock_irq(&bp->lock);
861
862         work_done = 0;
863         if (bp->istat & ISTAT_RX)
864                 work_done += b44_rx(bp, budget);
865
866         if (bp->istat & ISTAT_ERRORS) {
867                 unsigned long flags;
868
869                 spin_lock_irqsave(&bp->lock, flags);
870                 b44_halt(bp);
871                 b44_init_rings(bp);
872                 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
873                 netif_wake_queue(bp->dev);
874                 spin_unlock_irqrestore(&bp->lock, flags);
875                 work_done = 0;
876         }
877
878         if (work_done < budget) {
879                 netif_rx_complete(netdev, napi);
880                 b44_enable_ints(bp);
881         }
882
883         return work_done;
884 }
885
886 static irqreturn_t b44_interrupt(int irq, void *dev_id)
887 {
888         struct net_device *dev = dev_id;
889         struct b44 *bp = netdev_priv(dev);
890         u32 istat, imask;
891         int handled = 0;
892
893         spin_lock(&bp->lock);
894
895         istat = br32(bp, B44_ISTAT);
896         imask = br32(bp, B44_IMASK);
897
898         /* The interrupt mask register controls which interrupt bits
899          * will actually raise an interrupt to the CPU when set by hw/firmware,
900          * but doesn't mask off the bits.
901          */
902         istat &= imask;
903         if (istat) {
904                 handled = 1;
905
906                 if (unlikely(!netif_running(dev))) {
907                         printk(KERN_INFO "%s: late interrupt.\n", dev->name);
908                         goto irq_ack;
909                 }
910
911                 if (netif_rx_schedule_prep(dev, &bp->napi)) {
912                         /* NOTE: These writes are posted by the readback of
913                          *       the ISTAT register below.
914                          */
915                         bp->istat = istat;
916                         __b44_disable_ints(bp);
917                         __netif_rx_schedule(dev, &bp->napi);
918                 } else {
919                         printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
920                                dev->name);
921                 }
922
923 irq_ack:
924                 bw32(bp, B44_ISTAT, istat);
925                 br32(bp, B44_ISTAT);
926         }
927         spin_unlock(&bp->lock);
928         return IRQ_RETVAL(handled);
929 }
930
931 static void b44_tx_timeout(struct net_device *dev)
932 {
933         struct b44 *bp = netdev_priv(dev);
934
935         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
936                dev->name);
937
938         spin_lock_irq(&bp->lock);
939
940         b44_halt(bp);
941         b44_init_rings(bp);
942         b44_init_hw(bp, B44_FULL_RESET);
943
944         spin_unlock_irq(&bp->lock);
945
946         b44_enable_ints(bp);
947
948         netif_wake_queue(dev);
949 }
950
951 static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
952 {
953         struct b44 *bp = netdev_priv(dev);
954         int rc = NETDEV_TX_OK;
955         dma_addr_t mapping;
956         u32 len, entry, ctrl;
957
958         len = skb->len;
959         spin_lock_irq(&bp->lock);
960
961         /* This is a hard error, log it. */
962         if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
963                 netif_stop_queue(dev);
964                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
965                        dev->name);
966                 goto err_out;
967         }
968
969         mapping = dma_map_single(bp->sdev->dma_dev, skb->data, len, DMA_TO_DEVICE);
970         if (dma_mapping_error(mapping) || mapping + len > DMA_30BIT_MASK) {
971                 struct sk_buff *bounce_skb;
972
973                 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
974                 if (!dma_mapping_error(mapping))
975                         dma_unmap_single(bp->sdev->dma_dev, mapping, len,
976                                         DMA_TO_DEVICE);
977
978                 bounce_skb = __dev_alloc_skb(len, GFP_ATOMIC | GFP_DMA);
979                 if (!bounce_skb)
980                         goto err_out;
981
982                 mapping = dma_map_single(bp->sdev->dma_dev, bounce_skb->data,
983                                          len, DMA_TO_DEVICE);
984                 if (dma_mapping_error(mapping) || mapping + len > DMA_30BIT_MASK) {
985                         if (!dma_mapping_error(mapping))
986                                 dma_unmap_single(bp->sdev->dma_dev, mapping,
987                                          len, DMA_TO_DEVICE);
988                         dev_kfree_skb_any(bounce_skb);
989                         goto err_out;
990                 }
991
992                 skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
993                 dev_kfree_skb_any(skb);
994                 skb = bounce_skb;
995         }
996
997         entry = bp->tx_prod;
998         bp->tx_buffers[entry].skb = skb;
999         bp->tx_buffers[entry].mapping = mapping;
1000
1001         ctrl  = (len & DESC_CTRL_LEN);
1002         ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
1003         if (entry == (B44_TX_RING_SIZE - 1))
1004                 ctrl |= DESC_CTRL_EOT;
1005
1006         bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1007         bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1008
1009         if (bp->flags & B44_FLAG_TX_RING_HACK)
1010                 b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
1011                                             entry * sizeof(bp->tx_ring[0]),
1012                                             DMA_TO_DEVICE);
1013
1014         entry = NEXT_TX(entry);
1015
1016         bp->tx_prod = entry;
1017
1018         wmb();
1019
1020         bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1021         if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1022                 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1023         if (bp->flags & B44_FLAG_REORDER_BUG)
1024                 br32(bp, B44_DMATX_PTR);
1025
1026         if (TX_BUFFS_AVAIL(bp) < 1)
1027                 netif_stop_queue(dev);
1028
1029         dev->trans_start = jiffies;
1030
1031 out_unlock:
1032         spin_unlock_irq(&bp->lock);
1033
1034         return rc;
1035
1036 err_out:
1037         rc = NETDEV_TX_BUSY;
1038         goto out_unlock;
1039 }
1040
1041 static int b44_change_mtu(struct net_device *dev, int new_mtu)
1042 {
1043         struct b44 *bp = netdev_priv(dev);
1044
1045         if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1046                 return -EINVAL;
1047
1048         if (!netif_running(dev)) {
1049                 /* We'll just catch it later when the
1050                  * device is up'd.
1051                  */
1052                 dev->mtu = new_mtu;
1053                 return 0;
1054         }
1055
1056         spin_lock_irq(&bp->lock);
1057         b44_halt(bp);
1058         dev->mtu = new_mtu;
1059         b44_init_rings(bp);
1060         b44_init_hw(bp, B44_FULL_RESET);
1061         spin_unlock_irq(&bp->lock);
1062
1063         b44_enable_ints(bp);
1064
1065         return 0;
1066 }
1067
1068 /* Free up pending packets in all rx/tx rings.
1069  *
1070  * The chip has been shut down and the driver detached from
1071  * the networking, so no interrupts or new tx packets will
1072  * end up in the driver.  bp->lock is not held and we are not
1073  * in an interrupt context and thus may sleep.
1074  */
1075 static void b44_free_rings(struct b44 *bp)
1076 {
1077         struct ring_info *rp;
1078         int i;
1079
1080         for (i = 0; i < B44_RX_RING_SIZE; i++) {
1081                 rp = &bp->rx_buffers[i];
1082
1083                 if (rp->skb == NULL)
1084                         continue;
1085                 dma_unmap_single(bp->sdev->dma_dev, rp->mapping, RX_PKT_BUF_SZ,
1086                                         DMA_FROM_DEVICE);
1087                 dev_kfree_skb_any(rp->skb);
1088                 rp->skb = NULL;
1089         }
1090
1091         /* XXX needs changes once NETIF_F_SG is set... */
1092         for (i = 0; i < B44_TX_RING_SIZE; i++) {
1093                 rp = &bp->tx_buffers[i];
1094
1095                 if (rp->skb == NULL)
1096                         continue;
1097                 dma_unmap_single(bp->sdev->dma_dev, rp->mapping, rp->skb->len,
1098                                         DMA_TO_DEVICE);
1099                 dev_kfree_skb_any(rp->skb);
1100                 rp->skb = NULL;
1101         }
1102 }
1103
1104 /* Initialize tx/rx rings for packet processing.
1105  *
1106  * The chip has been shut down and the driver detached from
1107  * the networking, so no interrupts or new tx packets will
1108  * end up in the driver.
1109  */
1110 static void b44_init_rings(struct b44 *bp)
1111 {
1112         int i;
1113
1114         b44_free_rings(bp);
1115
1116         memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1117         memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1118
1119         if (bp->flags & B44_FLAG_RX_RING_HACK)
1120                 dma_sync_single_for_device(bp->sdev->dma_dev, bp->rx_ring_dma,
1121                                           DMA_TABLE_BYTES,
1122                                           DMA_BIDIRECTIONAL);
1123
1124         if (bp->flags & B44_FLAG_TX_RING_HACK)
1125                 dma_sync_single_for_device(bp->sdev->dma_dev, bp->tx_ring_dma,
1126                                           DMA_TABLE_BYTES,
1127                                           DMA_TO_DEVICE);
1128
1129         for (i = 0; i < bp->rx_pending; i++) {
1130                 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1131                         break;
1132         }
1133 }
1134
1135 /*
1136  * Must not be invoked with interrupt sources disabled and
1137  * the hardware shutdown down.
1138  */
1139 static void b44_free_consistent(struct b44 *bp)
1140 {
1141         kfree(bp->rx_buffers);
1142         bp->rx_buffers = NULL;
1143         kfree(bp->tx_buffers);
1144         bp->tx_buffers = NULL;
1145         if (bp->rx_ring) {
1146                 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1147                         dma_unmap_single(bp->sdev->dma_dev, bp->rx_ring_dma,
1148                                         DMA_TABLE_BYTES,
1149                                         DMA_BIDIRECTIONAL);
1150                         kfree(bp->rx_ring);
1151                 } else
1152                         dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
1153                                             bp->rx_ring, bp->rx_ring_dma);
1154                 bp->rx_ring = NULL;
1155                 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1156         }
1157         if (bp->tx_ring) {
1158                 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1159                         dma_unmap_single(bp->sdev->dma_dev, bp->tx_ring_dma,
1160                                         DMA_TABLE_BYTES,
1161                                         DMA_TO_DEVICE);
1162                         kfree(bp->tx_ring);
1163                 } else
1164                         dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
1165                                             bp->tx_ring, bp->tx_ring_dma);
1166                 bp->tx_ring = NULL;
1167                 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1168         }
1169 }
1170
1171 /*
1172  * Must not be invoked with interrupt sources disabled and
1173  * the hardware shutdown down.  Can sleep.
1174  */
1175 static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1176 {
1177         int size;
1178
1179         size  = B44_RX_RING_SIZE * sizeof(struct ring_info);
1180         bp->rx_buffers = kzalloc(size, gfp);
1181         if (!bp->rx_buffers)
1182                 goto out_err;
1183
1184         size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1185         bp->tx_buffers = kzalloc(size, gfp);
1186         if (!bp->tx_buffers)
1187                 goto out_err;
1188
1189         size = DMA_TABLE_BYTES;
1190         bp->rx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size, &bp->rx_ring_dma, gfp);
1191         if (!bp->rx_ring) {
1192                 /* Allocation may have failed due to pci_alloc_consistent
1193                    insisting on use of GFP_DMA, which is more restrictive
1194                    than necessary...  */
1195                 struct dma_desc *rx_ring;
1196                 dma_addr_t rx_ring_dma;
1197
1198                 rx_ring = kzalloc(size, gfp);
1199                 if (!rx_ring)
1200                         goto out_err;
1201
1202                 rx_ring_dma = dma_map_single(bp->sdev->dma_dev, rx_ring,
1203                                             DMA_TABLE_BYTES,
1204                                             DMA_BIDIRECTIONAL);
1205
1206                 if (dma_mapping_error(rx_ring_dma) ||
1207                         rx_ring_dma + size > DMA_30BIT_MASK) {
1208                         kfree(rx_ring);
1209                         goto out_err;
1210                 }
1211
1212                 bp->rx_ring = rx_ring;
1213                 bp->rx_ring_dma = rx_ring_dma;
1214                 bp->flags |= B44_FLAG_RX_RING_HACK;
1215         }
1216
1217         bp->tx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size, &bp->tx_ring_dma, gfp);
1218         if (!bp->tx_ring) {
1219                 /* Allocation may have failed due to dma_alloc_coherent
1220                    insisting on use of GFP_DMA, which is more restrictive
1221                    than necessary...  */
1222                 struct dma_desc *tx_ring;
1223                 dma_addr_t tx_ring_dma;
1224
1225                 tx_ring = kzalloc(size, gfp);
1226                 if (!tx_ring)
1227                         goto out_err;
1228
1229                 tx_ring_dma = dma_map_single(bp->sdev->dma_dev, tx_ring,
1230                                             DMA_TABLE_BYTES,
1231                                             DMA_TO_DEVICE);
1232
1233                 if (dma_mapping_error(tx_ring_dma) ||
1234                         tx_ring_dma + size > DMA_30BIT_MASK) {
1235                         kfree(tx_ring);
1236                         goto out_err;
1237                 }
1238
1239                 bp->tx_ring = tx_ring;
1240                 bp->tx_ring_dma = tx_ring_dma;
1241                 bp->flags |= B44_FLAG_TX_RING_HACK;
1242         }
1243
1244         return 0;
1245
1246 out_err:
1247         b44_free_consistent(bp);
1248         return -ENOMEM;
1249 }
1250
1251 /* bp->lock is held. */
1252 static void b44_clear_stats(struct b44 *bp)
1253 {
1254         unsigned long reg;
1255
1256         bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1257         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1258                 br32(bp, reg);
1259         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1260                 br32(bp, reg);
1261 }
1262
1263 /* bp->lock is held. */
1264 static void b44_chip_reset(struct b44 *bp, int reset_kind)
1265 {
1266         struct ssb_device *sdev = bp->sdev;
1267
1268         if (ssb_device_is_enabled(bp->sdev)) {
1269                 bw32(bp, B44_RCV_LAZY, 0);
1270                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1271                 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
1272                 bw32(bp, B44_DMATX_CTRL, 0);
1273                 bp->tx_prod = bp->tx_cons = 0;
1274                 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1275                         b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1276                                      100, 0);
1277                 }
1278                 bw32(bp, B44_DMARX_CTRL, 0);
1279                 bp->rx_prod = bp->rx_cons = 0;
1280         } else
1281                 ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);
1282
1283         ssb_device_enable(bp->sdev, 0);
1284         b44_clear_stats(bp);
1285
1286         /*
1287          * Don't enable PHY if we are doing a partial reset
1288          * we are probably going to power down
1289          */
1290         if (reset_kind == B44_CHIP_RESET_PARTIAL)
1291                 return;
1292
1293         switch (sdev->bus->bustype) {
1294         case SSB_BUSTYPE_SSB:
1295                 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1296                      (((ssb_clockspeed(sdev->bus) + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
1297                      & MDIO_CTRL_MAXF_MASK)));
1298                 break;
1299         case SSB_BUSTYPE_PCI:
1300         case SSB_BUSTYPE_PCMCIA:
1301                 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1302                      (0x0d & MDIO_CTRL_MAXF_MASK)));
1303                 break;
1304         }
1305
1306         br32(bp, B44_MDIO_CTRL);
1307
1308         if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1309                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1310                 br32(bp, B44_ENET_CTRL);
1311                 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1312         } else {
1313                 u32 val = br32(bp, B44_DEVCTRL);
1314
1315                 if (val & DEVCTRL_EPR) {
1316                         bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1317                         br32(bp, B44_DEVCTRL);
1318                         udelay(100);
1319                 }
1320                 bp->flags |= B44_FLAG_INTERNAL_PHY;
1321         }
1322 }
1323
1324 /* bp->lock is held. */
1325 static void b44_halt(struct b44 *bp)
1326 {
1327         b44_disable_ints(bp);
1328         /* reset PHY */
1329         b44_phy_reset(bp);
1330         /* power down PHY */
1331         printk(KERN_INFO PFX "%s: powering down PHY\n", bp->dev->name);
1332         bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
1333         /* now reset the chip, but without enabling the MAC&PHY
1334          * part of it. This has to be done _after_ we shut down the PHY */
1335         b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1336 }
1337
1338 /* bp->lock is held. */
1339 static void __b44_set_mac_addr(struct b44 *bp)
1340 {
1341         bw32(bp, B44_CAM_CTRL, 0);
1342         if (!(bp->dev->flags & IFF_PROMISC)) {
1343                 u32 val;
1344
1345                 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1346                 val = br32(bp, B44_CAM_CTRL);
1347                 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1348         }
1349 }
1350
1351 static int b44_set_mac_addr(struct net_device *dev, void *p)
1352 {
1353         struct b44 *bp = netdev_priv(dev);
1354         struct sockaddr *addr = p;
1355         u32 val;
1356
1357         if (netif_running(dev))
1358                 return -EBUSY;
1359
1360         if (!is_valid_ether_addr(addr->sa_data))
1361                 return -EINVAL;
1362
1363         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1364
1365         spin_lock_irq(&bp->lock);
1366
1367         val = br32(bp, B44_RXCONFIG);
1368         if (!(val & RXCONFIG_CAM_ABSENT))
1369                 __b44_set_mac_addr(bp);
1370
1371         spin_unlock_irq(&bp->lock);
1372
1373         return 0;
1374 }
1375
1376 /* Called at device open time to get the chip ready for
1377  * packet processing.  Invoked with bp->lock held.
1378  */
1379 static void __b44_set_rx_mode(struct net_device *);
1380 static void b44_init_hw(struct b44 *bp, int reset_kind)
1381 {
1382         u32 val;
1383
1384         b44_chip_reset(bp, B44_CHIP_RESET_FULL);
1385         if (reset_kind == B44_FULL_RESET) {
1386                 b44_phy_reset(bp);
1387                 b44_setup_phy(bp);
1388         }
1389
1390         /* Enable CRC32, set proper LED modes and power on PHY */
1391         bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1392         bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1393
1394         /* This sets the MAC address too.  */
1395         __b44_set_rx_mode(bp->dev);
1396
1397         /* MTU + eth header + possible VLAN tag + struct rx_header */
1398         bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1399         bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1400
1401         bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1402         if (reset_kind == B44_PARTIAL_RESET) {
1403                 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1404                                       (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1405         } else {
1406                 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1407                 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1408                 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1409                                       (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1410                 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1411
1412                 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1413                 bp->rx_prod = bp->rx_pending;
1414
1415                 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1416         }
1417
1418         val = br32(bp, B44_ENET_CTRL);
1419         bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1420 }
1421
1422 static int b44_open(struct net_device *dev)
1423 {
1424         struct b44 *bp = netdev_priv(dev);
1425         int err;
1426
1427         err = b44_alloc_consistent(bp, GFP_KERNEL);
1428         if (err)
1429                 goto out;
1430
1431         napi_enable(&bp->napi);
1432
1433         b44_init_rings(bp);
1434         b44_init_hw(bp, B44_FULL_RESET);
1435
1436         b44_check_phy(bp);
1437
1438         err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
1439         if (unlikely(err < 0)) {
1440                 napi_disable(&bp->napi);
1441                 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1442                 b44_free_rings(bp);
1443                 b44_free_consistent(bp);
1444                 goto out;
1445         }
1446
1447         init_timer(&bp->timer);
1448         bp->timer.expires = jiffies + HZ;
1449         bp->timer.data = (unsigned long) bp;
1450         bp->timer.function = b44_timer;
1451         add_timer(&bp->timer);
1452
1453         b44_enable_ints(bp);
1454         netif_start_queue(dev);
1455 out:
1456         return err;
1457 }
1458
1459 #ifdef CONFIG_NET_POLL_CONTROLLER
1460 /*
1461  * Polling receive - used by netconsole and other diagnostic tools
1462  * to allow network i/o with interrupts disabled.
1463  */
1464 static void b44_poll_controller(struct net_device *dev)
1465 {
1466         disable_irq(dev->irq);
1467         b44_interrupt(dev->irq, dev);
1468         enable_irq(dev->irq);
1469 }
1470 #endif
1471
1472 static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
1473 {
1474         u32 i;
1475         u32 *pattern = (u32 *) pp;
1476
1477         for (i = 0; i < bytes; i += sizeof(u32)) {
1478                 bw32(bp, B44_FILT_ADDR, table_offset + i);
1479                 bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
1480         }
1481 }
1482
1483 static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
1484 {
1485         int magicsync = 6;
1486         int k, j, len = offset;
1487         int ethaddr_bytes = ETH_ALEN;
1488
1489         memset(ppattern + offset, 0xff, magicsync);
1490         for (j = 0; j < magicsync; j++)
1491                 set_bit(len++, (unsigned long *) pmask);
1492
1493         for (j = 0; j < B44_MAX_PATTERNS; j++) {
1494                 if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
1495                         ethaddr_bytes = ETH_ALEN;
1496                 else
1497                         ethaddr_bytes = B44_PATTERN_SIZE - len;
1498                 if (ethaddr_bytes <=0)
1499                         break;
1500                 for (k = 0; k< ethaddr_bytes; k++) {
1501                         ppattern[offset + magicsync +
1502                                 (j * ETH_ALEN) + k] = macaddr[k];
1503                         len++;
1504                         set_bit(len, (unsigned long *) pmask);
1505                 }
1506         }
1507         return len - 1;
1508 }
1509
1510 /* Setup magic packet patterns in the b44 WOL
1511  * pattern matching filter.
1512  */
1513 static void b44_setup_pseudo_magicp(struct b44 *bp)
1514 {
1515
1516         u32 val;
1517         int plen0, plen1, plen2;
1518         u8 *pwol_pattern;
1519         u8 pwol_mask[B44_PMASK_SIZE];
1520
1521         pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
1522         if (!pwol_pattern) {
1523                 printk(KERN_ERR PFX "Memory not available for WOL\n");
1524                 return;
1525         }
1526
1527         /* Ipv4 magic packet pattern - pattern 0.*/
1528         memset(pwol_mask, 0, B44_PMASK_SIZE);
1529         plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1530                                   B44_ETHIPV4UDP_HLEN);
1531
1532         bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
1533         bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);
1534
1535         /* Raw ethernet II magic packet pattern - pattern 1 */
1536         memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1537         memset(pwol_mask, 0, B44_PMASK_SIZE);
1538         plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1539                                   ETH_HLEN);
1540
1541         bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1542                        B44_PATTERN_BASE + B44_PATTERN_SIZE);
1543         bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1544                        B44_PMASK_BASE + B44_PMASK_SIZE);
1545
1546         /* Ipv6 magic packet pattern - pattern 2 */
1547         memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1548         memset(pwol_mask, 0, B44_PMASK_SIZE);
1549         plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1550                                   B44_ETHIPV6UDP_HLEN);
1551
1552         bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1553                        B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
1554         bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1555                        B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);
1556
1557         kfree(pwol_pattern);
1558
1559         /* set these pattern's lengths: one less than each real length */
1560         val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
1561         bw32(bp, B44_WKUP_LEN, val);
1562
1563         /* enable wakeup pattern matching */
1564         val = br32(bp, B44_DEVCTRL);
1565         bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1566
1567 }
1568
1569 #ifdef CONFIG_B44_PCI
1570 static void b44_setup_wol_pci(struct b44 *bp)
1571 {
1572         u16 val;
1573
1574         if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
1575                 bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
1576                 pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
1577                 pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
1578         }
1579 }
1580 #else
1581 static inline void b44_setup_wol_pci(struct b44 *bp) { }
1582 #endif /* CONFIG_B44_PCI */
1583
1584 static void b44_setup_wol(struct b44 *bp)
1585 {
1586         u32 val;
1587
1588         bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
1589
1590         if (bp->flags & B44_FLAG_B0_ANDLATER) {
1591
1592                 bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
1593
1594                 val = bp->dev->dev_addr[2] << 24 |
1595                         bp->dev->dev_addr[3] << 16 |
1596                         bp->dev->dev_addr[4] << 8 |
1597                         bp->dev->dev_addr[5];
1598                 bw32(bp, B44_ADDR_LO, val);
1599
1600                 val = bp->dev->dev_addr[0] << 8 |
1601                         bp->dev->dev_addr[1];
1602                 bw32(bp, B44_ADDR_HI, val);
1603
1604                 val = br32(bp, B44_DEVCTRL);
1605                 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1606
1607         } else {
1608                 b44_setup_pseudo_magicp(bp);
1609         }
1610         b44_setup_wol_pci(bp);
1611 }
1612
1613 static int b44_close(struct net_device *dev)
1614 {
1615         struct b44 *bp = netdev_priv(dev);
1616
1617         netif_stop_queue(dev);
1618
1619         napi_disable(&bp->napi);
1620
1621         del_timer_sync(&bp->timer);
1622
1623         spin_lock_irq(&bp->lock);
1624
1625         b44_halt(bp);
1626         b44_free_rings(bp);
1627         netif_carrier_off(dev);
1628
1629         spin_unlock_irq(&bp->lock);
1630
1631         free_irq(dev->irq, dev);
1632
1633         if (bp->flags & B44_FLAG_WOL_ENABLE) {
1634                 b44_init_hw(bp, B44_PARTIAL_RESET);
1635                 b44_setup_wol(bp);
1636         }
1637
1638         b44_free_consistent(bp);
1639
1640         return 0;
1641 }
1642
1643 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1644 {
1645         struct b44 *bp = netdev_priv(dev);
1646         struct net_device_stats *nstat = &bp->stats;
1647         struct b44_hw_stats *hwstat = &bp->hw_stats;
1648
1649         /* Convert HW stats into netdevice stats. */
1650         nstat->rx_packets = hwstat->rx_pkts;
1651         nstat->tx_packets = hwstat->tx_pkts;
1652         nstat->rx_bytes   = hwstat->rx_octets;
1653         nstat->tx_bytes   = hwstat->tx_octets;
1654         nstat->tx_errors  = (hwstat->tx_jabber_pkts +
1655                              hwstat->tx_oversize_pkts +
1656                              hwstat->tx_underruns +
1657                              hwstat->tx_excessive_cols +
1658                              hwstat->tx_late_cols);
1659         nstat->multicast  = hwstat->tx_multicast_pkts;
1660         nstat->collisions = hwstat->tx_total_cols;
1661
1662         nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1663                                    hwstat->rx_undersize);
1664         nstat->rx_over_errors   = hwstat->rx_missed_pkts;
1665         nstat->rx_frame_errors  = hwstat->rx_align_errs;
1666         nstat->rx_crc_errors    = hwstat->rx_crc_errs;
1667         nstat->rx_errors        = (hwstat->rx_jabber_pkts +
1668                                    hwstat->rx_oversize_pkts +
1669                                    hwstat->rx_missed_pkts +
1670                                    hwstat->rx_crc_align_errs +
1671                                    hwstat->rx_undersize +
1672                                    hwstat->rx_crc_errs +
1673                                    hwstat->rx_align_errs +
1674                                    hwstat->rx_symbol_errs);
1675
1676         nstat->tx_aborted_errors = hwstat->tx_underruns;
1677 #if 0
1678         /* Carrier lost counter seems to be broken for some devices */
1679         nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1680 #endif
1681
1682         return nstat;
1683 }
1684
1685 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1686 {
1687         struct dev_mc_list *mclist;
1688         int i, num_ents;
1689
1690         num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1691         mclist = dev->mc_list;
1692         for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1693                 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1694         }
1695         return i+1;
1696 }
1697
1698 static void __b44_set_rx_mode(struct net_device *dev)
1699 {
1700         struct b44 *bp = netdev_priv(dev);
1701         u32 val;
1702
1703         val = br32(bp, B44_RXCONFIG);
1704         val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1705         if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
1706                 val |= RXCONFIG_PROMISC;
1707                 bw32(bp, B44_RXCONFIG, val);
1708         } else {
1709                 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1710                 int i = 1;
1711
1712                 __b44_set_mac_addr(bp);
1713
1714                 if ((dev->flags & IFF_ALLMULTI) ||
1715                     (dev->mc_count > B44_MCAST_TABLE_SIZE))
1716                         val |= RXCONFIG_ALLMULTI;
1717                 else
1718                         i = __b44_load_mcast(bp, dev);
1719
1720                 for (; i < 64; i++)
1721                         __b44_cam_write(bp, zero, i);
1722
1723                 bw32(bp, B44_RXCONFIG, val);
1724                 val = br32(bp, B44_CAM_CTRL);
1725                 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1726         }
1727 }
1728
1729 static void b44_set_rx_mode(struct net_device *dev)
1730 {
1731         struct b44 *bp = netdev_priv(dev);
1732
1733         spin_lock_irq(&bp->lock);
1734         __b44_set_rx_mode(dev);
1735         spin_unlock_irq(&bp->lock);
1736 }
1737
1738 static u32 b44_get_msglevel(struct net_device *dev)
1739 {
1740         struct b44 *bp = netdev_priv(dev);
1741         return bp->msg_enable;
1742 }
1743
1744 static void b44_set_msglevel(struct net_device *dev, u32 value)
1745 {
1746         struct b44 *bp = netdev_priv(dev);
1747         bp->msg_enable = value;
1748 }
1749
1750 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1751 {
1752         struct b44 *bp = netdev_priv(dev);
1753         struct ssb_bus *bus = bp->sdev->bus;
1754
1755         strncpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1756         strncpy(info->version, DRV_MODULE_VERSION, sizeof(info->driver));
1757         switch (bus->bustype) {
1758         case SSB_BUSTYPE_PCI:
1759                 strncpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
1760                 break;
1761         case SSB_BUSTYPE_PCMCIA:
1762         case SSB_BUSTYPE_SSB:
1763                 strncpy(info->bus_info, "SSB", sizeof(info->bus_info));
1764                 break;
1765         }
1766 }
1767
1768 static int b44_nway_reset(struct net_device *dev)
1769 {
1770         struct b44 *bp = netdev_priv(dev);
1771         u32 bmcr;
1772         int r;
1773
1774         spin_lock_irq(&bp->lock);
1775         b44_readphy(bp, MII_BMCR, &bmcr);
1776         b44_readphy(bp, MII_BMCR, &bmcr);
1777         r = -EINVAL;
1778         if (bmcr & BMCR_ANENABLE) {
1779                 b44_writephy(bp, MII_BMCR,
1780                              bmcr | BMCR_ANRESTART);
1781                 r = 0;
1782         }
1783         spin_unlock_irq(&bp->lock);
1784
1785         return r;
1786 }
1787
1788 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1789 {
1790         struct b44 *bp = netdev_priv(dev);
1791
1792         cmd->supported = (SUPPORTED_Autoneg);
1793         cmd->supported |= (SUPPORTED_100baseT_Half |
1794                           SUPPORTED_100baseT_Full |
1795                           SUPPORTED_10baseT_Half |
1796                           SUPPORTED_10baseT_Full |
1797                           SUPPORTED_MII);
1798
1799         cmd->advertising = 0;
1800         if (bp->flags & B44_FLAG_ADV_10HALF)
1801                 cmd->advertising |= ADVERTISED_10baseT_Half;
1802         if (bp->flags & B44_FLAG_ADV_10FULL)
1803                 cmd->advertising |= ADVERTISED_10baseT_Full;
1804         if (bp->flags & B44_FLAG_ADV_100HALF)
1805                 cmd->advertising |= ADVERTISED_100baseT_Half;
1806         if (bp->flags & B44_FLAG_ADV_100FULL)
1807                 cmd->advertising |= ADVERTISED_100baseT_Full;
1808         cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1809         cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1810                 SPEED_100 : SPEED_10;
1811         cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1812                 DUPLEX_FULL : DUPLEX_HALF;
1813         cmd->port = 0;
1814         cmd->phy_address = bp->phy_addr;
1815         cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1816                 XCVR_INTERNAL : XCVR_EXTERNAL;
1817         cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1818                 AUTONEG_DISABLE : AUTONEG_ENABLE;
1819         if (cmd->autoneg == AUTONEG_ENABLE)
1820                 cmd->advertising |= ADVERTISED_Autoneg;
1821         if (!netif_running(dev)){
1822                 cmd->speed = 0;
1823                 cmd->duplex = 0xff;
1824         }
1825         cmd->maxtxpkt = 0;
1826         cmd->maxrxpkt = 0;
1827         return 0;
1828 }
1829
1830 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1831 {
1832         struct b44 *bp = netdev_priv(dev);
1833
1834         /* We do not support gigabit. */
1835         if (cmd->autoneg == AUTONEG_ENABLE) {
1836                 if (cmd->advertising &
1837                     (ADVERTISED_1000baseT_Half |
1838                      ADVERTISED_1000baseT_Full))
1839                         return -EINVAL;
1840         } else if ((cmd->speed != SPEED_100 &&
1841                     cmd->speed != SPEED_10) ||
1842                    (cmd->duplex != DUPLEX_HALF &&
1843                     cmd->duplex != DUPLEX_FULL)) {
1844                         return -EINVAL;
1845         }
1846
1847         spin_lock_irq(&bp->lock);
1848
1849         if (cmd->autoneg == AUTONEG_ENABLE) {
1850                 bp->flags &= ~(B44_FLAG_FORCE_LINK |
1851                                B44_FLAG_100_BASE_T |
1852                                B44_FLAG_FULL_DUPLEX |
1853                                B44_FLAG_ADV_10HALF |
1854                                B44_FLAG_ADV_10FULL |
1855                                B44_FLAG_ADV_100HALF |
1856                                B44_FLAG_ADV_100FULL);
1857                 if (cmd->advertising == 0) {
1858                         bp->flags |= (B44_FLAG_ADV_10HALF |
1859                                       B44_FLAG_ADV_10FULL |
1860                                       B44_FLAG_ADV_100HALF |
1861                                       B44_FLAG_ADV_100FULL);
1862                 } else {
1863                         if (cmd->advertising & ADVERTISED_10baseT_Half)
1864                                 bp->flags |= B44_FLAG_ADV_10HALF;
1865                         if (cmd->advertising & ADVERTISED_10baseT_Full)
1866                                 bp->flags |= B44_FLAG_ADV_10FULL;
1867                         if (cmd->advertising & ADVERTISED_100baseT_Half)
1868                                 bp->flags |= B44_FLAG_ADV_100HALF;
1869                         if (cmd->advertising & ADVERTISED_100baseT_Full)
1870                                 bp->flags |= B44_FLAG_ADV_100FULL;
1871                 }
1872         } else {
1873                 bp->flags |= B44_FLAG_FORCE_LINK;
1874                 bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
1875                 if (cmd->speed == SPEED_100)
1876                         bp->flags |= B44_FLAG_100_BASE_T;
1877                 if (cmd->duplex == DUPLEX_FULL)
1878                         bp->flags |= B44_FLAG_FULL_DUPLEX;
1879         }
1880
1881         if (netif_running(dev))
1882                 b44_setup_phy(bp);
1883
1884         spin_unlock_irq(&bp->lock);
1885
1886         return 0;
1887 }
1888
1889 static void b44_get_ringparam(struct net_device *dev,
1890                               struct ethtool_ringparam *ering)
1891 {
1892         struct b44 *bp = netdev_priv(dev);
1893
1894         ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1895         ering->rx_pending = bp->rx_pending;
1896
1897         /* XXX ethtool lacks a tx_max_pending, oops... */
1898 }
1899
1900 static int b44_set_ringparam(struct net_device *dev,
1901                              struct ethtool_ringparam *ering)
1902 {
1903         struct b44 *bp = netdev_priv(dev);
1904
1905         if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1906             (ering->rx_mini_pending != 0) ||
1907             (ering->rx_jumbo_pending != 0) ||
1908             (ering->tx_pending > B44_TX_RING_SIZE - 1))
1909                 return -EINVAL;
1910
1911         spin_lock_irq(&bp->lock);
1912
1913         bp->rx_pending = ering->rx_pending;
1914         bp->tx_pending = ering->tx_pending;
1915
1916         b44_halt(bp);
1917         b44_init_rings(bp);
1918         b44_init_hw(bp, B44_FULL_RESET);
1919         netif_wake_queue(bp->dev);
1920         spin_unlock_irq(&bp->lock);
1921
1922         b44_enable_ints(bp);
1923
1924         return 0;
1925 }
1926
1927 static void b44_get_pauseparam(struct net_device *dev,
1928                                 struct ethtool_pauseparam *epause)
1929 {
1930         struct b44 *bp = netdev_priv(dev);
1931
1932         epause->autoneg =
1933                 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1934         epause->rx_pause =
1935                 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1936         epause->tx_pause =
1937                 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1938 }
1939
1940 static int b44_set_pauseparam(struct net_device *dev,
1941                                 struct ethtool_pauseparam *epause)
1942 {
1943         struct b44 *bp = netdev_priv(dev);
1944
1945         spin_lock_irq(&bp->lock);
1946         if (epause->autoneg)
1947                 bp->flags |= B44_FLAG_PAUSE_AUTO;
1948         else
1949                 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1950         if (epause->rx_pause)
1951                 bp->flags |= B44_FLAG_RX_PAUSE;
1952         else
1953                 bp->flags &= ~B44_FLAG_RX_PAUSE;
1954         if (epause->tx_pause)
1955                 bp->flags |= B44_FLAG_TX_PAUSE;
1956         else
1957                 bp->flags &= ~B44_FLAG_TX_PAUSE;
1958         if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1959                 b44_halt(bp);
1960                 b44_init_rings(bp);
1961                 b44_init_hw(bp, B44_FULL_RESET);
1962         } else {
1963                 __b44_set_flow_ctrl(bp, bp->flags);
1964         }
1965         spin_unlock_irq(&bp->lock);
1966
1967         b44_enable_ints(bp);
1968
1969         return 0;
1970 }
1971
1972 static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1973 {
1974         switch(stringset) {
1975         case ETH_SS_STATS:
1976                 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1977                 break;
1978         }
1979 }
1980
1981 static int b44_get_sset_count(struct net_device *dev, int sset)
1982 {
1983         switch (sset) {
1984         case ETH_SS_STATS:
1985                 return ARRAY_SIZE(b44_gstrings);
1986         default:
1987                 return -EOPNOTSUPP;
1988         }
1989 }
1990
1991 static void b44_get_ethtool_stats(struct net_device *dev,
1992                                   struct ethtool_stats *stats, u64 *data)
1993 {
1994         struct b44 *bp = netdev_priv(dev);
1995         u32 *val = &bp->hw_stats.tx_good_octets;
1996         u32 i;
1997
1998         spin_lock_irq(&bp->lock);
1999
2000         b44_stats_update(bp);
2001
2002         for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
2003                 *data++ = *val++;
2004
2005         spin_unlock_irq(&bp->lock);
2006 }
2007
2008 static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2009 {
2010         struct b44 *bp = netdev_priv(dev);
2011
2012         wol->supported = WAKE_MAGIC;
2013         if (bp->flags & B44_FLAG_WOL_ENABLE)
2014                 wol->wolopts = WAKE_MAGIC;
2015         else
2016                 wol->wolopts = 0;
2017         memset(&wol->sopass, 0, sizeof(wol->sopass));
2018 }
2019
2020 static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2021 {
2022         struct b44 *bp = netdev_priv(dev);
2023
2024         spin_lock_irq(&bp->lock);
2025         if (wol->wolopts & WAKE_MAGIC)
2026                 bp->flags |= B44_FLAG_WOL_ENABLE;
2027         else
2028                 bp->flags &= ~B44_FLAG_WOL_ENABLE;
2029         spin_unlock_irq(&bp->lock);
2030
2031         return 0;
2032 }
2033
2034 static const struct ethtool_ops b44_ethtool_ops = {
2035         .get_drvinfo            = b44_get_drvinfo,
2036         .get_settings           = b44_get_settings,
2037         .set_settings           = b44_set_settings,
2038         .nway_reset             = b44_nway_reset,
2039         .get_link               = ethtool_op_get_link,
2040         .get_wol                = b44_get_wol,
2041         .set_wol                = b44_set_wol,
2042         .get_ringparam          = b44_get_ringparam,
2043         .set_ringparam          = b44_set_ringparam,
2044         .get_pauseparam         = b44_get_pauseparam,
2045         .set_pauseparam         = b44_set_pauseparam,
2046         .get_msglevel           = b44_get_msglevel,
2047         .set_msglevel           = b44_set_msglevel,
2048         .get_strings            = b44_get_strings,
2049         .get_sset_count         = b44_get_sset_count,
2050         .get_ethtool_stats      = b44_get_ethtool_stats,
2051 };
2052
2053 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2054 {
2055         struct mii_ioctl_data *data = if_mii(ifr);
2056         struct b44 *bp = netdev_priv(dev);
2057         int err = -EINVAL;
2058
2059         if (!netif_running(dev))
2060                 goto out;
2061
2062         spin_lock_irq(&bp->lock);
2063         err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
2064         spin_unlock_irq(&bp->lock);
2065 out:
2066         return err;
2067 }
2068
2069 static int __devinit b44_get_invariants(struct b44 *bp)
2070 {
2071         struct ssb_device *sdev = bp->sdev;
2072         int err = 0;
2073         u8 *addr;
2074
2075         bp->dma_offset = ssb_dma_translation(sdev);
2076
2077         if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
2078             instance > 1) {
2079                 addr = sdev->bus->sprom.et1mac;
2080                 bp->phy_addr = sdev->bus->sprom.et1phyaddr;
2081         } else {
2082                 addr = sdev->bus->sprom.et0mac;
2083                 bp->phy_addr = sdev->bus->sprom.et0phyaddr;
2084         }
2085         /* Some ROMs have buggy PHY addresses with the high
2086          * bits set (sign extension?). Truncate them to a
2087          * valid PHY address. */
2088         bp->phy_addr &= 0x1F;
2089
2090         memcpy(bp->dev->dev_addr, addr, 6);
2091
2092         if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
2093                 printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
2094                 return -EINVAL;
2095         }
2096
2097         memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
2098
2099         bp->imask = IMASK_DEF;
2100
2101         /* XXX - really required?
2102            bp->flags |= B44_FLAG_BUGGY_TXPTR;
2103         */
2104
2105         if (bp->sdev->id.revision >= 7)
2106                 bp->flags |= B44_FLAG_B0_ANDLATER;
2107
2108         return err;
2109 }
2110
2111 static int __devinit b44_init_one(struct ssb_device *sdev,
2112                                   const struct ssb_device_id *ent)
2113 {
2114         static int b44_version_printed = 0;
2115         struct net_device *dev;
2116         struct b44 *bp;
2117         int err;
2118         DECLARE_MAC_BUF(mac);
2119
2120         instance++;
2121
2122         if (b44_version_printed++ == 0)
2123                 printk(KERN_INFO "%s", version);
2124
2125
2126         dev = alloc_etherdev(sizeof(*bp));
2127         if (!dev) {
2128                 dev_err(sdev->dev, "Etherdev alloc failed, aborting.\n");
2129                 err = -ENOMEM;
2130                 goto out;
2131         }
2132
2133         SET_NETDEV_DEV(dev, sdev->dev);
2134
2135         /* No interesting netdevice features in this card... */
2136         dev->features |= 0;
2137
2138         bp = netdev_priv(dev);
2139         bp->sdev = sdev;
2140         bp->dev = dev;
2141
2142         bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
2143
2144         spin_lock_init(&bp->lock);
2145
2146         bp->rx_pending = B44_DEF_RX_RING_PENDING;
2147         bp->tx_pending = B44_DEF_TX_RING_PENDING;
2148
2149         dev->open = b44_open;
2150         dev->stop = b44_close;
2151         dev->hard_start_xmit = b44_start_xmit;
2152         dev->get_stats = b44_get_stats;
2153         dev->set_multicast_list = b44_set_rx_mode;
2154         dev->set_mac_address = b44_set_mac_addr;
2155         dev->do_ioctl = b44_ioctl;
2156         dev->tx_timeout = b44_tx_timeout;
2157         netif_napi_add(dev, &bp->napi, b44_poll, 64);
2158         dev->watchdog_timeo = B44_TX_TIMEOUT;
2159 #ifdef CONFIG_NET_POLL_CONTROLLER
2160         dev->poll_controller = b44_poll_controller;
2161 #endif
2162         dev->change_mtu = b44_change_mtu;
2163         dev->irq = sdev->irq;
2164         SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
2165
2166         netif_carrier_off(dev);
2167
2168         err = ssb_bus_powerup(sdev->bus, 0);
2169         if (err) {
2170                 dev_err(sdev->dev,
2171                         "Failed to powerup the bus\n");
2172                 goto err_out_free_dev;
2173         }
2174         err = ssb_dma_set_mask(sdev, DMA_30BIT_MASK);
2175         if (err) {
2176                 dev_err(sdev->dev,
2177                         "Required 30BIT DMA mask unsupported by the system.\n");
2178                 goto err_out_powerdown;
2179         }
2180         err = b44_get_invariants(bp);
2181         if (err) {
2182                 dev_err(sdev->dev,
2183                         "Problem fetching invariants of chip, aborting.\n");
2184                 goto err_out_powerdown;
2185         }
2186
2187         bp->mii_if.dev = dev;
2188         bp->mii_if.mdio_read = b44_mii_read;
2189         bp->mii_if.mdio_write = b44_mii_write;
2190         bp->mii_if.phy_id = bp->phy_addr;
2191         bp->mii_if.phy_id_mask = 0x1f;
2192         bp->mii_if.reg_num_mask = 0x1f;
2193
2194         /* By default, advertise all speed/duplex settings. */
2195         bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2196                       B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2197
2198         /* By default, auto-negotiate PAUSE. */
2199         bp->flags |= B44_FLAG_PAUSE_AUTO;
2200
2201         err = register_netdev(dev);
2202         if (err) {
2203                 dev_err(sdev->dev, "Cannot register net device, aborting.\n");
2204                 goto err_out_powerdown;
2205         }
2206
2207         ssb_set_drvdata(sdev, dev);
2208
2209         /* Chip reset provides power to the b44 MAC & PCI cores, which
2210          * is necessary for MAC register access.
2211          */
2212         b44_chip_reset(bp, B44_CHIP_RESET_FULL);
2213
2214         printk(KERN_INFO "%s: Broadcom 44xx/47xx 10/100BaseT Ethernet %s\n",
2215                dev->name, print_mac(mac, dev->dev_addr));
2216
2217         return 0;
2218
2219 err_out_powerdown:
2220         ssb_bus_may_powerdown(sdev->bus);
2221
2222 err_out_free_dev:
2223         free_netdev(dev);
2224
2225 out:
2226         return err;
2227 }
2228
2229 static void __devexit b44_remove_one(struct ssb_device *sdev)
2230 {
2231         struct net_device *dev = ssb_get_drvdata(sdev);
2232
2233         unregister_netdev(dev);
2234         ssb_bus_may_powerdown(sdev->bus);
2235         free_netdev(dev);
2236         ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2237         ssb_set_drvdata(sdev, NULL);
2238 }
2239
2240 static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
2241 {
2242         struct net_device *dev = ssb_get_drvdata(sdev);
2243         struct b44 *bp = netdev_priv(dev);
2244
2245         if (!netif_running(dev))
2246                 return 0;
2247
2248         del_timer_sync(&bp->timer);
2249
2250         spin_lock_irq(&bp->lock);
2251
2252         b44_halt(bp);
2253         netif_carrier_off(bp->dev);
2254         netif_device_detach(bp->dev);
2255         b44_free_rings(bp);
2256
2257         spin_unlock_irq(&bp->lock);
2258
2259         free_irq(dev->irq, dev);
2260         if (bp->flags & B44_FLAG_WOL_ENABLE) {
2261                 b44_init_hw(bp, B44_PARTIAL_RESET);
2262                 b44_setup_wol(bp);
2263         }
2264
2265         ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2266         return 0;
2267 }
2268
2269 static int b44_resume(struct ssb_device *sdev)
2270 {
2271         struct net_device *dev = ssb_get_drvdata(sdev);
2272         struct b44 *bp = netdev_priv(dev);
2273         int rc = 0;
2274
2275         rc = ssb_bus_powerup(sdev->bus, 0);
2276         if (rc) {
2277                 dev_err(sdev->dev,
2278                         "Failed to powerup the bus\n");
2279                 return rc;
2280         }
2281
2282         if (!netif_running(dev))
2283                 return 0;
2284
2285         rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
2286         if (rc) {
2287                 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
2288                 return rc;
2289         }
2290
2291         spin_lock_irq(&bp->lock);
2292
2293         b44_init_rings(bp);
2294         b44_init_hw(bp, B44_FULL_RESET);
2295         netif_device_attach(bp->dev);
2296         spin_unlock_irq(&bp->lock);
2297
2298         b44_enable_ints(bp);
2299         netif_wake_queue(dev);
2300
2301         mod_timer(&bp->timer, jiffies + 1);
2302
2303         return 0;
2304 }
2305
2306 static struct ssb_driver b44_ssb_driver = {
2307         .name           = DRV_MODULE_NAME,
2308         .id_table       = b44_ssb_tbl,
2309         .probe          = b44_init_one,
2310         .remove         = __devexit_p(b44_remove_one),
2311         .suspend        = b44_suspend,
2312         .resume         = b44_resume,
2313 };
2314
2315 static inline int b44_pci_init(void)
2316 {
2317         int err = 0;
2318 #ifdef CONFIG_B44_PCI
2319         err = ssb_pcihost_register(&b44_pci_driver);
2320 #endif
2321         return err;
2322 }
2323
2324 static inline void b44_pci_exit(void)
2325 {
2326 #ifdef CONFIG_B44_PCI
2327         ssb_pcihost_unregister(&b44_pci_driver);
2328 #endif
2329 }
2330
2331 static int __init b44_init(void)
2332 {
2333         unsigned int dma_desc_align_size = dma_get_cache_alignment();
2334         int err;
2335
2336         /* Setup paramaters for syncing RX/TX DMA descriptors */
2337         dma_desc_align_mask = ~(dma_desc_align_size - 1);
2338         dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
2339
2340         err = b44_pci_init();
2341         if (err)
2342                 return err;
2343         err = ssb_driver_register(&b44_ssb_driver);
2344         if (err)
2345                 b44_pci_exit();
2346         return err;
2347 }
2348
2349 static void __exit b44_cleanup(void)
2350 {
2351         ssb_driver_unregister(&b44_ssb_driver);
2352         b44_pci_exit();
2353 }
2354
2355 module_init(b44_init);
2356 module_exit(b44_cleanup);
2357